Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
irqchip/gic-v5: Split IRS probing into OF and generic portions
Split the IRS driver code into OF specific and generic portions in order
to pave the way for adding ACPI firmware bindings support.
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Acked-by: Thomas Gleixner <tglx@kernel.org>
Link: https://patch.msgid.link/20260115-gicv5-host-acpi-v3-3-c13a9a150388@kernel.org
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
authored by
Lorenzo Pieralisi
and committed by
Rafael J. Wysocki
1c406fcd
a08df2fb
+60
-52
+60
-52
drivers/irqchip/irq-gic-v5-irs.c
+60
-52
drivers/irqchip/irq-gic-v5-irs.c
···
545
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static void __init gicv5_irs_init_bases(struct gicv5_irs_chip_data *irs_data,
547
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void __iomem *irs_base,
548
-
struct fwnode_handle *handle)
548
+
bool noncoherent)
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549
{
550
-
struct device_node *np = to_of_node(handle);
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u32 cr0, cr1;
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-
irs_data->fwnode = handle;
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irs_data->irs_base = irs_base;
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556
-
if (of_property_read_bool(np, "dma-noncoherent")) {
554
+
if (noncoherent) {
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555
/*
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* A non-coherent IRS implies that some cache levels cannot be
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* used coherently by the cores and GIC. Our only option is to mark
···
676
678
}
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}
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-
static int __init gicv5_irs_init(struct device_node *node)
681
+
static int __init gicv5_irs_init(struct gicv5_irs_chip_data *irs_data)
680
682
{
681
-
struct gicv5_irs_chip_data *irs_data;
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-
void __iomem *irs_base;
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-
u32 idr, spi_count;
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-
u8 iaffid_bits;
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-
int ret;
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+
u32 spi_count, idr = irs_readl_relaxed(irs_data, GICV5_IRS_IDR2);
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684
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-
irs_data = kzalloc(sizeof(*irs_data), GFP_KERNEL);
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-
if (!irs_data)
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-
return -ENOMEM;
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-
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-
raw_spin_lock_init(&irs_data->spi_config_lock);
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-
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-
ret = of_property_match_string(node, "reg-names", "ns-config");
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-
if (ret < 0) {
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-
pr_err("%pOF: ns-config reg-name not present\n", node);
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-
goto out_err;
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-
}
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-
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-
irs_base = of_io_request_and_map(node, ret, of_node_full_name(node));
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-
if (IS_ERR(irs_base)) {
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-
pr_err("%pOF: unable to map GICv5 IRS registers\n", node);
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-
ret = PTR_ERR(irs_base);
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-
goto out_err;
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-
}
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-
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-
gicv5_irs_init_bases(irs_data, irs_base, &node->fwnode);
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-
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-
idr = irs_readl_relaxed(irs_data, GICV5_IRS_IDR1);
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-
iaffid_bits = FIELD_GET(GICV5_IRS_IDR1_IAFFID_BITS, idr) + 1;
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-
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-
ret = gicv5_irs_of_init_affinity(node, irs_data, iaffid_bits);
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-
if (ret) {
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-
pr_err("Failed to parse CPU IAFFIDs from the device tree!\n");
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-
goto out_iomem;
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-
}
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-
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-
idr = irs_readl_relaxed(irs_data, GICV5_IRS_IDR2);
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685
if (WARN(!FIELD_GET(GICV5_IRS_IDR2_LPI, idr),
719
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"LPI support not available - no IPIs, can't proceed\n")) {
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-
ret = -ENODEV;
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-
goto out_iomem;
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+
return -ENODEV;
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}
723
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idr = irs_readl_relaxed(irs_data, GICV5_IRS_IDR7);
···
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idr = irs_readl_relaxed(irs_data, GICV5_IRS_IDR6);
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irs_data->spi_range = FIELD_GET(GICV5_IRS_IDR6_SPI_IRS_RANGE, idr);
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-
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-
if (irs_data->spi_range) {
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-
pr_info("%s detected SPI range [%u-%u]\n",
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-
of_node_full_name(node),
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-
irs_data->spi_min,
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-
irs_data->spi_min +
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-
irs_data->spi_range - 1);
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-
}
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731
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/*
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733
* Do the global setting only on the first IRS.
···
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list_add_tail(&irs_data->entry, &irs_nodes);
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return 0;
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+
}
764
+
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+
static int __init gicv5_irs_of_init(struct device_node *node)
766
+
{
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+
struct gicv5_irs_chip_data *irs_data;
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+
void __iomem *irs_base;
769
+
u8 iaffid_bits;
770
+
u32 idr;
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+
int ret;
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+
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+
irs_data = kzalloc(sizeof(*irs_data), GFP_KERNEL);
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+
if (!irs_data)
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+
return -ENOMEM;
776
+
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+
raw_spin_lock_init(&irs_data->spi_config_lock);
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+
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+
ret = of_property_match_string(node, "reg-names", "ns-config");
780
+
if (ret < 0) {
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+
pr_err("%pOF: ns-config reg-name not present\n", node);
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+
goto out_err;
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+
}
784
+
785
+
irs_base = of_io_request_and_map(node, ret, of_node_full_name(node));
786
+
if (IS_ERR(irs_base)) {
787
+
pr_err("%pOF: unable to map GICv5 IRS registers\n", node);
788
+
ret = PTR_ERR(irs_base);
789
+
goto out_err;
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+
}
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+
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+
irs_data->fwnode = of_fwnode_handle(node);
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+
gicv5_irs_init_bases(irs_data, irs_base, of_property_read_bool(node, "dma-noncoherent"));
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+
795
+
idr = irs_readl_relaxed(irs_data, GICV5_IRS_IDR1);
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+
iaffid_bits = FIELD_GET(GICV5_IRS_IDR1_IAFFID_BITS, idr) + 1;
797
+
798
+
ret = gicv5_irs_of_init_affinity(node, irs_data, iaffid_bits);
799
+
if (ret) {
800
+
pr_err("Failed to parse CPU IAFFIDs from the device tree!\n");
801
+
goto out_iomem;
802
+
}
803
+
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+
ret = gicv5_irs_init(irs_data);
805
+
if (ret)
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+
goto out_iomem;
807
+
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+
if (irs_data->spi_range) {
809
+
pr_info("%s detected SPI range [%u-%u]\n",
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+
of_node_full_name(node),
811
+
irs_data->spi_min,
812
+
irs_data->spi_min +
813
+
irs_data->spi_range - 1);
814
+
}
815
+
816
+
return ret;
717
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out_iomem:
719
819
iounmap(irs_base);
···
826
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if (!of_device_is_compatible(np, "arm,gic-v5-irs"))
827
819
continue;
828
820
829
-
ret = gicv5_irs_init(np);
821
+
ret = gicv5_irs_of_init(np);
830
822
if (ret)
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pr_err("Failed to init IRS %s\n", np->full_name);
832
824
}