tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'pci-v7.0-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci

Pull pci fixes from Bjorn Helgaas:

- Update MAINTAINERS email address (Shawn Guo)

- Refresh cached Endpoint driver MSI Message Address to fix a v7.0
regression when kernel changes the address after firmware has
configured it (Niklas Cassel)

- Flush Endpoint MSI-X writes so they complete before the outbound ATU
entry is unmapped (Niklas Cassel)

- Correct the PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 value, which broke VMM use
of PCI capabilities (Bjorn Helgaas)

* tag 'pci-v7.0-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci:
PCI: Correct PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 value
PCI: dwc: ep: Flush MSI-X write before unmapping its ATU entry
PCI: dwc: ep: Refresh MSI Message Address cache on change
MAINTAINERS: Update Shawn Guo's address for HiSilicon PCIe controller driver

Linus Torvalds 1c63df24 aed968f8

+18 -11
+1 -1
MAINTAINERS
··· 20507 20507 F: drivers/pci/controller/dwc/pcie-kirin.c 20508 20508 20509 20509 PCIE DRIVER FOR HISILICON STB 20510 - M: Shawn Guo <shawn.guo@linaro.org> 20510 + M: Shawn Guo <shawnguo@kernel.org> 20511 20511 L: linux-pci@vger.kernel.org 20512 20512 S: Maintained 20513 20513 F: Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt
+16 -9
drivers/pci/controller/dwc/pcie-designware-ep.c
··· 905 905 * supported, so we avoid reprogramming the region on every MSI, 906 906 * specifically unmapping immediately after writel(). 907 907 */ 908 + if (ep->msi_iatu_mapped && (ep->msi_msg_addr != msg_addr || 909 + ep->msi_map_size != map_size)) { 910 + /* 911 + * The host changed the MSI target address or the required 912 + * mapping size changed. Reprogramming the iATU when there are 913 + * operations in flight is unsafe on this controller. However, 914 + * there is no unified way to check if we have operations in 915 + * flight, thus we don't know if we should WARN() or not. 916 + */ 917 + dw_pcie_ep_unmap_addr(epc, func_no, 0, ep->msi_mem_phys); 918 + ep->msi_iatu_mapped = false; 919 + } 920 + 908 921 if (!ep->msi_iatu_mapped) { 909 922 ret = dw_pcie_ep_map_addr(epc, func_no, 0, 910 923 ep->msi_mem_phys, msg_addr, ··· 928 915 ep->msi_iatu_mapped = true; 929 916 ep->msi_msg_addr = msg_addr; 930 917 ep->msi_map_size = map_size; 931 - } else if (WARN_ON_ONCE(ep->msi_msg_addr != msg_addr || 932 - ep->msi_map_size != map_size)) { 933 - /* 934 - * The host changed the MSI target address or the required 935 - * mapping size changed. Reprogramming the iATU at runtime is 936 - * unsafe on this controller, so bail out instead of trying to 937 - * update the existing region. 938 - */ 939 - return -EINVAL; 940 918 } 941 919 942 920 writel(msg_data | (interrupt_num - 1), ep->msi_mem + offset); ··· 1013 1009 return ret; 1014 1010 1015 1011 writel(msg_data, ep->msi_mem + offset); 1012 + 1013 + /* flush posted write before unmap */ 1014 + readl(ep->msi_mem + offset); 1016 1015 1017 1016 dw_pcie_ep_unmap_addr(epc, func_no, 0, ep->msi_mem_phys); 1018 1017
+1 -1
include/uapi/linux/pci_regs.h
··· 712 712 #define PCI_EXP_LNKCTL2_HASD 0x0020 /* HW Autonomous Speed Disable */ 713 713 #define PCI_EXP_LNKSTA2 0x32 /* Link Status 2 */ 714 714 #define PCI_EXP_LNKSTA2_FLIT 0x0400 /* Flit Mode Status */ 715 - #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 0x32 /* end of v2 EPs w/ link */ 715 + #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 0x34 /* end of v2 EPs w/ link */ 716 716 #define PCI_EXP_SLTCAP2 0x34 /* Slot Capabilities 2 */ 717 717 #define PCI_EXP_SLTCAP2_IBPD 0x00000001 /* In-band PD Disable Supported */ 718 718 #define PCI_EXP_SLTCTL2 0x38 /* Slot Control 2 */