Merge tag 'mips_6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

+10 -1

Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml

··· 18 18 These SoCs have an XTAL from where the cpu clock is 19 19 provided as well as derived clocks for the bus and the peripherals. 20 20 21 + Each clock is assigned an identifier and client nodes use this identifier 22 + to specify the clock which they consume. 23 + 24 + All these identifiers could be found in: 25 + [1]: <include/dt-bindings/clock/mediatek,mtmips-sysc.h>. 26 + 21 27 properties: 22 28 compatible: 23 29 items: ··· 44 38 45 39 '#clock-cells': 46 40 description: 47 - The first cell indicates the clock number. 41 + The first cell indicates the clock number, see [1] for available 42 + clocks. 48 43 const: 1 49 44 50 45 '#reset-cells': ··· 63 56 64 57 examples: 65 58 - | 59 + #include <dt-bindings/clock/mediatek,mtmips-sysc.h> 60 + 66 61 syscon@0 { 67 62 compatible = "ralink,rt5350-sysc", "syscon"; 68 63 reg = <0x0 0x100>;

+57

Documentation/devicetree/bindings/mips/mti,mips-cm.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/mips/mti,mips-cm.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: MIPS Coherence Manager 8 + 9 + description: 10 + The Coherence Manager (CM) is responsible for establishing the 11 + global ordering of requests from all elements of the system and 12 + sending the correct data back to the requester. It supports Cache 13 + to Cache transfers. 14 + https://training.mips.com/cps_mips/PDF/CPS_Introduction.pdf 15 + https://training.mips.com/cps_mips/PDF/Coherency_Manager.pdf 16 + 17 + maintainers: 18 + - Jiaxun Yang <jiaxun.yang@flygoat.com> 19 + 20 + properties: 21 + compatible: 22 + oneOf: 23 + - const: mti,mips-cm 24 + - const: mobileye,eyeq6-cm 25 + description: 26 + On EyeQ6 the HCI (Hardware Cache Initialization) information for 27 + the L2 cache in multi-cluster configuration is broken. 28 + 29 + reg: 30 + description: 31 + Base address and size of the Global Configuration Registers 32 + referred to as CMGCR.They are the system programmer's interface 33 + to the Coherency Manager. Their location in the memory map is 34 + determined at core build time. In a functional system, the base 35 + address is provided by the Coprocessor 0, but some 36 + System-on-Chip (SoC) designs may not provide an accurate address 37 + that needs to be described statically. 38 + 39 + maxItems: 1 40 + 41 + required: 42 + - compatible 43 + 44 + additionalProperties: false 45 + 46 + examples: 47 + - | 48 + coherency-manager@1fbf8000 { 49 + compatible = "mti,mips-cm"; 50 + reg = <0x1bde8000 0x8000>; 51 + }; 52 + 53 + - | 54 + coherency-manager { 55 + compatible = "mobileye,eyeq6-cm"; 56 + }; 57 + ...

+1 -1

arch/mips/boot/dts/ingenic/gcw0.dts

··· 91 91 "MIC1N", "Built-in Mic"; 92 92 simple-audio-card,pin-switches = "Speaker", "Headphones"; 93 93 94 - simple-audio-card,hp-det-gpio = <&gpf 21 GPIO_ACTIVE_LOW>; 94 + simple-audio-card,hp-det-gpios = <&gpf 21 GPIO_ACTIVE_LOW>; 95 95 simple-audio-card,aux-devs = <&speaker_amp>, <&headphones_amp>; 96 96 97 97 simple-audio-card,bitclock-master = <&dai_codec>;

+1 -1

arch/mips/boot/dts/ingenic/rs90.dts

··· 148 148 "Speaker", "OUTR"; 149 149 simple-audio-card,pin-switches = "Speaker"; 150 150 151 - simple-audio-card,hp-det-gpio = <&gpd 16 GPIO_ACTIVE_LOW>; 151 + simple-audio-card,hp-det-gpios = <&gpd 16 GPIO_ACTIVE_LOW>; 152 152 simple-audio-card,aux-devs = <&amp>; 153 153 154 154 simple-audio-card,bitclock-master = <&dai_codec>;

+4

arch/mips/boot/dts/mobileye/eyeq6h.dtsi

··· 32 32 #interrupt-cells = <1>; 33 33 }; 34 34 35 + coherency-manager { 36 + compatible = "mobileye,eyeq6-cm"; 37 + }; 38 + 35 39 xtal: clock-30000000 { 36 40 compatible = "fixed-clock"; 37 41 #clock-cells = <0>;

+1 -1

arch/mips/boot/dts/ralink/gardena_smart_gateway_mt7688.dts

··· 5 5 6 6 /dts-v1/; 7 7 8 - /include/ "mt7628a.dtsi" 8 + #include "mt7628a.dtsi" 9 9 10 10 #include <dt-bindings/gpio/gpio.h> 11 11 #include <dt-bindings/input/input.h>

+8 -2

arch/mips/boot/dts/ralink/mt7620a.dtsi

··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 + #include <dt-bindings/clock/mediatek,mtmips-sysc.h> 3 + 2 4 / { 3 5 #address-cells = <1>; 4 6 #size-cells = <1>; ··· 27 25 #address-cells = <1>; 28 26 #size-cells = <1>; 29 27 30 - sysc@0 { 31 - compatible = "ralink,mt7620a-sysc"; 28 + sysc: syscon@0 { 29 + compatible = "ralink,mt7620-sysc", "syscon"; 32 30 reg = <0x0 0x100>; 31 + #clock-cells = <1>; 32 + #reset-cells = <1>; 33 33 }; 34 34 35 35 intc: intc@200 { ··· 53 49 uartlite@c00 { 54 50 compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a"; 55 51 reg = <0xc00 0x100>; 52 + 53 + clocks = <&sysc MT7620_CLK_UARTLITE>; 56 54 57 55 interrupt-parent = <&intc>; 58 56 interrupts = <12>;

+1 -1

arch/mips/boot/dts/ralink/mt7620a_eval.dts

··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 2 /dts-v1/; 3 3 4 - /include/ "mt7620a.dtsi" 4 + #include "mt7620a.dtsi" 5 5 6 6 / { 7 7 compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc";

+25 -15

arch/mips/boot/dts/ralink/mt7628a.dtsi

··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 + #include <dt-bindings/clock/mediatek,mtmips-sysc.h> 2 3 3 4 / { 4 5 #address-cells = <1>; ··· 17 16 }; 18 17 }; 19 18 20 - resetc: reset-controller { 21 - compatible = "ralink,rt2880-reset"; 22 - #reset-cells = <1>; 23 - }; 24 - 25 19 cpuintc: interrupt-controller { 26 20 #address-cells = <0>; 27 21 #interrupt-cells = <1>; ··· 32 36 #address-cells = <1>; 33 37 #size-cells = <1>; 34 38 35 - sysc: system-controller@0 { 36 - compatible = "ralink,mt7620a-sysc", "syscon"; 39 + sysc: syscon@0 { 40 + compatible = "ralink,mt7628-sysc", "syscon"; 37 41 reg = <0x0 0x60>; 42 + #clock-cells = <1>; 43 + #reset-cells = <1>; 38 44 }; 39 45 40 46 pinmux: pinmux@60 { ··· 136 138 compatible = "mediatek,mt7621-wdt"; 137 139 reg = <0x100 0x30>; 138 140 139 - resets = <&resetc 8>; 141 + resets = <&sysc 8>; 140 142 reset-names = "wdt"; 141 143 142 144 interrupt-parent = <&intc>; ··· 152 154 interrupt-controller; 153 155 #interrupt-cells = <1>; 154 156 155 - resets = <&resetc 9>; 157 + resets = <&sysc 9>; 156 158 reset-names = "intc"; 157 159 158 160 interrupt-parent = <&cpuintc>; ··· 188 190 pinctrl-names = "default"; 189 191 pinctrl-0 = <&pinmux_spi_spi>; 190 192 191 - resets = <&resetc 18>; 193 + clocks = <&sysc MT76X8_CLK_SPI1>; 194 + 195 + resets = <&sysc 18>; 192 196 reset-names = "spi"; 193 197 194 198 #address-cells = <1>; ··· 206 206 pinctrl-names = "default"; 207 207 pinctrl-0 = <&pinmux_i2c_i2c>; 208 208 209 - resets = <&resetc 16>; 209 + clocks = <&sysc MT76X8_CLK_I2C>; 210 + 211 + resets = <&sysc 16>; 210 212 reset-names = "i2c"; 211 213 212 214 #address-cells = <1>; ··· 224 222 pinctrl-names = "default"; 225 223 pinctrl-0 = <&pinmux_uart0_uart>; 226 224 227 - resets = <&resetc 12>; 225 + clocks = <&sysc MT76X8_CLK_UART0>; 226 + 227 + resets = <&sysc 12>; 228 228 reset-names = "uart0"; 229 229 230 230 interrupt-parent = <&intc>; ··· 242 238 pinctrl-names = "default"; 243 239 pinctrl-0 = <&pinmux_uart1_uart>; 244 240 245 - resets = <&resetc 19>; 241 + clocks = <&sysc MT76X8_CLK_UART1>; 242 + 243 + resets = <&sysc 19>; 246 244 reset-names = "uart1"; 247 245 248 246 interrupt-parent = <&intc>; ··· 260 254 pinctrl-names = "default"; 261 255 pinctrl-0 = <&pinmux_uart2_uart>; 262 256 263 - resets = <&resetc 20>; 257 + clocks = <&sysc MT76X8_CLK_UART2>; 258 + 259 + resets = <&sysc 20>; 264 260 reset-names = "uart2"; 265 261 266 262 interrupt-parent = <&intc>; ··· 279 271 #phy-cells = <0>; 280 272 281 273 ralink,sysctl = <&sysc>; 282 - resets = <&resetc 22 &resetc 25>; 274 + resets = <&sysc 22 &sysc 25>; 283 275 reset-names = "host", "device"; 284 276 }; 285 277 ··· 297 289 wmac: wmac@10300000 { 298 290 compatible = "mediatek,mt7628-wmac"; 299 291 reg = <0x10300000 0x100000>; 292 + 293 + clocks = <&sysc MT76X8_CLK_WMAC>; 300 294 301 295 interrupt-parent = <&cpuintc>; 302 296 interrupts = <6>;

+1 -1

arch/mips/boot/dts/ralink/omega2p.dts

··· 1 1 /dts-v1/; 2 2 3 - /include/ "mt7628a.dtsi" 3 + #include "mt7628a.dtsi" 4 4 5 5 / { 6 6 compatible = "onion,omega2+", "ralink,mt7688a-soc", "ralink,mt7628a-soc";

+8 -2

arch/mips/boot/dts/ralink/rt2880.dtsi

··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 + #include <dt-bindings/clock/mediatek,mtmips-sysc.h> 3 + 2 4 / { 3 5 #address-cells = <1>; 4 6 #size-cells = <1>; ··· 27 25 #address-cells = <1>; 28 26 #size-cells = <1>; 29 27 30 - sysc@0 { 31 - compatible = "ralink,rt2880-sysc"; 28 + sysc: syscon@0 { 29 + compatible = "ralink,rt2880-sysc", "syscon"; 32 30 reg = <0x0 0x100>; 31 + #clock-cells = <1>; 32 + #reset-cells = <1>; 33 33 }; 34 34 35 35 intc: intc@200 { ··· 53 49 uartlite@c00 { 54 50 compatible = "ralink,rt2880-uart", "ns16550a"; 55 51 reg = <0xc00 0x100>; 52 + 53 + clocks = <&sysc RT2880_CLK_UARTLITE>; 56 54 57 55 interrupt-parent = <&intc>; 58 56 interrupts = <8>;

+1 -1

arch/mips/boot/dts/ralink/rt2880_eval.dts

··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 2 /dts-v1/; 3 3 4 - /include/ "rt2880.dtsi" 4 + #include "rt2880.dtsi" 5 5 6 6 / { 7 7 compatible = "ralink,rt2880-eval-board", "ralink,rt2880-soc";

+8 -2

arch/mips/boot/dts/ralink/rt3050.dtsi

··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 + #include <dt-bindings/clock/mediatek,mtmips-sysc.h> 3 + 2 4 / { 3 5 #address-cells = <1>; 4 6 #size-cells = <1>; ··· 27 25 #address-cells = <1>; 28 26 #size-cells = <1>; 29 27 30 - sysc@0 { 31 - compatible = "ralink,rt3052-sysc", "ralink,rt3050-sysc"; 28 + sysc: syscon@0 { 29 + compatible = "ralink,rt3052-sysc", "ralink,rt3050-sysc", "syscon"; 32 30 reg = <0x0 0x100>; 31 + #clock-cells = <1>; 32 + #reset-cells = <1>; 33 33 }; 34 34 35 35 intc: intc@200 { ··· 53 49 uartlite@c00 { 54 50 compatible = "ralink,rt3052-uart", "ralink,rt2880-uart", "ns16550a"; 55 51 reg = <0xc00 0x100>; 52 + 53 + clocks = <&sysc RT305X_CLK_UARTLITE>; 56 54 57 55 interrupt-parent = <&intc>; 58 56 interrupts = <12>;

+8 -2

arch/mips/boot/dts/ralink/rt3883.dtsi

··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 + #include <dt-bindings/clock/mediatek,mtmips-sysc.h> 3 + 2 4 / { 3 5 #address-cells = <1>; 4 6 #size-cells = <1>; ··· 27 25 #address-cells = <1>; 28 26 #size-cells = <1>; 29 27 30 - sysc@0 { 31 - compatible = "ralink,rt3883-sysc", "ralink,rt3050-sysc"; 28 + sysc: syscon@0 { 29 + compatible = "ralink,rt3883-sysc", "syscon"; 32 30 reg = <0x0 0x100>; 31 + #clock-cells = <1>; 32 + #reset-cells = <1>; 33 33 }; 34 34 35 35 intc: intc@200 { ··· 53 49 uartlite@c00 { 54 50 compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a"; 55 51 reg = <0xc00 0x100>; 52 + 53 + clocks = <&sysc RT3883_CLK_UARTLITE>; 56 54 57 55 interrupt-parent = <&intc>; 58 56 interrupts = <12>;

+1 -1

arch/mips/boot/dts/ralink/rt3883_eval.dts

··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 2 /dts-v1/; 3 3 4 - /include/ "rt3883.dtsi" 4 + #include "rt3883.dtsi" 5 5 6 6 / { 7 7 compatible = "ralink,rt3883-eval-board", "ralink,rt3883-soc";

+9 -1

arch/mips/boot/dts/realtek/cisco_sg220-26.dts

··· 2 2 3 3 /dts-v1/; 4 4 5 - #include "rtl83xx.dtsi" 6 5 #include "rtl838x.dtsi" 6 + 7 + #include <dt-bindings/gpio/gpio.h> 7 8 8 9 / { 9 10 model = "Cisco SG220-26"; ··· 18 17 memory@0 { 19 18 device_type = "memory"; 20 19 reg = <0x0 0x8000000>; 20 + }; 21 + 22 + gpio-restart { 23 + compatible = "gpio-restart"; 24 + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; 25 + priority = <192>; 26 + open-source; 21 27 }; 22 28 }; 23 29

+109 -2

arch/mips/boot/dts/realtek/rtl838x.dtsi

··· 1 1 // SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause 2 2 3 3 / { 4 + #address-cells = <1>; 5 + #size-cells = <1>; 6 + 7 + aliases { 8 + serial0 = &uart0; 9 + serial1 = &uart1; 10 + }; 11 + 4 12 cpus { 5 13 #address-cells = <1>; 6 14 #size-cells = <0>; ··· 17 9 device_type = "cpu"; 18 10 compatible = "mips,mips4KEc"; 19 11 reg = <0>; 20 - clocks = <&baseclk 0>; 21 - clock-names = "cpu"; 12 + clocks = <&baseclk>; 22 13 }; 23 14 }; 24 15 ··· 25 18 compatible = "fixed-clock"; 26 19 #clock-cells = <0>; 27 20 clock-frequency = <500000000>; 21 + }; 22 + 23 + cpuintc: cpuintc { 24 + compatible = "mti,cpu-interrupt-controller"; 25 + #address-cells = <0>; 26 + #interrupt-cells = <1>; 27 + interrupt-controller; 28 + }; 29 + 30 + lx_clk: clock-lexra { 31 + compatible = "fixed-clock"; 32 + #clock-cells = <0>; 33 + clock-frequency = <200000000>; 34 + }; 35 + 36 + soc@18000000 { 37 + compatible = "simple-bus"; 38 + #address-cells = <1>; 39 + #size-cells = <1>; 40 + ranges = <0x0 0x18000000 0x10000>; 41 + 42 + spi0: spi@1200 { 43 + compatible = "realtek,rtl8380-spi"; 44 + reg = <0x1200 0x100>; 45 + 46 + #address-cells = <1>; 47 + #size-cells = <0>; 48 + }; 49 + 50 + uart0: serial@2000 { 51 + compatible = "ns16550a"; 52 + reg = <0x2000 0x100>; 53 + 54 + clocks = <&lx_clk>; 55 + 56 + interrupt-parent = <&intc>; 57 + interrupts = <31>; 58 + 59 + reg-io-width = <1>; 60 + reg-shift = <2>; 61 + fifo-size = <1>; 62 + no-loopback-test; 63 + 64 + status = "disabled"; 65 + }; 66 + 67 + uart1: serial@2100 { 68 + compatible = "ns16550a"; 69 + reg = <0x2100 0x100>; 70 + 71 + clocks = <&lx_clk>; 72 + 73 + interrupt-parent = <&intc>; 74 + interrupts = <30>; 75 + 76 + reg-io-width = <1>; 77 + reg-shift = <2>; 78 + fifo-size = <1>; 79 + no-loopback-test; 80 + 81 + status = "disabled"; 82 + }; 83 + 84 + intc: interrupt-controller@3000 { 85 + compatible = "realtek,rtl8380-intc", "realtek,rtl-intc"; 86 + reg = <0x3000 0x20>; 87 + interrupt-controller; 88 + #interrupt-cells = <1>; 89 + 90 + interrupt-parent = <&cpuintc>; 91 + interrupts = <2>, <3>, <4>, <5>, <6>; 92 + }; 93 + 94 + watchdog: watchdog@3150 { 95 + compatible = "realtek,rtl8380-wdt"; 96 + reg = <0x3150 0xc>; 97 + 98 + realtek,reset-mode = "soc"; 99 + 100 + clocks = <&lx_clk>; 101 + timeout-sec = <20>; 102 + 103 + interrupt-parent = <&intc>; 104 + interrupt-names = "phase1", "phase2"; 105 + interrupts = <19>, <18>; 106 + }; 107 + 108 + gpio0: gpio@3500 { 109 + compatible = "realtek,rtl8380-gpio", "realtek,otto-gpio"; 110 + reg = <0x3500 0x1c>; 111 + 112 + gpio-controller; 113 + #gpio-cells = <2>; 114 + ngpios = <24>; 115 + 116 + interrupt-controller; 117 + #interrupt-cells = <2>; 118 + interrupt-parent = <&intc>; 119 + interrupts = <23>; 120 + }; 28 121 }; 29 122 };

-59

arch/mips/boot/dts/realtek/rtl83xx.dtsi

··· 1 - // SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause 2 - 3 - / { 4 - #address-cells = <1>; 5 - #size-cells = <1>; 6 - 7 - aliases { 8 - serial0 = &uart0; 9 - serial1 = &uart1; 10 - }; 11 - 12 - cpuintc: cpuintc { 13 - compatible = "mti,cpu-interrupt-controller"; 14 - #address-cells = <0>; 15 - #interrupt-cells = <1>; 16 - interrupt-controller; 17 - }; 18 - 19 - soc: soc { 20 - compatible = "simple-bus"; 21 - #address-cells = <1>; 22 - #size-cells = <1>; 23 - ranges = <0x0 0x18000000 0x10000>; 24 - 25 - uart0: serial@2000 { 26 - compatible = "ns16550a"; 27 - reg = <0x2000 0x100>; 28 - 29 - clock-frequency = <200000000>; 30 - 31 - interrupt-parent = <&cpuintc>; 32 - interrupts = <31>; 33 - 34 - reg-io-width = <1>; 35 - reg-shift = <2>; 36 - fifo-size = <1>; 37 - no-loopback-test; 38 - 39 - status = "disabled"; 40 - }; 41 - 42 - uart1: serial@2100 { 43 - compatible = "ns16550a"; 44 - reg = <0x2100 0x100>; 45 - 46 - clock-frequency = <200000000>; 47 - 48 - interrupt-parent = <&cpuintc>; 49 - interrupts = <30>; 50 - 51 - reg-io-width = <1>; 52 - reg-shift = <2>; 53 - fifo-size = <1>; 54 - no-loopback-test; 55 - 56 - status = "disabled"; 57 - }; 58 - }; 59 - };

+90 -58

arch/mips/boot/dts/realtek/rtl930x.dtsi

··· 1 1 // SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause 2 2 3 - #include "rtl83xx.dtsi" 4 - 5 3 / { 6 4 compatible = "realtek,rtl9302-soc"; 5 + 6 + #address-cells = <1>; 7 + #size-cells = <1>; 8 + 9 + aliases { 10 + serial0 = &uart0; 11 + serial1 = &uart1; 12 + }; 13 + 14 + cpuintc: cpuintc { 15 + compatible = "mti,cpu-interrupt-controller"; 16 + #address-cells = <0>; 17 + #interrupt-cells = <1>; 18 + interrupt-controller; 19 + }; 7 20 8 21 cpus { 9 22 #address-cells = <1>; ··· 26 13 device_type = "cpu"; 27 14 compatible = "mips,mips34Kc"; 28 15 reg = <0>; 29 - clocks = <&baseclk 0>; 30 - clock-names = "cpu"; 16 + clocks = <&baseclk>; 31 17 }; 32 18 }; 33 19 ··· 70 58 status = "disabled"; 71 59 }; 72 60 }; 73 - }; 74 61 75 - &soc { 76 - ranges = <0x0 0x18000000 0x20000>; 77 - 78 - intc: interrupt-controller@3000 { 79 - compatible = "realtek,rtl9300-intc", "realtek,rtl-intc"; 80 - reg = <0x3000 0x18>, <0x3018 0x18>; 81 - interrupt-controller; 82 - #interrupt-cells = <1>; 83 - 84 - interrupt-parent = <&cpuintc>; 85 - interrupts = <2>, <3>, <4>, <5>, <6>, <7>; 86 - }; 87 - 88 - spi0: spi@1200 { 89 - compatible = "realtek,rtl8380-spi"; 90 - reg = <0x1200 0x100>; 91 - 62 + soc: soc@18000000 { 63 + compatible = "simple-bus"; 92 64 #address-cells = <1>; 93 - #size-cells = <0>; 94 - }; 65 + #size-cells = <1>; 66 + ranges = <0x0 0x18000000 0x20000>; 95 67 96 - timer0: timer@3200 { 97 - compatible = "realtek,rtl9302-timer", "realtek,otto-timer"; 98 - reg = <0x3200 0x10>, <0x3210 0x10>, <0x3220 0x10>, 99 - <0x3230 0x10>, <0x3240 0x10>; 68 + intc: interrupt-controller@3000 { 69 + compatible = "realtek,rtl9300-intc", "realtek,rtl-intc"; 70 + reg = <0x3000 0x18>, <0x3018 0x18>; 71 + interrupt-controller; 72 + #interrupt-cells = <1>; 100 73 101 - interrupt-parent = <&intc>; 102 - interrupts = <7>, <8>, <9>, <10>, <11>; 103 - clocks = <&lx_clk>; 104 - }; 74 + interrupt-parent = <&cpuintc>; 75 + interrupts = <2>, <3>, <4>, <5>, <6>, <7>; 76 + }; 105 77 106 - snand: spi@1a400 { 107 - compatible = "realtek,rtl9301-snand"; 108 - reg = <0x1a400 0x44>; 109 - interrupt-parent = <&intc>; 110 - interrupts = <19>; 111 - clocks = <&lx_clk>; 112 - #address-cells = <1>; 113 - #size-cells = <0>; 114 - status = "disabled"; 78 + spi0: spi@1200 { 79 + compatible = "realtek,rtl8380-spi"; 80 + reg = <0x1200 0x100>; 81 + 82 + #address-cells = <1>; 83 + #size-cells = <0>; 84 + }; 85 + 86 + timer0: timer@3200 { 87 + compatible = "realtek,rtl9302-timer", "realtek,otto-timer"; 88 + reg = <0x3200 0x10>, <0x3210 0x10>, <0x3220 0x10>, 89 + <0x3230 0x10>, <0x3240 0x10>; 90 + 91 + interrupt-parent = <&intc>; 92 + interrupts = <7>, <8>, <9>, <10>, <11>; 93 + clocks = <&lx_clk>; 94 + }; 95 + 96 + snand: spi@1a400 { 97 + compatible = "realtek,rtl9301-snand"; 98 + reg = <0x1a400 0x44>; 99 + interrupt-parent = <&intc>; 100 + interrupts = <19>; 101 + clocks = <&lx_clk>; 102 + #address-cells = <1>; 103 + #size-cells = <0>; 104 + status = "disabled"; 105 + }; 106 + 107 + uart0: serial@2000 { 108 + compatible = "ns16550a"; 109 + reg = <0x2000 0x100>; 110 + 111 + clocks = <&lx_clk>; 112 + 113 + interrupt-parent = <&intc>; 114 + interrupts = <30>; 115 + 116 + reg-io-width = <1>; 117 + reg-shift = <2>; 118 + fifo-size = <1>; 119 + no-loopback-test; 120 + 121 + status = "disabled"; 122 + }; 123 + 124 + uart1: serial@2100 { 125 + compatible = "ns16550a"; 126 + reg = <0x2100 0x100>; 127 + 128 + clocks = <&lx_clk>; 129 + 130 + interrupt-parent = <&intc>; 131 + interrupts = <31>; 132 + 133 + reg-io-width = <1>; 134 + reg-shift = <2>; 135 + fifo-size = <1>; 136 + no-loopback-test; 137 + 138 + status = "disabled"; 139 + }; 115 140 }; 116 141 }; 117 - 118 - &uart0 { 119 - /delete-property/ clock-frequency; 120 - clocks = <&lx_clk>; 121 - 122 - interrupt-parent = <&intc>; 123 - interrupts = <30>; 124 - }; 125 - 126 - &uart1 { 127 - /delete-property/ clock-frequency; 128 - clocks = <&lx_clk>; 129 - 130 - interrupt-parent = <&intc>; 131 - interrupts = <31>; 132 - }; 133 -

-1

arch/mips/configs/gpr_defconfig

··· 116 116 CONFIG_NET_SCH_NETEM=m 117 117 CONFIG_NET_SCH_INGRESS=m 118 118 CONFIG_NET_CLS_BASIC=m 119 - CONFIG_NET_CLS_TCINDEX=m 120 119 CONFIG_NET_CLS_ROUTE4=m 121 120 CONFIG_NET_CLS_FW=m 122 121 CONFIG_NET_CLS_U32=m

-1

arch/mips/configs/ip22_defconfig

··· 161 161 CONFIG_NET_SCH_NETEM=m 162 162 CONFIG_NET_SCH_INGRESS=m 163 163 CONFIG_NET_CLS_BASIC=m 164 - CONFIG_NET_CLS_TCINDEX=m 165 164 CONFIG_NET_CLS_ROUTE4=m 166 165 CONFIG_NET_CLS_FW=m 167 166 CONFIG_NET_CLS_U32=m

-1

arch/mips/configs/ip27_defconfig

··· 63 63 CONFIG_NET_SCH_NETEM=m 64 64 CONFIG_NET_SCH_INGRESS=m 65 65 CONFIG_NET_CLS_BASIC=m 66 - CONFIG_NET_CLS_TCINDEX=m 67 66 CONFIG_NET_CLS_ROUTE4=m 68 67 CONFIG_NET_CLS_FW=m 69 68 CONFIG_NET_CLS_U32=m

-1

arch/mips/configs/malta_defconfig

··· 190 190 CONFIG_NET_SCH_NETEM=m 191 191 CONFIG_NET_SCH_INGRESS=m 192 192 CONFIG_NET_CLS_BASIC=m 193 - CONFIG_NET_CLS_TCINDEX=m 194 193 CONFIG_NET_CLS_ROUTE4=m 195 194 CONFIG_NET_CLS_FW=m 196 195 CONFIG_NET_CLS_U32=m

-1

arch/mips/configs/malta_kvm_defconfig

··· 194 194 CONFIG_NET_SCH_NETEM=m 195 195 CONFIG_NET_SCH_INGRESS=m 196 196 CONFIG_NET_CLS_BASIC=m 197 - CONFIG_NET_CLS_TCINDEX=m 198 197 CONFIG_NET_CLS_ROUTE4=m 199 198 CONFIG_NET_CLS_FW=m 200 199 CONFIG_NET_CLS_U32=m

-1

arch/mips/configs/malta_qemu_32r6_defconfig

··· 64 64 CONFIG_NET_SCH_NETEM=m 65 65 CONFIG_NET_SCH_INGRESS=m 66 66 CONFIG_NET_CLS_BASIC=m 67 - CONFIG_NET_CLS_TCINDEX=m 68 67 CONFIG_NET_CLS_ROUTE4=m 69 68 CONFIG_NET_CLS_FW=m 70 69 CONFIG_NET_CLS_U32=m

-1

arch/mips/configs/maltaaprp_defconfig

··· 66 66 CONFIG_NET_SCH_NETEM=m 67 67 CONFIG_NET_SCH_INGRESS=m 68 68 CONFIG_NET_CLS_BASIC=m 69 - CONFIG_NET_CLS_TCINDEX=m 70 69 CONFIG_NET_CLS_ROUTE4=m 71 70 CONFIG_NET_CLS_FW=m 72 71 CONFIG_NET_CLS_U32=m

-1

arch/mips/configs/maltasmvp_defconfig

··· 67 67 CONFIG_NET_SCH_NETEM=m 68 68 CONFIG_NET_SCH_INGRESS=m 69 69 CONFIG_NET_CLS_BASIC=m 70 - CONFIG_NET_CLS_TCINDEX=m 71 70 CONFIG_NET_CLS_ROUTE4=m 72 71 CONFIG_NET_CLS_FW=m 73 72 CONFIG_NET_CLS_U32=m

-1

arch/mips/configs/maltasmvp_eva_defconfig

··· 68 68 CONFIG_NET_SCH_NETEM=m 69 69 CONFIG_NET_SCH_INGRESS=m 70 70 CONFIG_NET_CLS_BASIC=m 71 - CONFIG_NET_CLS_TCINDEX=m 72 71 CONFIG_NET_CLS_ROUTE4=m 73 72 CONFIG_NET_CLS_FW=m 74 73 CONFIG_NET_CLS_U32=m

-1

arch/mips/configs/maltaup_defconfig

··· 65 65 CONFIG_NET_SCH_NETEM=m 66 66 CONFIG_NET_SCH_INGRESS=m 67 67 CONFIG_NET_CLS_BASIC=m 68 - CONFIG_NET_CLS_TCINDEX=m 69 68 CONFIG_NET_CLS_ROUTE4=m 70 69 CONFIG_NET_CLS_FW=m 71 70 CONFIG_NET_CLS_U32=m

-1

arch/mips/configs/maltaup_xpa_defconfig

··· 191 191 CONFIG_NET_SCH_NETEM=m 192 192 CONFIG_NET_SCH_INGRESS=m 193 193 CONFIG_NET_CLS_BASIC=m 194 - CONFIG_NET_CLS_TCINDEX=m 195 194 CONFIG_NET_CLS_ROUTE4=m 196 195 CONFIG_NET_CLS_FW=m 197 196 CONFIG_NET_CLS_U32=m

-1

arch/mips/configs/mtx1_defconfig

··· 162 162 CONFIG_NET_SCH_NETEM=m 163 163 CONFIG_NET_SCH_INGRESS=m 164 164 CONFIG_NET_CLS_BASIC=m 165 - CONFIG_NET_CLS_TCINDEX=m 166 165 CONFIG_NET_CLS_ROUTE4=m 167 166 CONFIG_NET_CLS_FW=m 168 167 CONFIG_NET_CLS_U32=m

+1

arch/mips/configs/omega2p_defconfig

··· 61 61 CONFIG_USB_EHCI_HCD=y 62 62 CONFIG_USB_EHCI_HCD_PLATFORM=y 63 63 CONFIG_MMC=y 64 + CONFIG_CLK_MTMIPS=y 64 65 # CONFIG_IOMMU_SUPPORT is not set 65 66 CONFIG_MEMORY=y 66 67 CONFIG_PHY_RALINK_USB=y

-1

arch/mips/configs/rb532_defconfig

··· 77 77 CONFIG_NET_SCH_PRIO=m 78 78 CONFIG_NET_SCH_NETEM=m 79 79 CONFIG_NET_CLS_BASIC=m 80 - CONFIG_NET_CLS_TCINDEX=m 81 80 CONFIG_NET_CLS_ROUTE4=m 82 81 CONFIG_NET_CLS_FW=m 83 82 CONFIG_NET_CLS_U32=m

-1

arch/mips/configs/rm200_defconfig

··· 143 143 CONFIG_NET_SCH_DSMARK=m 144 144 CONFIG_NET_SCH_NETEM=m 145 145 CONFIG_NET_CLS_BASIC=m 146 - CONFIG_NET_CLS_TCINDEX=m 147 146 CONFIG_NET_CLS_ROUTE4=m 148 147 CONFIG_NET_CLS_FW=m 149 148 CONFIG_NET_CLS_U32=m

+1

arch/mips/configs/vocore2_defconfig

··· 61 61 CONFIG_USB_EHCI_HCD=y 62 62 CONFIG_USB_EHCI_HCD_PLATFORM=y 63 63 CONFIG_MMC=y 64 + CONFIG_CLK_MTMIPS=y 64 65 # CONFIG_IOMMU_SUPPORT is not set 65 66 CONFIG_MEMORY=y 66 67 CONFIG_PHY_RALINK_USB=y

+1 -1

arch/mips/dec/prom/init.c

··· 42 42 * Detect which PROM the DECSTATION has, and set the callback vectors 43 43 * appropriately. 44 44 */ 45 - void __init which_prom(s32 magic, s32 *prom_vec) 45 + static void __init which_prom(s32 magic, s32 *prom_vec) 46 46 { 47 47 /* 48 48 * No sign of the REX PROM's magic number means we assume a non-REX

+1 -1

arch/mips/include/asm/ds1287.h

··· 8 8 #define __ASM_DS1287_H 9 9 10 10 extern int ds1287_timer_state(void); 11 - extern void ds1287_set_base_clock(unsigned int clock); 11 + extern int ds1287_set_base_clock(unsigned int hz); 12 12 extern int ds1287_clockevent_init(int irq); 13 13 14 14 #endif

+16

arch/mips/include/asm/ftrace.h

··· 91 91 92 92 #endif /* __ASSEMBLY__ */ 93 93 #endif /* CONFIG_FUNCTION_TRACER */ 94 + 95 + #ifdef CONFIG_FTRACE_SYSCALLS 96 + #ifndef __ASSEMBLY__ 97 + /* 98 + * Some syscall entry functions on mips start with "__sys_" (fork and clone, 99 + * for instance). We should also match the sys_ variant with those. 100 + */ 101 + #define ARCH_HAS_SYSCALL_MATCH_SYM_NAME 102 + static inline bool arch_syscall_match_sym_name(const char *sym, 103 + const char *name) 104 + { 105 + return !strcmp(sym, name) || 106 + (!strncmp(sym, "__sys_", 6) && !strcmp(sym + 6, name + 4)); 107 + } 108 + #endif /* __ASSEMBLY__ */ 109 + #endif /* CONFIG_FTRACE_SYSCALLS */ 94 110 #endif /* _ASM_MIPS_FTRACE_H */

+1 -1

arch/mips/include/asm/mach-rc32434/pci.h

··· 167 167 #define PCI_CFGA_DEV 0x0000f800 168 168 #define PCI_CFGA_DEV_INTERN 0 169 169 #define PCI_CFGA_BUS_BIT 16 170 - #define PCI CFGA_BUS 0x00ff0000 170 + #define PCI_CFGA_BUS 0x00ff0000 171 171 #define PCI_CFGA_BUS_TYPE0 0 172 172 #define PCI_CFGA_EN (1 << 31) 173 173

+40

arch/mips/include/asm/mips-cm.h

··· 59 59 */ 60 60 extern int mips_cm_is64; 61 61 62 + /* 63 + * mips_cm_is_l2_hci_broken - determine if HCI is broken 64 + * 65 + * Some CM reports show that Hardware Cache Initialization is 66 + * complete, but in reality it's not the case. They also incorrectly 67 + * indicate that Hardware Cache Initialization is supported. This 68 + * flags allows warning about this broken feature. 69 + */ 70 + extern bool mips_cm_is_l2_hci_broken; 71 + 62 72 /** 63 73 * mips_cm_error_report - Report CM cache errors 64 74 */ ··· 106 96 return false; 107 97 #endif 108 98 } 99 + 100 + /** 101 + * mips_cm_update_property - update property from the device tree 102 + * 103 + * Retrieve the properties from the device tree if a CM node exist and 104 + * update the internal variable based on this. 105 + */ 106 + #ifdef CONFIG_MIPS_CM 107 + extern void mips_cm_update_property(void); 108 + #else 109 + static inline void mips_cm_update_property(void) {} 110 + #endif 109 111 110 112 /** 111 113 * mips_cm_has_l2sync - determine whether an L2-only sync region is present ··· 277 255 GCR_ACCESSOR_RO(32, 0x150, sys_config2) 278 256 #define CM_GCR_SYS_CONFIG2_MAXVPW GENMASK(3, 0) 279 257 258 + /* GCR_L2-RAM_CONFIG - Configuration & status of L2 cache RAMs */ 259 + GCR_ACCESSOR_RW(64, 0x240, l2_ram_config) 260 + #define CM_GCR_L2_RAM_CONFIG_PRESENT BIT(31) 261 + #define CM_GCR_L2_RAM_CONFIG_HCI_DONE BIT(30) 262 + #define CM_GCR_L2_RAM_CONFIG_HCI_SUPPORTED BIT(29) 263 + 280 264 /* GCR_L2_PFT_CONTROL - Controls hardware L2 prefetching */ 281 265 GCR_ACCESSOR_RW(32, 0x300, l2_pft_control) 282 266 #define CM_GCR_L2_PFT_CONTROL_PAGEMASK GENMASK(31, 12) ··· 293 265 GCR_ACCESSOR_RW(32, 0x308, l2_pft_control_b) 294 266 #define CM_GCR_L2_PFT_CONTROL_B_CEN BIT(8) 295 267 #define CM_GCR_L2_PFT_CONTROL_B_PORTID GENMASK(7, 0) 268 + 269 + /* GCR_L2_TAG_ADDR - Access addresses in L2 cache tags */ 270 + GCR_ACCESSOR_RW(64, 0x600, l2_tag_addr) 271 + 272 + /* GCR_L2_TAG_STATE - Access L2 cache tag state */ 273 + GCR_ACCESSOR_RW(64, 0x608, l2_tag_state) 274 + 275 + /* GCR_L2_DATA - Access data in L2 cache lines */ 276 + GCR_ACCESSOR_RW(64, 0x610, l2_data) 277 + 278 + /* GCR_L2_ECC - Access ECC information from L2 cache lines */ 279 + GCR_ACCESSOR_RW(64, 0x618, l2_ecc) 296 280 297 281 /* GCR_L2SM_COP - L2 cache op state machine control */ 298 282 GCR_ACCESSOR_RW(32, 0x620, l2sm_cop)

+6 -1

arch/mips/include/asm/smp-cps.h

··· 22 22 struct vpe_boot_config *vpe_config; 23 23 }; 24 24 25 - extern struct core_boot_config *mips_cps_core_bootcfg; 25 + struct cluster_boot_config { 26 + unsigned long *core_power; 27 + struct core_boot_config *core_config; 28 + }; 29 + 30 + extern struct cluster_boot_config *mips_cps_cluster_bootcfg; 26 31 27 32 extern void mips_cps_core_boot(int cca, void __iomem *gcr_base); 28 33 extern void mips_cps_core_init(void);

+3

arch/mips/kernel/asm-offsets.c

··· 410 410 { 411 411 COMMENT(" MIPS CPS offsets. "); 412 412 413 + OFFSET(CLUSTERBOOTCFG_CORECONFIG, cluster_boot_config, core_config); 414 + DEFINE(CLUSTERBOOTCFG_SIZE, sizeof(struct cluster_boot_config)); 415 + 413 416 OFFSET(COREBOOTCFG_VPEMASK, core_boot_config, vpe_mask); 414 417 OFFSET(COREBOOTCFG_VPECONFIG, core_boot_config, vpe_config); 415 418 DEFINE(COREBOOTCFG_SIZE, sizeof(struct core_boot_config));

+1

arch/mips/kernel/cevt-ds1287.c

··· 10 10 #include <linux/mc146818rtc.h> 11 11 #include <linux/irq.h> 12 12 13 + #include <asm/ds1287.h> 13 14 #include <asm/time.h> 14 15 15 16 int ds1287_timer_state(void)

+16 -3

arch/mips/kernel/cps-vec.S

··· 19 19 #define GCR_CPC_BASE_OFS 0x0088 20 20 #define GCR_CL_COHERENCE_OFS 0x2008 21 21 #define GCR_CL_ID_OFS 0x2028 22 + #define CM3_GCR_Cx_ID_CLUSTER_SHF 8 23 + #define CM3_GCR_Cx_ID_CLUSTER_MSK (0xff << 8) 24 + #define CM3_GCR_Cx_ID_CORENUM_SHF 0 25 + #define CM3_GCR_Cx_ID_CORENUM_MSK (0xff << 0) 22 26 23 27 #define CPC_CL_VC_STOP_OFS 0x2020 24 28 #define CPC_CL_VC_RUN_OFS 0x2028 ··· 275 271 */ 276 272 LEAF(mips_cps_get_bootcfg) 277 273 /* Calculate a pointer to this cores struct core_boot_config */ 274 + PTR_LA v0, mips_cps_cluster_bootcfg 275 + PTR_L v0, 0(v0) 278 276 lw t0, GCR_CL_ID_OFS(s1) 277 + #ifdef CONFIG_CPU_MIPSR6 278 + ext t1, t0, CM3_GCR_Cx_ID_CLUSTER_SHF, 8 279 + li t2, CLUSTERBOOTCFG_SIZE 280 + mul t1, t1, t2 281 + PTR_ADDU \ 282 + v0, v0, t1 283 + #endif 284 + PTR_L v0, CLUSTERBOOTCFG_CORECONFIG(v0) 285 + andi t0, t0, CM3_GCR_Cx_ID_CORENUM_MSK 279 286 li t1, COREBOOTCFG_SIZE 280 287 mul t0, t0, t1 281 - PTR_LA t1, mips_cps_core_bootcfg 282 - PTR_L t1, 0(t1) 283 - PTR_ADDU v0, t0, t1 288 + PTR_ADDU v0, v0, t0 284 289 285 290 /* Calculate this VPEs ID. If the core doesn't support MT use 0 */ 286 291 li t9, 0

+17 -1

arch/mips/kernel/mips-cm.c

··· 5 5 */ 6 6 7 7 #include <linux/errno.h> 8 + #include <linux/of.h> 8 9 #include <linux/percpu.h> 9 10 #include <linux/spinlock.h> 10 11 ··· 15 14 void __iomem *mips_gcr_base; 16 15 void __iomem *mips_cm_l2sync_base; 17 16 int mips_cm_is64; 17 + bool mips_cm_is_l2_hci_broken; 18 18 19 19 static char *cm2_tr[8] = { 20 20 "mem", "gcr", "gic", "mmio", ··· 239 237 mips_cm_l2sync_base = ioremap(addr, MIPS_CM_L2SYNC_SIZE); 240 238 } 241 239 240 + void mips_cm_update_property(void) 241 + { 242 + struct device_node *cm_node; 243 + 244 + cm_node = of_find_compatible_node(of_root, NULL, "mobileye,eyeq6-cm"); 245 + if (!cm_node) 246 + return; 247 + pr_info("HCI (Hardware Cache Init for the L2 cache) in GCR_L2_RAM_CONFIG from the CM3 is broken"); 248 + mips_cm_is_l2_hci_broken = true; 249 + of_node_put(cm_node); 250 + } 251 + 242 252 int mips_cm_probe(void) 243 253 { 244 254 phys_addr_t addr; ··· 322 308 FIELD_PREP(CM3_GCR_Cx_OTHER_VP, vp); 323 309 324 310 if (cm_rev >= CM_REV_CM3_5) { 325 - val |= CM_GCR_Cx_OTHER_CLUSTER_EN; 311 + if (cluster != cpu_cluster(&current_cpu_data)) 312 + val |= CM_GCR_Cx_OTHER_CLUSTER_EN; 313 + val |= CM_GCR_Cx_OTHER_GIC_EN; 326 314 val |= FIELD_PREP(CM_GCR_Cx_OTHER_CLUSTER, cluster); 327 315 val |= FIELD_PREP(CM_GCR_Cx_OTHER_BLOCK, block); 328 316 } else {

+21 -14

arch/mips/kernel/pm-cps.c

··· 57 57 /* Indicates online CPUs coupled with the current CPU */ 58 58 static DEFINE_PER_CPU_ALIGNED(cpumask_t, online_coupled); 59 59 60 - /* 61 - * Used to synchronize entry to deep idle states. Actually per-core rather 62 - * than per-CPU. 63 - */ 60 + /* Used to synchronize entry to deep idle states */ 64 61 static DEFINE_PER_CPU_ALIGNED(atomic_t, pm_barrier); 65 62 66 63 /* Saved CPU state across the CPS_PM_POWER_GATED state */ ··· 101 104 int cps_pm_enter_state(enum cps_pm_state state) 102 105 { 103 106 unsigned cpu = smp_processor_id(); 107 + unsigned int cluster = cpu_cluster(&current_cpu_data); 104 108 unsigned core = cpu_core(&current_cpu_data); 105 109 unsigned online, left; 106 110 cpumask_t *coupled_mask = this_cpu_ptr(&online_coupled); 107 111 u32 *core_ready_count, *nc_core_ready_count; 108 112 void *nc_addr; 109 113 cps_nc_entry_fn entry; 114 + struct cluster_boot_config *cluster_cfg; 110 115 struct core_boot_config *core_cfg; 111 116 struct vpe_boot_config *vpe_cfg; 117 + atomic_t *barrier; 112 118 113 119 /* Check that there is an entry function for this state */ 114 - entry = per_cpu(nc_asm_enter, core)[state]; 120 + entry = per_cpu(nc_asm_enter, cpu)[state]; 115 121 if (!entry) 116 122 return -EINVAL; 117 123 ··· 138 138 if (!mips_cps_smp_in_use()) 139 139 return -EINVAL; 140 140 141 - core_cfg = &mips_cps_core_bootcfg[core]; 141 + cluster_cfg = &mips_cps_cluster_bootcfg[cluster]; 142 + core_cfg = &cluster_cfg->core_config[core]; 142 143 vpe_cfg = &core_cfg->vpe_config[cpu_vpe_id(&current_cpu_data)]; 143 144 vpe_cfg->pc = (unsigned long)mips_cps_pm_restore; 144 145 vpe_cfg->gp = (unsigned long)current_thread_info(); ··· 151 150 smp_mb__after_atomic(); 152 151 153 152 /* Create a non-coherent mapping of the core ready_count */ 154 - core_ready_count = per_cpu(ready_count, core); 153 + core_ready_count = per_cpu(ready_count, cpu); 155 154 nc_addr = kmap_noncoherent(virt_to_page(core_ready_count), 156 155 (unsigned long)core_ready_count); 157 156 nc_addr += ((unsigned long)core_ready_count & ~PAGE_MASK); ··· 159 158 160 159 /* Ensure ready_count is zero-initialised before the assembly runs */ 161 160 WRITE_ONCE(*nc_core_ready_count, 0); 162 - coupled_barrier(&per_cpu(pm_barrier, core), online); 161 + barrier = &per_cpu(pm_barrier, cpumask_first(&cpu_sibling_map[cpu])); 162 + coupled_barrier(barrier, online); 163 163 164 164 /* Run the generated entry code */ 165 165 left = entry(online, nc_core_ready_count); ··· 631 629 632 630 static int cps_pm_online_cpu(unsigned int cpu) 633 631 { 634 - enum cps_pm_state state; 635 - unsigned core = cpu_core(&cpu_data[cpu]); 632 + unsigned int sibling, core; 636 633 void *entry_fn, *core_rc; 634 + enum cps_pm_state state; 635 + 636 + core = cpu_core(&cpu_data[cpu]); 637 637 638 638 for (state = CPS_PM_NC_WAIT; state < CPS_PM_STATE_COUNT; state++) { 639 - if (per_cpu(nc_asm_enter, core)[state]) 639 + if (per_cpu(nc_asm_enter, cpu)[state]) 640 640 continue; 641 641 if (!test_bit(state, state_support)) 642 642 continue; ··· 650 646 clear_bit(state, state_support); 651 647 } 652 648 653 - per_cpu(nc_asm_enter, core)[state] = entry_fn; 649 + for_each_cpu(sibling, &cpu_sibling_map[cpu]) 650 + per_cpu(nc_asm_enter, sibling)[state] = entry_fn; 654 651 } 655 652 656 - if (!per_cpu(ready_count, core)) { 653 + if (!per_cpu(ready_count, cpu)) { 657 654 core_rc = kmalloc(sizeof(u32), GFP_KERNEL); 658 655 if (!core_rc) { 659 656 pr_err("Failed allocate core %u ready_count\n", core); 660 657 return -ENOMEM; 661 658 } 662 - per_cpu(ready_count, core) = core_rc; 659 + 660 + for_each_cpu(sibling, &cpu_sibling_map[cpu]) 661 + per_cpu(ready_count, sibling) = core_rc; 663 662 } 664 663 665 664 return 0;

+241 -49

arch/mips/kernel/smp-cps.c

··· 36 36 37 37 UASM_L_LA(_not_nmi) 38 38 39 - static DECLARE_BITMAP(core_power, NR_CPUS); 40 39 static u64 core_entry_reg; 41 40 static phys_addr_t cps_vec_pa; 42 41 43 - struct core_boot_config *mips_cps_core_bootcfg; 42 + struct cluster_boot_config *mips_cps_cluster_bootcfg; 43 + 44 + static void power_up_other_cluster(unsigned int cluster) 45 + { 46 + u32 stat, seq_state; 47 + unsigned int timeout; 48 + 49 + mips_cm_lock_other(cluster, CM_GCR_Cx_OTHER_CORE_CM, 0, 50 + CM_GCR_Cx_OTHER_BLOCK_LOCAL); 51 + stat = read_cpc_co_stat_conf(); 52 + mips_cm_unlock_other(); 53 + 54 + seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE; 55 + seq_state >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE); 56 + if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U5) 57 + return; 58 + 59 + /* Set endianness & power up the CM */ 60 + mips_cm_lock_other(cluster, 0, 0, CM_GCR_Cx_OTHER_BLOCK_GLOBAL); 61 + write_cpc_redir_sys_config(IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)); 62 + write_cpc_redir_pwrup_ctl(1); 63 + mips_cm_unlock_other(); 64 + 65 + /* Wait for the CM to start up */ 66 + timeout = 1000; 67 + mips_cm_lock_other(cluster, CM_GCR_Cx_OTHER_CORE_CM, 0, 68 + CM_GCR_Cx_OTHER_BLOCK_LOCAL); 69 + while (1) { 70 + stat = read_cpc_co_stat_conf(); 71 + seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE; 72 + seq_state >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE); 73 + if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U5) 74 + break; 75 + 76 + if (timeout) { 77 + mdelay(1); 78 + timeout--; 79 + } else { 80 + pr_warn("Waiting for cluster %u CM to power up... STAT_CONF=0x%x\n", 81 + cluster, stat); 82 + mdelay(1000); 83 + } 84 + } 85 + 86 + mips_cm_unlock_other(); 87 + } 44 88 45 89 static unsigned __init core_vpe_count(unsigned int cluster, unsigned core) 46 90 { ··· 222 178 pr_cont(","); 223 179 pr_cont("{"); 224 180 181 + if (mips_cm_revision() >= CM_REV_CM3_5) 182 + power_up_other_cluster(cl); 183 + 225 184 ncores = mips_cps_numcores(cl); 226 185 for (c = 0; c < ncores; c++) { 227 186 core_vpes = core_vpe_count(cl, c); ··· 252 205 253 206 /* Indicate present CPUs (CPU being synonymous with VPE) */ 254 207 for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) { 255 - set_cpu_possible(v, cpu_cluster(&cpu_data[v]) == 0); 256 - set_cpu_present(v, cpu_cluster(&cpu_data[v]) == 0); 208 + set_cpu_possible(v, true); 209 + set_cpu_present(v, true); 257 210 __cpu_number_map[v] = v; 258 211 __cpu_logical_map[v] = v; 259 212 } 260 213 261 214 /* Set a coherent default CCA (CWB) */ 262 215 change_c0_config(CONF_CM_CMASK, 0x5); 263 - 264 - /* Core 0 is powered up (we're running on it) */ 265 - bitmap_set(core_power, 0, 1); 266 216 267 217 /* Initialise core 0 */ 268 218 mips_cps_core_init(); ··· 282 238 283 239 static void __init cps_prepare_cpus(unsigned int max_cpus) 284 240 { 285 - unsigned ncores, core_vpes, c, cca; 241 + unsigned int nclusters, ncores, core_vpes, c, cl, cca; 286 242 bool cca_unsuitable, cores_limited; 243 + struct cluster_boot_config *cluster_bootcfg; 244 + struct core_boot_config *core_bootcfg; 287 245 288 246 mips_mt_set_cpuoptions(); 289 247 ··· 327 281 328 282 setup_cps_vecs(); 329 283 330 - /* Allocate core boot configuration structs */ 331 - ncores = mips_cps_numcores(0); 332 - mips_cps_core_bootcfg = kcalloc(ncores, sizeof(*mips_cps_core_bootcfg), 333 - GFP_KERNEL); 334 - if (!mips_cps_core_bootcfg) { 335 - pr_err("Failed to allocate boot config for %u cores\n", ncores); 336 - goto err_out; 337 - } 284 + /* Allocate cluster boot configuration structs */ 285 + nclusters = mips_cps_numclusters(); 286 + mips_cps_cluster_bootcfg = kcalloc(nclusters, 287 + sizeof(*mips_cps_cluster_bootcfg), 288 + GFP_KERNEL); 338 289 339 - /* Allocate VPE boot configuration structs */ 340 - for (c = 0; c < ncores; c++) { 341 - core_vpes = core_vpe_count(0, c); 342 - mips_cps_core_bootcfg[c].vpe_config = kcalloc(core_vpes, 343 - sizeof(*mips_cps_core_bootcfg[c].vpe_config), 344 - GFP_KERNEL); 345 - if (!mips_cps_core_bootcfg[c].vpe_config) { 346 - pr_err("Failed to allocate %u VPE boot configs\n", 347 - core_vpes); 290 + if (nclusters > 1) 291 + mips_cm_update_property(); 292 + 293 + for (cl = 0; cl < nclusters; cl++) { 294 + /* Allocate core boot configuration structs */ 295 + ncores = mips_cps_numcores(cl); 296 + core_bootcfg = kcalloc(ncores, sizeof(*core_bootcfg), 297 + GFP_KERNEL); 298 + if (!core_bootcfg) 348 299 goto err_out; 300 + mips_cps_cluster_bootcfg[cl].core_config = core_bootcfg; 301 + 302 + mips_cps_cluster_bootcfg[cl].core_power = 303 + kcalloc(BITS_TO_LONGS(ncores), sizeof(unsigned long), 304 + GFP_KERNEL); 305 + 306 + /* Allocate VPE boot configuration structs */ 307 + for (c = 0; c < ncores; c++) { 308 + core_vpes = core_vpe_count(cl, c); 309 + core_bootcfg[c].vpe_config = kcalloc(core_vpes, 310 + sizeof(*core_bootcfg[c].vpe_config), 311 + GFP_KERNEL); 312 + if (!core_bootcfg[c].vpe_config) 313 + goto err_out; 349 314 } 350 315 } 351 316 352 - /* Mark this CPU as booted */ 353 - atomic_set(&mips_cps_core_bootcfg[cpu_core(&current_cpu_data)].vpe_mask, 354 - 1 << cpu_vpe_id(&current_cpu_data)); 317 + /* Mark this CPU as powered up & booted */ 318 + cl = cpu_cluster(&current_cpu_data); 319 + c = cpu_core(&current_cpu_data); 320 + cluster_bootcfg = &mips_cps_cluster_bootcfg[cl]; 321 + core_bootcfg = &cluster_bootcfg->core_config[c]; 322 + bitmap_set(cluster_bootcfg->core_power, cpu_core(&current_cpu_data), 1); 323 + atomic_set(&core_bootcfg->vpe_mask, 1 << cpu_vpe_id(&current_cpu_data)); 355 324 356 325 return; 357 326 err_out: 358 327 /* Clean up allocations */ 359 - if (mips_cps_core_bootcfg) { 360 - for (c = 0; c < ncores; c++) 361 - kfree(mips_cps_core_bootcfg[c].vpe_config); 362 - kfree(mips_cps_core_bootcfg); 363 - mips_cps_core_bootcfg = NULL; 328 + if (mips_cps_cluster_bootcfg) { 329 + for (cl = 0; cl < nclusters; cl++) { 330 + cluster_bootcfg = &mips_cps_cluster_bootcfg[cl]; 331 + ncores = mips_cps_numcores(cl); 332 + for (c = 0; c < ncores; c++) { 333 + core_bootcfg = &cluster_bootcfg->core_config[c]; 334 + kfree(core_bootcfg->vpe_config); 335 + } 336 + kfree(mips_cps_cluster_bootcfg[c].core_config); 337 + } 338 + kfree(mips_cps_cluster_bootcfg); 339 + mips_cps_cluster_bootcfg = NULL; 364 340 } 365 341 366 342 /* Effectively disable SMP by declaring CPUs not present */ ··· 393 325 } 394 326 } 395 327 396 - static void boot_core(unsigned int core, unsigned int vpe_id) 328 + static void init_cluster_l2(void) 397 329 { 398 - u32 stat, seq_state; 399 - unsigned timeout; 330 + u32 l2_cfg, l2sm_cop, result; 331 + 332 + while (!mips_cm_is_l2_hci_broken) { 333 + l2_cfg = read_gcr_redir_l2_ram_config(); 334 + 335 + /* If HCI is not supported, use the state machine below */ 336 + if (!(l2_cfg & CM_GCR_L2_RAM_CONFIG_PRESENT)) 337 + break; 338 + if (!(l2_cfg & CM_GCR_L2_RAM_CONFIG_HCI_SUPPORTED)) 339 + break; 340 + 341 + /* If the HCI_DONE bit is set, we're finished */ 342 + if (l2_cfg & CM_GCR_L2_RAM_CONFIG_HCI_DONE) 343 + return; 344 + } 345 + 346 + l2sm_cop = read_gcr_redir_l2sm_cop(); 347 + if (WARN(!(l2sm_cop & CM_GCR_L2SM_COP_PRESENT), 348 + "L2 init not supported on this system yet")) 349 + return; 350 + 351 + /* Clear L2 tag registers */ 352 + write_gcr_redir_l2_tag_state(0); 353 + write_gcr_redir_l2_ecc(0); 354 + 355 + /* Ensure the L2 tag writes complete before the state machine starts */ 356 + mb(); 357 + 358 + /* Wait for the L2 state machine to be idle */ 359 + do { 360 + l2sm_cop = read_gcr_redir_l2sm_cop(); 361 + } while (l2sm_cop & CM_GCR_L2SM_COP_RUNNING); 362 + 363 + /* Start a store tag operation */ 364 + l2sm_cop = CM_GCR_L2SM_COP_TYPE_IDX_STORETAG; 365 + l2sm_cop <<= __ffs(CM_GCR_L2SM_COP_TYPE); 366 + l2sm_cop |= CM_GCR_L2SM_COP_CMD_START; 367 + write_gcr_redir_l2sm_cop(l2sm_cop); 368 + 369 + /* Ensure the state machine starts before we poll for completion */ 370 + mb(); 371 + 372 + /* Wait for the operation to be complete */ 373 + do { 374 + l2sm_cop = read_gcr_redir_l2sm_cop(); 375 + result = l2sm_cop & CM_GCR_L2SM_COP_RESULT; 376 + result >>= __ffs(CM_GCR_L2SM_COP_RESULT); 377 + } while (!result); 378 + 379 + WARN(result != CM_GCR_L2SM_COP_RESULT_DONE_OK, 380 + "L2 state machine failed cache init with error %u\n", result); 381 + } 382 + 383 + static void boot_core(unsigned int cluster, unsigned int core, 384 + unsigned int vpe_id) 385 + { 386 + struct cluster_boot_config *cluster_cfg; 387 + u32 access, stat, seq_state; 388 + unsigned int timeout, ncores; 389 + 390 + cluster_cfg = &mips_cps_cluster_bootcfg[cluster]; 391 + ncores = mips_cps_numcores(cluster); 392 + 393 + if ((cluster != cpu_cluster(&current_cpu_data)) && 394 + bitmap_empty(cluster_cfg->core_power, ncores)) { 395 + power_up_other_cluster(cluster); 396 + 397 + mips_cm_lock_other(cluster, core, 0, 398 + CM_GCR_Cx_OTHER_BLOCK_GLOBAL); 399 + 400 + /* Ensure cluster GCRs are where we expect */ 401 + write_gcr_redir_base(read_gcr_base()); 402 + write_gcr_redir_cpc_base(read_gcr_cpc_base()); 403 + write_gcr_redir_gic_base(read_gcr_gic_base()); 404 + 405 + init_cluster_l2(); 406 + 407 + /* Mirror L2 configuration */ 408 + write_gcr_redir_l2_only_sync_base(read_gcr_l2_only_sync_base()); 409 + write_gcr_redir_l2_pft_control(read_gcr_l2_pft_control()); 410 + write_gcr_redir_l2_pft_control_b(read_gcr_l2_pft_control_b()); 411 + 412 + /* Mirror ECC/parity setup */ 413 + write_gcr_redir_err_control(read_gcr_err_control()); 414 + 415 + /* Set BEV base */ 416 + write_gcr_redir_bev_base(core_entry_reg); 417 + 418 + mips_cm_unlock_other(); 419 + } 420 + 421 + if (cluster != cpu_cluster(&current_cpu_data)) { 422 + mips_cm_lock_other(cluster, core, 0, 423 + CM_GCR_Cx_OTHER_BLOCK_GLOBAL); 424 + 425 + /* Ensure the core can access the GCRs */ 426 + access = read_gcr_redir_access(); 427 + access |= BIT(core); 428 + write_gcr_redir_access(access); 429 + 430 + mips_cm_unlock_other(); 431 + } else { 432 + /* Ensure the core can access the GCRs */ 433 + access = read_gcr_access(); 434 + access |= BIT(core); 435 + write_gcr_access(access); 436 + } 400 437 401 438 /* Select the appropriate core */ 402 - mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL); 439 + mips_cm_lock_other(cluster, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL); 403 440 404 441 /* Set its reset vector */ 405 442 if (mips_cm_is64) ··· 573 400 mips_cm_unlock_other(); 574 401 575 402 /* The core is now powered up */ 576 - bitmap_set(core_power, core, 1); 403 + bitmap_set(cluster_cfg->core_power, core, 1); 404 + 405 + /* 406 + * Restore CM_PWRUP=0 so that the CM can power down if all the cores in 407 + * the cluster do (eg. if they're all removed via hotplug. 408 + */ 409 + if (mips_cm_revision() >= CM_REV_CM3_5) { 410 + mips_cm_lock_other(cluster, 0, 0, CM_GCR_Cx_OTHER_BLOCK_GLOBAL); 411 + write_cpc_redir_pwrup_ctl(0); 412 + mips_cm_unlock_other(); 413 + } 577 414 } 578 415 579 416 static void remote_vpe_boot(void *dummy) 580 417 { 418 + unsigned int cluster = cpu_cluster(&current_cpu_data); 581 419 unsigned core = cpu_core(&current_cpu_data); 582 - struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core]; 420 + struct cluster_boot_config *cluster_cfg = 421 + &mips_cps_cluster_bootcfg[cluster]; 422 + struct core_boot_config *core_cfg = &cluster_cfg->core_config[core]; 583 423 584 424 mips_cps_boot_vpes(core_cfg, cpu_vpe_id(&current_cpu_data)); 585 425 } 586 426 587 427 static int cps_boot_secondary(int cpu, struct task_struct *idle) 588 428 { 429 + unsigned int cluster = cpu_cluster(&cpu_data[cpu]); 589 430 unsigned core = cpu_core(&cpu_data[cpu]); 590 431 unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]); 591 - struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core]; 432 + struct cluster_boot_config *cluster_cfg = 433 + &mips_cps_cluster_bootcfg[cluster]; 434 + struct core_boot_config *core_cfg = &cluster_cfg->core_config[core]; 592 435 struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id]; 593 436 unsigned int remote; 594 437 int err; 595 - 596 - /* We don't yet support booting CPUs in other clusters */ 597 - if (cpu_cluster(&cpu_data[cpu]) != cpu_cluster(&raw_current_cpu_data)) 598 - return -ENOSYS; 599 438 600 439 vpe_cfg->pc = (unsigned long)&smp_bootstrap; 601 440 vpe_cfg->sp = __KSTK_TOS(idle); ··· 617 432 618 433 preempt_disable(); 619 434 620 - if (!test_bit(core, core_power)) { 435 + if (!test_bit(core, cluster_cfg->core_power)) { 621 436 /* Boot a VPE on a powered down core */ 622 - boot_core(core, vpe_id); 437 + boot_core(cluster, core, vpe_id); 623 438 goto out; 624 439 } 625 440 626 441 if (cpu_has_vp) { 627 - mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL); 442 + mips_cm_lock_other(cluster, core, vpe_id, 443 + CM_GCR_Cx_OTHER_BLOCK_LOCAL); 628 444 if (mips_cm_is64) 629 445 write_gcr_co_reset64_base(core_entry_reg); 630 446 else ··· 762 576 static int cps_cpu_disable(void) 763 577 { 764 578 unsigned cpu = smp_processor_id(); 579 + struct cluster_boot_config *cluster_cfg; 765 580 struct core_boot_config *core_cfg; 766 581 767 582 if (!cps_pm_support_state(CPS_PM_POWER_GATED)) 768 583 return -EINVAL; 769 584 770 - core_cfg = &mips_cps_core_bootcfg[cpu_core(&current_cpu_data)]; 585 + cluster_cfg = &mips_cps_cluster_bootcfg[cpu_cluster(&current_cpu_data)]; 586 + core_cfg = &cluster_cfg->core_config[cpu_core(&current_cpu_data)]; 771 587 atomic_sub(1 << cpu_vpe_id(&current_cpu_data), &core_cfg->vpe_mask); 772 588 smp_mb__after_atomic(); 773 589 set_cpu_online(cpu, false); ··· 835 647 836 648 static void cps_cleanup_dead_cpu(unsigned cpu) 837 649 { 650 + unsigned int cluster = cpu_cluster(&cpu_data[cpu]); 838 651 unsigned core = cpu_core(&cpu_data[cpu]); 839 652 unsigned int vpe_id = cpu_vpe_id(&cpu_data[cpu]); 840 653 ktime_t fail_time; 841 654 unsigned stat; 842 655 int err; 656 + struct cluster_boot_config *cluster_cfg; 657 + 658 + cluster_cfg = &mips_cps_cluster_bootcfg[cluster]; 843 659 844 660 /* 845 661 * Now wait for the CPU to actually offline. Without doing this that ··· 895 703 } while (1); 896 704 897 705 /* Indicate the core is powered off */ 898 - bitmap_clear(core_power, core, 1); 706 + bitmap_clear(cluster_cfg->core_power, core, 1); 899 707 } else if (cpu_has_mipsmt) { 900 708 /* 901 709 * Have a CPU with access to the offlined CPUs registers wait

+1 -2

arch/mips/loongson2ef/common/machtype.c

··· 48 48 return; 49 49 } 50 50 p += strlen("machtype="); 51 - strncpy(str, p, MACHTYPE_LEN); 52 - str[MACHTYPE_LEN] = '\0'; 51 + strscpy(str, p); 53 52 p = strstr(str, " "); 54 53 if (p) 55 54 *p = '\0';

-1

arch/mips/sni/setup.c

··· 12 12 #include <linux/init.h> 13 13 #include <linux/export.h> 14 14 #include <linux/console.h> 15 - #include <linux/fb.h> 16 15 #include <linux/screen_info.h> 17 16 18 17 #ifdef CONFIG_FW_ARC

+3 -3

drivers/clocksource/mips-gic-timer.c

··· 115 115 116 116 static int gic_starting_cpu(unsigned int cpu) 117 117 { 118 + /* Ensure the GIC counter is running */ 119 + clear_gic_config(GIC_CONFIG_COUNTSTOP); 120 + 118 121 gic_clockevent_cpu_init(cpu, this_cpu_ptr(&gic_clockevent_device)); 119 122 return 0; 120 123 } ··· 290 287 if (clk_notifier_register(clk, &gic_clk_nb) < 0) 291 288 pr_warn("Unable to register clock notifier\n"); 292 289 } 293 - 294 - /* And finally start the counter */ 295 - clear_gic_config(GIC_CONFIG_COUNTSTOP); 296 290 297 291 /* 298 292 * It's safe to use the MIPS GIC timer as a sched clock source only if

+130

include/dt-bindings/clock/mediatek,mtmips-sysc.h

··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com> 4 + */ 5 + 6 + #ifndef _DT_BINDINGS_CLK_MTMIPS_H 7 + #define _DT_BINDINGS_CLK_MTMIPS_H 8 + 9 + /* Ralink RT-2880 clocks */ 10 + 11 + #define RT2880_CLK_XTAL 0 12 + #define RT2880_CLK_CPU 1 13 + #define RT2880_CLK_BUS 2 14 + #define RT2880_CLK_TIMER 3 15 + #define RT2880_CLK_WATCHDOG 4 16 + #define RT2880_CLK_UART 5 17 + #define RT2880_CLK_I2C 6 18 + #define RT2880_CLK_UARTLITE 7 19 + #define RT2880_CLK_ETHERNET 8 20 + #define RT2880_CLK_WMAC 9 21 + 22 + /* Ralink RT-305X clocks */ 23 + 24 + #define RT305X_CLK_XTAL 0 25 + #define RT305X_CLK_CPU 1 26 + #define RT305X_CLK_BUS 2 27 + #define RT305X_CLK_TIMER 3 28 + #define RT305X_CLK_WATCHDOG 4 29 + #define RT305X_CLK_UART 5 30 + #define RT305X_CLK_I2C 6 31 + #define RT305X_CLK_I2S 7 32 + #define RT305X_CLK_SPI1 8 33 + #define RT305X_CLK_SPI2 9 34 + #define RT305X_CLK_UARTLITE 10 35 + #define RT305X_CLK_ETHERNET 11 36 + #define RT305X_CLK_WMAC 12 37 + 38 + /* Ralink RT-3352 clocks */ 39 + 40 + #define RT3352_CLK_XTAL 0 41 + #define RT3352_CLK_CPU 1 42 + #define RT3352_CLK_PERIPH 2 43 + #define RT3352_CLK_BUS 3 44 + #define RT3352_CLK_TIMER 4 45 + #define RT3352_CLK_WATCHDOG 5 46 + #define RT3352_CLK_UART 6 47 + #define RT3352_CLK_I2C 7 48 + #define RT3352_CLK_I2S 8 49 + #define RT3352_CLK_SPI1 9 50 + #define RT3352_CLK_SPI2 10 51 + #define RT3352_CLK_UARTLITE 11 52 + #define RT3352_CLK_ETHERNET 12 53 + #define RT3352_CLK_WMAC 13 54 + 55 + /* Ralink RT-3883 clocks */ 56 + 57 + #define RT3883_CLK_XTAL 0 58 + #define RT3883_CLK_CPU 1 59 + #define RT3883_CLK_BUS 2 60 + #define RT3883_CLK_PERIPH 3 61 + #define RT3883_CLK_TIMER 4 62 + #define RT3883_CLK_WATCHDOG 5 63 + #define RT3883_CLK_UART 6 64 + #define RT3883_CLK_I2C 7 65 + #define RT3883_CLK_I2S 8 66 + #define RT3883_CLK_SPI1 9 67 + #define RT3883_CLK_SPI2 10 68 + #define RT3883_CLK_UARTLITE 11 69 + #define RT3883_CLK_ETHERNET 12 70 + #define RT3883_CLK_WMAC 13 71 + 72 + /* Ralink RT-5350 clocks */ 73 + 74 + #define RT5350_CLK_XTAL 0 75 + #define RT5350_CLK_CPU 1 76 + #define RT5350_CLK_BUS 2 77 + #define RT5350_CLK_PERIPH 3 78 + #define RT5350_CLK_TIMER 4 79 + #define RT5350_CLK_WATCHDOG 5 80 + #define RT5350_CLK_UART 6 81 + #define RT5350_CLK_I2C 7 82 + #define RT5350_CLK_I2S 8 83 + #define RT5350_CLK_SPI1 9 84 + #define RT5350_CLK_SPI2 10 85 + #define RT5350_CLK_UARTLITE 11 86 + #define RT5350_CLK_ETHERNET 12 87 + #define RT5350_CLK_WMAC 13 88 + 89 + /* Ralink MT-7620 clocks */ 90 + 91 + #define MT7620_CLK_XTAL 0 92 + #define MT7620_CLK_PLL 1 93 + #define MT7620_CLK_CPU 2 94 + #define MT7620_CLK_PERIPH 3 95 + #define MT7620_CLK_BUS 4 96 + #define MT7620_CLK_BBPPLL 5 97 + #define MT7620_CLK_SDHC 6 98 + #define MT7620_CLK_TIMER 7 99 + #define MT7620_CLK_WATCHDOG 8 100 + #define MT7620_CLK_UART 9 101 + #define MT7620_CLK_I2C 10 102 + #define MT7620_CLK_I2S 11 103 + #define MT7620_CLK_SPI1 12 104 + #define MT7620_CLK_SPI2 13 105 + #define MT7620_CLK_UARTLITE 14 106 + #define MT7620_CLK_MMC 15 107 + #define MT7620_CLK_WMAC 16 108 + 109 + /* Ralink MT-76X8 clocks */ 110 + 111 + #define MT76X8_CLK_XTAL 0 112 + #define MT76X8_CLK_CPU 1 113 + #define MT76X8_CLK_BBPPLL 2 114 + #define MT76X8_CLK_PCMI2S 3 115 + #define MT76X8_CLK_PERIPH 4 116 + #define MT76X8_CLK_BUS 5 117 + #define MT76X8_CLK_SDHC 6 118 + #define MT76X8_CLK_TIMER 7 119 + #define MT76X8_CLK_WATCHDOG 8 120 + #define MT76X8_CLK_I2C 9 121 + #define MT76X8_CLK_I2S 10 122 + #define MT76X8_CLK_SPI1 11 123 + #define MT76X8_CLK_SPI2 12 124 + #define MT76X8_CLK_UART0 13 125 + #define MT76X8_CLK_UART1 14 126 + #define MT76X8_CLK_UART2 15 127 + #define MT76X8_CLK_MMC 16 128 + #define MT76X8_CLK_WMAC 17 129 + 130 + #endif /* _DT_BINDINGS_CLK_MTMIPS_H */

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