Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'tty-6.10-final' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty
Pull tty / serial fixes from Greg KH:
"Here are some small serial driver fixes for 6.10-final. Included in
here are:
- qcom-geni fixes for a much much much discussed issue and everyone
now seems to be agreed that this is the proper way forward to
resolve the reported lockups
- imx serial driver bugfixes
- 8250_omap errata fix
- ma35d1 serial driver bugfix
All of these have been in linux-next for over a week with no reported
issues"
* tag 'tty-6.10-final' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty:
serial: qcom-geni: do not kill the machine on fifo underrun
serial: qcom-geni: fix hard lockup on buffer flush
serial: qcom-geni: fix soft lockup on sw flow control and suspend
serial: imx: ensure RTS signal is not left active after shutdown
tty: serial: ma35d1: Add a NULL check for of_node
serial: 8250_omap: Fix Errata i2310 with RX FIFO level check
serial: imx: only set receiver level if it is zero
+104
-22
+2
-1
drivers/tty/serial/8250/8250_omap.c
+2
-1
drivers/tty/serial/8250/8250_omap.c
···
672
672
* https://www.ti.com/lit/pdf/sprz536
673
673
*/
674
674
if (priv->habit & UART_RX_TIMEOUT_QUIRK &&
675
-
(iir & UART_IIR_RX_TIMEOUT) == UART_IIR_RX_TIMEOUT) {
675
+
(iir & UART_IIR_RX_TIMEOUT) == UART_IIR_RX_TIMEOUT &&
676
+
serial_port_in(port, UART_OMAP_RX_LVL) == 0) {
676
677
unsigned char efr2, timeout_h, timeout_l;
677
678
678
679
efr2 = serial_in(up, UART_OMAP_EFR2);
+57
-2
drivers/tty/serial/imx.c
+57
-2
drivers/tty/serial/imx.c
···
120
120
#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
121
121
#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
122
122
#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
123
+
#define UFCR_RXTL_MASK 0x3F /* Receiver trigger 6 bits wide */
123
124
#define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
124
125
#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
125
126
#define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
···
1552
1551
struct imx_port *sport = (struct imx_port *)port;
1553
1552
unsigned long flags;
1554
1553
u32 ucr1, ucr2, ucr4, uts;
1554
+
int loops;
1555
1555
1556
1556
if (sport->dma_is_enabled) {
1557
1557
dmaengine_terminate_sync(sport->dma_chan_tx);
···
1614
1612
ucr4 = imx_uart_readl(sport, UCR4);
1615
1613
ucr4 &= ~UCR4_TCEN;
1616
1614
imx_uart_writel(sport, ucr4, UCR4);
1615
+
1616
+
/*
1617
+
* We have to ensure the tx state machine ends up in OFF. This
1618
+
* is especially important for rs485 where we must not leave
1619
+
* the RTS signal high, blocking the bus indefinitely.
1620
+
*
1621
+
* All interrupts are now disabled, so imx_uart_stop_tx() will
1622
+
* no longer be called from imx_uart_transmit_buffer(). It may
1623
+
* still be called via the hrtimers, and if those are in play,
1624
+
* we have to honour the delays.
1625
+
*/
1626
+
if (sport->tx_state == WAIT_AFTER_RTS || sport->tx_state == SEND)
1627
+
imx_uart_stop_tx(port);
1628
+
1629
+
/*
1630
+
* In many cases (rs232 mode, or if tx_state was
1631
+
* WAIT_AFTER_RTS, or if tx_state was SEND and there is no
1632
+
* delay_rts_after_send), this will have moved directly to
1633
+
* OFF. In rs485 mode, tx_state might already have been
1634
+
* WAIT_AFTER_SEND and the hrtimer thus already started, or
1635
+
* the above imx_uart_stop_tx() call could have started it. In
1636
+
* those cases, we have to wait for the hrtimer to fire and
1637
+
* complete the transition to OFF.
1638
+
*/
1639
+
loops = port->rs485.flags & SER_RS485_ENABLED ?
1640
+
port->rs485.delay_rts_after_send : 0;
1641
+
while (sport->tx_state != OFF && loops--) {
1642
+
uart_port_unlock_irqrestore(&sport->port, flags);
1643
+
msleep(1);
1644
+
uart_port_lock_irqsave(&sport->port, &flags);
1645
+
}
1646
+
1647
+
if (sport->tx_state != OFF) {
1648
+
dev_warn(sport->port.dev, "unexpected tx_state %d\n",
1649
+
sport->tx_state);
1650
+
/*
1651
+
* This machine may be busted, but ensure the RTS
1652
+
* signal is inactive in order not to block other
1653
+
* devices.
1654
+
*/
1655
+
if (port->rs485.flags & SER_RS485_ENABLED) {
1656
+
ucr2 = imx_uart_readl(sport, UCR2);
1657
+
if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1658
+
imx_uart_rts_active(sport, &ucr2);
1659
+
else
1660
+
imx_uart_rts_inactive(sport, &ucr2);
1661
+
imx_uart_writel(sport, ucr2, UCR2);
1662
+
}
1663
+
sport->tx_state = OFF;
1664
+
}
1617
1665
1618
1666
uart_port_unlock_irqrestore(&sport->port, flags);
1619
1667
···
1985
1933
struct serial_rs485 *rs485conf)
1986
1934
{
1987
1935
struct imx_port *sport = (struct imx_port *)port;
1988
-
u32 ucr2;
1936
+
u32 ucr2, ufcr;
1989
1937
1990
1938
if (rs485conf->flags & SER_RS485_ENABLED) {
1991
1939
/* Enable receiver if low-active RTS signal is requested */
···
2005
1953
/* Make sure Rx is enabled in case Tx is active with Rx disabled */
2006
1954
if (!(rs485conf->flags & SER_RS485_ENABLED) ||
2007
1955
rs485conf->flags & SER_RS485_RX_DURING_TX) {
2008
-
imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1956
+
/* If the receiver trigger is 0, set it to a default value */
1957
+
ufcr = imx_uart_readl(sport, UFCR);
1958
+
if ((ufcr & UFCR_RXTL_MASK) == 0)
1959
+
imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
2009
1960
imx_uart_start_rx(port);
2010
1961
}
2011
1962
+7
-6
drivers/tty/serial/ma35d1_serial.c
+7
-6
drivers/tty/serial/ma35d1_serial.c
···
688
688
struct uart_ma35d1_port *up;
689
689
int ret = 0;
690
690
691
-
if (pdev->dev.of_node) {
692
-
ret = of_alias_get_id(pdev->dev.of_node, "serial");
693
-
if (ret < 0) {
694
-
dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n", ret);
695
-
return ret;
696
-
}
691
+
if (!pdev->dev.of_node)
692
+
return -ENODEV;
693
+
694
+
ret = of_alias_get_id(pdev->dev.of_node, "serial");
695
+
if (ret < 0) {
696
+
dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n", ret);
697
+
return ret;
697
698
}
698
699
up = &ma35d1serial_ports[ret];
699
700
up->port.line = ret;
+38
-13
drivers/tty/serial/qcom_geni_serial.c
+38
-13
drivers/tty/serial/qcom_geni_serial.c
···
649
649
650
650
static void qcom_geni_serial_start_tx_fifo(struct uart_port *uport)
651
651
{
652
+
unsigned char c;
652
653
u32 irq_en;
653
654
654
-
if (qcom_geni_serial_main_active(uport) ||
655
-
!qcom_geni_serial_tx_empty(uport))
656
-
return;
655
+
/*
656
+
* Start a new transfer in case the previous command was cancelled and
657
+
* left data in the FIFO which may prevent the watermark interrupt
658
+
* from triggering. Note that the stale data is discarded.
659
+
*/
660
+
if (!qcom_geni_serial_main_active(uport) &&
661
+
!qcom_geni_serial_tx_empty(uport)) {
662
+
if (uart_fifo_out(uport, &c, 1) == 1) {
663
+
writel(M_CMD_DONE_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
664
+
qcom_geni_serial_setup_tx(uport, 1);
665
+
writel(c, uport->membase + SE_GENI_TX_FIFOn);
666
+
}
667
+
}
657
668
658
669
irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
659
670
irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN;
660
-
661
671
writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
662
672
writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
663
673
}
···
675
665
static void qcom_geni_serial_stop_tx_fifo(struct uart_port *uport)
676
666
{
677
667
u32 irq_en;
678
-
struct qcom_geni_serial_port *port = to_dev_port(uport);
679
668
680
669
irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
681
670
irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN);
682
671
writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG);
683
672
writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
684
-
/* Possible stop tx is called multiple times. */
673
+
}
674
+
675
+
static void qcom_geni_serial_cancel_tx_cmd(struct uart_port *uport)
676
+
{
677
+
struct qcom_geni_serial_port *port = to_dev_port(uport);
678
+
685
679
if (!qcom_geni_serial_main_active(uport))
686
680
return;
687
681
···
698
684
writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
699
685
}
700
686
writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
687
+
688
+
port->tx_remaining = 0;
701
689
}
702
690
703
691
static void qcom_geni_serial_handle_rx_fifo(struct uart_port *uport, bool drop)
···
878
862
memset(buf, 0, sizeof(buf));
879
863
tx_bytes = min(remaining, BYTES_PER_FIFO_WORD);
880
864
881
-
tx_bytes = uart_fifo_out(uport, buf, tx_bytes);
865
+
uart_fifo_out(uport, buf, tx_bytes);
882
866
883
867
iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1);
884
868
···
906
890
else
907
891
pending = kfifo_len(&tport->xmit_fifo);
908
892
909
-
/* All data has been transmitted and acknowledged as received */
910
-
if (!pending && !status && done) {
893
+
/* All data has been transmitted or command has been cancelled */
894
+
if (!pending && done) {
911
895
qcom_geni_serial_stop_tx_fifo(uport);
912
896
goto out_write_wakeup;
913
897
}
914
898
915
-
avail = port->tx_fifo_depth - (status & TX_FIFO_WC);
899
+
if (active)
900
+
avail = port->tx_fifo_depth - (status & TX_FIFO_WC);
901
+
else
902
+
avail = port->tx_fifo_depth;
903
+
916
904
avail *= BYTES_PER_FIFO_WORD;
917
905
918
906
chunk = min(avail, pending);
···
1089
1069
{
1090
1070
disable_irq(uport->irq);
1091
1071
1092
-
if (uart_console(uport))
1093
-
return;
1094
-
1095
1072
qcom_geni_serial_stop_tx(uport);
1096
1073
qcom_geni_serial_stop_rx(uport);
1074
+
1075
+
qcom_geni_serial_cancel_tx_cmd(uport);
1076
+
}
1077
+
1078
+
static void qcom_geni_serial_flush_buffer(struct uart_port *uport)
1079
+
{
1080
+
qcom_geni_serial_cancel_tx_cmd(uport);
1097
1081
}
1098
1082
1099
1083
static int qcom_geni_serial_port_setup(struct uart_port *uport)
···
1556
1532
.request_port = qcom_geni_serial_request_port,
1557
1533
.config_port = qcom_geni_serial_config_port,
1558
1534
.shutdown = qcom_geni_serial_shutdown,
1535
+
.flush_buffer = qcom_geni_serial_flush_buffer,
1559
1536
.type = qcom_geni_serial_get_type,
1560
1537
.set_mctrl = qcom_geni_serial_set_mctrl,
1561
1538
.get_mctrl = qcom_geni_serial_get_mctrl,