Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-for-v4.7-rc7' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"One nouveau fix, and a few AMD Polaris fixes and some Allwinner fixes.
I've got some vmware fixes that I might send separate over the
weekend, they fix some black screens, but I'm still debating them"
* tag 'drm-fixes-for-v4.7-rc7' of git://people.freedesktop.org/~airlied/linux:
drm/amd/powerplay: Update CKS on/ CKS off voltage offset calculation.
drm/amd/powerplay: fix bug that get wrong polaris evv voltage.
drm/amd/powerplay: incorrectly use of the function return value
drm/amd/powerplay: fix incorrect voltage table value for tonga
drm/amd/powerplay: fix incorrect voltage table value for polaris10
drm/nouveau/disp/sor/gf119: select correct sor when poking training pattern
gpu: drm: sun4i_drv: add missing of_node_put after calling of_parse_phandle
drm/sun4i: Send vblank event when the CRTC is disabled
drm/sun4i: Report proper vblank
+32
-24
+15
-17
drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
+15
-17
drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
···
98
98
#define PCIE_BUS_CLK 10000
99
99
#define TCLK (PCIE_BUS_CLK / 10)
100
100
101
-
#define CEILING_UCHAR(double) ((double-(uint8_t)(double)) > 0 ? (uint8_t)(double+1) : (uint8_t)(double))
102
101
103
102
static const uint16_t polaris10_clock_stretcher_lookup_table[2][4] =
104
103
{ {600, 1050, 3, 0}, {600, 1050, 6, 1} };
···
732
733
table->Smio[level] |=
733
734
data->mvdd_voltage_table.entries[level].smio_low;
734
735
}
735
-
table->SmioMask2 = data->vddci_voltage_table.mask_low;
736
+
table->SmioMask2 = data->mvdd_voltage_table.mask_low;
736
737
737
738
table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
738
739
}
···
1806
1807
1807
1808
ro = efuse * (max -min)/255 + min;
1808
1809
1809
-
/* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset
1810
-
* there is a little difference in calculating
1811
-
* volt_with_cks with windows */
1810
+
/* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
1812
1811
for (i = 0; i < sclk_table->count; i++) {
1813
1812
data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1814
1813
sclk_table->entries[i].cks_enable << i;
1815
1814
if (hwmgr->chip_id == CHIP_POLARIS10) {
1816
-
volt_without_cks = (uint32_t)((2753594000 + (sclk_table->entries[i].clk/100) * 136418 -(ro - 70) * 1000000) / \
1815
+
volt_without_cks = (uint32_t)((2753594000U + (sclk_table->entries[i].clk/100) * 136418 -(ro - 70) * 1000000) / \
1817
1816
(2424180 - (sclk_table->entries[i].clk/100) * 1132925/1000));
1818
-
volt_with_cks = (uint32_t)((279720200 + sclk_table->entries[i].clk * 3232 - (ro - 65) * 100000000) / \
1819
-
(252248000 - sclk_table->entries[i].clk/100 * 115764));
1817
+
volt_with_cks = (uint32_t)((2797202000U + sclk_table->entries[i].clk/100 * 3232 - (ro - 65) * 1000000) / \
1818
+
(2522480 - sclk_table->entries[i].clk/100 * 115764/100));
1820
1819
} else {
1821
-
volt_without_cks = (uint32_t)((2416794800 + (sclk_table->entries[i].clk/100) * 1476925/10 -(ro - 50) * 1000000) / \
1822
-
(2625416 - (sclk_table->entries[i].clk/100) * 12586807/10000));
1823
-
volt_with_cks = (uint32_t)((2999656000 + sclk_table->entries[i].clk * 392803/100 - (ro - 44) * 1000000) / \
1824
-
(3422454 - sclk_table->entries[i].clk/100 * 18886376/10000));
1820
+
volt_without_cks = (uint32_t)((2416794800U + (sclk_table->entries[i].clk/100) * 1476925/10 -(ro - 50) * 1000000) / \
1821
+
(2625416 - (sclk_table->entries[i].clk/100) * (12586807/10000)));
1822
+
volt_with_cks = (uint32_t)((2999656000U - sclk_table->entries[i].clk/100 * 392803 - (ro - 44) * 1000000) / \
1823
+
(3422454 - sclk_table->entries[i].clk/100 * (18886376/10000)));
1825
1824
}
1826
1825
1827
1826
if (volt_without_cks >= volt_with_cks)
1828
-
volt_offset = (uint8_t)CEILING_UCHAR((volt_without_cks - volt_with_cks +
1829
-
sclk_table->entries[i].cks_voffset) * 100 / 625);
1827
+
volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
1828
+
sclk_table->entries[i].cks_voffset) * 100 + 624) / 625);
1830
1829
1831
1830
data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1832
1831
}
···
2682
2685
{
2683
2686
struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2684
2687
uint16_t vv_id;
2685
-
uint16_t vddc = 0;
2688
+
uint32_t vddc = 0;
2686
2689
uint16_t i, j;
2687
2690
uint32_t sclk = 0;
2688
2691
struct phm_ppt_v1_information *table_info =
···
2713
2716
continue);
2714
2717
2715
2718
2716
-
/* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
2717
-
PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0),
2719
+
/* need to make sure vddc is less than 2v or else, it could burn the ASIC.
2720
+
* real voltage level in unit of 0.01mv */
2721
+
PP_ASSERT_WITH_CODE((vddc < 200000 && vddc != 0),
2718
2722
"Invalid VDDC value", result = -EINVAL;);
2719
2723
2720
2724
/* the voltage should not be zero nor equal to leakage ID */
+2
-2
drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
+2
-2
drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
···
1256
1256
}
1257
1257
1258
1258
int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
1259
-
uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage)
1259
+
uint32_t sclk, uint16_t virtual_voltage_Id, uint32_t *voltage)
1260
1260
{
1261
1261
1262
1262
int result;
···
1274
1274
if (0 != result)
1275
1275
return result;
1276
1276
1277
-
*voltage = get_voltage_info_param_space.usVoltageLevel;
1277
+
*voltage = ((GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3 *)(&get_voltage_info_param_space))->ulVoltageLevel;
1278
1278
1279
1279
return result;
1280
1280
}
+1
-1
drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h
+1
-1
drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h
···
305
305
extern int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock,
306
306
uint8_t level);
307
307
extern int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
308
-
uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage);
308
+
uint32_t sclk, uint16_t virtual_voltage_Id, uint32_t *voltage);
309
309
extern int atomctrl_get_smc_sclk_range_table(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl_sclk_range_table *table);
310
310
311
311
extern int atomctrl_get_avfs_information(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl__avfs_parameters *param);
+1
-1
drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
+1
-1
drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
···
1302
1302
table->Smio[count] |=
1303
1303
data->mvdd_voltage_table.entries[count].smio_low;
1304
1304
}
1305
-
table->SmioMask2 = data->vddci_voltage_table.mask_low;
1305
+
table->SmioMask2 = data->mvdd_voltage_table.mask_low;
1306
1306
1307
1307
CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount);
1308
1308
}
+1
-1
drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
+1
-1
drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
···
302
302
(((unsigned long)powerplay_table) + le16_to_cpu(powerplay_table->usPPMTableOffset));
303
303
304
304
if (0 != powerplay_table->usPPMTableOffset) {
305
-
if (1 == get_platform_power_management_table(hwmgr, atom_ppm_table)) {
305
+
if (get_platform_power_management_table(hwmgr, atom_ppm_table) == 0) {
306
306
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
307
307
PHM_PlatformCaps_EnablePlatformPowerManagement);
308
308
}
+2
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c
+2
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c
···
40
40
gf119_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern)
41
41
{
42
42
struct nvkm_device *device = outp->base.disp->engine.subdev.device;
43
-
nvkm_mask(device, 0x61c110, 0x0f0f0f0f, 0x01010101 * pattern);
43
+
const u32 soff = gf119_sor_soff(outp);
44
+
nvkm_mask(device, 0x61c110 + soff, 0x0f0f0f0f, 0x01010101 * pattern);
44
45
return 0;
45
46
}
46
47
+8
drivers/gpu/drm/sun4i/sun4i_crtc.c
+8
drivers/gpu/drm/sun4i/sun4i_crtc.c
···
65
65
DRM_DEBUG_DRIVER("Disabling the CRTC\n");
66
66
67
67
sun4i_tcon_disable(drv->tcon);
68
+
69
+
if (crtc->state->event && !crtc->state->active) {
70
+
spin_lock_irq(&crtc->dev->event_lock);
71
+
drm_crtc_send_vblank_event(crtc, crtc->state->event);
72
+
spin_unlock_irq(&crtc->dev->event_lock);
73
+
74
+
crtc->state->event = NULL;
75
+
}
68
76
}
69
77
70
78
static void sun4i_crtc_enable(struct drm_crtc *crtc)
+2
-1
drivers/gpu/drm/sun4i/sun4i_drv.c
+2
-1
drivers/gpu/drm/sun4i/sun4i_drv.c
···
92
92
/* Frame Buffer Operations */
93
93
94
94
/* VBlank Operations */
95
-
.get_vblank_counter = drm_vblank_count,
95
+
.get_vblank_counter = drm_vblank_no_hw_counter,
96
96
.enable_vblank = sun4i_drv_enable_vblank,
97
97
.disable_vblank = sun4i_drv_disable_vblank,
98
98
};
···
310
310
311
311
count += sun4i_drv_add_endpoints(&pdev->dev, &match,
312
312
pipeline);
313
+
of_node_put(pipeline);
313
314
314
315
DRM_DEBUG_DRIVER("Queued %d outputs on pipeline %d\n",
315
316
count, i);