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clk: rockchip: Set parent rate for DCLK_VOP clock on RK3228

Similar to DCLK_LCDC on RK3328, the DCLK_VOP on RK3228 is typically
parented by the hdmiphy clk and it is expected that the DCLK_VOP and
hdmiphy clk rate are kept in sync.

Use CLK_SET_RATE_PARENT and CLK_SET_RATE_NO_REPARENT flags, same as used
on RK3328, to make full use of all possible supported display modes.

Fixes: 0a9d4ac08ebc ("clk: rockchip: set the clock ids for RK3228 VOP")
Fixes: 307a2e9ac524 ("clk: rockchip: add clock controller for rk3228")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20240615170417.3134517-3-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

authored by

Jonas Karlman and committed by
Heiko Stuebner 1d34b975 8400291e

+1 -1
+1 -1
drivers/clk/rockchip/clk-rk3228.c
··· 409 409 RK2928_CLKSEL_CON(29), 0, 3, DFLAGS), 410 410 DIV(0, "sclk_vop_pre", "sclk_vop_src", 0, 411 411 RK2928_CLKSEL_CON(27), 8, 8, DFLAGS), 412 - MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, 0, 412 + MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 413 413 RK2928_CLKSEL_CON(27), 1, 1, MFLAGS), 414 414 415 415 FACTOR(0, "xin12m", "xin24m", 0, 1, 2),