tjh.dev / kernel
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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: (21 commits)
x86/PCI: use dev_printk when possible
PCI: add D3 power state avoidance quirk
PCI: fix bogus "'device' may be used uninitialized" warning in pci_slot
PCI: add an option to allow ASPM enabled forcibly
PCI: disable ASPM on pre-1.1 PCIe devices
PCI: disable ASPM per ACPI FADT setting
PCI MSI: Don't disable MSIs if the mask bit isn't supported
PCI: handle 64-bit resources better on 32-bit machines
PCI: rewrite PCI BAR reading code
PCI: document pci_target_state
PCI hotplug: fix typo in pcie hotplug output
x86 gart: replace to_pages macro with iommu_num_pages
x86, AMD IOMMU: replace to_pages macro with iommu_num_pages
iommu: add iommu_num_pages helper function
dma-coherent: add documentation to new interfaces
Cris: convert to using generic dma-coherent mem allocator
Sh: use generic per-device coherent dma allocator
ARM: support generic per-device coherent dma mem
Generic dma-coherent: fix DMA_MEMORY_EXCLUSIVE
x86: use generic per-device dma coherent allocator
...

Linus Torvalds 1d9b9f6a a3ad7f12

+516 -572
+1
arch/arm/Kconfig
··· 17 17 select HAVE_KRETPROBES if (HAVE_KPROBES) 18 18 select HAVE_FTRACE if (!XIP_KERNEL) 19 19 select HAVE_DYNAMIC_FTRACE if (HAVE_FTRACE) 20 + select HAVE_GENERIC_DMA_COHERENT 20 21 help 21 22 The ARM series is a line of low-power-consumption RISC chip designs 22 23 licensed by ARM Ltd and targeted at embedded applications and
+8
arch/arm/mm/consistent.c
··· 274 274 void * 275 275 dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp) 276 276 { 277 + void *memory; 278 + 279 + if (dma_alloc_from_coherent(dev, size, handle, &memory)) 280 + return memory; 281 + 277 282 if (arch_is_coherent()) { 278 283 void *virt; 279 284 ··· 366 361 u32 off; 367 362 368 363 WARN_ON(irqs_disabled()); 364 + 365 + if (dma_release_from_coherent(dev, get_order(size), cpu_addr)) 366 + return; 369 367 370 368 if (arch_is_coherent()) { 371 369 kfree(cpu_addr);
+1
arch/cris/arch-v32/drivers/Kconfig
··· 641 641 bool 642 642 depends on ETRAX_CARDBUS 643 643 default y 644 + select HAVE_GENERIC_DMA_COHERENT 644 645 645 646 config ETRAX_IOP_FW_LOAD 646 647 tristate "IO-processor hotplug firmware loading support"
+3 -103
arch/cris/arch-v32/drivers/pci/dma.c
··· 15 15 #include <linux/pci.h> 16 16 #include <asm/io.h> 17 17 18 - struct dma_coherent_mem { 19 - void *virt_base; 20 - u32 device_base; 21 - int size; 22 - int flags; 23 - unsigned long *bitmap; 24 - }; 25 - 26 18 void *dma_alloc_coherent(struct device *dev, size_t size, 27 19 dma_addr_t *dma_handle, gfp_t gfp) 28 20 { 29 21 void *ret; 30 - struct dma_coherent_mem *mem = dev ? dev->dma_mem : NULL; 31 22 int order = get_order(size); 32 23 /* ignore region specifiers */ 33 24 gfp &= ~(__GFP_DMA | __GFP_HIGHMEM); 34 25 35 - if (mem) { 36 - int page = bitmap_find_free_region(mem->bitmap, mem->size, 37 - order); 38 - if (page >= 0) { 39 - *dma_handle = mem->device_base + (page << PAGE_SHIFT); 40 - ret = mem->virt_base + (page << PAGE_SHIFT); 41 - memset(ret, 0, size); 42 - return ret; 43 - } 44 - if (mem->flags & DMA_MEMORY_EXCLUSIVE) 45 - return NULL; 46 - } 26 + if (dma_alloc_from_coherent(dev, size, dma_handle, &ret)) 27 + return ret; 47 28 48 29 if (dev == NULL || (dev->coherent_dma_mask < 0xffffffff)) 49 30 gfp |= GFP_DMA; ··· 41 60 void dma_free_coherent(struct device *dev, size_t size, 42 61 void *vaddr, dma_addr_t dma_handle) 43 62 { 44 - struct dma_coherent_mem *mem = dev ? dev->dma_mem : NULL; 45 63 int order = get_order(size); 46 64 47 - if (mem && vaddr >= mem->virt_base && vaddr < (mem->virt_base + (mem->size << PAGE_SHIFT))) { 48 - int page = (vaddr - mem->virt_base) >> PAGE_SHIFT; 49 - 50 - bitmap_release_region(mem->bitmap, page, order); 51 - } else 65 + if (!dma_release_from_coherent(dev, order, vaddr)) 52 66 free_pages((unsigned long)vaddr, order); 53 67 } 54 68 55 - int dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr, 56 - dma_addr_t device_addr, size_t size, int flags) 57 - { 58 - void __iomem *mem_base; 59 - int pages = size >> PAGE_SHIFT; 60 - int bitmap_size = BITS_TO_LONGS(pages) * sizeof(long); 61 - 62 - if ((flags & (DMA_MEMORY_MAP | DMA_MEMORY_IO)) == 0) 63 - goto out; 64 - if (!size) 65 - goto out; 66 - if (dev->dma_mem) 67 - goto out; 68 - 69 - /* FIXME: this routine just ignores DMA_MEMORY_INCLUDES_CHILDREN */ 70 - 71 - mem_base = ioremap(bus_addr, size); 72 - if (!mem_base) 73 - goto out; 74 - 75 - dev->dma_mem = kzalloc(sizeof(struct dma_coherent_mem), GFP_KERNEL); 76 - if (!dev->dma_mem) 77 - goto iounmap_out; 78 - dev->dma_mem->bitmap = kzalloc(bitmap_size, GFP_KERNEL); 79 - if (!dev->dma_mem->bitmap) 80 - goto free1_out; 81 - 82 - dev->dma_mem->virt_base = mem_base; 83 - dev->dma_mem->device_base = device_addr; 84 - dev->dma_mem->size = pages; 85 - dev->dma_mem->flags = flags; 86 - 87 - if (flags & DMA_MEMORY_MAP) 88 - return DMA_MEMORY_MAP; 89 - 90 - return DMA_MEMORY_IO; 91 - 92 - free1_out: 93 - kfree(dev->dma_mem); 94 - iounmap_out: 95 - iounmap(mem_base); 96 - out: 97 - return 0; 98 - } 99 - EXPORT_SYMBOL(dma_declare_coherent_memory); 100 - 101 - void dma_release_declared_memory(struct device *dev) 102 - { 103 - struct dma_coherent_mem *mem = dev->dma_mem; 104 - 105 - if(!mem) 106 - return; 107 - dev->dma_mem = NULL; 108 - iounmap(mem->virt_base); 109 - kfree(mem->bitmap); 110 - kfree(mem); 111 - } 112 - EXPORT_SYMBOL(dma_release_declared_memory); 113 - 114 - void *dma_mark_declared_memory_occupied(struct device *dev, 115 - dma_addr_t device_addr, size_t size) 116 - { 117 - struct dma_coherent_mem *mem = dev->dma_mem; 118 - int pages = (size + (device_addr & ~PAGE_MASK) + PAGE_SIZE - 1) >> PAGE_SHIFT; 119 - int pos, err; 120 - 121 - if (!mem) 122 - return ERR_PTR(-EINVAL); 123 - 124 - pos = (device_addr - mem->device_base) >> PAGE_SHIFT; 125 - err = bitmap_allocate_region(mem->bitmap, pos, get_order(pages)); 126 - if (err != 0) 127 - return ERR_PTR(err); 128 - return mem->virt_base + (pos << PAGE_SHIFT); 129 - } 130 - EXPORT_SYMBOL(dma_mark_declared_memory_occupied);
+1
arch/sh/Kconfig
··· 11 11 select HAVE_CLK 12 12 select HAVE_IDE 13 13 select HAVE_OPROFILE 14 + select HAVE_GENERIC_DMA_COHERENT 14 15 help 15 16 The SuperH is a RISC processor targeted for use in embedded systems 16 17 and consumer electronics; it was also used in the Sega Dreamcast
+3 -95
arch/sh/mm/consistent.c
··· 28 28 dma_addr_t *dma_handle, gfp_t gfp) 29 29 { 30 30 void *ret, *ret_nocache; 31 - struct dma_coherent_mem *mem = dev ? dev->dma_mem : NULL; 32 31 int order = get_order(size); 33 32 34 - if (mem) { 35 - int page = bitmap_find_free_region(mem->bitmap, mem->size, 36 - order); 37 - if (page >= 0) { 38 - *dma_handle = mem->device_base + (page << PAGE_SHIFT); 39 - ret = mem->virt_base + (page << PAGE_SHIFT); 40 - memset(ret, 0, size); 41 - return ret; 42 - } 43 - if (mem->flags & DMA_MEMORY_EXCLUSIVE) 44 - return NULL; 45 - } 33 + if (dma_alloc_from_coherent(dev, size, dma_handle, &ret)) 34 + return ret; 46 35 47 36 ret = (void *)__get_free_pages(gfp, order); 48 37 if (!ret) ··· 61 72 struct dma_coherent_mem *mem = dev ? dev->dma_mem : NULL; 62 73 int order = get_order(size); 63 74 64 - if (mem && vaddr >= mem->virt_base && vaddr < (mem->virt_base + (mem->size << PAGE_SHIFT))) { 65 - int page = (vaddr - mem->virt_base) >> PAGE_SHIFT; 66 - 67 - bitmap_release_region(mem->bitmap, page, order); 68 - } else { 75 + if (!dma_release_from_coherent(dev, order, vaddr)) { 69 76 WARN_ON(irqs_disabled()); /* for portability */ 70 77 BUG_ON(mem && mem->flags & DMA_MEMORY_EXCLUSIVE); 71 78 free_pages((unsigned long)phys_to_virt(dma_handle), order); ··· 69 84 } 70 85 } 71 86 EXPORT_SYMBOL(dma_free_coherent); 72 - 73 - int dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr, 74 - dma_addr_t device_addr, size_t size, int flags) 75 - { 76 - void __iomem *mem_base = NULL; 77 - int pages = size >> PAGE_SHIFT; 78 - int bitmap_size = BITS_TO_LONGS(pages) * sizeof(long); 79 - 80 - if ((flags & (DMA_MEMORY_MAP | DMA_MEMORY_IO)) == 0) 81 - goto out; 82 - if (!size) 83 - goto out; 84 - if (dev->dma_mem) 85 - goto out; 86 - 87 - /* FIXME: this routine just ignores DMA_MEMORY_INCLUDES_CHILDREN */ 88 - 89 - mem_base = ioremap_nocache(bus_addr, size); 90 - if (!mem_base) 91 - goto out; 92 - 93 - dev->dma_mem = kmalloc(sizeof(struct dma_coherent_mem), GFP_KERNEL); 94 - if (!dev->dma_mem) 95 - goto out; 96 - dev->dma_mem->bitmap = kzalloc(bitmap_size, GFP_KERNEL); 97 - if (!dev->dma_mem->bitmap) 98 - goto free1_out; 99 - 100 - dev->dma_mem->virt_base = mem_base; 101 - dev->dma_mem->device_base = device_addr; 102 - dev->dma_mem->size = pages; 103 - dev->dma_mem->flags = flags; 104 - 105 - if (flags & DMA_MEMORY_MAP) 106 - return DMA_MEMORY_MAP; 107 - 108 - return DMA_MEMORY_IO; 109 - 110 - free1_out: 111 - kfree(dev->dma_mem); 112 - out: 113 - if (mem_base) 114 - iounmap(mem_base); 115 - return 0; 116 - } 117 - EXPORT_SYMBOL(dma_declare_coherent_memory); 118 - 119 - void dma_release_declared_memory(struct device *dev) 120 - { 121 - struct dma_coherent_mem *mem = dev->dma_mem; 122 - 123 - if (!mem) 124 - return; 125 - dev->dma_mem = NULL; 126 - iounmap(mem->virt_base); 127 - kfree(mem->bitmap); 128 - kfree(mem); 129 - } 130 - EXPORT_SYMBOL(dma_release_declared_memory); 131 - 132 - void *dma_mark_declared_memory_occupied(struct device *dev, 133 - dma_addr_t device_addr, size_t size) 134 - { 135 - struct dma_coherent_mem *mem = dev->dma_mem; 136 - int pages = (size + (device_addr & ~PAGE_MASK) + PAGE_SIZE - 1) >> PAGE_SHIFT; 137 - int pos, err; 138 - 139 - if (!mem) 140 - return ERR_PTR(-EINVAL); 141 - 142 - pos = (device_addr - mem->device_base) >> PAGE_SHIFT; 143 - err = bitmap_allocate_region(mem->bitmap, pos, get_order(pages)); 144 - if (err != 0) 145 - return ERR_PTR(err); 146 - return mem->virt_base + (pos << PAGE_SHIFT); 147 - } 148 - EXPORT_SYMBOL(dma_mark_declared_memory_occupied); 149 87 150 88 void dma_cache_sync(struct device *dev, void *vaddr, size_t size, 151 89 enum dma_data_direction direction)
+1
arch/x86/Kconfig
··· 30 30 select HAVE_FTRACE 31 31 select HAVE_KVM if ((X86_32 && !X86_VOYAGER && !X86_VISWS && !X86_NUMAQ) || X86_64) 32 32 select HAVE_ARCH_KGDB if !X86_VOYAGER 33 + select HAVE_GENERIC_DMA_COHERENT if X86_32 33 34 select HAVE_EFFICIENT_UNALIGNED_ACCESS 34 35 35 36 config ARCH_DEFCONFIG
+5 -8
arch/x86/kernel/amd_iommu.c
··· 29 29 30 30 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) 31 31 32 - #define to_pages(addr, size) \ 33 - (round_up(((addr) & ~PAGE_MASK) + (size), PAGE_SIZE) >> PAGE_SHIFT) 34 - 35 32 #define EXIT_LOOP_COUNT 10000000 36 33 37 34 static DEFINE_RWLOCK(amd_iommu_devtable_lock); ··· 182 185 u64 address, size_t size) 183 186 { 184 187 int s = 0; 185 - unsigned pages = to_pages(address, size); 188 + unsigned pages = iommu_num_pages(address, size); 186 189 187 190 address &= PAGE_MASK; 188 191 ··· 554 557 if (iommu->exclusion_start && 555 558 iommu->exclusion_start < dma_dom->aperture_size) { 556 559 unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT; 557 - int pages = to_pages(iommu->exclusion_start, 558 - iommu->exclusion_length); 560 + int pages = iommu_num_pages(iommu->exclusion_start, 561 + iommu->exclusion_length); 559 562 dma_ops_reserve_addresses(dma_dom, startpage, pages); 560 563 } 561 564 ··· 764 767 unsigned int pages; 765 768 int i; 766 769 767 - pages = to_pages(paddr, size); 770 + pages = iommu_num_pages(paddr, size); 768 771 paddr &= PAGE_MASK; 769 772 770 773 address = dma_ops_alloc_addresses(dev, dma_dom, pages); ··· 799 802 if ((dma_addr == 0) || (dma_addr + size > dma_dom->aperture_size)) 800 803 return; 801 804 802 - pages = to_pages(dma_addr, size); 805 + pages = iommu_num_pages(dma_addr, size); 803 806 dma_addr &= PAGE_MASK; 804 807 start = dma_addr; 805 808
+2 -120
arch/x86/kernel/pci-dma.c
··· 192 192 } 193 193 early_param("iommu", iommu_setup); 194 194 195 - #ifdef CONFIG_X86_32 196 - int dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr, 197 - dma_addr_t device_addr, size_t size, int flags) 198 - { 199 - void __iomem *mem_base = NULL; 200 - int pages = size >> PAGE_SHIFT; 201 - int bitmap_size = BITS_TO_LONGS(pages) * sizeof(long); 202 - 203 - if ((flags & (DMA_MEMORY_MAP | DMA_MEMORY_IO)) == 0) 204 - goto out; 205 - if (!size) 206 - goto out; 207 - if (dev->dma_mem) 208 - goto out; 209 - 210 - /* FIXME: this routine just ignores DMA_MEMORY_INCLUDES_CHILDREN */ 211 - 212 - mem_base = ioremap(bus_addr, size); 213 - if (!mem_base) 214 - goto out; 215 - 216 - dev->dma_mem = kzalloc(sizeof(struct dma_coherent_mem), GFP_KERNEL); 217 - if (!dev->dma_mem) 218 - goto out; 219 - dev->dma_mem->bitmap = kzalloc(bitmap_size, GFP_KERNEL); 220 - if (!dev->dma_mem->bitmap) 221 - goto free1_out; 222 - 223 - dev->dma_mem->virt_base = mem_base; 224 - dev->dma_mem->device_base = device_addr; 225 - dev->dma_mem->size = pages; 226 - dev->dma_mem->flags = flags; 227 - 228 - if (flags & DMA_MEMORY_MAP) 229 - return DMA_MEMORY_MAP; 230 - 231 - return DMA_MEMORY_IO; 232 - 233 - free1_out: 234 - kfree(dev->dma_mem); 235 - out: 236 - if (mem_base) 237 - iounmap(mem_base); 238 - return 0; 239 - } 240 - EXPORT_SYMBOL(dma_declare_coherent_memory); 241 - 242 - void dma_release_declared_memory(struct device *dev) 243 - { 244 - struct dma_coherent_mem *mem = dev->dma_mem; 245 - 246 - if (!mem) 247 - return; 248 - dev->dma_mem = NULL; 249 - iounmap(mem->virt_base); 250 - kfree(mem->bitmap); 251 - kfree(mem); 252 - } 253 - EXPORT_SYMBOL(dma_release_declared_memory); 254 - 255 - void *dma_mark_declared_memory_occupied(struct device *dev, 256 - dma_addr_t device_addr, size_t size) 257 - { 258 - struct dma_coherent_mem *mem = dev->dma_mem; 259 - int pos, err; 260 - int pages = (size + (device_addr & ~PAGE_MASK) + PAGE_SIZE - 1); 261 - 262 - pages >>= PAGE_SHIFT; 263 - 264 - if (!mem) 265 - return ERR_PTR(-EINVAL); 266 - 267 - pos = (device_addr - mem->device_base) >> PAGE_SHIFT; 268 - err = bitmap_allocate_region(mem->bitmap, pos, get_order(pages)); 269 - if (err != 0) 270 - return ERR_PTR(err); 271 - return mem->virt_base + (pos << PAGE_SHIFT); 272 - } 273 - EXPORT_SYMBOL(dma_mark_declared_memory_occupied); 274 - 275 - static int dma_alloc_from_coherent_mem(struct device *dev, ssize_t size, 276 - dma_addr_t *dma_handle, void **ret) 277 - { 278 - struct dma_coherent_mem *mem = dev ? dev->dma_mem : NULL; 279 - int order = get_order(size); 280 - 281 - if (mem) { 282 - int page = bitmap_find_free_region(mem->bitmap, mem->size, 283 - order); 284 - if (page >= 0) { 285 - *dma_handle = mem->device_base + (page << PAGE_SHIFT); 286 - *ret = mem->virt_base + (page << PAGE_SHIFT); 287 - memset(*ret, 0, size); 288 - } 289 - if (mem->flags & DMA_MEMORY_EXCLUSIVE) 290 - *ret = NULL; 291 - } 292 - return (mem != NULL); 293 - } 294 - 295 - static int dma_release_coherent(struct device *dev, int order, void *vaddr) 296 - { 297 - struct dma_coherent_mem *mem = dev ? dev->dma_mem : NULL; 298 - 299 - if (mem && vaddr >= mem->virt_base && vaddr < 300 - (mem->virt_base + (mem->size << PAGE_SHIFT))) { 301 - int page = (vaddr - mem->virt_base) >> PAGE_SHIFT; 302 - 303 - bitmap_release_region(mem->bitmap, page, order); 304 - return 1; 305 - } 306 - return 0; 307 - } 308 - #else 309 - #define dma_alloc_from_coherent_mem(dev, size, handle, ret) (0) 310 - #define dma_release_coherent(dev, order, vaddr) (0) 311 - #endif /* CONFIG_X86_32 */ 312 - 313 195 int dma_supported(struct device *dev, u64 mask) 314 196 { 315 197 struct dma_mapping_ops *ops = get_dma_ops(dev); ··· 261 379 /* ignore region specifiers */ 262 380 gfp &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); 263 381 264 - if (dma_alloc_from_coherent_mem(dev, size, dma_handle, &memory)) 382 + if (dma_alloc_from_coherent(dev, size, dma_handle, &memory)) 265 383 return memory; 266 384 267 385 if (!dev) { ··· 366 484 367 485 int order = get_order(size); 368 486 WARN_ON(irqs_disabled()); /* for portability */ 369 - if (dma_release_coherent(dev, order, vaddr)) 487 + if (dma_release_from_coherent(dev, order, vaddr)) 370 488 return; 371 489 if (ops->unmap_single) 372 490 ops->unmap_single(dev, bus, size, 0);
+4 -7
arch/x86/kernel/pci-gart_64.c
··· 67 67 (((x) & 0xfffff000) | (((x) >> 32) << 4) | GPTE_VALID | GPTE_COHERENT) 68 68 #define GPTE_DECODE(x) (((x) & 0xfffff000) | (((u64)(x) & 0xff0) << 28)) 69 69 70 - #define to_pages(addr, size) \ 71 - (round_up(((addr) & ~PAGE_MASK) + (size), PAGE_SIZE) >> PAGE_SHIFT) 72 - 73 70 #define EMERGENCY_PAGES 32 /* = 128KB */ 74 71 75 72 #ifdef CONFIG_AGP ··· 238 241 static dma_addr_t dma_map_area(struct device *dev, dma_addr_t phys_mem, 239 242 size_t size, int dir) 240 243 { 241 - unsigned long npages = to_pages(phys_mem, size); 244 + unsigned long npages = iommu_num_pages(phys_mem, size); 242 245 unsigned long iommu_page = alloc_iommu(dev, npages); 243 246 int i; 244 247 ··· 301 304 return; 302 305 303 306 iommu_page = (dma_addr - iommu_bus_base)>>PAGE_SHIFT; 304 - npages = to_pages(dma_addr, size); 307 + npages = iommu_num_pages(dma_addr, size); 305 308 for (i = 0; i < npages; i++) { 306 309 iommu_gatt_base[iommu_page + i] = gart_unmapped_entry; 307 310 CLEAR_LEAK(iommu_page + i); ··· 384 387 } 385 388 386 389 addr = phys_addr; 387 - pages = to_pages(s->offset, s->length); 390 + pages = iommu_num_pages(s->offset, s->length); 388 391 while (pages--) { 389 392 iommu_gatt_base[iommu_page] = GPTE_ENCODE(addr); 390 393 SET_LEAK(iommu_page); ··· 467 470 468 471 seg_size += s->length; 469 472 need = nextneed; 470 - pages += to_pages(s->offset, s->length); 473 + pages += iommu_num_pages(s->offset, s->length); 471 474 ps = s; 472 475 } 473 476 if (dma_map_cont(dev, start_sg, i - start, sgmap, pages, need) < 0)
+2 -1
arch/x86/pci/fixup.c
··· 23 23 pci_read_config_byte(d, reg++, &busno); 24 24 pci_read_config_byte(d, reg++, &suba); 25 25 pci_read_config_byte(d, reg++, &subb); 26 - DBG("i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno, suba, subb); 26 + dev_dbg(&d->dev, "i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno, 27 + suba, subb); 27 28 if (busno) 28 29 pci_scan_bus_with_sysdata(busno); /* Bus A */ 29 30 if (suba < subb)
+11 -15
arch/x86/pci/i386.c
··· 128 128 pr = pci_find_parent_resource(dev, r); 129 129 if (!r->start || !pr || 130 130 request_resource(pr, r) < 0) { 131 - printk(KERN_ERR "PCI: Cannot allocate " 132 - "resource region %d " 133 - "of bridge %s\n", 134 - idx, pci_name(dev)); 131 + dev_err(&dev->dev, "BAR %d: can't " 132 + "allocate resource\n", idx); 135 133 /* 136 134 * Something is wrong with the region. 137 135 * Invalidate the resource to prevent ··· 164 166 else 165 167 disabled = !(command & PCI_COMMAND_MEMORY); 166 168 if (pass == disabled) { 167 - DBG("PCI: Resource %08lx-%08lx " 168 - "(f=%lx, d=%d, p=%d)\n", 169 - r->start, r->end, r->flags, disabled, pass); 169 + dev_dbg(&dev->dev, "resource %#08llx-%#08llx " 170 + "(f=%lx, d=%d, p=%d)\n", 171 + (unsigned long long) r->start, 172 + (unsigned long long) r->end, 173 + r->flags, disabled, pass); 170 174 pr = pci_find_parent_resource(dev, r); 171 175 if (!pr || request_resource(pr, r) < 0) { 172 - printk(KERN_ERR "PCI: Cannot allocate " 173 - "resource region %d " 174 - "of device %s\n", 175 - idx, pci_name(dev)); 176 + dev_err(&dev->dev, "BAR %d: can't " 177 + "allocate resource\n", idx); 176 178 /* We'll assign a new address later */ 177 179 r->end -= r->start; 178 180 r->start = 0; ··· 185 187 /* Turn the ROM off, leave the resource region, 186 188 * but keep it unregistered. */ 187 189 u32 reg; 188 - DBG("PCI: Switching off ROM of %s\n", 189 - pci_name(dev)); 190 + dev_dbg(&dev->dev, "disabling ROM\n"); 190 191 r->flags &= ~IORESOURCE_ROM_ENABLE; 191 192 pci_read_config_dword(dev, 192 193 dev->rom_base_reg, &reg); ··· 254 257 lat = pcibios_max_latency; 255 258 else 256 259 return; 257 - printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", 258 - pci_name(dev), lat); 260 + dev_printk(KERN_DEBUG, &dev->dev, "setting latency timer to %d\n", lat); 259 261 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); 260 262 } 261 263
+48 -58
arch/x86/pci/irq.c
··· 436 436 { 437 437 WARN_ON_ONCE(pirq >= 9); 438 438 if (pirq > 8) { 439 - printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq); 439 + dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq); 440 440 return 0; 441 441 } 442 442 return read_config_nybble(router, 0x74, pirq-1); ··· 446 446 { 447 447 WARN_ON_ONCE(pirq >= 9); 448 448 if (pirq > 8) { 449 - printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq); 449 + dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq); 450 450 return 0; 451 451 } 452 452 write_config_nybble(router, 0x74, pirq-1, irq); ··· 492 492 irq = 0; 493 493 if (pirq <= 4) 494 494 irq = read_config_nybble(router, 0x56, pirq - 1); 495 - printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d get irq : %2d\n", 496 - dev->vendor, dev->device, pirq, irq); 495 + dev_info(&dev->dev, 496 + "AMD756: dev [%04x/%04x], router PIRQ %d get IRQ %d\n", 497 + dev->vendor, dev->device, pirq, irq); 497 498 return irq; 498 499 } 499 500 500 501 static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 501 502 { 502 - printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d SET irq : %2d\n", 503 - dev->vendor, dev->device, pirq, irq); 503 + dev_info(&dev->dev, 504 + "AMD756: dev [%04x/%04x], router PIRQ %d set IRQ %d\n", 505 + dev->vendor, dev->device, pirq, irq); 504 506 if (pirq <= 4) 505 507 write_config_nybble(router, 0x56, pirq - 1, irq); 506 508 return 1; ··· 732 730 switch (device) { 733 731 case PCI_DEVICE_ID_AL_M1533: 734 732 case PCI_DEVICE_ID_AL_M1563: 735 - printk(KERN_DEBUG "PCI: Using ALI IRQ Router\n"); 736 733 r->name = "ALI"; 737 734 r->get = pirq_ali_get; 738 735 r->set = pirq_ali_set; ··· 841 840 h->probe(r, pirq_router_dev, pirq_router_dev->device)) 842 841 break; 843 842 } 844 - printk(KERN_INFO "PCI: Using IRQ router %s [%04x/%04x] at %s\n", 845 - pirq_router.name, 846 - pirq_router_dev->vendor, 847 - pirq_router_dev->device, 848 - pci_name(pirq_router_dev)); 843 + dev_info(&pirq_router_dev->dev, "%s IRQ router [%04x/%04x]\n", 844 + pirq_router.name, 845 + pirq_router_dev->vendor, pirq_router_dev->device); 849 846 850 847 /* The device remains referenced for the kernel lifetime */ 851 848 } ··· 876 877 /* Find IRQ pin */ 877 878 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 878 879 if (!pin) { 879 - DBG(KERN_DEBUG " -> no interrupt pin\n"); 880 + dev_dbg(&dev->dev, "no interrupt pin\n"); 880 881 return 0; 881 882 } 882 883 pin = pin - 1; ··· 886 887 if (!pirq_table) 887 888 return 0; 888 889 889 - DBG(KERN_DEBUG "IRQ for %s[%c]", pci_name(dev), 'A' + pin); 890 890 info = pirq_get_info(dev); 891 891 if (!info) { 892 - DBG(" -> not found in routing table\n" KERN_DEBUG); 892 + dev_dbg(&dev->dev, "PCI INT %c not found in routing table\n", 893 + 'A' + pin); 893 894 return 0; 894 895 } 895 896 pirq = info->irq[pin].link; 896 897 mask = info->irq[pin].bitmap; 897 898 if (!pirq) { 898 - DBG(" -> not routed\n" KERN_DEBUG); 899 + dev_dbg(&dev->dev, "PCI INT %c not routed\n", 'A' + pin); 899 900 return 0; 900 901 } 901 - DBG(" -> PIRQ %02x, mask %04x, excl %04x", pirq, mask, 902 - pirq_table->exclusive_irqs); 902 + dev_dbg(&dev->dev, "PCI INT %c -> PIRQ %02x, mask %04x, excl %04x", 903 + 'A' + pin, pirq, mask, pirq_table->exclusive_irqs); 903 904 mask &= pcibios_irq_mask; 904 905 905 906 /* Work around broken HP Pavilion Notebooks which assign USB to ··· 929 930 if (pci_probe & PCI_USE_PIRQ_MASK) 930 931 newirq = 0; 931 932 else 932 - printk("\n" KERN_WARNING 933 - "PCI: IRQ %i for device %s doesn't match PIRQ mask - try pci=usepirqmask\n" 934 - KERN_DEBUG, newirq, 935 - pci_name(dev)); 933 + dev_warn(&dev->dev, "IRQ %d doesn't match PIRQ mask " 934 + "%#x; try pci=usepirqmask\n", newirq, mask); 936 935 } 937 936 if (!newirq && assign) { 938 937 for (i = 0; i < 16; i++) { ··· 941 944 newirq = i; 942 945 } 943 946 } 944 - DBG(" -> newirq=%d", newirq); 947 + dev_dbg(&dev->dev, "PCI INT %c -> newirq %d", 'A' + pin, newirq); 945 948 946 949 /* Check if it is hardcoded */ 947 950 if ((pirq & 0xf0) == 0xf0) { 948 951 irq = pirq & 0xf; 949 - DBG(" -> hardcoded IRQ %d\n", irq); 950 - msg = "Hardcoded"; 952 + msg = "hardcoded"; 951 953 } else if (r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \ 952 954 ((!(pci_probe & PCI_USE_PIRQ_MASK)) || ((1 << irq) & mask))) { 953 - DBG(" -> got IRQ %d\n", irq); 954 - msg = "Found"; 955 + msg = "found"; 955 956 eisa_set_level_irq(irq); 956 957 } else if (newirq && r->set && 957 958 (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) { 958 - DBG(" -> assigning IRQ %d", newirq); 959 959 if (r->set(pirq_router_dev, dev, pirq, newirq)) { 960 960 eisa_set_level_irq(newirq); 961 - DBG(" ... OK\n"); 962 - msg = "Assigned"; 961 + msg = "assigned"; 963 962 irq = newirq; 964 963 } 965 964 } 966 965 967 966 if (!irq) { 968 - DBG(" ... failed\n"); 969 967 if (newirq && mask == (1 << newirq)) { 970 - msg = "Guessed"; 968 + msg = "guessed"; 971 969 irq = newirq; 972 - } else 970 + } else { 971 + dev_dbg(&dev->dev, "can't route interrupt\n"); 973 972 return 0; 973 + } 974 974 } 975 - printk(KERN_INFO "PCI: %s IRQ %d for device %s\n", msg, irq, 976 - pci_name(dev)); 975 + dev_info(&dev->dev, "%s PCI INT %c -> IRQ %d\n", msg, 'A' + pin, irq); 977 976 978 977 /* Update IRQ for all devices with the same pirq value */ 979 978 while ((dev2 = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev2)) != NULL) { ··· 989 996 (!(pci_probe & PCI_USE_PIRQ_MASK) || \ 990 997 ((1 << dev2->irq) & mask))) { 991 998 #ifndef CONFIG_PCI_MSI 992 - printk(KERN_INFO "IRQ routing conflict for %s, have irq %d, want irq %d\n", 993 - pci_name(dev2), dev2->irq, irq); 999 + dev_info(&dev2->dev, "IRQ routing conflict: " 1000 + "have IRQ %d, want IRQ %d\n", 1001 + dev2->irq, irq); 994 1002 #endif 995 1003 continue; 996 1004 } 997 1005 dev2->irq = irq; 998 1006 pirq_penalty[irq]++; 999 1007 if (dev != dev2) 1000 - printk(KERN_INFO 1001 - "PCI: Sharing IRQ %d with %s\n", 1002 - irq, pci_name(dev2)); 1008 + dev_info(&dev->dev, "sharing IRQ %d with %s\n", 1009 + irq, pci_name(dev2)); 1003 1010 } 1004 1011 } 1005 1012 return 1; ··· 1018 1025 * already in use. 1019 1026 */ 1020 1027 if (dev->irq >= 16) { 1021 - DBG(KERN_DEBUG "%s: ignoring bogus IRQ %d\n", 1022 - pci_name(dev), dev->irq); 1028 + dev_dbg(&dev->dev, "ignoring bogus IRQ %d\n", dev->irq); 1023 1029 dev->irq = 0; 1024 1030 } 1025 1031 /* ··· 1062 1070 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number, 1063 1071 PCI_SLOT(bridge->devfn), pin); 1064 1072 if (irq >= 0) 1065 - printk(KERN_WARNING "PCI: using PPB %s[%c] to get irq %d\n", 1066 - pci_name(bridge), 'A' + pin, irq); 1073 + dev_warn(&dev->dev, "using bridge %s INT %c to get IRQ %d\n", 1074 + pci_name(bridge), 1075 + 'A' + pin, irq); 1067 1076 } 1068 1077 if (irq >= 0) { 1069 - printk(KERN_INFO "PCI->APIC IRQ transform: %s[%c] -> IRQ %d\n", 1070 - pci_name(dev), 'A' + pin, irq); 1078 + dev_info(&dev->dev, "PCI->APIC IRQ transform: INT %c -> IRQ %d\n", 'A' + pin, irq); 1071 1079 dev->irq = irq; 1072 1080 } 1073 1081 } ··· 1223 1231 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number, 1224 1232 PCI_SLOT(bridge->devfn), pin); 1225 1233 if (irq >= 0) 1226 - printk(KERN_WARNING 1227 - "PCI: using PPB %s[%c] to get irq %d\n", 1228 - pci_name(bridge), 1229 - 'A' + pin, irq); 1234 + dev_warn(&dev->dev, "using bridge %s " 1235 + "INT %c to get IRQ %d\n", 1236 + pci_name(bridge), 'A' + pin, 1237 + irq); 1230 1238 dev = bridge; 1231 1239 } 1232 1240 dev = temp_dev; 1233 1241 if (irq >= 0) { 1234 - printk(KERN_INFO 1235 - "PCI->APIC IRQ transform: %s[%c] -> IRQ %d\n", 1236 - pci_name(dev), 'A' + pin, irq); 1242 + dev_info(&dev->dev, "PCI->APIC IRQ transform: " 1243 + "INT %c -> IRQ %d\n", 'A' + pin, irq); 1237 1244 dev->irq = irq; 1238 1245 return 0; 1239 1246 } else 1240 - msg = " Probably buggy MP table."; 1247 + msg = "; probably buggy MP table"; 1241 1248 } else if (pci_probe & PCI_BIOS_IRQ_SCAN) 1242 1249 msg = ""; 1243 1250 else 1244 - msg = " Please try using pci=biosirq."; 1251 + msg = "; please try using pci=biosirq"; 1245 1252 1246 1253 /* 1247 1254 * With IDE legacy devices the IRQ lookup failure is not ··· 1250 1259 !(dev->class & 0x5)) 1251 1260 return 0; 1252 1261 1253 - printk(KERN_WARNING 1254 - "PCI: No IRQ known for interrupt pin %c of device %s.%s\n", 1255 - 'A' + pin, pci_name(dev), msg); 1262 + dev_warn(&dev->dev, "can't find IRQ for PCI INT %c%s\n", 1263 + 'A' + pin, msg); 1256 1264 } 1257 1265 return 0; 1258 1266 }
+3 -2
arch/x86/pci/numaq_32.c
··· 131 131 u8 busno, suba, subb; 132 132 int quad = BUS2QUAD(d->bus->number); 133 133 134 - printk("PCI: Searching for i450NX host bridges on %s\n", pci_name(d)); 134 + dev_info(&d->dev, "searching for i450NX host bridges\n"); 135 135 reg = 0xd0; 136 136 for(pxb=0; pxb<2; pxb++) { 137 137 pci_read_config_byte(d, reg++, &busno); 138 138 pci_read_config_byte(d, reg++, &suba); 139 139 pci_read_config_byte(d, reg++, &subb); 140 - DBG("i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno, suba, subb); 140 + dev_dbg(&d->dev, "i450NX PXB %d: %02x/%02x/%02x\n", 141 + pxb, busno, suba, subb); 141 142 if (busno) { 142 143 /* Bus A */ 143 144 pci_scan_bus_with_sysdata(QUADLOCAL2BUS(quad, busno));
+7 -11
drivers/acpi/pci_slot.c
··· 76 76 }; 77 77 78 78 static int 79 - check_slot(acpi_handle handle, int *device, unsigned long *sun) 79 + check_slot(acpi_handle handle, unsigned long *sun) 80 80 { 81 - int retval = 0; 81 + int device = -1; 82 82 unsigned long adr, sta; 83 83 acpi_status status; 84 84 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; ··· 89 89 if (check_sta_before_sun) { 90 90 /* If SxFy doesn't have _STA, we just assume it's there */ 91 91 status = acpi_evaluate_integer(handle, "_STA", NULL, &sta); 92 - if (ACPI_SUCCESS(status) && !(sta & ACPI_STA_DEVICE_PRESENT)) { 93 - retval = -1; 92 + if (ACPI_SUCCESS(status) && !(sta & ACPI_STA_DEVICE_PRESENT)) 94 93 goto out; 95 - } 96 94 } 97 95 98 96 status = acpi_evaluate_integer(handle, "_ADR", NULL, &adr); 99 97 if (ACPI_FAILURE(status)) { 100 98 dbg("_ADR returned %d on %s\n", status, (char *)buffer.pointer); 101 - retval = -1; 102 99 goto out; 103 100 } 104 - 105 - *device = (adr >> 16) & 0xffff; 106 101 107 102 /* No _SUN == not a slot == bail */ 108 103 status = acpi_evaluate_integer(handle, "_SUN", NULL, sun); 109 104 if (ACPI_FAILURE(status)) { 110 105 dbg("_SUN returned %d on %s\n", status, (char *)buffer.pointer); 111 - retval = -1; 112 106 goto out; 113 107 } 114 108 109 + device = (adr >> 16) & 0xffff; 115 110 out: 116 111 kfree(buffer.pointer); 117 - return retval; 112 + return device; 118 113 } 119 114 120 115 struct callback_args { ··· 139 144 struct callback_args *parent_context = context; 140 145 struct pci_bus *pci_bus = parent_context->pci_bus; 141 146 142 - if (check_slot(handle, &device, &sun)) 147 + device = check_slot(handle, &sun); 148 + if (device < 0) 143 149 return AE_OK; 144 150 145 151 slot = kmalloc(sizeof(*slot), GFP_KERNEL);
+1 -1
drivers/pci/hotplug/pciehp_hpc.c
··· 1103 1103 dbg(" Power Indicator : %3s\n", PWR_LED(ctrl) ? "yes" : "no"); 1104 1104 dbg(" Hot-Plug Surprise : %3s\n", HP_SUPR_RM(ctrl) ? "yes" : "no"); 1105 1105 dbg(" EMI Present : %3s\n", EMI(ctrl) ? "yes" : "no"); 1106 - dbg(" Comamnd Completed : %3s\n", NO_CMD_CMPL(ctrl)? "no" : "yes"); 1106 + dbg(" Command Completed : %3s\n", NO_CMD_CMPL(ctrl)? "no" : "yes"); 1107 1107 pciehp_readw(ctrl, SLOTSTATUS, &reg16); 1108 1108 dbg("Slot Status : 0x%04x\n", reg16); 1109 1109 pciehp_readw(ctrl, SLOTCTRL, &reg16);
+12 -3
drivers/pci/msi.c
··· 126 126 } 127 127 } 128 128 129 - static void msi_set_mask_bits(unsigned int irq, u32 mask, u32 flag) 129 + /* 130 + * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to 131 + * mask all MSI interrupts by clearing the MSI enable bit does not work 132 + * reliably as devices without an INTx disable bit will then generate a 133 + * level IRQ which will never be cleared. 134 + * 135 + * Returns 1 if it succeeded in masking the interrupt and 0 if the device 136 + * doesn't support MSI masking. 137 + */ 138 + static int msi_set_mask_bits(unsigned int irq, u32 mask, u32 flag) 130 139 { 131 140 struct msi_desc *entry; 132 141 ··· 153 144 mask_bits |= flag & mask; 154 145 pci_write_config_dword(entry->dev, pos, mask_bits); 155 146 } else { 156 - __msi_set_enable(entry->dev, entry->msi_attrib.pos, 157 - !flag); 147 + return 0; 158 148 } 159 149 break; 160 150 case PCI_CAP_ID_MSIX: ··· 169 161 break; 170 162 } 171 163 entry->msi_attrib.masked = !!flag; 164 + return 1; 172 165 } 173 166 174 167 void read_msi_msg(unsigned int irq, struct msi_msg *msg)
+7
drivers/pci/pci-acpi.c
··· 11 11 #include <linux/init.h> 12 12 #include <linux/pci.h> 13 13 #include <linux/module.h> 14 + #include <linux/pci-aspm.h> 14 15 #include <acpi/acpi.h> 15 16 #include <acpi/acnamesp.h> 16 17 #include <acpi/acresrc.h> ··· 373 372 printk(KERN_INFO"ACPI FADT declares the system doesn't support MSI, so disable it\n"); 374 373 pci_no_msi(); 375 374 } 375 + 376 + if (acpi_gbl_FADT.boot_flags & BAF_PCIE_ASPM_CONTROL) { 377 + printk(KERN_INFO"ACPI FADT declares the system doesn't support PCIe ASPM, so disable it\n"); 378 + pcie_no_aspm(); 379 + } 380 + 376 381 ret = register_acpi_bus_type(&acpi_pci_bus); 377 382 if (ret) 378 383 return 0;
+10
drivers/pci/pci.c
··· 572 572 if (!ret) 573 573 pci_update_current_state(dev); 574 574 } 575 + /* This device is quirked not to be put into D3, so 576 + don't put it in D3 */ 577 + if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) 578 + return 0; 575 579 576 580 error = pci_raw_set_power_state(dev, state); 577 581 ··· 1127 1123 } 1128 1124 1129 1125 /** 1126 + * pci_target_state - find an appropriate low power state for a given PCI dev 1127 + * @dev: PCI device 1128 + * 1129 + * Use underlying platform code to find a supported low power state for @dev. 1130 + * If the platform can't manage @dev, return the deepest state from which it 1131 + * can generate wake events, based on any available PME info. 1130 1132 */ 1131 1133 pci_power_t pci_target_state(struct pci_dev *dev) 1132 1134 {
+29 -3
drivers/pci/pcie/aspm.c
··· 55 55 struct endpoint_state endpoints[8]; 56 56 }; 57 57 58 - static int aspm_disabled; 58 + static int aspm_disabled, aspm_force; 59 59 static DEFINE_MUTEX(aspm_lock); 60 60 static LIST_HEAD(link_list); 61 61 ··· 510 510 { 511 511 struct pci_dev *child_dev; 512 512 int child_pos; 513 + u32 reg32; 513 514 514 515 /* 515 516 * Some functions in a slot might not all be PCIE functions, very ··· 520 519 child_pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP); 521 520 if (!child_pos) 522 521 return -EINVAL; 522 + 523 + /* 524 + * Disable ASPM for pre-1.1 PCIe device, we follow MS to use 525 + * RBER bit to determine if a function is 1.1 version device 526 + */ 527 + pci_read_config_dword(child_dev, child_pos + PCI_EXP_DEVCAP, 528 + &reg32); 529 + if (!(reg32 & PCI_EXP_DEVCAP_RBER && !aspm_force)) { 530 + printk("Pre-1.1 PCIe device detected, " 531 + "disable ASPM for %s. It can be enabled forcedly" 532 + " with 'pcie_aspm=force'\n", pci_name(pdev)); 533 + return -EINVAL; 534 + } 523 535 } 524 536 return 0; 525 537 } ··· 816 802 817 803 static int __init pcie_aspm_disable(char *str) 818 804 { 819 - aspm_disabled = 1; 805 + if (!strcmp(str, "off")) { 806 + aspm_disabled = 1; 807 + printk(KERN_INFO "PCIe ASPM is disabled\n"); 808 + } else if (!strcmp(str, "force")) { 809 + aspm_force = 1; 810 + printk(KERN_INFO "PCIe ASPM is forcedly enabled\n"); 811 + } 820 812 return 1; 821 813 } 822 814 823 - __setup("pcie_noaspm", pcie_aspm_disable); 815 + __setup("pcie_aspm=", pcie_aspm_disable); 816 + 817 + void pcie_no_aspm(void) 818 + { 819 + if (!aspm_force) 820 + aspm_disabled = 1; 821 + } 824 822 825 823 #ifdef CONFIG_ACPI 826 824 #include <acpi/acpi_bus.h>
+129 -124
drivers/pci/probe.c
··· 163 163 return IORESOURCE_MEM; 164 164 } 165 165 166 - /* 167 - * Find the extent of a PCI decode.. 168 - */ 169 - static u32 pci_size(u32 base, u32 maxbase, u32 mask) 170 - { 171 - u32 size = mask & maxbase; /* Find the significant bits */ 172 - if (!size) 173 - return 0; 174 - 175 - /* Get the lowest of them to find the decode size, and 176 - from that the extent. */ 177 - size = (size & ~(size-1)) - 1; 178 - 179 - /* base == maxbase can be valid only if the BAR has 180 - already been programmed with all 1s. */ 181 - if (base == maxbase && ((base | size) & mask) != mask) 182 - return 0; 183 - 184 - return size; 185 - } 186 - 187 - static u64 pci_size64(u64 base, u64 maxbase, u64 mask) 166 + static u64 pci_size(u64 base, u64 maxbase, u64 mask) 188 167 { 189 168 u64 size = mask & maxbase; /* Find the significant bits */ 190 169 if (!size) ··· 181 202 return size; 182 203 } 183 204 184 - static inline int is_64bit_memory(u32 mask) 205 + enum pci_bar_type { 206 + pci_bar_unknown, /* Standard PCI BAR probe */ 207 + pci_bar_io, /* An io port BAR */ 208 + pci_bar_mem32, /* A 32-bit memory BAR */ 209 + pci_bar_mem64, /* A 64-bit memory BAR */ 210 + }; 211 + 212 + static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar) 185 213 { 186 - if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) == 187 - (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64)) 188 - return 1; 189 - return 0; 214 + if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { 215 + res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; 216 + return pci_bar_io; 217 + } 218 + 219 + res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; 220 + 221 + if (res->flags == PCI_BASE_ADDRESS_MEM_TYPE_64) 222 + return pci_bar_mem64; 223 + return pci_bar_mem32; 224 + } 225 + 226 + /* 227 + * If the type is not unknown, we assume that the lowest bit is 'enable'. 228 + * Returns 1 if the BAR was 64-bit and 0 if it was 32-bit. 229 + */ 230 + static int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 231 + struct resource *res, unsigned int pos) 232 + { 233 + u32 l, sz, mask; 234 + 235 + mask = type ? ~PCI_ROM_ADDRESS_ENABLE : ~0; 236 + 237 + res->name = pci_name(dev); 238 + 239 + pci_read_config_dword(dev, pos, &l); 240 + pci_write_config_dword(dev, pos, mask); 241 + pci_read_config_dword(dev, pos, &sz); 242 + pci_write_config_dword(dev, pos, l); 243 + 244 + /* 245 + * All bits set in sz means the device isn't working properly. 246 + * If the BAR isn't implemented, all bits must be 0. If it's a 247 + * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit 248 + * 1 must be clear. 249 + */ 250 + if (!sz || sz == 0xffffffff) 251 + goto fail; 252 + 253 + /* 254 + * I don't know how l can have all bits set. Copied from old code. 255 + * Maybe it fixes a bug on some ancient platform. 256 + */ 257 + if (l == 0xffffffff) 258 + l = 0; 259 + 260 + if (type == pci_bar_unknown) { 261 + type = decode_bar(res, l); 262 + res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN; 263 + if (type == pci_bar_io) { 264 + l &= PCI_BASE_ADDRESS_IO_MASK; 265 + mask = PCI_BASE_ADDRESS_IO_MASK & 0xffff; 266 + } else { 267 + l &= PCI_BASE_ADDRESS_MEM_MASK; 268 + mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; 269 + } 270 + } else { 271 + res->flags |= (l & IORESOURCE_ROM_ENABLE); 272 + l &= PCI_ROM_ADDRESS_MASK; 273 + mask = (u32)PCI_ROM_ADDRESS_MASK; 274 + } 275 + 276 + if (type == pci_bar_mem64) { 277 + u64 l64 = l; 278 + u64 sz64 = sz; 279 + u64 mask64 = mask | (u64)~0 << 32; 280 + 281 + pci_read_config_dword(dev, pos + 4, &l); 282 + pci_write_config_dword(dev, pos + 4, ~0); 283 + pci_read_config_dword(dev, pos + 4, &sz); 284 + pci_write_config_dword(dev, pos + 4, l); 285 + 286 + l64 |= ((u64)l << 32); 287 + sz64 |= ((u64)sz << 32); 288 + 289 + sz64 = pci_size(l64, sz64, mask64); 290 + 291 + if (!sz64) 292 + goto fail; 293 + 294 + if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) { 295 + dev_err(&dev->dev, "can't handle 64-bit BAR\n"); 296 + goto fail; 297 + } else if ((sizeof(resource_size_t) < 8) && l) { 298 + /* Address above 32-bit boundary; disable the BAR */ 299 + pci_write_config_dword(dev, pos, 0); 300 + pci_write_config_dword(dev, pos + 4, 0); 301 + res->start = 0; 302 + res->end = sz64; 303 + } else { 304 + res->start = l64; 305 + res->end = l64 + sz64; 306 + } 307 + } else { 308 + sz = pci_size(l, sz, mask); 309 + 310 + if (!sz) 311 + goto fail; 312 + 313 + res->start = l; 314 + res->end = l + sz; 315 + } 316 + 317 + out: 318 + return (type == pci_bar_mem64) ? 1 : 0; 319 + fail: 320 + res->flags = 0; 321 + goto out; 190 322 } 191 323 192 324 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) 193 325 { 194 - unsigned int pos, reg, next; 195 - u32 l, sz; 196 - struct resource *res; 326 + unsigned int pos, reg; 197 327 198 - for(pos=0; pos<howmany; pos = next) { 199 - u64 l64; 200 - u64 sz64; 201 - u32 raw_sz; 202 - 203 - next = pos+1; 204 - res = &dev->resource[pos]; 205 - res->name = pci_name(dev); 328 + for (pos = 0; pos < howmany; pos++) { 329 + struct resource *res = &dev->resource[pos]; 206 330 reg = PCI_BASE_ADDRESS_0 + (pos << 2); 207 - pci_read_config_dword(dev, reg, &l); 208 - pci_write_config_dword(dev, reg, ~0); 209 - pci_read_config_dword(dev, reg, &sz); 210 - pci_write_config_dword(dev, reg, l); 211 - if (!sz || sz == 0xffffffff) 212 - continue; 213 - if (l == 0xffffffff) 214 - l = 0; 215 - raw_sz = sz; 216 - if ((l & PCI_BASE_ADDRESS_SPACE) == 217 - PCI_BASE_ADDRESS_SPACE_MEMORY) { 218 - sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK); 219 - /* 220 - * For 64bit prefetchable memory sz could be 0, if the 221 - * real size is bigger than 4G, so we need to check 222 - * szhi for that. 223 - */ 224 - if (!is_64bit_memory(l) && !sz) 225 - continue; 226 - res->start = l & PCI_BASE_ADDRESS_MEM_MASK; 227 - res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK; 228 - } else { 229 - sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff); 230 - if (!sz) 231 - continue; 232 - res->start = l & PCI_BASE_ADDRESS_IO_MASK; 233 - res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK; 234 - } 235 - res->end = res->start + (unsigned long) sz; 236 - res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN; 237 - if (is_64bit_memory(l)) { 238 - u32 szhi, lhi; 239 - 240 - pci_read_config_dword(dev, reg+4, &lhi); 241 - pci_write_config_dword(dev, reg+4, ~0); 242 - pci_read_config_dword(dev, reg+4, &szhi); 243 - pci_write_config_dword(dev, reg+4, lhi); 244 - sz64 = ((u64)szhi << 32) | raw_sz; 245 - l64 = ((u64)lhi << 32) | l; 246 - sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK); 247 - next++; 248 - #if BITS_PER_LONG == 64 249 - if (!sz64) { 250 - res->start = 0; 251 - res->end = 0; 252 - res->flags = 0; 253 - continue; 254 - } 255 - res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK; 256 - res->end = res->start + sz64; 257 - #else 258 - if (sz64 > 0x100000000ULL) { 259 - dev_err(&dev->dev, "BAR %d: can't handle 64-bit" 260 - " BAR\n", pos); 261 - res->start = 0; 262 - res->flags = 0; 263 - } else if (lhi) { 264 - /* 64-bit wide address, treat as disabled */ 265 - pci_write_config_dword(dev, reg, 266 - l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK); 267 - pci_write_config_dword(dev, reg+4, 0); 268 - res->start = 0; 269 - res->end = sz; 270 - } 271 - #endif 272 - } 331 + pos += __pci_read_base(dev, pci_bar_unknown, res, reg); 273 332 } 333 + 274 334 if (rom) { 335 + struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; 275 336 dev->rom_base_reg = rom; 276 - res = &dev->resource[PCI_ROM_RESOURCE]; 277 - res->name = pci_name(dev); 278 - pci_read_config_dword(dev, rom, &l); 279 - pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE); 280 - pci_read_config_dword(dev, rom, &sz); 281 - pci_write_config_dword(dev, rom, l); 282 - if (l == 0xffffffff) 283 - l = 0; 284 - if (sz && sz != 0xffffffff) { 285 - sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK); 286 - if (sz) { 287 - res->flags = (l & IORESOURCE_ROM_ENABLE) | 288 - IORESOURCE_MEM | IORESOURCE_PREFETCH | 289 - IORESOURCE_READONLY | IORESOURCE_CACHEABLE | 290 - IORESOURCE_SIZEALIGN; 291 - res->start = l & PCI_ROM_ADDRESS_MASK; 292 - res->end = res->start + (unsigned long) sz; 293 - } 294 - } 337 + res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | 338 + IORESOURCE_READONLY | IORESOURCE_CACHEABLE | 339 + IORESOURCE_SIZEALIGN; 340 + __pci_read_base(dev, pci_bar_mem32, res, rom); 295 341 } 296 342 } 297 343 ··· 1057 1053 } 1058 1054 } 1059 1055 1060 - if (bus->self) 1056 + /* only one slot has pcie device */ 1057 + if (bus->self && nr) 1061 1058 pcie_aspm_init_link_state(bus->self); 1062 1059 1063 1060 return nr;
+13
drivers/pci/quirks.c
··· 923 923 } 924 924 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 925 925 926 + /* 927 + * Some ATA devices break if put into D3 928 + */ 929 + 930 + static void __devinit quirk_no_ata_d3(struct pci_dev *pdev) 931 + { 932 + /* Quirk the legacy ATA devices only. The AHCI ones are ok */ 933 + if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) 934 + pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; 935 + } 936 + DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, quirk_no_ata_d3); 937 + DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, quirk_no_ata_d3); 938 + 926 939 /* This was originally an Alpha specific thing, but it really fits here. 927 940 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 928 941 */
+1
include/acpi/actbl.h
··· 277 277 #define BAF_LEGACY_DEVICES 0x0001 278 278 #define BAF_8042_KEYBOARD_CONTROLLER 0x0002 279 279 #define BAF_MSI_NOT_SUPPORTED 0x0008 280 + #define BAF_PCIE_ASPM_CONTROL 0x0010 280 281 281 282 #define FADT2_REVISION_ID 3 282 283 #define FADT2_MINUS_REVISION_ID 2
+2
include/asm-arm/dma-mapping.h
··· 7 7 8 8 #include <linux/scatterlist.h> 9 9 10 + #include <asm-generic/dma-coherent.h> 11 + 10 12 /* 11 13 * DMA-consistent mapping functions. These allocate/free a region of 12 14 * uncached, unwrite-buffered mapped memory space for use with DMA
+2
include/asm-cris/dma-mapping.h
··· 14 14 #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) 15 15 16 16 #ifdef CONFIG_PCI 17 + #include <asm-generic/dma-coherent.h> 18 + 17 19 void *dma_alloc_coherent(struct device *dev, size_t size, 18 20 dma_addr_t *dma_handle, gfp_t flag); 19 21
+32
include/asm-generic/dma-coherent.h
··· 1 + #ifndef DMA_COHERENT_H 2 + #define DMA_COHERENT_H 3 + 4 + #ifdef CONFIG_HAVE_GENERIC_DMA_COHERENT 5 + /* 6 + * These two functions are only for dma allocator. 7 + * Don't use them in device drivers. 8 + */ 9 + int dma_alloc_from_coherent(struct device *dev, ssize_t size, 10 + dma_addr_t *dma_handle, void **ret); 11 + int dma_release_from_coherent(struct device *dev, int order, void *vaddr); 12 + 13 + /* 14 + * Standard interface 15 + */ 16 + #define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY 17 + extern int 18 + dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr, 19 + dma_addr_t device_addr, size_t size, int flags); 20 + 21 + extern void 22 + dma_release_declared_memory(struct device *dev); 23 + 24 + extern void * 25 + dma_mark_declared_memory_occupied(struct device *dev, 26 + dma_addr_t device_addr, size_t size); 27 + #else 28 + #define dma_alloc_from_coherent(dev, size, handle, ret) (0) 29 + #define dma_release_from_coherent(dev, order, vaddr) (0) 30 + #endif 31 + 32 + #endif
+1
include/asm-sh/dma-mapping.h
··· 5 5 #include <linux/scatterlist.h> 6 6 #include <asm/cacheflush.h> 7 7 #include <asm/io.h> 8 + #include <asm-generic/dma-coherent.h> 8 9 9 10 extern struct bus_type pci_bus_type; 10 11
+1 -21
include/asm-x86/dma-mapping.h
··· 249 249 250 250 #define dma_is_consistent(d, h) (1) 251 251 252 - #ifdef CONFIG_X86_32 253 - # define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY 254 - struct dma_coherent_mem { 255 - void *virt_base; 256 - u32 device_base; 257 - int size; 258 - int flags; 259 - unsigned long *bitmap; 260 - }; 261 - 262 - extern int 263 - dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr, 264 - dma_addr_t device_addr, size_t size, int flags); 265 - 266 - extern void 267 - dma_release_declared_memory(struct device *dev); 268 - 269 - extern void * 270 - dma_mark_declared_memory_occupied(struct device *dev, 271 - dma_addr_t device_addr, size_t size); 272 - #endif /* CONFIG_X86_32 */ 252 + #include <asm-generic/dma-coherent.h> 273 253 #endif
+1
include/linux/iommu-helper.h
··· 8 8 unsigned long align_mask); 9 9 extern void iommu_area_free(unsigned long *map, unsigned long start, 10 10 unsigned int nr); 11 + extern unsigned long iommu_num_pages(unsigned long addr, unsigned long len);
+5
include/linux/pci-aspm.h
··· 27 27 extern void pcie_aspm_exit_link_state(struct pci_dev *pdev); 28 28 extern void pcie_aspm_pm_state_change(struct pci_dev *pdev); 29 29 extern void pci_disable_link_state(struct pci_dev *pdev, int state); 30 + extern void pcie_no_aspm(void); 30 31 #else 31 32 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) 32 33 { ··· 39 38 { 40 39 } 41 40 static inline void pci_disable_link_state(struct pci_dev *pdev, int state) 41 + { 42 + } 43 + 44 + static inline void pcie_no_aspm(void) 42 45 { 43 46 } 44 47 #endif
+2
include/linux/pci.h
··· 124 124 * generation too. 125 125 */ 126 126 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1, 127 + /* Device configuration is irrevocably lost if disabled into D3 */ 128 + PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2, 127 129 }; 128 130 129 131 typedef unsigned short __bitwise pci_bus_flags_t;
+1
include/linux/pci_regs.h
··· 374 374 #define PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */ 375 375 #define PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */ 376 376 #define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */ 377 + #define PCI_EXP_DEVCAP_RBER 0x8000 /* Role-Based Error Reporting */ 377 378 #define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */ 378 379 #define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */ 379 380 #define PCI_EXP_DEVCTL 8 /* Device Control */
+4
init/Kconfig
··· 802 802 803 803 endmenu # General setup 804 804 805 + config HAVE_GENERIC_DMA_COHERENT 806 + bool 807 + default n 808 + 805 809 config SLABINFO 806 810 bool 807 811 depends on PROC_FS
+1
kernel/Makefile
··· 84 84 obj-$(CONFIG_TASKSTATS) += taskstats.o tsacct.o 85 85 obj-$(CONFIG_MARKERS) += marker.o 86 86 obj-$(CONFIG_LATENCYTOP) += latencytop.o 87 + obj-$(CONFIG_HAVE_GENERIC_DMA_COHERENT) += dma-coherent.o 87 88 obj-$(CONFIG_FTRACE) += trace/ 88 89 obj-$(CONFIG_TRACING) += trace/ 89 90 obj-$(CONFIG_SMP) += sched_cpupri.o
+154
kernel/dma-coherent.c
··· 1 + /* 2 + * Coherent per-device memory handling. 3 + * Borrowed from i386 4 + */ 5 + #include <linux/kernel.h> 6 + #include <linux/dma-mapping.h> 7 + 8 + struct dma_coherent_mem { 9 + void *virt_base; 10 + u32 device_base; 11 + int size; 12 + int flags; 13 + unsigned long *bitmap; 14 + }; 15 + 16 + int dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr, 17 + dma_addr_t device_addr, size_t size, int flags) 18 + { 19 + void __iomem *mem_base = NULL; 20 + int pages = size >> PAGE_SHIFT; 21 + int bitmap_size = BITS_TO_LONGS(pages) * sizeof(long); 22 + 23 + if ((flags & (DMA_MEMORY_MAP | DMA_MEMORY_IO)) == 0) 24 + goto out; 25 + if (!size) 26 + goto out; 27 + if (dev->dma_mem) 28 + goto out; 29 + 30 + /* FIXME: this routine just ignores DMA_MEMORY_INCLUDES_CHILDREN */ 31 + 32 + mem_base = ioremap(bus_addr, size); 33 + if (!mem_base) 34 + goto out; 35 + 36 + dev->dma_mem = kzalloc(sizeof(struct dma_coherent_mem), GFP_KERNEL); 37 + if (!dev->dma_mem) 38 + goto out; 39 + dev->dma_mem->bitmap = kzalloc(bitmap_size, GFP_KERNEL); 40 + if (!dev->dma_mem->bitmap) 41 + goto free1_out; 42 + 43 + dev->dma_mem->virt_base = mem_base; 44 + dev->dma_mem->device_base = device_addr; 45 + dev->dma_mem->size = pages; 46 + dev->dma_mem->flags = flags; 47 + 48 + if (flags & DMA_MEMORY_MAP) 49 + return DMA_MEMORY_MAP; 50 + 51 + return DMA_MEMORY_IO; 52 + 53 + free1_out: 54 + kfree(dev->dma_mem); 55 + out: 56 + if (mem_base) 57 + iounmap(mem_base); 58 + return 0; 59 + } 60 + EXPORT_SYMBOL(dma_declare_coherent_memory); 61 + 62 + void dma_release_declared_memory(struct device *dev) 63 + { 64 + struct dma_coherent_mem *mem = dev->dma_mem; 65 + 66 + if (!mem) 67 + return; 68 + dev->dma_mem = NULL; 69 + iounmap(mem->virt_base); 70 + kfree(mem->bitmap); 71 + kfree(mem); 72 + } 73 + EXPORT_SYMBOL(dma_release_declared_memory); 74 + 75 + void *dma_mark_declared_memory_occupied(struct device *dev, 76 + dma_addr_t device_addr, size_t size) 77 + { 78 + struct dma_coherent_mem *mem = dev->dma_mem; 79 + int pos, err; 80 + int pages = (size + (device_addr & ~PAGE_MASK) + PAGE_SIZE - 1); 81 + 82 + pages >>= PAGE_SHIFT; 83 + 84 + if (!mem) 85 + return ERR_PTR(-EINVAL); 86 + 87 + pos = (device_addr - mem->device_base) >> PAGE_SHIFT; 88 + err = bitmap_allocate_region(mem->bitmap, pos, get_order(pages)); 89 + if (err != 0) 90 + return ERR_PTR(err); 91 + return mem->virt_base + (pos << PAGE_SHIFT); 92 + } 93 + EXPORT_SYMBOL(dma_mark_declared_memory_occupied); 94 + 95 + /** 96 + * Try to allocate memory from the per-device coherent area. 97 + * 98 + * @dev: device from which we allocate memory 99 + * @size: size of requested memory area 100 + * @dma_handle: This will be filled with the correct dma handle 101 + * @ret: This pointer will be filled with the virtual address 102 + * to allocated area. 103 + * 104 + * This function should be only called from per-arch %dma_alloc_coherent() 105 + * to support allocation from per-device coherent memory pools. 106 + * 107 + * Returns 0 if dma_alloc_coherent should continue with allocating from 108 + * generic memory areas, or !0 if dma_alloc_coherent should return %ret. 109 + */ 110 + int dma_alloc_from_coherent(struct device *dev, ssize_t size, 111 + dma_addr_t *dma_handle, void **ret) 112 + { 113 + struct dma_coherent_mem *mem = dev ? dev->dma_mem : NULL; 114 + int order = get_order(size); 115 + 116 + if (mem) { 117 + int page = bitmap_find_free_region(mem->bitmap, mem->size, 118 + order); 119 + if (page >= 0) { 120 + *dma_handle = mem->device_base + (page << PAGE_SHIFT); 121 + *ret = mem->virt_base + (page << PAGE_SHIFT); 122 + memset(*ret, 0, size); 123 + } else if (mem->flags & DMA_MEMORY_EXCLUSIVE) 124 + *ret = NULL; 125 + } 126 + return (mem != NULL); 127 + } 128 + 129 + /** 130 + * Try to free the memory allocated from per-device coherent memory pool. 131 + * @dev: device from which the memory was allocated 132 + * @order: the order of pages allocated 133 + * @vaddr: virtual address of allocated pages 134 + * 135 + * This checks whether the memory was allocated from the per-device 136 + * coherent memory pool and if so, releases that memory. 137 + * 138 + * Returns 1 if we correctly released the memory, or 0 if 139 + * %dma_release_coherent() should proceed with releasing memory from 140 + * generic pools. 141 + */ 142 + int dma_release_from_coherent(struct device *dev, int order, void *vaddr) 143 + { 144 + struct dma_coherent_mem *mem = dev ? dev->dma_mem : NULL; 145 + 146 + if (mem && vaddr >= mem->virt_base && vaddr < 147 + (mem->virt_base + (mem->size << PAGE_SHIFT))) { 148 + int page = (vaddr - mem->virt_base) >> PAGE_SHIFT; 149 + 150 + bitmap_release_region(mem->bitmap, page, order); 151 + return 1; 152 + } 153 + return 0; 154 + }
+8
lib/iommu-helper.c
··· 80 80 } 81 81 } 82 82 EXPORT_SYMBOL(iommu_area_free); 83 + 84 + unsigned long iommu_num_pages(unsigned long addr, unsigned long len) 85 + { 86 + unsigned long size = roundup((addr & ~PAGE_MASK) + len, PAGE_SIZE); 87 + 88 + return size >> PAGE_SHIFT; 89 + } 90 + EXPORT_SYMBOL(iommu_num_pages);