tjh.dev / kernel
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RDMA/bnxt_re: introduce wqe mode to select execution path

The bnxt_re driver need to decide on how much SQ and RQ memory should to
be allocated and which wqe posting/polling algorithm to use.

Making changes to set the wqe-mode to a default value during device
registration sequence. The wqe-mode is passed to the lower layer driver as
well. Going forward in the lower layer driver wqe-mode will be used to
decide execution path. Initializing the wqe-mode to static wqe type for
now.

Link: https://lore.kernel.org/r/1594822619-4098-2-git-send-email-devesh.sharma@broadcom.com
Signed-off-by: Devesh Sharma <devesh.sharma@broadcom.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>

authored by

Devesh Sharma and committed by
Jason Gunthorpe 1da968e0 ca4beeee

+42 -17
+1
drivers/infiniband/hw/bnxt_re/ib_verbs.c
··· 1183 1183 goto out; 1184 1184 } 1185 1185 qplqp->type = (u8)qptype; 1186 + qplqp->wqe_mode = rdev->chip_ctx->modes.wqe_mode; 1186 1187 1187 1188 if (init_attr->qp_type == IB_QPT_RC) { 1188 1189 qplqp->max_rd_atomic = dev_attr->max_qp_rd_atom;
+17 -6
drivers/infiniband/hw/bnxt_re/main.c
··· 82 82 static void bnxt_re_dealloc_driver(struct ib_device *ib_dev); 83 83 static void bnxt_re_stop_irq(void *handle); 84 84 85 + static void bnxt_re_set_drv_mode(struct bnxt_re_dev *rdev, u8 mode) 86 + { 87 + struct bnxt_qplib_chip_ctx *cctx; 88 + 89 + cctx = rdev->chip_ctx; 90 + cctx->modes.wqe_mode = bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx) ? 91 + mode : BNXT_QPLIB_WQE_MODE_STATIC; 92 + } 93 + 85 94 static void bnxt_re_destroy_chip_ctx(struct bnxt_re_dev *rdev) 86 95 { 87 96 struct bnxt_qplib_chip_ctx *chip_ctx; ··· 106 97 kfree(chip_ctx); 107 98 } 108 99 109 - static int bnxt_re_setup_chip_ctx(struct bnxt_re_dev *rdev) 100 + static int bnxt_re_setup_chip_ctx(struct bnxt_re_dev *rdev, u8 wqe_mode) 110 101 { 111 102 struct bnxt_qplib_chip_ctx *chip_ctx; 112 103 struct bnxt_en_dev *en_dev; ··· 126 117 rdev->qplib_res.cctx = rdev->chip_ctx; 127 118 rdev->rcfw.res = &rdev->qplib_res; 128 119 120 + bnxt_re_set_drv_mode(rdev, wqe_mode); 129 121 return 0; 130 122 } 131 123 ··· 1396 1386 schedule_delayed_work(&rdev->worker, msecs_to_jiffies(30000)); 1397 1387 } 1398 1388 1399 - static int bnxt_re_dev_init(struct bnxt_re_dev *rdev) 1389 + static int bnxt_re_dev_init(struct bnxt_re_dev *rdev, u8 wqe_mode) 1400 1390 { 1401 1391 struct bnxt_qplib_creq_ctx *creq; 1402 1392 struct bnxt_re_ring_attr rattr; ··· 1416 1406 } 1417 1407 set_bit(BNXT_RE_FLAG_NETDEV_REGISTERED, &rdev->flags); 1418 1408 1419 - rc = bnxt_re_setup_chip_ctx(rdev); 1409 + rc = bnxt_re_setup_chip_ctx(rdev, wqe_mode); 1420 1410 if (rc) { 1421 1411 ibdev_err(&rdev->ibdev, "Failed to get chip context\n"); 1422 1412 return -EINVAL; ··· 1595 1585 } 1596 1586 1597 1587 static int bnxt_re_add_device(struct bnxt_re_dev **rdev, 1598 - struct net_device *netdev) 1588 + struct net_device *netdev, u8 wqe_mode) 1599 1589 { 1600 1590 int rc; 1601 1591 ··· 1609 1599 } 1610 1600 1611 1601 pci_dev_get((*rdev)->en_dev->pdev); 1612 - rc = bnxt_re_dev_init(*rdev); 1602 + rc = bnxt_re_dev_init(*rdev, wqe_mode); 1613 1603 if (rc) { 1614 1604 pci_dev_put((*rdev)->en_dev->pdev); 1615 1605 bnxt_re_dev_unreg(*rdev); ··· 1721 1711 case NETDEV_REGISTER: 1722 1712 if (rdev) 1723 1713 break; 1724 - rc = bnxt_re_add_device(&rdev, real_dev); 1714 + rc = bnxt_re_add_device(&rdev, real_dev, 1715 + BNXT_QPLIB_WQE_MODE_STATIC); 1725 1716 if (!rc) 1726 1717 sch_work = true; 1727 1718 release = false;
+2 -1
drivers/infiniband/hw/bnxt_re/qplib_fp.h
··· 224 224 u32 id; 225 225 u8 type; 226 226 u8 sig_type; 227 - u32 modify_flags; 227 + u8 wqe_mode; 228 228 u8 state; 229 229 u8 cur_qp_state; 230 + u64 modify_flags; 230 231 u32 max_inline_data; 231 232 u32 mtu; 232 233 u8 path_mtu;
+22 -10
drivers/infiniband/hw/bnxt_re/qplib_res.h
··· 41 41 42 42 extern const struct bnxt_qplib_gid bnxt_qplib_gid_zero; 43 43 44 + #define CHIP_NUM_57508 0x1750 45 + #define CHIP_NUM_57504 0x1751 46 + #define CHIP_NUM_57502 0x1752 47 + 48 + enum bnxt_qplib_wqe_mode { 49 + BNXT_QPLIB_WQE_MODE_STATIC = 0x00, 50 + BNXT_QPLIB_WQE_MODE_VARIABLE = 0x01, 51 + BNXT_QPLIB_WQE_MODE_INVALID = 0x02 52 + }; 53 + 54 + struct bnxt_qplib_drv_modes { 55 + u8 wqe_mode; 56 + /* Other modes to follow here */ 57 + }; 58 + 59 + struct bnxt_qplib_chip_ctx { 60 + u16 chip_num; 61 + u8 chip_rev; 62 + u8 chip_metal; 63 + struct bnxt_qplib_drv_modes modes; 64 + }; 65 + 44 66 #define PTR_CNT_PER_PG (PAGE_SIZE / sizeof(void *)) 45 67 #define PTR_MAX_IDX_PER_PG (PTR_CNT_PER_PG - 1) 46 68 #define PTR_PG(x) (((x) & ~PTR_MAX_IDX_PER_PG) / PTR_CNT_PER_PG) ··· 251 229 struct bnxt_qplib_vf_res vf_res; 252 230 u64 hwrm_intf_ver; 253 231 }; 254 - 255 - struct bnxt_qplib_chip_ctx { 256 - u16 chip_num; 257 - u8 chip_rev; 258 - u8 chip_metal; 259 - }; 260 - 261 - #define CHIP_NUM_57508 0x1750 262 - #define CHIP_NUM_57504 0x1751 263 - #define CHIP_NUM_57502 0x1752 264 232 265 233 struct bnxt_qplib_res { 266 234 struct pci_dev *pdev;