Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"I'm briefly working between holidays and LCA, so this is close to a
couple of weeks of fixes,
Two sets of amdkfd fixes, this is a new feature this kernel, and this
pull fixes a few issues since it got merged, ordering when built-in to
kernel and also the iommu vs gpu ordering patch, it also reworks the
ioctl before the initial release.
Otherwise:
- radeon: some misc fixes all over, hdmi, 4k, dpm
- nouveau: mcp77 init fixes, oops fix, bug on fix, msi fix
- i915: power fixes, revert VGACNTR patch
Probably be quiteer next week since I'll be at LCA anyways"
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (33 commits)
drm/amdkfd: rewrite kfd_ioctl() according to drm_ioctl()
drm/amdkfd: reformat IOCTL definitions to drm-style
drm/amdkfd: Do copy_to/from_user in general kfd_ioctl()
drm/radeon: integer underflow in radeon_cp_dispatch_texture()
drm/radeon: adjust default bapm settings for KV
drm/radeon: properly filter DP1.2 4k modes on non-DP1.2 hw
drm/radeon: fix sad_count check for dce3
drm/radeon: KV has three PPLLs (v2)
drm/amdkfd: unmap VMID<-->PASID when relesing VMID (non-HWS)
drm/radeon: Init amdkfd only if it was compiled
amdkfd: actually allocate longs for the pasid bitmask
drm/nouveau/nouveau: Do not BUG_ON(!spin_is_locked()) on UP
drm/nv4c/mc: disable msi
drm/nouveau/fb/ram/mcp77: enable NISO poller
drm/nouveau/fb/ram/mcp77: use carveout reg to determine size
drm/nouveau/fb/ram/mcp77: subclass nouveau_ram
drm/nouveau: wake up the card if necessary during gem callbacks
drm/nouveau/device: Add support for GK208B, resolves bug 86935
drm/nouveau: fix missing return statement in nouveau_ttm_tt_unpopulate
drm/nouveau/bios: fix oops on pre-nv50 chipsets
...
+415
-263
+4
-2
drivers/Makefile
+4
-2
drivers/Makefile
···
50
50
obj-y += tty/
51
51
obj-y += char/
52
52
53
-
# gpu/ comes after char for AGP vs DRM startup
53
+
# iommu/ comes before gpu as gpu are using iommu controllers
54
+
obj-$(CONFIG_IOMMU_SUPPORT) += iommu/
55
+
56
+
# gpu/ comes after char for AGP vs DRM startup and after iommu
54
57
obj-y += gpu/
55
58
56
59
obj-$(CONFIG_CONNECTOR) += connector/
···
144
141
145
142
obj-$(CONFIG_MAILBOX) += mailbox/
146
143
obj-$(CONFIG_HWSPINLOCK) += hwspinlock/
147
-
obj-$(CONFIG_IOMMU_SUPPORT) += iommu/
148
144
obj-$(CONFIG_REMOTEPROC) += remoteproc/
149
145
obj-$(CONFIG_RPMSG) += rpmsg/
150
146
+1
-1
drivers/gpu/drm/Makefile
+1
-1
drivers/gpu/drm/Makefile
···
37
37
obj-$(CONFIG_DRM_TTM) += ttm/
38
38
obj-$(CONFIG_DRM_TDFX) += tdfx/
39
39
obj-$(CONFIG_DRM_R128) += r128/
40
+
obj-$(CONFIG_HSA_AMD) += amd/amdkfd/
40
41
obj-$(CONFIG_DRM_RADEON)+= radeon/
41
42
obj-$(CONFIG_DRM_MGA) += mga/
42
43
obj-$(CONFIG_DRM_I810) += i810/
···
68
67
obj-y += i2c/
69
68
obj-y += panel/
70
69
obj-y += bridge/
71
-
obj-$(CONFIG_HSA_AMD) += amd/amdkfd/
+169
-149
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+169
-149
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
···
31
31
#include <uapi/linux/kfd_ioctl.h>
32
32
#include <linux/time.h>
33
33
#include <linux/mm.h>
34
-
#include <linux/uaccess.h>
35
34
#include <uapi/asm-generic/mman-common.h>
36
35
#include <asm/processor.h>
37
36
#include "kfd_priv.h"
···
126
127
return 0;
127
128
}
128
129
129
-
static long kfd_ioctl_get_version(struct file *filep, struct kfd_process *p,
130
-
void __user *arg)
130
+
static int kfd_ioctl_get_version(struct file *filep, struct kfd_process *p,
131
+
void *data)
131
132
{
132
-
struct kfd_ioctl_get_version_args args;
133
+
struct kfd_ioctl_get_version_args *args = data;
133
134
int err = 0;
134
135
135
-
args.major_version = KFD_IOCTL_MAJOR_VERSION;
136
-
args.minor_version = KFD_IOCTL_MINOR_VERSION;
137
-
138
-
if (copy_to_user(arg, &args, sizeof(args)))
139
-
err = -EFAULT;
136
+
args->major_version = KFD_IOCTL_MAJOR_VERSION;
137
+
args->minor_version = KFD_IOCTL_MINOR_VERSION;
140
138
141
139
return err;
142
140
}
···
217
221
return 0;
218
222
}
219
223
220
-
static long kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p,
221
-
void __user *arg)
224
+
static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p,
225
+
void *data)
222
226
{
223
-
struct kfd_ioctl_create_queue_args args;
227
+
struct kfd_ioctl_create_queue_args *args = data;
224
228
struct kfd_dev *dev;
225
229
int err = 0;
226
230
unsigned int queue_id;
···
229
233
230
234
memset(&q_properties, 0, sizeof(struct queue_properties));
231
235
232
-
if (copy_from_user(&args, arg, sizeof(args)))
233
-
return -EFAULT;
234
-
235
236
pr_debug("kfd: creating queue ioctl\n");
236
237
237
-
err = set_queue_properties_from_user(&q_properties, &args);
238
+
err = set_queue_properties_from_user(&q_properties, args);
238
239
if (err)
239
240
return err;
240
241
241
-
dev = kfd_device_by_id(args.gpu_id);
242
+
dev = kfd_device_by_id(args->gpu_id);
242
243
if (dev == NULL)
243
244
return -EINVAL;
244
245
···
243
250
244
251
pdd = kfd_bind_process_to_device(dev, p);
245
252
if (IS_ERR(pdd)) {
246
-
err = PTR_ERR(pdd);
253
+
err = -ESRCH;
247
254
goto err_bind_process;
248
255
}
249
256
···
256
263
if (err != 0)
257
264
goto err_create_queue;
258
265
259
-
args.queue_id = queue_id;
266
+
args->queue_id = queue_id;
260
267
261
268
/* Return gpu_id as doorbell offset for mmap usage */
262
-
args.doorbell_offset = args.gpu_id << PAGE_SHIFT;
263
-
264
-
if (copy_to_user(arg, &args, sizeof(args))) {
265
-
err = -EFAULT;
266
-
goto err_copy_args_out;
267
-
}
269
+
args->doorbell_offset = args->gpu_id << PAGE_SHIFT;
268
270
269
271
mutex_unlock(&p->mutex);
270
272
271
-
pr_debug("kfd: queue id %d was created successfully\n", args.queue_id);
273
+
pr_debug("kfd: queue id %d was created successfully\n", args->queue_id);
272
274
273
275
pr_debug("ring buffer address == 0x%016llX\n",
274
-
args.ring_base_address);
276
+
args->ring_base_address);
275
277
276
278
pr_debug("read ptr address == 0x%016llX\n",
277
-
args.read_pointer_address);
279
+
args->read_pointer_address);
278
280
279
281
pr_debug("write ptr address == 0x%016llX\n",
280
-
args.write_pointer_address);
282
+
args->write_pointer_address);
281
283
282
284
return 0;
283
285
284
-
err_copy_args_out:
285
-
pqm_destroy_queue(&p->pqm, queue_id);
286
286
err_create_queue:
287
287
err_bind_process:
288
288
mutex_unlock(&p->mutex);
···
283
297
}
284
298
285
299
static int kfd_ioctl_destroy_queue(struct file *filp, struct kfd_process *p,
286
-
void __user *arg)
300
+
void *data)
287
301
{
288
302
int retval;
289
-
struct kfd_ioctl_destroy_queue_args args;
290
-
291
-
if (copy_from_user(&args, arg, sizeof(args)))
292
-
return -EFAULT;
303
+
struct kfd_ioctl_destroy_queue_args *args = data;
293
304
294
305
pr_debug("kfd: destroying queue id %d for PASID %d\n",
295
-
args.queue_id,
306
+
args->queue_id,
296
307
p->pasid);
297
308
298
309
mutex_lock(&p->mutex);
299
310
300
-
retval = pqm_destroy_queue(&p->pqm, args.queue_id);
311
+
retval = pqm_destroy_queue(&p->pqm, args->queue_id);
301
312
302
313
mutex_unlock(&p->mutex);
303
314
return retval;
304
315
}
305
316
306
317
static int kfd_ioctl_update_queue(struct file *filp, struct kfd_process *p,
307
-
void __user *arg)
318
+
void *data)
308
319
{
309
320
int retval;
310
-
struct kfd_ioctl_update_queue_args args;
321
+
struct kfd_ioctl_update_queue_args *args = data;
311
322
struct queue_properties properties;
312
323
313
-
if (copy_from_user(&args, arg, sizeof(args)))
314
-
return -EFAULT;
315
-
316
-
if (args.queue_percentage > KFD_MAX_QUEUE_PERCENTAGE) {
324
+
if (args->queue_percentage > KFD_MAX_QUEUE_PERCENTAGE) {
317
325
pr_err("kfd: queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n");
318
326
return -EINVAL;
319
327
}
320
328
321
-
if (args.queue_priority > KFD_MAX_QUEUE_PRIORITY) {
329
+
if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) {
322
330
pr_err("kfd: queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n");
323
331
return -EINVAL;
324
332
}
325
333
326
-
if ((args.ring_base_address) &&
334
+
if ((args->ring_base_address) &&
327
335
(!access_ok(VERIFY_WRITE,
328
-
(const void __user *) args.ring_base_address,
336
+
(const void __user *) args->ring_base_address,
329
337
sizeof(uint64_t)))) {
330
338
pr_err("kfd: can't access ring base address\n");
331
339
return -EFAULT;
332
340
}
333
341
334
-
if (!is_power_of_2(args.ring_size) && (args.ring_size != 0)) {
342
+
if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) {
335
343
pr_err("kfd: ring size must be a power of 2 or 0\n");
336
344
return -EINVAL;
337
345
}
338
346
339
-
properties.queue_address = args.ring_base_address;
340
-
properties.queue_size = args.ring_size;
341
-
properties.queue_percent = args.queue_percentage;
342
-
properties.priority = args.queue_priority;
347
+
properties.queue_address = args->ring_base_address;
348
+
properties.queue_size = args->ring_size;
349
+
properties.queue_percent = args->queue_percentage;
350
+
properties.priority = args->queue_priority;
343
351
344
352
pr_debug("kfd: updating queue id %d for PASID %d\n",
345
-
args.queue_id, p->pasid);
353
+
args->queue_id, p->pasid);
346
354
347
355
mutex_lock(&p->mutex);
348
356
349
-
retval = pqm_update_queue(&p->pqm, args.queue_id, &properties);
357
+
retval = pqm_update_queue(&p->pqm, args->queue_id, &properties);
350
358
351
359
mutex_unlock(&p->mutex);
352
360
353
361
return retval;
354
362
}
355
363
356
-
static long kfd_ioctl_set_memory_policy(struct file *filep,
357
-
struct kfd_process *p, void __user *arg)
364
+
static int kfd_ioctl_set_memory_policy(struct file *filep,
365
+
struct kfd_process *p, void *data)
358
366
{
359
-
struct kfd_ioctl_set_memory_policy_args args;
367
+
struct kfd_ioctl_set_memory_policy_args *args = data;
360
368
struct kfd_dev *dev;
361
369
int err = 0;
362
370
struct kfd_process_device *pdd;
363
371
enum cache_policy default_policy, alternate_policy;
364
372
365
-
if (copy_from_user(&args, arg, sizeof(args)))
366
-
return -EFAULT;
367
-
368
-
if (args.default_policy != KFD_IOC_CACHE_POLICY_COHERENT
369
-
&& args.default_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) {
373
+
if (args->default_policy != KFD_IOC_CACHE_POLICY_COHERENT
374
+
&& args->default_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) {
370
375
return -EINVAL;
371
376
}
372
377
373
-
if (args.alternate_policy != KFD_IOC_CACHE_POLICY_COHERENT
374
-
&& args.alternate_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) {
378
+
if (args->alternate_policy != KFD_IOC_CACHE_POLICY_COHERENT
379
+
&& args->alternate_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) {
375
380
return -EINVAL;
376
381
}
377
382
378
-
dev = kfd_device_by_id(args.gpu_id);
383
+
dev = kfd_device_by_id(args->gpu_id);
379
384
if (dev == NULL)
380
385
return -EINVAL;
381
386
···
374
397
375
398
pdd = kfd_bind_process_to_device(dev, p);
376
399
if (IS_ERR(pdd)) {
377
-
err = PTR_ERR(pdd);
400
+
err = -ESRCH;
378
401
goto out;
379
402
}
380
403
381
-
default_policy = (args.default_policy == KFD_IOC_CACHE_POLICY_COHERENT)
404
+
default_policy = (args->default_policy == KFD_IOC_CACHE_POLICY_COHERENT)
382
405
? cache_policy_coherent : cache_policy_noncoherent;
383
406
384
407
alternate_policy =
385
-
(args.alternate_policy == KFD_IOC_CACHE_POLICY_COHERENT)
408
+
(args->alternate_policy == KFD_IOC_CACHE_POLICY_COHERENT)
386
409
? cache_policy_coherent : cache_policy_noncoherent;
387
410
388
411
if (!dev->dqm->set_cache_memory_policy(dev->dqm,
389
412
&pdd->qpd,
390
413
default_policy,
391
414
alternate_policy,
392
-
(void __user *)args.alternate_aperture_base,
393
-
args.alternate_aperture_size))
415
+
(void __user *)args->alternate_aperture_base,
416
+
args->alternate_aperture_size))
394
417
err = -EINVAL;
395
418
396
419
out:
···
399
422
return err;
400
423
}
401
424
402
-
static long kfd_ioctl_get_clock_counters(struct file *filep,
403
-
struct kfd_process *p, void __user *arg)
425
+
static int kfd_ioctl_get_clock_counters(struct file *filep,
426
+
struct kfd_process *p, void *data)
404
427
{
405
-
struct kfd_ioctl_get_clock_counters_args args;
428
+
struct kfd_ioctl_get_clock_counters_args *args = data;
406
429
struct kfd_dev *dev;
407
430
struct timespec time;
408
431
409
-
if (copy_from_user(&args, arg, sizeof(args)))
410
-
return -EFAULT;
411
-
412
-
dev = kfd_device_by_id(args.gpu_id);
432
+
dev = kfd_device_by_id(args->gpu_id);
413
433
if (dev == NULL)
414
434
return -EINVAL;
415
435
416
436
/* Reading GPU clock counter from KGD */
417
-
args.gpu_clock_counter = kfd2kgd->get_gpu_clock_counter(dev->kgd);
437
+
args->gpu_clock_counter = kfd2kgd->get_gpu_clock_counter(dev->kgd);
418
438
419
439
/* No access to rdtsc. Using raw monotonic time */
420
440
getrawmonotonic(&time);
421
-
args.cpu_clock_counter = (uint64_t)timespec_to_ns(&time);
441
+
args->cpu_clock_counter = (uint64_t)timespec_to_ns(&time);
422
442
423
443
get_monotonic_boottime(&time);
424
-
args.system_clock_counter = (uint64_t)timespec_to_ns(&time);
444
+
args->system_clock_counter = (uint64_t)timespec_to_ns(&time);
425
445
426
446
/* Since the counter is in nano-seconds we use 1GHz frequency */
427
-
args.system_clock_freq = 1000000000;
428
-
429
-
if (copy_to_user(arg, &args, sizeof(args)))
430
-
return -EFAULT;
447
+
args->system_clock_freq = 1000000000;
431
448
432
449
return 0;
433
450
}
434
451
435
452
436
453
static int kfd_ioctl_get_process_apertures(struct file *filp,
437
-
struct kfd_process *p, void __user *arg)
454
+
struct kfd_process *p, void *data)
438
455
{
439
-
struct kfd_ioctl_get_process_apertures_args args;
456
+
struct kfd_ioctl_get_process_apertures_args *args = data;
440
457
struct kfd_process_device_apertures *pAperture;
441
458
struct kfd_process_device *pdd;
442
459
443
460
dev_dbg(kfd_device, "get apertures for PASID %d", p->pasid);
444
461
445
-
if (copy_from_user(&args, arg, sizeof(args)))
446
-
return -EFAULT;
447
-
448
-
args.num_of_nodes = 0;
462
+
args->num_of_nodes = 0;
449
463
450
464
mutex_lock(&p->mutex);
451
465
···
445
477
/* Run over all pdd of the process */
446
478
pdd = kfd_get_first_process_device_data(p);
447
479
do {
448
-
pAperture = &args.process_apertures[args.num_of_nodes];
480
+
pAperture =
481
+
&args->process_apertures[args->num_of_nodes];
449
482
pAperture->gpu_id = pdd->dev->id;
450
483
pAperture->lds_base = pdd->lds_base;
451
484
pAperture->lds_limit = pdd->lds_limit;
···
456
487
pAperture->scratch_limit = pdd->scratch_limit;
457
488
458
489
dev_dbg(kfd_device,
459
-
"node id %u\n", args.num_of_nodes);
490
+
"node id %u\n", args->num_of_nodes);
460
491
dev_dbg(kfd_device,
461
492
"gpu id %u\n", pdd->dev->id);
462
493
dev_dbg(kfd_device,
···
472
503
dev_dbg(kfd_device,
473
504
"scratch_limit %llX\n", pdd->scratch_limit);
474
505
475
-
args.num_of_nodes++;
506
+
args->num_of_nodes++;
476
507
} while ((pdd = kfd_get_next_process_device_data(p, pdd)) != NULL &&
477
-
(args.num_of_nodes < NUM_OF_SUPPORTED_GPUS));
508
+
(args->num_of_nodes < NUM_OF_SUPPORTED_GPUS));
478
509
}
479
510
480
511
mutex_unlock(&p->mutex);
481
512
482
-
if (copy_to_user(arg, &args, sizeof(args)))
483
-
return -EFAULT;
484
-
485
513
return 0;
486
514
}
515
+
516
+
#define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \
517
+
[_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, .cmd_drv = 0, .name = #ioctl}
518
+
519
+
/** Ioctl table */
520
+
static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = {
521
+
AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_VERSION,
522
+
kfd_ioctl_get_version, 0),
523
+
524
+
AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_QUEUE,
525
+
kfd_ioctl_create_queue, 0),
526
+
527
+
AMDKFD_IOCTL_DEF(AMDKFD_IOC_DESTROY_QUEUE,
528
+
kfd_ioctl_destroy_queue, 0),
529
+
530
+
AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_MEMORY_POLICY,
531
+
kfd_ioctl_set_memory_policy, 0),
532
+
533
+
AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_CLOCK_COUNTERS,
534
+
kfd_ioctl_get_clock_counters, 0),
535
+
536
+
AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_PROCESS_APERTURES,
537
+
kfd_ioctl_get_process_apertures, 0),
538
+
539
+
AMDKFD_IOCTL_DEF(AMDKFD_IOC_UPDATE_QUEUE,
540
+
kfd_ioctl_update_queue, 0),
541
+
};
542
+
543
+
#define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls)
487
544
488
545
static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
489
546
{
490
547
struct kfd_process *process;
491
-
long err = -EINVAL;
548
+
amdkfd_ioctl_t *func;
549
+
const struct amdkfd_ioctl_desc *ioctl = NULL;
550
+
unsigned int nr = _IOC_NR(cmd);
551
+
char stack_kdata[128];
552
+
char *kdata = NULL;
553
+
unsigned int usize, asize;
554
+
int retcode = -EINVAL;
492
555
493
-
dev_dbg(kfd_device,
494
-
"ioctl cmd 0x%x (#%d), arg 0x%lx\n",
495
-
cmd, _IOC_NR(cmd), arg);
556
+
if (nr >= AMDKFD_CORE_IOCTL_COUNT)
557
+
goto err_i1;
558
+
559
+
if ((nr >= AMDKFD_COMMAND_START) && (nr < AMDKFD_COMMAND_END)) {
560
+
u32 amdkfd_size;
561
+
562
+
ioctl = &amdkfd_ioctls[nr];
563
+
564
+
amdkfd_size = _IOC_SIZE(ioctl->cmd);
565
+
usize = asize = _IOC_SIZE(cmd);
566
+
if (amdkfd_size > asize)
567
+
asize = amdkfd_size;
568
+
569
+
cmd = ioctl->cmd;
570
+
} else
571
+
goto err_i1;
572
+
573
+
dev_dbg(kfd_device, "ioctl cmd 0x%x (#%d), arg 0x%lx\n", cmd, nr, arg);
496
574
497
575
process = kfd_get_process(current);
498
-
if (IS_ERR(process))
499
-
return PTR_ERR(process);
500
-
501
-
switch (cmd) {
502
-
case KFD_IOC_GET_VERSION:
503
-
err = kfd_ioctl_get_version(filep, process, (void __user *)arg);
504
-
break;
505
-
case KFD_IOC_CREATE_QUEUE:
506
-
err = kfd_ioctl_create_queue(filep, process,
507
-
(void __user *)arg);
508
-
break;
509
-
510
-
case KFD_IOC_DESTROY_QUEUE:
511
-
err = kfd_ioctl_destroy_queue(filep, process,
512
-
(void __user *)arg);
513
-
break;
514
-
515
-
case KFD_IOC_SET_MEMORY_POLICY:
516
-
err = kfd_ioctl_set_memory_policy(filep, process,
517
-
(void __user *)arg);
518
-
break;
519
-
520
-
case KFD_IOC_GET_CLOCK_COUNTERS:
521
-
err = kfd_ioctl_get_clock_counters(filep, process,
522
-
(void __user *)arg);
523
-
break;
524
-
525
-
case KFD_IOC_GET_PROCESS_APERTURES:
526
-
err = kfd_ioctl_get_process_apertures(filep, process,
527
-
(void __user *)arg);
528
-
break;
529
-
530
-
case KFD_IOC_UPDATE_QUEUE:
531
-
err = kfd_ioctl_update_queue(filep, process,
532
-
(void __user *)arg);
533
-
break;
534
-
535
-
default:
536
-
dev_err(kfd_device,
537
-
"unknown ioctl cmd 0x%x, arg 0x%lx)\n",
538
-
cmd, arg);
539
-
err = -EINVAL;
540
-
break;
576
+
if (IS_ERR(process)) {
577
+
dev_dbg(kfd_device, "no process\n");
578
+
goto err_i1;
541
579
}
542
580
543
-
if (err < 0)
544
-
dev_err(kfd_device,
545
-
"ioctl error %ld for ioctl cmd 0x%x (#%d)\n",
546
-
err, cmd, _IOC_NR(cmd));
581
+
/* Do not trust userspace, use our own definition */
582
+
func = ioctl->func;
547
583
548
-
return err;
584
+
if (unlikely(!func)) {
585
+
dev_dbg(kfd_device, "no function\n");
586
+
retcode = -EINVAL;
587
+
goto err_i1;
588
+
}
589
+
590
+
if (cmd & (IOC_IN | IOC_OUT)) {
591
+
if (asize <= sizeof(stack_kdata)) {
592
+
kdata = stack_kdata;
593
+
} else {
594
+
kdata = kmalloc(asize, GFP_KERNEL);
595
+
if (!kdata) {
596
+
retcode = -ENOMEM;
597
+
goto err_i1;
598
+
}
599
+
}
600
+
if (asize > usize)
601
+
memset(kdata + usize, 0, asize - usize);
602
+
}
603
+
604
+
if (cmd & IOC_IN) {
605
+
if (copy_from_user(kdata, (void __user *)arg, usize) != 0) {
606
+
retcode = -EFAULT;
607
+
goto err_i1;
608
+
}
609
+
} else if (cmd & IOC_OUT) {
610
+
memset(kdata, 0, usize);
611
+
}
612
+
613
+
retcode = func(filep, process, kdata);
614
+
615
+
if (cmd & IOC_OUT)
616
+
if (copy_to_user((void __user *)arg, kdata, usize) != 0)
617
+
retcode = -EFAULT;
618
+
619
+
err_i1:
620
+
if (!ioctl)
621
+
dev_dbg(kfd_device, "invalid ioctl: pid=%d, cmd=0x%02x, nr=0x%02x\n",
622
+
task_pid_nr(current), cmd, nr);
623
+
624
+
if (kdata != stack_kdata)
625
+
kfree(kdata);
626
+
627
+
if (retcode)
628
+
dev_dbg(kfd_device, "ret = %d\n", retcode);
629
+
630
+
return retcode;
549
631
}
550
632
551
633
static int kfd_mmap(struct file *filp, struct vm_area_struct *vma)
+26
-2
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+26
-2
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
···
161
161
{
162
162
int bit = qpd->vmid - KFD_VMID_START_OFFSET;
163
163
164
+
/* Release the vmid mapping */
165
+
set_pasid_vmid_mapping(dqm, 0, qpd->vmid);
166
+
164
167
set_bit(bit, (unsigned long *)&dqm->vmid_bitmap);
165
168
qpd->vmid = 0;
166
169
q->properties.vmid = 0;
···
275
272
return retval;
276
273
}
277
274
275
+
pr_debug("kfd: loading mqd to hqd on pipe (%d) queue (%d)\n",
276
+
q->pipe,
277
+
q->queue);
278
+
279
+
retval = mqd->load_mqd(mqd, q->mqd, q->pipe,
280
+
q->queue, q->properties.write_ptr);
281
+
if (retval != 0) {
282
+
deallocate_hqd(dqm, q);
283
+
mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj);
284
+
return retval;
285
+
}
286
+
278
287
return 0;
279
288
}
280
289
···
335
320
{
336
321
int retval;
337
322
struct mqd_manager *mqd;
323
+
bool prev_active = false;
338
324
339
325
BUG_ON(!dqm || !q || !q->mqd);
340
326
···
346
330
return -ENOMEM;
347
331
}
348
332
349
-
retval = mqd->update_mqd(mqd, q->mqd, &q->properties);
350
333
if (q->properties.is_active == true)
334
+
prev_active = true;
335
+
336
+
/*
337
+
*
338
+
* check active state vs. the previous state
339
+
* and modify counter accordingly
340
+
*/
341
+
retval = mqd->update_mqd(mqd, q->mqd, &q->properties);
342
+
if ((q->properties.is_active == true) && (prev_active == false))
351
343
dqm->queue_count++;
352
-
else
344
+
else if ((q->properties.is_active == false) && (prev_active == true))
353
345
dqm->queue_count--;
354
346
355
347
if (sched_policy != KFD_SCHED_POLICY_NO_HWS)
+1
-1
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
+1
-1
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
+1
-1
drivers/gpu/drm/amd/amdkfd/kfd_pasid.c
+1
-1
drivers/gpu/drm/amd/amdkfd/kfd_pasid.c
+18
drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+18
drivers/gpu/drm/amd/amdkfd/kfd_priv.h
···
463
463
bool is_32bit_user_mode;
464
464
};
465
465
466
+
/**
467
+
* Ioctl function type.
468
+
*
469
+
* \param filep pointer to file structure.
470
+
* \param p amdkfd process pointer.
471
+
* \param data pointer to arg that was copied from user.
472
+
*/
473
+
typedef int amdkfd_ioctl_t(struct file *filep, struct kfd_process *p,
474
+
void *data);
475
+
476
+
struct amdkfd_ioctl_desc {
477
+
unsigned int cmd;
478
+
int flags;
479
+
amdkfd_ioctl_t *func;
480
+
unsigned int cmd_drv;
481
+
const char *name;
482
+
};
483
+
466
484
void kfd_process_create_wq(void);
467
485
void kfd_process_destroy_wq(void);
468
486
struct kfd_process *kfd_create_process(const struct task_struct *);
+1
-1
drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+1
-1
drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+1
-1
drivers/gpu/drm/amd/include/kgd_kfd_interface.h
+1
-1
drivers/gpu/drm/amd/include/kgd_kfd_interface.h
···
183
183
int (*hqd_load)(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
184
184
uint32_t queue_id, uint32_t __user *wptr);
185
185
186
-
bool (*hqd_is_occupies)(struct kgd_dev *kgd, uint64_t queue_address,
186
+
bool (*hqd_is_occupied)(struct kgd_dev *kgd, uint64_t queue_address,
187
187
uint32_t pipe_id, uint32_t queue_id);
188
188
189
189
int (*hqd_destroy)(struct kgd_dev *kgd, uint32_t reset_type,
-2
drivers/gpu/drm/i915/i915_drv.h
-2
drivers/gpu/drm/i915/i915_drv.h
+7
-1
drivers/gpu/drm/i915/i915_gem.c
+7
-1
drivers/gpu/drm/i915/i915_gem.c
···
1048
1048
i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1049
1049
struct drm_file *file)
1050
1050
{
1051
+
struct drm_i915_private *dev_priv = dev->dev_private;
1051
1052
struct drm_i915_gem_pwrite *args = data;
1052
1053
struct drm_i915_gem_object *obj;
1053
1054
int ret;
···
1068
1067
return -EFAULT;
1069
1068
}
1070
1069
1070
+
intel_runtime_pm_get(dev_priv);
1071
+
1071
1072
ret = i915_mutex_lock_interruptible(dev);
1072
1073
if (ret)
1073
-
return ret;
1074
+
goto put_rpm;
1074
1075
1075
1076
obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1076
1077
if (&obj->base == NULL) {
···
1124
1121
drm_gem_object_unreference(&obj->base);
1125
1122
unlock:
1126
1123
mutex_unlock(&dev->struct_mutex);
1124
+
put_rpm:
1125
+
intel_runtime_pm_put(dev_priv);
1126
+
1127
1127
return ret;
1128
1128
}
1129
1129
+2
-4
drivers/gpu/drm/i915/i915_irq.c
+2
-4
drivers/gpu/drm/i915/i915_irq.c
···
3725
3725
if ((iir & flip_pending) == 0)
3726
3726
goto check_page_flip;
3727
3727
3728
-
intel_prepare_page_flip(dev, plane);
3729
-
3730
3728
/* We detect FlipDone by looking for the change in PendingFlip from '1'
3731
3729
* to '0' on the following vblank, i.e. IIR has the Pendingflip
3732
3730
* asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
···
3734
3736
if (I915_READ16(ISR) & flip_pending)
3735
3737
goto check_page_flip;
3736
3738
3739
+
intel_prepare_page_flip(dev, plane);
3737
3740
intel_finish_page_flip(dev, pipe);
3738
3741
return true;
3739
3742
···
3906
3907
if ((iir & flip_pending) == 0)
3907
3908
goto check_page_flip;
3908
3909
3909
-
intel_prepare_page_flip(dev, plane);
3910
-
3911
3910
/* We detect FlipDone by looking for the change in PendingFlip from '1'
3912
3911
* to '0' on the following vblank, i.e. IIR has the Pendingflip
3913
3912
* asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
···
3915
3918
if (I915_READ(ISR) & flip_pending)
3916
3919
goto check_page_flip;
3917
3920
3921
+
intel_prepare_page_flip(dev, plane);
3918
3922
intel_finish_page_flip(dev, pipe);
3919
3923
return true;
3920
3924
+1
-7
drivers/gpu/drm/i915/intel_display.c
+1
-7
drivers/gpu/drm/i915/intel_display.c
···
13057
13057
vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13058
13058
udelay(300);
13059
13059
13060
-
/*
13061
-
* Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
13062
-
* from S3 without preserving (some of?) the other bits.
13063
-
*/
13064
-
I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
13060
+
I915_WRITE(vga_reg, VGA_DISP_DISABLE);
13065
13061
POSTING_READ(vga_reg);
13066
13062
}
13067
13063
···
13142
13146
13143
13147
intel_shared_dpll_init(dev);
13144
13148
13145
-
/* save the BIOS value before clobbering it */
13146
-
dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
13147
13149
/* Just disable it once at startup */
13148
13150
i915_disable_vga(dev);
13149
13151
intel_setup_outputs(dev);
-27
drivers/gpu/drm/i915/intel_runtime_pm.c
-27
drivers/gpu/drm/i915/intel_runtime_pm.c
···
615
615
vlv_power_sequencer_reset(dev_priv);
616
616
}
617
617
618
-
static void check_power_well_state(struct drm_i915_private *dev_priv,
619
-
struct i915_power_well *power_well)
620
-
{
621
-
bool enabled = power_well->ops->is_enabled(dev_priv, power_well);
622
-
623
-
if (power_well->always_on || !i915.disable_power_well) {
624
-
if (!enabled)
625
-
goto mismatch;
626
-
627
-
return;
628
-
}
629
-
630
-
if (enabled != (power_well->count > 0))
631
-
goto mismatch;
632
-
633
-
return;
634
-
635
-
mismatch:
636
-
WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
637
-
power_well->name, power_well->always_on, enabled,
638
-
power_well->count, i915.disable_power_well);
639
-
}
640
-
641
618
/**
642
619
* intel_display_power_get - grab a power domain reference
643
620
* @dev_priv: i915 device instance
···
646
669
power_well->ops->enable(dev_priv, power_well);
647
670
power_well->hw_enabled = true;
648
671
}
649
-
650
-
check_power_well_state(dev_priv, power_well);
651
672
}
652
673
653
674
power_domains->domain_use_count[domain]++;
···
684
709
power_well->hw_enabled = false;
685
710
power_well->ops->disable(dev_priv, power_well);
686
711
}
687
-
688
-
check_power_well_state(dev_priv, power_well);
689
712
}
690
713
691
714
mutex_unlock(&power_domains->lock);
+2
-2
drivers/gpu/drm/nouveau/core/core/event.c
+2
-2
drivers/gpu/drm/nouveau/core/core/event.c
···
26
26
void
27
27
nvkm_event_put(struct nvkm_event *event, u32 types, int index)
28
28
{
29
-
BUG_ON(!spin_is_locked(&event->refs_lock));
29
+
assert_spin_locked(&event->refs_lock);
30
30
while (types) {
31
31
int type = __ffs(types); types &= ~(1 << type);
32
32
if (--event->refs[index * event->types_nr + type] == 0) {
···
39
39
void
40
40
nvkm_event_get(struct nvkm_event *event, u32 types, int index)
41
41
{
42
-
BUG_ON(!spin_is_locked(&event->refs_lock));
42
+
assert_spin_locked(&event->refs_lock);
43
43
while (types) {
44
44
int type = __ffs(types); types &= ~(1 << type);
45
45
if (++event->refs[index * event->types_nr + type] == 1) {
+1
-1
drivers/gpu/drm/nouveau/core/core/notify.c
+1
-1
drivers/gpu/drm/nouveau/core/core/notify.c
+33
drivers/gpu/drm/nouveau/core/engine/device/nve0.c
+33
drivers/gpu/drm/nouveau/core/engine/device/nve0.c
···
249
249
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
250
250
device->oclass[NVDEV_ENGINE_PERFMON] = &nvf0_perfmon_oclass;
251
251
break;
252
+
case 0x106:
253
+
device->cname = "GK208B";
254
+
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
255
+
device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
256
+
device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
257
+
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
258
+
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
259
+
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
260
+
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
261
+
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
262
+
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
263
+
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
264
+
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
265
+
device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
266
+
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
267
+
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
268
+
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
269
+
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
270
+
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
271
+
device->oclass[NVDEV_SUBDEV_PWR ] = nv108_pwr_oclass;
272
+
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
273
+
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
274
+
device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
275
+
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
276
+
device->oclass[NVDEV_ENGINE_GR ] = nv108_graph_oclass;
277
+
device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass;
278
+
device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
279
+
device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
280
+
device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
281
+
device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
282
+
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
283
+
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
284
+
break;
252
285
case 0x108:
253
286
device->cname = "GK208";
254
287
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
+4
-2
drivers/gpu/drm/nouveau/core/subdev/bios/shadowramin.c
+4
-2
drivers/gpu/drm/nouveau/core/subdev/bios/shadowramin.c
+51
-14
drivers/gpu/drm/nouveau/core/subdev/fb/ramnvaa.c
+51
-14
drivers/gpu/drm/nouveau/core/subdev/fb/ramnvaa.c
···
24
24
25
25
#include "nv50.h"
26
26
27
+
struct nvaa_ram_priv {
28
+
struct nouveau_ram base;
29
+
u64 poller_base;
30
+
};
31
+
27
32
static int
28
33
nvaa_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
29
34
struct nouveau_oclass *oclass, void *data, u32 datasize,
30
35
struct nouveau_object **pobject)
31
36
{
32
-
const u32 rsvd_head = ( 256 * 1024) >> 12; /* vga memory */
33
-
const u32 rsvd_tail = (1024 * 1024) >> 12; /* vbios etc */
37
+
u32 rsvd_head = ( 256 * 1024); /* vga memory */
38
+
u32 rsvd_tail = (1024 * 1024); /* vbios etc */
34
39
struct nouveau_fb *pfb = nouveau_fb(parent);
35
-
struct nouveau_ram *ram;
40
+
struct nvaa_ram_priv *priv;
36
41
int ret;
37
42
38
-
ret = nouveau_ram_create(parent, engine, oclass, &ram);
39
-
*pobject = nv_object(ram);
43
+
ret = nouveau_ram_create(parent, engine, oclass, &priv);
44
+
*pobject = nv_object(priv);
40
45
if (ret)
41
46
return ret;
42
47
43
-
ram->size = nv_rd32(pfb, 0x10020c);
44
-
ram->size = (ram->size & 0xffffff00) | ((ram->size & 0x000000ff) << 32);
48
+
priv->base.type = NV_MEM_TYPE_STOLEN;
49
+
priv->base.stolen = (u64)nv_rd32(pfb, 0x100e10) << 12;
50
+
priv->base.size = (u64)nv_rd32(pfb, 0x100e14) << 12;
45
51
46
-
ret = nouveau_mm_init(&pfb->vram, rsvd_head, (ram->size >> 12) -
47
-
(rsvd_head + rsvd_tail), 1);
52
+
rsvd_tail += 0x1000;
53
+
priv->poller_base = priv->base.size - rsvd_tail;
54
+
55
+
ret = nouveau_mm_init(&pfb->vram, rsvd_head >> 12,
56
+
(priv->base.size - (rsvd_head + rsvd_tail)) >> 12,
57
+
1);
48
58
if (ret)
49
59
return ret;
50
60
51
-
ram->type = NV_MEM_TYPE_STOLEN;
52
-
ram->stolen = (u64)nv_rd32(pfb, 0x100e10) << 12;
53
-
ram->get = nv50_ram_get;
54
-
ram->put = nv50_ram_put;
61
+
priv->base.get = nv50_ram_get;
62
+
priv->base.put = nv50_ram_put;
63
+
return 0;
64
+
}
65
+
66
+
static int
67
+
nvaa_ram_init(struct nouveau_object *object)
68
+
{
69
+
struct nouveau_fb *pfb = nouveau_fb(object);
70
+
struct nvaa_ram_priv *priv = (void *)object;
71
+
int ret;
72
+
u64 dniso, hostnb, flush;
73
+
74
+
ret = nouveau_ram_init(&priv->base);
75
+
if (ret)
76
+
return ret;
77
+
78
+
dniso = ((priv->base.size - (priv->poller_base + 0x00)) >> 5) - 1;
79
+
hostnb = ((priv->base.size - (priv->poller_base + 0x20)) >> 5) - 1;
80
+
flush = ((priv->base.size - (priv->poller_base + 0x40)) >> 5) - 1;
81
+
82
+
/* Enable NISO poller for various clients and set their associated
83
+
* read address, only for MCP77/78 and MCP79/7A. (fd#25701)
84
+
*/
85
+
nv_wr32(pfb, 0x100c18, dniso);
86
+
nv_mask(pfb, 0x100c14, 0x00000000, 0x00000001);
87
+
nv_wr32(pfb, 0x100c1c, hostnb);
88
+
nv_mask(pfb, 0x100c14, 0x00000000, 0x00000002);
89
+
nv_wr32(pfb, 0x100c24, flush);
90
+
nv_mask(pfb, 0x100c14, 0x00000000, 0x00010000);
91
+
55
92
return 0;
56
93
}
57
94
···
97
60
.ofuncs = &(struct nouveau_ofuncs) {
98
61
.ctor = nvaa_ram_ctor,
99
62
.dtor = _nouveau_ram_dtor,
100
-
.init = _nouveau_ram_init,
63
+
.init = nvaa_ram_init,
101
64
.fini = _nouveau_ram_fini,
102
65
},
103
66
};
-8
drivers/gpu/drm/nouveau/core/subdev/mc/nv4c.c
-8
drivers/gpu/drm/nouveau/core/subdev/mc/nv4c.c
···
24
24
25
25
#include "nv04.h"
26
26
27
-
static void
28
-
nv4c_mc_msi_rearm(struct nouveau_mc *pmc)
29
-
{
30
-
struct nv04_mc_priv *priv = (void *)pmc;
31
-
nv_wr08(priv, 0x088050, 0xff);
32
-
}
33
-
34
27
struct nouveau_oclass *
35
28
nv4c_mc_oclass = &(struct nouveau_mc_oclass) {
36
29
.base.handle = NV_SUBDEV(MC, 0x4c),
···
34
41
.fini = _nouveau_mc_fini,
35
42
},
36
43
.intr = nv04_mc_intr,
37
-
.msi_rearm = nv4c_mc_msi_rearm,
38
44
}.base;
+3
-1
drivers/gpu/drm/nouveau/nouveau_bo.c
+3
-1
drivers/gpu/drm/nouveau/nouveau_bo.c
···
1572
1572
* so use the DMA API for them.
1573
1573
*/
1574
1574
if (!nv_device_is_cpu_coherent(device) &&
1575
-
ttm->caching_state == tt_uncached)
1575
+
ttm->caching_state == tt_uncached) {
1576
1576
ttm_dma_unpopulate(ttm_dma, dev->dev);
1577
+
return;
1578
+
}
1577
1579
1578
1580
#if __OS_HAS_AGP
1579
1581
if (drm->agp.stat == ENABLED) {
+31
-6
drivers/gpu/drm/nouveau/nouveau_gem.c
+31
-6
drivers/gpu/drm/nouveau/nouveau_gem.c
···
36
36
nouveau_gem_object_del(struct drm_gem_object *gem)
37
37
{
38
38
struct nouveau_bo *nvbo = nouveau_gem_object(gem);
39
+
struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
39
40
struct ttm_buffer_object *bo = &nvbo->bo;
41
+
struct device *dev = drm->dev->dev;
42
+
int ret;
43
+
44
+
ret = pm_runtime_get_sync(dev);
45
+
if (WARN_ON(ret < 0 && ret != -EACCES))
46
+
return;
40
47
41
48
if (gem->import_attach)
42
49
drm_prime_gem_destroy(gem, nvbo->bo.sg);
···
53
46
/* reset filp so nouveau_bo_del_ttm() can test for it */
54
47
gem->filp = NULL;
55
48
ttm_bo_unref(&bo);
49
+
50
+
pm_runtime_mark_last_busy(dev);
51
+
pm_runtime_put_autosuspend(dev);
56
52
}
57
53
58
54
int
···
63
53
{
64
54
struct nouveau_cli *cli = nouveau_cli(file_priv);
65
55
struct nouveau_bo *nvbo = nouveau_gem_object(gem);
56
+
struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
66
57
struct nouveau_vma *vma;
58
+
struct device *dev = drm->dev->dev;
67
59
int ret;
68
60
69
61
if (!cli->vm)
···
83
71
goto out;
84
72
}
85
73
86
-
ret = nouveau_bo_vma_add(nvbo, cli->vm, vma);
87
-
if (ret) {
88
-
kfree(vma);
74
+
ret = pm_runtime_get_sync(dev);
75
+
if (ret < 0 && ret != -EACCES)
89
76
goto out;
90
-
}
77
+
78
+
ret = nouveau_bo_vma_add(nvbo, cli->vm, vma);
79
+
if (ret)
80
+
kfree(vma);
81
+
82
+
pm_runtime_mark_last_busy(dev);
83
+
pm_runtime_put_autosuspend(dev);
91
84
} else {
92
85
vma->refcount++;
93
86
}
···
146
129
{
147
130
struct nouveau_cli *cli = nouveau_cli(file_priv);
148
131
struct nouveau_bo *nvbo = nouveau_gem_object(gem);
132
+
struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
133
+
struct device *dev = drm->dev->dev;
149
134
struct nouveau_vma *vma;
150
135
int ret;
151
136
···
160
141
161
142
vma = nouveau_bo_vma_find(nvbo, cli->vm);
162
143
if (vma) {
163
-
if (--vma->refcount == 0)
164
-
nouveau_gem_object_unmap(nvbo, vma);
144
+
if (--vma->refcount == 0) {
145
+
ret = pm_runtime_get_sync(dev);
146
+
if (!WARN_ON(ret < 0 && ret != -EACCES)) {
147
+
nouveau_gem_object_unmap(nvbo, vma);
148
+
pm_runtime_mark_last_busy(dev);
149
+
pm_runtime_put_autosuspend(dev);
150
+
}
151
+
}
165
152
}
166
153
ttm_bo_unreserve(&nvbo->bo);
167
154
}
+4
-4
drivers/gpu/drm/radeon/atombios_crtc.c
+4
-4
drivers/gpu/drm/radeon/atombios_crtc.c
···
1851
1851
return pll;
1852
1852
}
1853
1853
/* otherwise, pick one of the plls */
1854
-
if ((rdev->family == CHIP_KAVERI) ||
1855
-
(rdev->family == CHIP_KABINI) ||
1854
+
if ((rdev->family == CHIP_KABINI) ||
1856
1855
(rdev->family == CHIP_MULLINS)) {
1857
-
/* KB/KV/ML has PPLL1 and PPLL2 */
1856
+
/* KB/ML has PPLL1 and PPLL2 */
1858
1857
pll_in_use = radeon_get_pll_use_mask(crtc);
1859
1858
if (!(pll_in_use & (1 << ATOM_PPLL2)))
1860
1859
return ATOM_PPLL2;
···
1862
1863
DRM_ERROR("unable to allocate a PPLL\n");
1863
1864
return ATOM_PPLL_INVALID;
1864
1865
} else {
1865
-
/* CI has PPLL0, PPLL1, and PPLL2 */
1866
+
/* CI/KV has PPLL0, PPLL1, and PPLL2 */
1866
1867
pll_in_use = radeon_get_pll_use_mask(crtc);
1867
1868
if (!(pll_in_use & (1 << ATOM_PPLL2)))
1868
1869
return ATOM_PPLL2;
···
2154
2155
case ATOM_PPLL0:
2155
2156
/* disable the ppll */
2156
2157
if ((rdev->family == CHIP_ARUBA) ||
2158
+
(rdev->family == CHIP_KAVERI) ||
2157
2159
(rdev->family == CHIP_BONAIRE) ||
2158
2160
(rdev->family == CHIP_HAWAII))
2159
2161
atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
+4
drivers/gpu/drm/radeon/atombios_dp.c
+4
drivers/gpu/drm/radeon/atombios_dp.c
···
492
492
struct radeon_connector_atom_dig *dig_connector;
493
493
int dp_clock;
494
494
495
+
if ((mode->clock > 340000) &&
496
+
(!radeon_connector_is_dp12_capable(connector)))
497
+
return MODE_CLOCK_HIGH;
498
+
495
499
if (!radeon_connector->con_priv)
496
500
return MODE_CLOCK_HIGH;
497
501
dig_connector = radeon_connector->con_priv;
+2
drivers/gpu/drm/radeon/cikd.h
+2
drivers/gpu/drm/radeon/cikd.h
+1
-1
drivers/gpu/drm/radeon/dce3_1_afmt.c
+1
-1
drivers/gpu/drm/radeon/dce3_1_afmt.c
+4
-6
drivers/gpu/drm/radeon/kv_dpm.c
+4
-6
drivers/gpu/drm/radeon/kv_dpm.c
···
2745
2745
pi->enable_auto_thermal_throttling = true;
2746
2746
pi->disable_nb_ps3_in_battery = false;
2747
2747
if (radeon_bapm == -1) {
2748
-
/* There are stability issues reported on with
2749
-
* bapm enabled on an asrock system.
2750
-
*/
2751
-
if (rdev->pdev->subsystem_vendor == 0x1849)
2752
-
pi->bapm_enable = false;
2753
-
else
2748
+
/* only enable bapm on KB, ML by default */
2749
+
if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS)
2754
2750
pi->bapm_enable = true;
2751
+
else
2752
+
pi->bapm_enable = false;
2755
2753
} else if (radeon_bapm == 0) {
2756
2754
pi->bapm_enable = false;
2757
2755
} else {
+20
-3
drivers/gpu/drm/radeon/radeon_kfd.c
+20
-3
drivers/gpu/drm/radeon/radeon_kfd.c
···
72
72
static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
73
73
uint32_t queue_id, uint32_t __user *wptr);
74
74
75
-
static bool kgd_hqd_is_occupies(struct kgd_dev *kgd, uint64_t queue_address,
75
+
static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
76
76
uint32_t pipe_id, uint32_t queue_id);
77
77
78
78
static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type,
···
92
92
.init_memory = kgd_init_memory,
93
93
.init_pipeline = kgd_init_pipeline,
94
94
.hqd_load = kgd_hqd_load,
95
-
.hqd_is_occupies = kgd_hqd_is_occupies,
95
+
.hqd_is_occupied = kgd_hqd_is_occupied,
96
96
.hqd_destroy = kgd_hqd_destroy,
97
97
.get_fw_version = get_fw_version
98
98
};
···
101
101
102
102
bool radeon_kfd_init(void)
103
103
{
104
+
#if defined(CONFIG_HSA_AMD_MODULE)
104
105
bool (*kgd2kfd_init_p)(unsigned, const struct kfd2kgd_calls*,
105
106
const struct kgd2kfd_calls**);
106
107
···
118
117
}
119
118
120
119
return true;
120
+
#elif defined(CONFIG_HSA_AMD)
121
+
if (!kgd2kfd_init(KFD_INTERFACE_VERSION, &kfd2kgd, &kgd2kfd)) {
122
+
kgd2kfd = NULL;
123
+
124
+
return false;
125
+
}
126
+
127
+
return true;
128
+
#else
129
+
return false;
130
+
#endif
121
131
}
122
132
123
133
void radeon_kfd_fini(void)
···
390
378
cpu_relax();
391
379
write_register(kgd, ATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid);
392
380
381
+
/* Mapping vmid to pasid also for IH block */
382
+
write_register(kgd, IH_VMID_0_LUT + vmid * sizeof(uint32_t),
383
+
pasid_mapping);
384
+
393
385
return 0;
394
386
}
395
387
···
533
517
return 0;
534
518
}
535
519
536
-
static bool kgd_hqd_is_occupies(struct kgd_dev *kgd, uint64_t queue_address,
520
+
static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
537
521
uint32_t pipe_id, uint32_t queue_id)
538
522
{
539
523
uint32_t act;
···
572
556
if (timeout == 0) {
573
557
pr_err("kfd: cp queue preemption time out (%dms)\n",
574
558
temp);
559
+
release_queue(kgd);
575
560
return -ETIME;
576
561
}
577
562
msleep(20);
+1
-1
drivers/gpu/drm/radeon/radeon_state.c
+1
-1
drivers/gpu/drm/radeon/radeon_state.c
+22
-15
include/uapi/linux/kfd_ioctl.h
+22
-15
include/uapi/linux/kfd_ioctl.h
···
128
128
uint32_t pad;
129
129
};
130
130
131
-
#define KFD_IOC_MAGIC 'K'
131
+
#define AMDKFD_IOCTL_BASE 'K'
132
+
#define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr)
133
+
#define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type)
134
+
#define AMDKFD_IOW(nr, type) _IOW(AMDKFD_IOCTL_BASE, nr, type)
135
+
#define AMDKFD_IOWR(nr, type) _IOWR(AMDKFD_IOCTL_BASE, nr, type)
132
136
133
-
#define KFD_IOC_GET_VERSION \
134
-
_IOR(KFD_IOC_MAGIC, 1, struct kfd_ioctl_get_version_args)
137
+
#define AMDKFD_IOC_GET_VERSION \
138
+
AMDKFD_IOR(0x01, struct kfd_ioctl_get_version_args)
135
139
136
-
#define KFD_IOC_CREATE_QUEUE \
137
-
_IOWR(KFD_IOC_MAGIC, 2, struct kfd_ioctl_create_queue_args)
140
+
#define AMDKFD_IOC_CREATE_QUEUE \
141
+
AMDKFD_IOWR(0x02, struct kfd_ioctl_create_queue_args)
138
142
139
-
#define KFD_IOC_DESTROY_QUEUE \
140
-
_IOWR(KFD_IOC_MAGIC, 3, struct kfd_ioctl_destroy_queue_args)
143
+
#define AMDKFD_IOC_DESTROY_QUEUE \
144
+
AMDKFD_IOWR(0x03, struct kfd_ioctl_destroy_queue_args)
141
145
142
-
#define KFD_IOC_SET_MEMORY_POLICY \
143
-
_IOW(KFD_IOC_MAGIC, 4, struct kfd_ioctl_set_memory_policy_args)
146
+
#define AMDKFD_IOC_SET_MEMORY_POLICY \
147
+
AMDKFD_IOW(0x04, struct kfd_ioctl_set_memory_policy_args)
144
148
145
-
#define KFD_IOC_GET_CLOCK_COUNTERS \
146
-
_IOWR(KFD_IOC_MAGIC, 5, struct kfd_ioctl_get_clock_counters_args)
149
+
#define AMDKFD_IOC_GET_CLOCK_COUNTERS \
150
+
AMDKFD_IOWR(0x05, struct kfd_ioctl_get_clock_counters_args)
147
151
148
-
#define KFD_IOC_GET_PROCESS_APERTURES \
149
-
_IOR(KFD_IOC_MAGIC, 6, struct kfd_ioctl_get_process_apertures_args)
152
+
#define AMDKFD_IOC_GET_PROCESS_APERTURES \
153
+
AMDKFD_IOR(0x06, struct kfd_ioctl_get_process_apertures_args)
150
154
151
-
#define KFD_IOC_UPDATE_QUEUE \
152
-
_IOW(KFD_IOC_MAGIC, 7, struct kfd_ioctl_update_queue_args)
155
+
#define AMDKFD_IOC_UPDATE_QUEUE \
156
+
AMDKFD_IOW(0x07, struct kfd_ioctl_update_queue_args)
157
+
158
+
#define AMDKFD_COMMAND_START 0x01
159
+
#define AMDKFD_COMMAND_END 0x08
153
160
154
161
#endif