···339339340340 if (def != data)341341 WREG32_PCIE(smnPCIE_CONFIG_CNTL, data);342342-343343- if (amdgpu_sriov_vf(adev))344344- adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,345345- mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;346342}347343348344#define NAVI10_PCIE__LC_L0S_INACTIVITY_DEFAULT 0x00000000 // off by default, no gains over L1