Merge branch 'bnxt_en-update-for-net-next'

+104 -10

drivers/net/ethernet/broadcom/bnxt/bnxt.c

··· 1296 1296 return RX_AGG_CMP_VALID(agg, *raw_cons); 1297 1297 } 1298 1298 1299 - static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data, 1300 - unsigned int len, 1301 - dma_addr_t mapping) 1299 + static struct sk_buff *bnxt_copy_data(struct bnxt_napi *bnapi, u8 *data, 1300 + unsigned int len, 1301 + dma_addr_t mapping) 1302 1302 { 1303 1303 struct bnxt *bp = bnapi->bp; 1304 1304 struct pci_dev *pdev = bp->pdev; ··· 1318 1318 bp->rx_dir); 1319 1319 1320 1320 skb_put(skb, len); 1321 + 1322 + return skb; 1323 + } 1324 + 1325 + static struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data, 1326 + unsigned int len, 1327 + dma_addr_t mapping) 1328 + { 1329 + return bnxt_copy_data(bnapi, data, len, mapping); 1330 + } 1331 + 1332 + static struct sk_buff *bnxt_copy_xdp(struct bnxt_napi *bnapi, 1333 + struct xdp_buff *xdp, 1334 + unsigned int len, 1335 + dma_addr_t mapping) 1336 + { 1337 + unsigned int metasize = 0; 1338 + u8 *data = xdp->data; 1339 + struct sk_buff *skb; 1340 + 1341 + len = xdp->data_end - xdp->data_meta; 1342 + metasize = xdp->data - xdp->data_meta; 1343 + data = xdp->data_meta; 1344 + 1345 + skb = bnxt_copy_data(bnapi, data, len, mapping); 1346 + if (!skb) 1347 + return skb; 1348 + 1349 + if (metasize) { 1350 + skb_metadata_set(skb, metasize); 1351 + __skb_pull(skb, metasize); 1352 + } 1353 + 1321 1354 return skb; 1322 1355 } 1323 1356 ··· 2137 2104 } 2138 2105 2139 2106 if (xdp_active) { 2140 - if (bnxt_rx_xdp(bp, rxr, cons, xdp, data, &data_ptr, &len, event)) { 2107 + if (bnxt_rx_xdp(bp, rxr, cons, &xdp, data, &data_ptr, &len, event)) { 2141 2108 rc = 1; 2142 2109 goto next_rx; 2143 2110 } 2144 2111 } 2145 2112 2146 2113 if (len <= bp->rx_copy_thresh) { 2147 - skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr); 2114 + if (!xdp_active) 2115 + skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr); 2116 + else 2117 + skb = bnxt_copy_xdp(bnapi, &xdp, len, dma_addr); 2148 2118 bnxt_reuse_rx_data(rxr, cons, data); 2149 2119 if (!skb) { 2150 2120 if (agg_bufs) { ··· 2525 2489 } 2526 2490 return false; 2527 2491 } 2492 + case ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED: 2493 + netdev_warn(bp->dev, "Speed change not supported with dual rate transceivers on this board\n"); 2494 + break; 2528 2495 default: 2529 2496 netdev_err(bp->dev, "FW reported unknown error type %u\n", 2530 2497 err_type); ··· 3598 3559 } 3599 3560 3600 3561 static int bnxt_alloc_rx_page_pool(struct bnxt *bp, 3601 - struct bnxt_rx_ring_info *rxr) 3562 + struct bnxt_rx_ring_info *rxr, 3563 + int numa_node) 3602 3564 { 3603 3565 struct page_pool_params pp = { 0 }; 3604 3566 3605 3567 pp.pool_size = bp->rx_agg_ring_size; 3606 3568 if (BNXT_RX_PAGE_MODE(bp)) 3607 3569 pp.pool_size += bp->rx_ring_size; 3608 - pp.nid = dev_to_node(&bp->pdev->dev); 3570 + pp.nid = numa_node; 3609 3571 pp.napi = &rxr->bnapi->napi; 3610 3572 pp.netdev = bp->dev; 3611 3573 pp.dev = &bp->pdev->dev; ··· 3626 3586 3627 3587 static int bnxt_alloc_rx_rings(struct bnxt *bp) 3628 3588 { 3629 - int i, rc = 0, agg_rings = 0; 3589 + int numa_node = dev_to_node(&bp->pdev->dev); 3590 + int i, rc = 0, agg_rings = 0, cpu; 3630 3591 3631 3592 if (!bp->rx_ring) 3632 3593 return -ENOMEM; ··· 3638 3597 for (i = 0; i < bp->rx_nr_rings; i++) { 3639 3598 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; 3640 3599 struct bnxt_ring_struct *ring; 3600 + int cpu_node; 3641 3601 3642 3602 ring = &rxr->rx_ring_struct; 3643 3603 3644 - rc = bnxt_alloc_rx_page_pool(bp, rxr); 3604 + cpu = cpumask_local_spread(i, numa_node); 3605 + cpu_node = cpu_to_node(cpu); 3606 + netdev_dbg(bp->dev, "Allocating page pool for rx_ring[%d] on numa_node: %d\n", 3607 + i, cpu_node); 3608 + rc = bnxt_alloc_rx_page_pool(bp, rxr, cpu_node); 3645 3609 if (rc) 3646 3610 return rc; 3647 3611 ··· 11850 11804 bnxt_cfg_one_usr_fltr(bp, usr_fltr); 11851 11805 } 11852 11806 11807 + static int bnxt_set_xps_mapping(struct bnxt *bp) 11808 + { 11809 + int numa_node = dev_to_node(&bp->pdev->dev); 11810 + unsigned int q_idx, map_idx, cpu, i; 11811 + const struct cpumask *cpu_mask_ptr; 11812 + int nr_cpus = num_online_cpus(); 11813 + cpumask_t *q_map; 11814 + int rc = 0; 11815 + 11816 + q_map = kcalloc(bp->tx_nr_rings_per_tc, sizeof(*q_map), GFP_KERNEL); 11817 + if (!q_map) 11818 + return -ENOMEM; 11819 + 11820 + /* Create CPU mask for all TX queues across MQPRIO traffic classes. 11821 + * Each TC has the same number of TX queues. The nth TX queue for each 11822 + * TC will have the same CPU mask. 11823 + */ 11824 + for (i = 0; i < nr_cpus; i++) { 11825 + map_idx = i % bp->tx_nr_rings_per_tc; 11826 + cpu = cpumask_local_spread(i, numa_node); 11827 + cpu_mask_ptr = get_cpu_mask(cpu); 11828 + cpumask_or(&q_map[map_idx], &q_map[map_idx], cpu_mask_ptr); 11829 + } 11830 + 11831 + /* Register CPU mask for each TX queue except the ones marked for XDP */ 11832 + for (q_idx = 0; q_idx < bp->dev->real_num_tx_queues; q_idx++) { 11833 + map_idx = q_idx % bp->tx_nr_rings_per_tc; 11834 + rc = netif_set_xps_queue(bp->dev, &q_map[map_idx], q_idx); 11835 + if (rc) { 11836 + netdev_warn(bp->dev, "Error setting XPS for q:%d\n", 11837 + q_idx); 11838 + break; 11839 + } 11840 + } 11841 + 11842 + kfree(q_map); 11843 + 11844 + return rc; 11845 + } 11846 + 11853 11847 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 11854 11848 { 11855 11849 int rc = 0; ··· 11952 11866 } 11953 11867 } 11954 11868 11955 - if (irq_re_init) 11869 + if (irq_re_init) { 11956 11870 udp_tunnel_nic_reset_ntf(bp->dev); 11871 + rc = bnxt_set_xps_mapping(bp); 11872 + if (rc) 11873 + netdev_warn(bp->dev, "failed to set xps mapping\n"); 11874 + } 11957 11875 11958 11876 if (bp->tx_nr_rings_xdp < num_possible_cpus()) { 11959 11877 if (!static_key_enabled(&bnxt_xdp_locking_key)) ··· 15639 15549 int off; 15640 15550 15641 15551 netdev_info(bp->dev, "PCI Slot Reset\n"); 15552 + 15553 + if (!(bp->flags & BNXT_FLAG_CHIP_P5_PLUS) && 15554 + test_bit(BNXT_STATE_PCI_CHANNEL_IO_FROZEN, &bp->state)) 15555 + msleep(900); 15642 15556 15643 15557 rtnl_lock(); 15644 15558

+137 -47

drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h

··· 468 468 #define HWRM_TF_GLOBAL_CFG_GET 0x2fdUL 469 469 #define HWRM_TF_IF_TBL_SET 0x2feUL 470 470 #define HWRM_TF_IF_TBL_GET 0x2ffUL 471 + #define HWRM_TF_RESC_USAGE_SET 0x300UL 472 + #define HWRM_TF_RESC_USAGE_QUERY 0x301UL 473 + #define HWRM_TF_TBL_TYPE_ALLOC 0x302UL 474 + #define HWRM_TF_TBL_TYPE_FREE 0x303UL 471 475 #define HWRM_TFC_TBL_SCOPE_QCAPS 0x380UL 472 476 #define HWRM_TFC_TBL_SCOPE_ID_ALLOC 0x381UL 473 477 #define HWRM_TFC_TBL_SCOPE_CONFIG 0x382UL ··· 499 495 #define HWRM_TFC_IF_TBL_SET 0x398UL 500 496 #define HWRM_TFC_IF_TBL_GET 0x399UL 501 497 #define HWRM_TFC_TBL_SCOPE_CONFIG_GET 0x39aUL 498 + #define HWRM_TFC_RESC_USAGE_QUERY 0x39bUL 502 499 #define HWRM_SV 0x400UL 503 500 #define HWRM_DBG_READ_DIRECT 0xff10UL 504 501 #define HWRM_DBG_READ_INDIRECT 0xff11UL ··· 609 604 #define HWRM_VERSION_MAJOR 1 610 605 #define HWRM_VERSION_MINOR 10 611 606 #define HWRM_VERSION_UPDATE 3 612 - #define HWRM_VERSION_RSVD 15 613 - #define HWRM_VERSION_STR "1.10.3.15" 607 + #define HWRM_VERSION_RSVD 39 608 + #define HWRM_VERSION_STR "1.10.3.39" 614 609 615 610 /* hwrm_ver_get_input (size:192b/24B) */ 616 611 struct hwrm_ver_get_input { ··· 1333 1328 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 0x2UL 1334 1329 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM 0x3UL 1335 1330 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 0x4UL 1336 - #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_THERMAL_THRESHOLD 0x5UL 1337 - #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_THERMAL_THRESHOLD 1331 + #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_THERMAL_THRESHOLD 0x5UL 1332 + #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED 0x6UL 1333 + #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED 1338 1334 }; 1339 1335 1340 1336 /* hwrm_async_event_cmpl_error_report_pause_storm (size:128b/16B) */ ··· 1482 1476 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_DECREASING (0x0UL << 11) 1483 1477 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_INCREASING (0x1UL << 11) 1484 1478 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_INCREASING 1479 + }; 1480 + 1481 + /* hwrm_async_event_cmpl_error_report_dual_data_rate_not_supported (size:128b/16B) */ 1482 + struct hwrm_async_event_cmpl_error_report_dual_data_rate_not_supported { 1483 + __le16 type; 1484 + #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_MASK 0x3fUL 1485 + #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_SFT 0 1486 + #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1487 + #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_HWRM_ASYNC_EVENT 1488 + __le16 event_id; 1489 + #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_ID_ERROR_REPORT 0x45UL 1490 + #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_ID_ERROR_REPORT 1491 + __le32 event_data2; 1492 + u8 opaque_v; 1493 + #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_V 0x1UL 1494 + #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_OPAQUE_MASK 0xfeUL 1495 + #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_OPAQUE_SFT 1 1496 + u8 timestamp_lo; 1497 + __le16 timestamp_hi; 1498 + __le32 event_data1; 1499 + #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1500 + #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_SFT 0 1501 + #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED 0x6UL 1502 + #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED 1485 1503 }; 1486 1504 1487 1505 /* hwrm_func_reset_input (size:192b/24B) */ ··· 1811 1781 #define FUNC_QCAPS_RESP_FLAGS_EXT2_ROCE_VF_RESOURCE_MGMT_SUPPORTED 0x100000UL 1812 1782 #define FUNC_QCAPS_RESP_FLAGS_EXT2_UDCC_SUPPORTED 0x200000UL 1813 1783 #define FUNC_QCAPS_RESP_FLAGS_EXT2_TIMED_TX_SO_TXTIME_SUPPORTED 0x400000UL 1784 + #define FUNC_QCAPS_RESP_FLAGS_EXT2_SW_MAX_RESOURCE_LIMITS_SUPPORTED 0x800000UL 1785 + #define FUNC_QCAPS_RESP_FLAGS_EXT2_TF_INGRESS_NIC_FLOW_SUPPORTED 0x1000000UL 1786 + #define FUNC_QCAPS_RESP_FLAGS_EXT2_LPBK_STATS_SUPPORTED 0x2000000UL 1814 1787 __le16 tunnel_disable_flag; 1815 1788 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_VXLAN 0x1UL 1816 1789 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_NGE 0x2UL ··· 1824 1791 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_MPLS 0x40UL 1825 1792 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_PPPOE 0x80UL 1826 1793 __le16 xid_partition_cap; 1827 - #define FUNC_QCAPS_RESP_XID_PARTITION_CAP_KTLS_TKC 0x1UL 1828 - #define FUNC_QCAPS_RESP_XID_PARTITION_CAP_KTLS_RKC 0x2UL 1829 - #define FUNC_QCAPS_RESP_XID_PARTITION_CAP_QUIC_TKC 0x4UL 1830 - #define FUNC_QCAPS_RESP_XID_PARTITION_CAP_QUIC_RKC 0x8UL 1794 + #define FUNC_QCAPS_RESP_XID_PARTITION_CAP_TX_CK 0x1UL 1795 + #define FUNC_QCAPS_RESP_XID_PARTITION_CAP_RX_CK 0x2UL 1831 1796 u8 device_serial_number[8]; 1832 1797 __le16 ctxs_per_partition; 1833 1798 u8 unused_2[2]; ··· 1875 1844 #define FUNC_QCFG_RESP_FLAGS_FAST_RESET_ALLOWED 0x1000UL 1876 1845 #define FUNC_QCFG_RESP_FLAGS_MULTI_ROOT 0x2000UL 1877 1846 #define FUNC_QCFG_RESP_FLAGS_ENABLE_RDMA_SRIOV 0x4000UL 1847 + #define FUNC_QCFG_RESP_FLAGS_ROCE_VNIC_ID_VALID 0x8000UL 1878 1848 u8 mac_address[6]; 1879 1849 __le16 pci_id; 1880 1850 __le16 alloc_rsscos_ctx; ··· 1987 1955 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_2MB 0x9UL 1988 1956 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_4MB 0xaUL 1989 1957 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_LAST FUNC_QCFG_RESP_DB_PAGE_SIZE_4MB 1990 - u8 unused_2[2]; 1958 + __le16 roce_vnic_id; 1991 1959 __le32 partition_min_bw; 1992 1960 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1993 1961 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_SFT 0 ··· 2035 2003 __le32 roce_max_srq_per_vf; 2036 2004 __le32 roce_max_gid_per_vf; 2037 2005 __le16 xid_partition_cfg; 2006 + #define FUNC_QCFG_RESP_XID_PARTITION_CFG_TX_CK 0x1UL 2007 + #define FUNC_QCFG_RESP_XID_PARTITION_CFG_RX_CK 0x2UL 2038 2008 u8 unused_7; 2039 2009 u8 valid; 2040 2010 }; ··· 2263 2229 __le32 roce_max_srq_per_vf; 2264 2230 __le32 roce_max_gid_per_vf; 2265 2231 __le16 xid_partition_cfg; 2266 - #define FUNC_CFG_REQ_XID_PARTITION_CFG_KTLS_TKC 0x1UL 2267 - #define FUNC_CFG_REQ_XID_PARTITION_CFG_KTLS_RKC 0x2UL 2268 - #define FUNC_CFG_REQ_XID_PARTITION_CFG_QUIC_TKC 0x4UL 2269 - #define FUNC_CFG_REQ_XID_PARTITION_CFG_QUIC_RKC 0x8UL 2232 + #define FUNC_CFG_REQ_XID_PARTITION_CFG_TX_CK 0x1UL 2233 + #define FUNC_CFG_REQ_XID_PARTITION_CFG_RX_CK 0x2UL 2270 2234 __le16 unused_2; 2271 2235 }; 2272 2236 ··· 2448 2416 #define FUNC_DRV_RGTR_REQ_FLAGS_RSS_STRICT_HASH_TYPE_SUPPORT 0x100UL 2449 2417 #define FUNC_DRV_RGTR_REQ_FLAGS_NPAR_1_2_SUPPORT 0x200UL 2450 2418 #define FUNC_DRV_RGTR_REQ_FLAGS_ASYM_QUEUE_CFG_SUPPORT 0x400UL 2419 + #define FUNC_DRV_RGTR_REQ_FLAGS_TF_INGRESS_NIC_FLOW_MODE 0x800UL 2451 2420 __le32 enables; 2452 2421 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 2453 2422 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL ··· 3669 3636 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_FP_TQM_RING 0x6UL 3670 3637 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MRAV 0xeUL 3671 3638 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TIM 0xfUL 3672 - #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TKC 0x13UL 3673 - #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RKC 0x14UL 3674 3639 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MP_TQM_RING 0x15UL 3675 3640 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SQ_DB_SHADOW 0x16UL 3676 3641 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RQ_DB_SHADOW 0x17UL 3677 3642 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL 3678 3643 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CQ_DB_SHADOW 0x19UL 3679 - #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_QUIC_TKC 0x1aUL 3680 - #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_QUIC_RKC 0x1bUL 3681 3644 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TBL_SCOPE 0x1cUL 3682 3645 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_XID_PARTITION 0x1dUL 3683 - #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID 0xffffUL 3684 - #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID 3646 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRT_TRACE 0x1eUL 3647 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRT2_TRACE 0x1fUL 3648 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CRT_TRACE 0x20UL 3649 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CRT2_TRACE 0x21UL 3650 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RIGP0_TRACE 0x22UL 3651 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_L2_HWRM_TRACE 0x23UL 3652 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_ROCE_HWRM_TRACE 0x24UL 3653 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID 0xffffUL 3654 + #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID 3685 3655 __le16 instance; 3686 3656 __le32 flags; 3687 3657 #define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_PREBOOT_MODE 0x1UL ··· 3743 3707 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_FP_TQM_RING 0x6UL 3744 3708 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_MRAV 0xeUL 3745 3709 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TIM 0xfUL 3746 - #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TKC 0x13UL 3747 - #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RKC 0x14UL 3710 + #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TX_CK 0x13UL 3711 + #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RX_CK 0x14UL 3748 3712 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_MP_TQM_RING 0x15UL 3749 3713 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SQ_DB_SHADOW 0x16UL 3750 3714 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RQ_DB_SHADOW 0x17UL 3751 3715 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL 3752 3716 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CQ_DB_SHADOW 0x19UL 3753 - #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_QUIC_TKC 0x1aUL 3754 - #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_QUIC_RKC 0x1bUL 3755 3717 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TBL_SCOPE 0x1cUL 3756 3718 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_XID_PARTITION_TABLE 0x1dUL 3719 + #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRT_TRACE 0x1eUL 3720 + #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRT2_TRACE 0x1fUL 3721 + #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CRT_TRACE 0x20UL 3722 + #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CRT2_TRACE 0x21UL 3723 + #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RIGP0_TRACE 0x22UL 3724 + #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_L2_HWRM_TRACE 0x23UL 3725 + #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_ROCE_HWRM_TRACE 0x24UL 3757 3726 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID 0xffffUL 3758 3727 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID 3759 3728 __le16 instance; ··· 3781 3740 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_FP_TQM_RING 0x6UL 3782 3741 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MRAV 0xeUL 3783 3742 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TIM 0xfUL 3784 - #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TKC 0x13UL 3785 - #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_RKC 0x14UL 3786 3743 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MP_TQM_RING 0x15UL 3787 - #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_QUIC_TKC 0x1aUL 3788 - #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_QUIC_RKC 0x1bUL 3789 3744 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TBL_SCOPE 0x1cUL 3790 3745 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_XID_PARTITION 0x1dUL 3791 - #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID 0xffffUL 3792 - #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID 3746 + #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SRT_TRACE 0x1eUL 3747 + #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SRT2_TRACE 0x1fUL 3748 + #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CRT_TRACE 0x20UL 3749 + #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CRT2_TRACE 0x21UL 3750 + #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_RIGP0_TRACE 0x22UL 3751 + #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_L2_HWRM_TRACE 0x23UL 3752 + #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_ROCE_HWRM_TRACE 0x24UL 3753 + #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID 0xffffUL 3754 + #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID 3793 3755 __le16 instance; 3794 3756 __le32 flags; 3795 3757 __le64 page_dir; ··· 3885 3841 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_FP_TQM_RING 0x6UL 3886 3842 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MRAV 0xeUL 3887 3843 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TIM 0xfUL 3888 - #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_KTLS_TKC 0x13UL 3889 - #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_KTLS_RKC 0x14UL 3890 3844 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MP_TQM_RING 0x15UL 3891 3845 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SQ_DB_SHADOW 0x16UL 3892 3846 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RQ_DB_SHADOW 0x17UL 3893 3847 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL 3894 3848 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ_DB_SHADOW 0x19UL 3895 - #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QUIC_TKC 0x1aUL 3896 - #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QUIC_RKC 0x1bUL 3897 3849 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TBL_SCOPE 0x1cUL 3898 3850 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_XID_PARTITION 0x1dUL 3899 - #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID 0xffffUL 3900 - #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID 3851 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRT_TRACE 0x1eUL 3852 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRT2_TRACE 0x1fUL 3853 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CRT_TRACE 0x20UL 3854 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CRT2_TRACE 0x21UL 3855 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RIGP0_TRACE 0x22UL 3856 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_L2_HWRM_TRACE 0x23UL 3857 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_ROCE_HWRM_TRACE 0x24UL 3858 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID 0xffffUL 3859 + #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID 3901 3860 u8 rsvd[6]; 3902 3861 }; 3903 3862 ··· 3920 3873 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_FP_TQM_RING 0x6UL 3921 3874 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MRAV 0xeUL 3922 3875 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TIM 0xfUL 3923 - #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_KTLS_TKC 0x13UL 3924 - #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_KTLS_RKC 0x14UL 3925 3876 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MP_TQM_RING 0x15UL 3926 3877 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SQ_DB_SHADOW 0x16UL 3927 3878 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RQ_DB_SHADOW 0x17UL 3928 3879 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRQ_DB_SHADOW 0x18UL 3929 3880 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CQ_DB_SHADOW 0x19UL 3930 - #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_QUIC_TKC 0x1aUL 3931 - #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_QUIC_RKC 0x1bUL 3932 3881 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TBL_SCOPE 0x1cUL 3933 3882 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_XID_PARTITION 0x1dUL 3934 - #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID 0xffffUL 3935 - #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_LAST FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID 3883 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRT_TRACE 0x1eUL 3884 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRT2_TRACE 0x1fUL 3885 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CRT_TRACE 0x20UL 3886 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CRT2_TRACE 0x21UL 3887 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RIGP0_TRACE 0x22UL 3888 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_L2_HWRM_TRACE 0x23UL 3889 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_ROCE_HWRM_TRACE 0x24UL 3890 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID 0xffffUL 3891 + #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_LAST FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID 3936 3892 __le16 entry_size; 3937 3893 __le32 flags; 3938 3894 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_ENABLE_CTX_KIND_INIT 0x1UL ··· 4040 3990 __le32 flags; 4041 3991 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE 0x1UL 4042 3992 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE 0x2UL 3993 + #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_CAPS_CHANGE 0x4UL 4043 3994 u8 unused_0[3]; 4044 3995 u8 valid; 4045 3996 }; ··· 4523 4472 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24) 4524 4473 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24) 4525 4474 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24) 4526 - #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 4475 + #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPDD (0x18UL << 24) 4476 + #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP112 (0x1eUL << 24) 4477 + #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFPDD (0x1fUL << 24) 4478 + #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_CSFP (0x20UL << 24) 4479 + #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_CSFP 4527 4480 __le16 fec_cfg; 4528 4481 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL 4529 4482 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL ··· 7435 7380 u8 valid; 7436 7381 }; 7437 7382 7438 - /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */ 7383 + /* hwrm_cfa_l2_filter_cfg_input (size:384b/48B) */ 7439 7384 struct hwrm_cfa_l2_filter_cfg_input { 7440 7385 __le16 req_type; 7441 7386 __le16 cmpl_ring; ··· 7454 7399 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 2) 7455 7400 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 2) 7456 7401 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE 7402 + #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_MASK 0x30UL 7403 + #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_SFT 4 7404 + #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_NO_UPDATE (0x0UL << 4) 7405 + #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_BYPASS_LKUP (0x1UL << 4) 7406 + #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_ENABLE_LKUP (0x2UL << 4) 7407 + #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_ENABLE_LKUP 7457 7408 __le32 enables; 7458 7409 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL 7459 7410 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 7411 + #define CFA_L2_FILTER_CFG_REQ_ENABLES_PROF_FUNC 0x4UL 7412 + #define CFA_L2_FILTER_CFG_REQ_ENABLES_L2_CONTEXT_ID 0x8UL 7460 7413 __le64 l2_filter_id; 7461 7414 __le32 dst_id; 7462 7415 __le32 new_mirror_vnic_id; 7416 + __le32 prof_func; 7417 + __le32 l2_context_id; 7463 7418 }; 7464 7419 7465 7420 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */ ··· 8531 8466 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_SRV6 0xfUL 8532 8467 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 8533 8468 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GRE 0x11UL 8534 - #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GRE 8469 + #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR 0x12UL 8470 + #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES01 0x13UL 8471 + #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES02 0x14UL 8472 + #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES03 0x15UL 8473 + #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES04 0x16UL 8474 + #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES05 0x17UL 8475 + #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES06 0x18UL 8476 + #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 0x19UL 8477 + #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 8535 8478 u8 tunnel_next_proto; 8536 8479 u8 unused_0[6]; 8537 8480 }; ··· 8587 8514 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_SRV6 0xfUL 8588 8515 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 8589 8516 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GRE 0x11UL 8590 - #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GRE 8517 + #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR 0x12UL 8518 + #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES01 0x13UL 8519 + #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES02 0x14UL 8520 + #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES03 0x15UL 8521 + #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES04 0x16UL 8522 + #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES05 0x17UL 8523 + #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES06 0x18UL 8524 + #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 0x19UL 8525 + #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 8591 8526 u8 tunnel_next_proto; 8592 8527 __be16 tunnel_dst_port_val; 8593 8528 u8 unused_0[4]; ··· 8646 8565 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_SRV6 0xfUL 8647 8566 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 8648 8567 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GRE 0x11UL 8649 - #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GRE 8568 + #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR 0x12UL 8569 + #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES01 0x13UL 8570 + #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES02 0x14UL 8571 + #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES03 0x15UL 8572 + #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES04 0x16UL 8573 + #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES05 0x17UL 8574 + #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES06 0x18UL 8575 + #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 0x19UL 8576 + #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 8650 8577 u8 tunnel_next_proto; 8651 8578 __le16 tunnel_dst_port_id; 8652 8579 u8 unused_0[4]; ··· 8949 8860 u8 valid; 8950 8861 }; 8951 8862 8952 - /* generic_sw_hw_stats (size:1408b/176B) */ 8863 + /* generic_sw_hw_stats (size:1472b/184B) */ 8953 8864 struct generic_sw_hw_stats { 8954 8865 __le64 pcie_statistics_tx_tlp; 8955 8866 __le64 pcie_statistics_rx_tlp; ··· 8973 8884 __le64 hw_db_recov_dbs_dropped; 8974 8885 __le64 hw_db_recov_drops_serviced; 8975 8886 __le64 hw_db_recov_dbs_recovered; 8887 + __le64 hw_db_recov_oo_drop_count; 8976 8888 }; 8977 8889 8978 8890 /* hwrm_fw_reset_input (size:192b/24B) */

+15 -15

drivers/net/ethernet/broadcom/bnxt/bnxt_xdp.c

··· 197 197 dma_sync_single_for_cpu(&pdev->dev, mapping + offset, len, bp->rx_dir); 198 198 199 199 xdp_init_buff(xdp, buflen, &rxr->xdp_rxq); 200 - xdp_prepare_buff(xdp, data_ptr - offset, offset, len, false); 200 + xdp_prepare_buff(xdp, data_ptr - offset, offset, len, true); 201 201 } 202 202 203 203 void bnxt_xdp_buff_frags_free(struct bnxt_rx_ring_info *rxr, ··· 222 222 * false - packet should be passed to the stack. 223 223 */ 224 224 bool bnxt_rx_xdp(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, u16 cons, 225 - struct xdp_buff xdp, struct page *page, u8 **data_ptr, 225 + struct xdp_buff *xdp, struct page *page, u8 **data_ptr, 226 226 unsigned int *len, u8 *event) 227 227 { 228 228 struct bpf_prog *xdp_prog = READ_ONCE(rxr->xdp_prog); ··· 244 244 245 245 txr = rxr->bnapi->tx_ring[0]; 246 246 /* BNXT_RX_PAGE_MODE(bp) when XDP enabled */ 247 - orig_data = xdp.data; 247 + orig_data = xdp->data; 248 248 249 - act = bpf_prog_run_xdp(xdp_prog, &xdp); 249 + act = bpf_prog_run_xdp(xdp_prog, xdp); 250 250 251 251 tx_avail = bnxt_tx_avail(bp, txr); 252 252 /* If the tx ring is not full, we must not update the rx producer yet ··· 255 255 if (tx_avail != bp->tx_ring_size) 256 256 *event &= ~BNXT_RX_EVENT; 257 257 258 - *len = xdp.data_end - xdp.data; 259 - if (orig_data != xdp.data) { 260 - offset = xdp.data - xdp.data_hard_start; 261 - *data_ptr = xdp.data_hard_start + offset; 258 + *len = xdp->data_end - xdp->data; 259 + if (orig_data != xdp->data) { 260 + offset = xdp->data - xdp->data_hard_start; 261 + *data_ptr = xdp->data_hard_start + offset; 262 262 } 263 263 264 264 switch (act) { ··· 270 270 mapping = rx_buf->mapping - bp->rx_dma_offset; 271 271 *event &= BNXT_TX_CMP_EVENT; 272 272 273 - if (unlikely(xdp_buff_has_frags(&xdp))) { 274 - struct skb_shared_info *sinfo = xdp_get_shared_info_from_buff(&xdp); 273 + if (unlikely(xdp_buff_has_frags(xdp))) { 274 + struct skb_shared_info *sinfo = xdp_get_shared_info_from_buff(xdp); 275 275 276 276 tx_needed += sinfo->nr_frags; 277 277 *event = BNXT_AGG_EVENT; ··· 279 279 280 280 if (tx_avail < tx_needed) { 281 281 trace_xdp_exception(bp->dev, xdp_prog, act); 282 - bnxt_xdp_buff_frags_free(rxr, &xdp); 282 + bnxt_xdp_buff_frags_free(rxr, xdp); 283 283 bnxt_reuse_rx_data(rxr, cons, page); 284 284 return true; 285 285 } ··· 289 289 290 290 *event |= BNXT_TX_EVENT; 291 291 __bnxt_xmit_xdp(bp, txr, mapping + offset, *len, 292 - NEXT_RX(rxr->rx_prod), &xdp); 292 + NEXT_RX(rxr->rx_prod), xdp); 293 293 bnxt_reuse_rx_data(rxr, cons, page); 294 294 return true; 295 295 case XDP_REDIRECT: ··· 306 306 /* if we are unable to allocate a new buffer, abort and reuse */ 307 307 if (bnxt_alloc_rx_data(bp, rxr, rxr->rx_prod, GFP_ATOMIC)) { 308 308 trace_xdp_exception(bp->dev, xdp_prog, act); 309 - bnxt_xdp_buff_frags_free(rxr, &xdp); 309 + bnxt_xdp_buff_frags_free(rxr, xdp); 310 310 bnxt_reuse_rx_data(rxr, cons, page); 311 311 return true; 312 312 } 313 313 314 - if (xdp_do_redirect(bp->dev, &xdp, xdp_prog)) { 314 + if (xdp_do_redirect(bp->dev, xdp, xdp_prog)) { 315 315 trace_xdp_exception(bp->dev, xdp_prog, act); 316 316 page_pool_recycle_direct(rxr->page_pool, page); 317 317 return true; ··· 326 326 trace_xdp_exception(bp->dev, xdp_prog, act); 327 327 fallthrough; 328 328 case XDP_DROP: 329 - bnxt_xdp_buff_frags_free(rxr, &xdp); 329 + bnxt_xdp_buff_frags_free(rxr, xdp); 330 330 bnxt_reuse_rx_data(rxr, cons, page); 331 331 break; 332 332 }

+1 -1

drivers/net/ethernet/broadcom/bnxt/bnxt_xdp.h

··· 18 18 struct xdp_buff *xdp); 19 19 void bnxt_tx_int_xdp(struct bnxt *bp, struct bnxt_napi *bnapi, int budget); 20 20 bool bnxt_rx_xdp(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, u16 cons, 21 - struct xdp_buff xdp, struct page *page, u8 **data_ptr, 21 + struct xdp_buff *xdp, struct page *page, u8 **data_ptr, 22 22 unsigned int *len, u8 *event); 23 23 int bnxt_xdp(struct net_device *dev, struct netdev_bpf *xdp); 24 24 int bnxt_xdp_xmit(struct net_device *dev, int num_frames,

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