tjh.dev / kernel
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Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull arm64 fixes from Catalin Marinas:

- Cortex-A55 errata workaround (repeat TLBI)

- AMPERE1 added to the Spectre-BHB affected list

- MTE fix to avoid setting PG_mte_tagged if no tags have been touched
on a page

- Fixed typo in the SCTLR_EL1.SPINTMASK bit naming (the commit log has
other typos)

- perf: return value check in ali_drw_pmu_probe(),
ALIBABA_UNCORE_DRW_PMU dependency on ACPI

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
arm64: Add AMPERE1 to the Spectre-BHB affected list
arm64: mte: Avoid setting PG_mte_tagged if no tags cleared or restored
MAINTAINERS: rectify file entry in ALIBABA PMU DRIVER
drivers/perf: ALIBABA_UNCORE_DRW_PMU should depend on ACPI
drivers/perf: fix return value check in ali_drw_pmu_probe()
arm64: errata: Add Cortex-A55 to the repeat tlbi list
arm64/sysreg: Fix typo in SCTR_EL1.SPINTMASK

Linus Torvalds 1df046ab 5e714bf1

+52 -8
+2
Documentation/arm64/silicon-errata.rst
··· 76 76 +----------------+-----------------+-----------------+-----------------------------+ 77 77 | ARM | Cortex-A55 | #1530923 | ARM64_ERRATUM_1530923 | 78 78 +----------------+-----------------+-----------------+-----------------------------+ 79 + | ARM | Cortex-A55 | #2441007 | ARM64_ERRATUM_2441007 | 80 + +----------------+-----------------+-----------------+-----------------------------+ 79 81 | ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 | 80 82 +----------------+-----------------+-----------------+-----------------------------+ 81 83 | ARM | Cortex-A57 | #852523 | N/A |
+1 -1
MAINTAINERS
··· 752 752 M: Shuai Xue <xueshuai@linux.alibaba.com> 753 753 S: Supported 754 754 F: Documentation/admin-guide/perf/alibaba_pmu.rst 755 - F: drivers/perf/alibaba_uncore_dwr_pmu.c 755 + F: drivers/perf/alibaba_uncore_drw_pmu.c 756 756 757 757 ALIENWARE WMI DRIVER 758 758 L: Dell.Client.Kernel@dell.com
+17
arch/arm64/Kconfig
··· 632 632 config ARM64_WORKAROUND_REPEAT_TLBI 633 633 bool 634 634 635 + config ARM64_ERRATUM_2441007 636 + bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI" 637 + default y 638 + select ARM64_WORKAROUND_REPEAT_TLBI 639 + help 640 + This option adds a workaround for ARM Cortex-A55 erratum #2441007. 641 + 642 + Under very rare circumstances, affected Cortex-A55 CPUs 643 + may not handle a race between a break-before-make sequence on one 644 + CPU, and another CPU accessing the same page. This could allow a 645 + store to a page that has been unmapped. 646 + 647 + Work around this by adding the affected CPUs to the list that needs 648 + TLB sequences to be done twice. 649 + 650 + If unsure, say Y. 651 + 635 652 config ARM64_ERRATUM_1286807 636 653 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation" 637 654 default y
+4
arch/arm64/include/asm/cputype.h
··· 60 60 #define ARM_CPU_IMP_FUJITSU 0x46 61 61 #define ARM_CPU_IMP_HISI 0x48 62 62 #define ARM_CPU_IMP_APPLE 0x61 63 + #define ARM_CPU_IMP_AMPERE 0xC0 63 64 64 65 #define ARM_CPU_PART_AEM_V8 0xD0F 65 66 #define ARM_CPU_PART_FOUNDATION 0xD00 ··· 124 123 #define APPLE_CPU_PART_M1_ICESTORM_MAX 0x028 125 124 #define APPLE_CPU_PART_M1_FIRESTORM_MAX 0x029 126 125 126 + #define AMPERE_CPU_PART_AMPERE1 0xAC3 127 + 127 128 #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) 128 129 #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) 129 130 #define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72) ··· 175 172 #define MIDR_APPLE_M1_FIRESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_PRO) 176 173 #define MIDR_APPLE_M1_ICESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_MAX) 177 174 #define MIDR_APPLE_M1_FIRESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_MAX) 175 + #define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1) 178 176 179 177 /* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */ 180 178 #define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX
+5
arch/arm64/kernel/cpu_errata.c
··· 230 230 ERRATA_MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xe), 231 231 }, 232 232 #endif 233 + #ifdef CONFIG_ARM64_ERRATUM_2441007 234 + { 235 + ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 236 + }, 237 + #endif 233 238 #ifdef CONFIG_ARM64_ERRATUM_2441009 234 239 { 235 240 /* Cortex-A510 r0p0 -> r1p1. Fixed in r1p2 */
+7 -2
arch/arm64/kernel/mte.c
··· 48 48 if (!pte_is_tagged) 49 49 return; 50 50 51 - mte_clear_page_tags(page_address(page)); 51 + /* 52 + * Test PG_mte_tagged again in case it was racing with another 53 + * set_pte_at(). 54 + */ 55 + if (!test_and_set_bit(PG_mte_tagged, &page->flags)) 56 + mte_clear_page_tags(page_address(page)); 52 57 } 53 58 54 59 void mte_sync_tags(pte_t old_pte, pte_t pte) ··· 69 64 70 65 /* if PG_mte_tagged is set, tags have already been initialised */ 71 66 for (i = 0; i < nr_pages; i++, page++) { 72 - if (!test_and_set_bit(PG_mte_tagged, &page->flags)) 67 + if (!test_bit(PG_mte_tagged, &page->flags)) 73 68 mte_sync_page_tags(page, old_pte, check_swap, 74 69 pte_is_tagged); 75 70 }
+6
arch/arm64/kernel/proton-pack.c
··· 868 868 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1), 869 869 {}, 870 870 }; 871 + static const struct midr_range spectre_bhb_k11_list[] = { 872 + MIDR_ALL_VERSIONS(MIDR_AMPERE1), 873 + {}, 874 + }; 871 875 static const struct midr_range spectre_bhb_k8_list[] = { 872 876 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 873 877 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), ··· 882 878 k = 32; 883 879 else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k24_list)) 884 880 k = 24; 881 + else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k11_list)) 882 + k = 11; 885 883 else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k8_list)) 886 884 k = 8; 887 885
+6 -1
arch/arm64/mm/mteswap.c
··· 53 53 if (!tags) 54 54 return false; 55 55 56 - mte_restore_page_tags(page_address(page), tags); 56 + /* 57 + * Test PG_mte_tagged again in case it was racing with another 58 + * set_pte_at(). 59 + */ 60 + if (!test_and_set_bit(PG_mte_tagged, &page->flags)) 61 + mte_restore_page_tags(page_address(page), tags); 57 62 58 63 return true; 59 64 }
+1 -1
arch/arm64/tools/sysreg
··· 732 732 733 733 Sysreg SCTLR_EL1 3 0 1 0 0 734 734 Field 63 TIDCP 735 - Field 62 SPINMASK 735 + Field 62 SPINTMASK 736 736 Field 61 NMI 737 737 Field 60 EnTP2 738 738 Res0 59:58
+1 -1
drivers/perf/Kconfig
··· 185 185 186 186 config ALIBABA_UNCORE_DRW_PMU 187 187 tristate "Alibaba T-Head Yitian 710 DDR Sub-system Driveway PMU driver" 188 - depends on ARM64 || COMPILE_TEST 188 + depends on (ARM64 && ACPI) || COMPILE_TEST 189 189 help 190 190 Support for Driveway PMU events monitoring on Yitian 710 DDR 191 191 Sub-system.
+2 -2
drivers/perf/alibaba_uncore_drw_pmu.c
··· 658 658 659 659 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 660 660 drw_pmu->cfg_base = devm_ioremap_resource(&pdev->dev, res); 661 - if (!drw_pmu->cfg_base) 662 - return -ENOMEM; 661 + if (IS_ERR(drw_pmu->cfg_base)) 662 + return PTR_ERR(drw_pmu->cfg_base); 663 663 664 664 name = devm_kasprintf(drw_pmu->dev, GFP_KERNEL, "ali_drw_%llx", 665 665 (u64) (res->start >> ALI_DRW_PMU_PA_SHIFT));