tjh.dev / kernel
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Merge branch kvm-arm64/resx into kvmarm-master/next

* kvm-arm64/resx:
: .
: Add infrastructure to deal with the full gamut of RESx bits
: for NV. As a result, it is now possible to have the expected
: semantics for some bits such as SCTLR_EL2.SPAN.
: .
KVM: arm64: Add debugfs file dumping computed RESx values
KVM: arm64: Add sanitisation to SCTLR_EL2
KVM: arm64: Remove all traces of HCR_EL2.MIOCNCE
KVM: arm64: Remove all traces of FEAT_TME
KVM: arm64: Simplify handling of full register invalid constraint
KVM: arm64: Get rid of FIXED_VALUE altogether
KVM: arm64: Simplify handling of HCR_EL2.E2H RESx
KVM: arm64: Move RESx into individual register descriptors
KVM: arm64: Add RES1_WHEN_E2Hx constraints as configuration flags
KVM: arm64: Add REQUIRES_E2H1 constraint as configuration flags
KVM: arm64: Simplify FIXED_VALUE handling
KVM: arm64: Convert HCR_EL2.RW to AS_RES1
KVM: arm64: Correctly handle SCTLR_EL1 RES1 bits for unsupported features
KVM: arm64: Allow RES1 bits to be inferred from configuration
KVM: arm64: Inherit RESx bits from FGT register descriptors
KVM: arm64: Extend unified RESx handling to runtime sanitisation
KVM: arm64: Introduce data structure tracking both RES0 and RES1 bits
KVM: arm64: Introduce standalone FGU computing primitive
KVM: arm64: Remove duplicate configuration for SCTLR_EL1.{EE,E0E}
arm64: Convert SCTLR_EL2 to sysreg infrastructure

Signed-off-by: Marc Zyngier <maz@kernel.org>

Marc Zyngier 1df3f01e 3ef5ba66

+482 -317
+33 -7
arch/arm64/include/asm/kvm_host.h
··· 492 492 DBGVCR32_EL2, /* Debug Vector Catch Register */ 493 493 494 494 /* EL2 registers */ 495 - SCTLR_EL2, /* System Control Register (EL2) */ 496 495 ACTLR_EL2, /* Auxiliary Control Register (EL2) */ 497 496 CPTR_EL2, /* Architectural Feature Trap Register (EL2) */ 498 497 HACR_EL2, /* Hypervisor Auxiliary Control Register */ ··· 522 523 523 524 /* Anything from this can be RES0/RES1 sanitised */ 524 525 MARKER(__SANITISED_REG_START__), 526 + SCTLR_EL2, /* System Control Register (EL2) */ 525 527 TCR2_EL2, /* Extended Translation Control Register (EL2) */ 526 528 SCTLR2_EL2, /* System Control Register 2 (EL2) */ 527 529 MDCR_EL2, /* Monitor Debug Configuration Register (EL2) */ ··· 623 623 NR_SYS_REGS /* Nothing after this line! */ 624 624 }; 625 625 626 - struct kvm_sysreg_masks { 627 - struct { 628 - u64 res0; 629 - u64 res1; 630 - } mask[NR_SYS_REGS - __SANITISED_REG_START__]; 626 + struct resx { 627 + u64 res0; 628 + u64 res1; 631 629 }; 630 + 631 + struct kvm_sysreg_masks { 632 + struct resx mask[NR_SYS_REGS - __SANITISED_REG_START__]; 633 + }; 634 + 635 + static inline struct resx __kvm_get_sysreg_resx(struct kvm_arch *arch, 636 + enum vcpu_sysreg sr) 637 + { 638 + struct kvm_sysreg_masks *masks; 639 + 640 + masks = arch->sysreg_masks; 641 + if (likely(masks && 642 + sr >= __SANITISED_REG_START__ && sr < NR_SYS_REGS)) 643 + return masks->mask[sr - __SANITISED_REG_START__]; 644 + 645 + return (struct resx){}; 646 + } 647 + 648 + #define kvm_get_sysreg_resx(k, sr) __kvm_get_sysreg_resx(&(k)->arch, (sr)) 649 + 650 + static inline void __kvm_set_sysreg_resx(struct kvm_arch *arch, 651 + enum vcpu_sysreg sr, struct resx resx) 652 + { 653 + arch->sysreg_masks->mask[sr - __SANITISED_REG_START__] = resx; 654 + } 655 + 656 + #define kvm_set_sysreg_resx(k, sr, resx) \ 657 + __kvm_set_sysreg_resx(&(k)->arch, (sr), (resx)) 632 658 633 659 struct fgt_masks { 634 660 const char *str; ··· 1630 1604 } 1631 1605 1632 1606 void compute_fgu(struct kvm *kvm, enum fgt_group_id fgt); 1633 - void get_reg_fixed_bits(struct kvm *kvm, enum vcpu_sysreg reg, u64 *res0, u64 *res1); 1607 + struct resx get_reg_fixed_bits(struct kvm *kvm, enum vcpu_sysreg reg); 1634 1608 void check_feature_map(void); 1635 1609 void kvm_vcpu_load_fgt(struct kvm_vcpu *vcpu); 1636 1610
-7
arch/arm64/include/asm/sysreg.h
··· 504 504 #define SYS_VPIDR_EL2 sys_reg(3, 4, 0, 0, 0) 505 505 #define SYS_VMPIDR_EL2 sys_reg(3, 4, 0, 0, 5) 506 506 507 - #define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0) 508 507 #define SYS_ACTLR_EL2 sys_reg(3, 4, 1, 0, 1) 509 508 #define SYS_SCTLR2_EL2 sys_reg(3, 4, 1, 0, 3) 510 509 #define SYS_HCR_EL2 sys_reg(3, 4, 1, 1, 0) ··· 835 836 #define SCTLR_ELx_A (BIT(1)) 836 837 #define SCTLR_ELx_M (BIT(0)) 837 838 838 - /* SCTLR_EL2 specific flags. */ 839 - #define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \ 840 - (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \ 841 - (BIT(29))) 842 - 843 - #define SCTLR_EL2_BT (BIT(36)) 844 839 #ifdef CONFIG_CPU_BIG_ENDIAN 845 840 #define ENDIAN_SET_EL2 SCTLR_ELx_EE 846 841 #else
+236 -197
arch/arm64/kvm/config.c
··· 22 22 23 23 #define NEVER_FGU BIT(0) /* Can trap, but never UNDEF */ 24 24 #define CALL_FUNC BIT(1) /* Needs to evaluate tons of crap */ 25 - #define FIXED_VALUE BIT(2) /* RAZ/WI or RAO/WI in KVM */ 25 + #define FORCE_RESx BIT(2) /* Unconditional RESx */ 26 26 #define MASKS_POINTER BIT(3) /* Pointer to fgt_masks struct instead of bits */ 27 + #define AS_RES1 BIT(4) /* RES1 when not supported */ 28 + #define REQUIRES_E2H1 BIT(5) /* Add HCR_EL2.E2H RES1 as a pre-condition */ 29 + #define RES1_WHEN_E2H0 BIT(6) /* RES1 when E2H=0 and not supported */ 30 + #define RES1_WHEN_E2H1 BIT(7) /* RES1 when E2H=1 and not supported */ 27 31 28 32 unsigned long flags; 29 33 ··· 40 36 s8 lo_lim; 41 37 }; 42 38 bool (*match)(struct kvm *); 43 - bool (*fval)(struct kvm *, u64 *); 44 39 }; 45 40 }; 46 41 ··· 72 69 .lo_lim = id ##_## fld ##_## lim \ 73 70 } 74 71 75 - #define __NEEDS_FEAT_2(m, f, w, fun, dummy) \ 76 - { \ 77 - .w = (m), \ 78 - .flags = (f) | CALL_FUNC, \ 79 - .fval = (fun), \ 80 - } 81 - 82 72 #define __NEEDS_FEAT_1(m, f, w, fun) \ 83 73 { \ 84 74 .w = (m), \ ··· 79 83 .match = (fun), \ 80 84 } 81 85 86 + #define __NEEDS_FEAT_0(m, f, w, ...) \ 87 + { \ 88 + .w = (m), \ 89 + .flags = (f), \ 90 + } 91 + 82 92 #define __NEEDS_FEAT_FLAG(m, f, w, ...) \ 83 93 CONCATENATE(__NEEDS_FEAT_, COUNT_ARGS(__VA_ARGS__))(m, f, w, __VA_ARGS__) 84 94 85 95 #define NEEDS_FEAT_FLAG(m, f, ...) \ 86 96 __NEEDS_FEAT_FLAG(m, f, bits, __VA_ARGS__) 87 - 88 - #define NEEDS_FEAT_FIXED(m, ...) \ 89 - __NEEDS_FEAT_FLAG(m, FIXED_VALUE, bits, __VA_ARGS__, 0) 90 97 91 98 #define NEEDS_FEAT_MASKS(p, ...) \ 92 99 __NEEDS_FEAT_FLAG(p, MASKS_POINTER, masks, __VA_ARGS__) ··· 100 101 */ 101 102 #define NEEDS_FEAT(m, ...) NEEDS_FEAT_FLAG(m, 0, __VA_ARGS__) 102 103 104 + /* Declare fixed RESx bits */ 105 + #define FORCE_RES0(m) NEEDS_FEAT_FLAG(m, FORCE_RESx) 106 + #define FORCE_RES1(m) NEEDS_FEAT_FLAG(m, FORCE_RESx | AS_RES1) 107 + 103 108 /* 104 - * Declare the dependency between a non-FGT register, a set of 105 - * feature, and the set of individual bits it contains. This generates 106 - * a struct reg_feat_map_desc. 109 + * Declare the dependency between a non-FGT register, a set of features, 110 + * and the set of individual bits it contains. This generates a struct 111 + * reg_feat_map_desc. 107 112 */ 108 113 #define DECLARE_FEAT_MAP(n, r, m, f) \ 109 114 struct reg_feat_map_desc n = { \ ··· 187 184 #define FEAT_RME ID_AA64PFR0_EL1, RME, IMP 188 185 #define FEAT_MPAM ID_AA64PFR0_EL1, MPAM, 1 189 186 #define FEAT_S2FWB ID_AA64MMFR2_EL1, FWB, IMP 190 - #define FEAT_TME ID_AA64ISAR0_EL1, TME, IMP 191 187 #define FEAT_TWED ID_AA64MMFR1_EL1, TWED, IMP 192 188 #define FEAT_E2H0 ID_AA64MMFR4_EL1, E2H0, IMP 193 189 #define FEAT_SRMASK ID_AA64MMFR4_EL1, SRMASK, IMP ··· 312 310 (read_sysreg_s(SYS_TRBIDR_EL1) & TRBIDR_EL1_MPAM)); 313 311 } 314 312 315 - static bool feat_asid2_e2h1(struct kvm *kvm) 316 - { 317 - return kvm_has_feat(kvm, FEAT_ASID2) && !kvm_has_feat(kvm, FEAT_E2H0); 318 - } 319 - 320 - static bool feat_d128_e2h1(struct kvm *kvm) 321 - { 322 - return kvm_has_feat(kvm, FEAT_D128) && !kvm_has_feat(kvm, FEAT_E2H0); 323 - } 324 - 325 - static bool feat_mec_e2h1(struct kvm *kvm) 326 - { 327 - return kvm_has_feat(kvm, FEAT_MEC) && !kvm_has_feat(kvm, FEAT_E2H0); 328 - } 329 - 330 313 static bool feat_ebep_pmuv3_ss(struct kvm *kvm) 331 314 { 332 315 return kvm_has_feat(kvm, FEAT_EBEP) || kvm_has_feat(kvm, FEAT_PMUv3_SS); ··· 373 386 static bool feat_vmid16(struct kvm *kvm) 374 387 { 375 388 return kvm_has_feat_enum(kvm, ID_AA64MMFR1_EL1, VMIDBits, 16); 376 - } 377 - 378 - static bool compute_hcr_rw(struct kvm *kvm, u64 *bits) 379 - { 380 - /* This is purely academic: AArch32 and NV are mutually exclusive */ 381 - if (bits) { 382 - if (kvm_has_feat(kvm, FEAT_AA32EL1)) 383 - *bits &= ~HCR_EL2_RW; 384 - else 385 - *bits |= HCR_EL2_RW; 386 - } 387 - 388 - return true; 389 - } 390 - 391 - static bool compute_hcr_e2h(struct kvm *kvm, u64 *bits) 392 - { 393 - if (bits) { 394 - if (kvm_has_feat(kvm, FEAT_E2H0)) 395 - *bits &= ~HCR_EL2_E2H; 396 - else 397 - *bits |= HCR_EL2_E2H; 398 - } 399 - 400 - return true; 401 389 } 402 390 403 391 static const struct reg_bits_to_feat_map hfgrtr_feat_map[] = { ··· 928 966 929 967 static const struct reg_bits_to_feat_map hcr_feat_map[] = { 930 968 NEEDS_FEAT(HCR_EL2_TID0, FEAT_AA32EL0), 931 - NEEDS_FEAT_FIXED(HCR_EL2_RW, compute_hcr_rw), 969 + NEEDS_FEAT_FLAG(HCR_EL2_RW, AS_RES1, FEAT_AA32EL1), 932 970 NEEDS_FEAT(HCR_EL2_HCD, not_feat_aa64el3), 933 971 NEEDS_FEAT(HCR_EL2_AMO | 934 972 HCR_EL2_BSU | ··· 938 976 HCR_EL2_FMO | 939 977 HCR_EL2_ID | 940 978 HCR_EL2_IMO | 941 - HCR_EL2_MIOCNCE | 942 979 HCR_EL2_PTW | 943 980 HCR_EL2_SWIO | 944 981 HCR_EL2_TACR | ··· 989 1028 NEEDS_FEAT(HCR_EL2_FIEN, feat_rasv1p1), 990 1029 NEEDS_FEAT(HCR_EL2_GPF, FEAT_RME), 991 1030 NEEDS_FEAT(HCR_EL2_FWB, FEAT_S2FWB), 992 - NEEDS_FEAT(HCR_EL2_TME, FEAT_TME), 993 1031 NEEDS_FEAT(HCR_EL2_TWEDEL | 994 1032 HCR_EL2_TWEDEn, 995 1033 FEAT_TWED), 996 - NEEDS_FEAT_FIXED(HCR_EL2_E2H, compute_hcr_e2h), 1034 + NEEDS_FEAT_FLAG(HCR_EL2_E2H, RES1_WHEN_E2H1 | FORCE_RESx), 1035 + FORCE_RES0(HCR_EL2_RES0), 1036 + FORCE_RES1(HCR_EL2_RES1), 997 1037 }; 998 1038 999 1039 static const DECLARE_FEAT_MAP(hcr_desc, HCR_EL2, ··· 1015 1053 SCTLR2_EL1_CPTM | 1016 1054 SCTLR2_EL1_CPTM0, 1017 1055 FEAT_CPA2), 1056 + FORCE_RES0(SCTLR2_EL1_RES0), 1057 + FORCE_RES1(SCTLR2_EL1_RES1), 1018 1058 }; 1019 1059 1020 1060 static const DECLARE_FEAT_MAP(sctlr2_desc, SCTLR2_EL1, 1021 1061 sctlr2_feat_map, FEAT_SCTLR2); 1022 1062 1023 1063 static const struct reg_bits_to_feat_map tcr2_el2_feat_map[] = { 1024 - NEEDS_FEAT(TCR2_EL2_FNG1 | 1025 - TCR2_EL2_FNG0 | 1026 - TCR2_EL2_A2, 1027 - feat_asid2_e2h1), 1028 - NEEDS_FEAT(TCR2_EL2_DisCH1 | 1029 - TCR2_EL2_DisCH0 | 1030 - TCR2_EL2_D128, 1031 - feat_d128_e2h1), 1032 - NEEDS_FEAT(TCR2_EL2_AMEC1, feat_mec_e2h1), 1064 + NEEDS_FEAT_FLAG(TCR2_EL2_FNG1 | 1065 + TCR2_EL2_FNG0 | 1066 + TCR2_EL2_A2, 1067 + REQUIRES_E2H1, FEAT_ASID2), 1068 + NEEDS_FEAT_FLAG(TCR2_EL2_DisCH1 | 1069 + TCR2_EL2_DisCH0 | 1070 + TCR2_EL2_D128, 1071 + REQUIRES_E2H1, FEAT_D128), 1072 + NEEDS_FEAT_FLAG(TCR2_EL2_AMEC1, REQUIRES_E2H1, FEAT_MEC), 1033 1073 NEEDS_FEAT(TCR2_EL2_AMEC0, FEAT_MEC), 1034 1074 NEEDS_FEAT(TCR2_EL2_HAFT, FEAT_HAFT), 1035 1075 NEEDS_FEAT(TCR2_EL2_PTTWI | ··· 1042 1078 TCR2_EL2_E0POE, 1043 1079 FEAT_S1POE), 1044 1080 NEEDS_FEAT(TCR2_EL2_PIE, FEAT_S1PIE), 1081 + FORCE_RES0(TCR2_EL2_RES0), 1082 + FORCE_RES1(TCR2_EL2_RES1), 1045 1083 }; 1046 1084 1047 1085 static const DECLARE_FEAT_MAP(tcr2_el2_desc, TCR2_EL2, 1048 1086 tcr2_el2_feat_map, FEAT_TCR2); 1049 1087 1050 1088 static const struct reg_bits_to_feat_map sctlr_el1_feat_map[] = { 1051 - NEEDS_FEAT(SCTLR_EL1_CP15BEN | 1052 - SCTLR_EL1_ITD | 1053 - SCTLR_EL1_SED, 1054 - FEAT_AA32EL0), 1089 + NEEDS_FEAT(SCTLR_EL1_CP15BEN, FEAT_AA32EL0), 1090 + NEEDS_FEAT_FLAG(SCTLR_EL1_ITD | 1091 + SCTLR_EL1_SED, 1092 + AS_RES1, FEAT_AA32EL0), 1055 1093 NEEDS_FEAT(SCTLR_EL1_BT0 | 1056 1094 SCTLR_EL1_BT1, 1057 1095 FEAT_BTI), 1058 1096 NEEDS_FEAT(SCTLR_EL1_CMOW, FEAT_CMOW), 1059 - NEEDS_FEAT(SCTLR_EL1_TSCXT, feat_csv2_2_csv2_1p2), 1060 - NEEDS_FEAT(SCTLR_EL1_EIS | 1061 - SCTLR_EL1_EOS, 1062 - FEAT_ExS), 1097 + NEEDS_FEAT_FLAG(SCTLR_EL1_TSCXT, 1098 + AS_RES1, feat_csv2_2_csv2_1p2), 1099 + NEEDS_FEAT_FLAG(SCTLR_EL1_EIS | 1100 + SCTLR_EL1_EOS, 1101 + AS_RES1, FEAT_ExS), 1063 1102 NEEDS_FEAT(SCTLR_EL1_EnFPM, FEAT_FPMR), 1064 1103 NEEDS_FEAT(SCTLR_EL1_IESB, FEAT_IESB), 1065 1104 NEEDS_FEAT(SCTLR_EL1_EnALS, FEAT_LS64), 1066 1105 NEEDS_FEAT(SCTLR_EL1_EnAS0, FEAT_LS64_ACCDATA), 1067 1106 NEEDS_FEAT(SCTLR_EL1_EnASR, FEAT_LS64_V), 1068 1107 NEEDS_FEAT(SCTLR_EL1_nAA, FEAT_LSE2), 1069 - NEEDS_FEAT(SCTLR_EL1_LSMAOE | 1070 - SCTLR_EL1_nTLSMD, 1071 - FEAT_LSMAOC), 1108 + NEEDS_FEAT_FLAG(SCTLR_EL1_LSMAOE | 1109 + SCTLR_EL1_nTLSMD, 1110 + AS_RES1, FEAT_LSMAOC), 1072 1111 NEEDS_FEAT(SCTLR_EL1_EE, FEAT_MixedEnd), 1073 1112 NEEDS_FEAT(SCTLR_EL1_E0E, feat_mixedendel0), 1074 1113 NEEDS_FEAT(SCTLR_EL1_MSCEn, FEAT_MOPS), ··· 1087 1120 NEEDS_FEAT(SCTLR_EL1_NMI | 1088 1121 SCTLR_EL1_SPINTMASK, 1089 1122 FEAT_NMI), 1090 - NEEDS_FEAT(SCTLR_EL1_SPAN, FEAT_PAN), 1123 + NEEDS_FEAT_FLAG(SCTLR_EL1_SPAN, 1124 + AS_RES1, FEAT_PAN), 1091 1125 NEEDS_FEAT(SCTLR_EL1_EPAN, FEAT_PAN3), 1092 1126 NEEDS_FEAT(SCTLR_EL1_EnDA | 1093 1127 SCTLR_EL1_EnDB | ··· 1099 1131 NEEDS_FEAT(SCTLR_EL1_EnRCTX, FEAT_SPECRES), 1100 1132 NEEDS_FEAT(SCTLR_EL1_DSSBS, FEAT_SSBS), 1101 1133 NEEDS_FEAT(SCTLR_EL1_TIDCP, FEAT_TIDCP1), 1102 - NEEDS_FEAT(SCTLR_EL1_TME0 | 1103 - SCTLR_EL1_TME | 1104 - SCTLR_EL1_TMT0 | 1105 - SCTLR_EL1_TMT, 1106 - FEAT_TME), 1107 1134 NEEDS_FEAT(SCTLR_EL1_TWEDEL | 1108 1135 SCTLR_EL1_TWEDEn, 1109 1136 FEAT_TWED), 1110 1137 NEEDS_FEAT(SCTLR_EL1_UCI | 1111 - SCTLR_EL1_EE | 1112 - SCTLR_EL1_E0E | 1113 1138 SCTLR_EL1_WXN | 1114 1139 SCTLR_EL1_nTWE | 1115 1140 SCTLR_EL1_nTWI | ··· 1116 1155 SCTLR_EL1_A | 1117 1156 SCTLR_EL1_M, 1118 1157 FEAT_AA64EL1), 1158 + FORCE_RES0(SCTLR_EL1_RES0), 1159 + FORCE_RES1(SCTLR_EL1_RES1), 1119 1160 }; 1120 1161 1121 1162 static const DECLARE_FEAT_MAP(sctlr_el1_desc, SCTLR_EL1, 1122 1163 sctlr_el1_feat_map, FEAT_AA64EL1); 1164 + 1165 + static const struct reg_bits_to_feat_map sctlr_el2_feat_map[] = { 1166 + NEEDS_FEAT_FLAG(SCTLR_EL2_CP15BEN, 1167 + RES1_WHEN_E2H0 | REQUIRES_E2H1, 1168 + FEAT_AA32EL0), 1169 + NEEDS_FEAT_FLAG(SCTLR_EL2_ITD | 1170 + SCTLR_EL2_SED, 1171 + RES1_WHEN_E2H1 | REQUIRES_E2H1, 1172 + FEAT_AA32EL0), 1173 + NEEDS_FEAT_FLAG(SCTLR_EL2_BT0, REQUIRES_E2H1, FEAT_BTI), 1174 + NEEDS_FEAT(SCTLR_EL2_BT, FEAT_BTI), 1175 + NEEDS_FEAT_FLAG(SCTLR_EL2_CMOW, REQUIRES_E2H1, FEAT_CMOW), 1176 + NEEDS_FEAT_FLAG(SCTLR_EL2_TSCXT, 1177 + RES1_WHEN_E2H1 | REQUIRES_E2H1, 1178 + feat_csv2_2_csv2_1p2), 1179 + NEEDS_FEAT_FLAG(SCTLR_EL2_EIS | 1180 + SCTLR_EL2_EOS, 1181 + AS_RES1, FEAT_ExS), 1182 + NEEDS_FEAT(SCTLR_EL2_EnFPM, FEAT_FPMR), 1183 + NEEDS_FEAT(SCTLR_EL2_IESB, FEAT_IESB), 1184 + NEEDS_FEAT_FLAG(SCTLR_EL2_EnALS, REQUIRES_E2H1, FEAT_LS64), 1185 + NEEDS_FEAT_FLAG(SCTLR_EL2_EnAS0, REQUIRES_E2H1, FEAT_LS64_ACCDATA), 1186 + NEEDS_FEAT_FLAG(SCTLR_EL2_EnASR, REQUIRES_E2H1, FEAT_LS64_V), 1187 + NEEDS_FEAT(SCTLR_EL2_nAA, FEAT_LSE2), 1188 + NEEDS_FEAT_FLAG(SCTLR_EL2_LSMAOE | 1189 + SCTLR_EL2_nTLSMD, 1190 + AS_RES1 | REQUIRES_E2H1, FEAT_LSMAOC), 1191 + NEEDS_FEAT(SCTLR_EL2_EE, FEAT_MixedEnd), 1192 + NEEDS_FEAT_FLAG(SCTLR_EL2_E0E, REQUIRES_E2H1, feat_mixedendel0), 1193 + NEEDS_FEAT_FLAG(SCTLR_EL2_MSCEn, REQUIRES_E2H1, FEAT_MOPS), 1194 + NEEDS_FEAT_FLAG(SCTLR_EL2_ATA0 | 1195 + SCTLR_EL2_TCF0, 1196 + REQUIRES_E2H1, FEAT_MTE2), 1197 + NEEDS_FEAT(SCTLR_EL2_ATA | 1198 + SCTLR_EL2_TCF, 1199 + FEAT_MTE2), 1200 + NEEDS_FEAT(SCTLR_EL2_ITFSB, feat_mte_async), 1201 + NEEDS_FEAT_FLAG(SCTLR_EL2_TCSO0, REQUIRES_E2H1, FEAT_MTE_STORE_ONLY), 1202 + NEEDS_FEAT(SCTLR_EL2_TCSO, 1203 + FEAT_MTE_STORE_ONLY), 1204 + NEEDS_FEAT(SCTLR_EL2_NMI | 1205 + SCTLR_EL2_SPINTMASK, 1206 + FEAT_NMI), 1207 + NEEDS_FEAT_FLAG(SCTLR_EL2_SPAN, AS_RES1 | REQUIRES_E2H1, FEAT_PAN), 1208 + NEEDS_FEAT_FLAG(SCTLR_EL2_EPAN, REQUIRES_E2H1, FEAT_PAN3), 1209 + NEEDS_FEAT(SCTLR_EL2_EnDA | 1210 + SCTLR_EL2_EnDB | 1211 + SCTLR_EL2_EnIA | 1212 + SCTLR_EL2_EnIB, 1213 + feat_pauth), 1214 + NEEDS_FEAT_FLAG(SCTLR_EL2_EnTP2, REQUIRES_E2H1, FEAT_SME), 1215 + NEEDS_FEAT(SCTLR_EL2_EnRCTX, FEAT_SPECRES), 1216 + NEEDS_FEAT(SCTLR_EL2_DSSBS, FEAT_SSBS), 1217 + NEEDS_FEAT_FLAG(SCTLR_EL2_TIDCP, REQUIRES_E2H1, FEAT_TIDCP1), 1218 + NEEDS_FEAT_FLAG(SCTLR_EL2_TWEDEL | 1219 + SCTLR_EL2_TWEDEn, 1220 + REQUIRES_E2H1, FEAT_TWED), 1221 + NEEDS_FEAT_FLAG(SCTLR_EL2_nTWE | 1222 + SCTLR_EL2_nTWI, 1223 + AS_RES1 | REQUIRES_E2H1, FEAT_AA64EL2), 1224 + NEEDS_FEAT_FLAG(SCTLR_EL2_UCI | 1225 + SCTLR_EL2_UCT | 1226 + SCTLR_EL2_DZE | 1227 + SCTLR_EL2_SA0, 1228 + REQUIRES_E2H1, FEAT_AA64EL2), 1229 + NEEDS_FEAT(SCTLR_EL2_WXN | 1230 + SCTLR_EL2_I | 1231 + SCTLR_EL2_SA | 1232 + SCTLR_EL2_C | 1233 + SCTLR_EL2_A | 1234 + SCTLR_EL2_M, 1235 + FEAT_AA64EL2), 1236 + FORCE_RES0(SCTLR_EL2_RES0), 1237 + FORCE_RES1(SCTLR_EL2_RES1), 1238 + }; 1239 + 1240 + static const DECLARE_FEAT_MAP(sctlr_el2_desc, SCTLR_EL2, 1241 + sctlr_el2_feat_map, FEAT_AA64EL2); 1123 1242 1124 1243 static const struct reg_bits_to_feat_map mdcr_el2_feat_map[] = { 1125 1244 NEEDS_FEAT(MDCR_EL2_EBWE, FEAT_Debugv8p9), ··· 1230 1189 MDCR_EL2_TDE | 1231 1190 MDCR_EL2_TDRA, 1232 1191 FEAT_AA64EL1), 1192 + FORCE_RES0(MDCR_EL2_RES0), 1193 + FORCE_RES1(MDCR_EL2_RES1), 1233 1194 }; 1234 1195 1235 1196 static const DECLARE_FEAT_MAP(mdcr_el2_desc, MDCR_EL2, ··· 1270 1227 VTCR_EL2_SL0 | 1271 1228 VTCR_EL2_T0SZ, 1272 1229 FEAT_AA64EL1), 1230 + FORCE_RES0(VTCR_EL2_RES0), 1231 + FORCE_RES1(VTCR_EL2_RES1), 1273 1232 }; 1274 1233 1275 1234 static const DECLARE_FEAT_MAP(vtcr_el2_desc, VTCR_EL2, ··· 1282 1237 { 1283 1238 u64 mask = 0; 1284 1239 1240 + /* 1241 + * Don't account for FORCE_RESx that are architectural, and 1242 + * therefore part of the resx parameter. Other FORCE_RESx bits 1243 + * are implementation choices, and therefore accounted for. 1244 + */ 1285 1245 for (int i = 0; i < map_size; i++) 1286 - mask |= map[i].bits; 1246 + if (!((map[i].flags & FORCE_RESx) && (map[i].bits & resx))) 1247 + mask |= map[i].bits; 1287 1248 1288 1249 if (mask != ~resx) 1289 1250 kvm_err("Undefined %s behaviour, bits %016llx\n", ··· 1325 1274 check_reg_desc(&sctlr2_desc); 1326 1275 check_reg_desc(&tcr2_el2_desc); 1327 1276 check_reg_desc(&sctlr_el1_desc); 1277 + check_reg_desc(&sctlr_el2_desc); 1328 1278 check_reg_desc(&mdcr_el2_desc); 1329 1279 check_reg_desc(&vtcr_el2_desc); 1330 1280 } ··· 1344 1292 } 1345 1293 } 1346 1294 1347 - static u64 __compute_fixed_bits(struct kvm *kvm, 1348 - const struct reg_bits_to_feat_map *map, 1349 - int map_size, 1350 - u64 *fixed_bits, 1351 - unsigned long require, 1352 - unsigned long exclude) 1295 + static struct resx compute_resx_bits(struct kvm *kvm, 1296 + const struct reg_bits_to_feat_map *map, 1297 + int map_size, 1298 + unsigned long require, 1299 + unsigned long exclude) 1353 1300 { 1354 - u64 val = 0; 1301 + bool e2h0 = kvm_has_feat(kvm, FEAT_E2H0); 1302 + struct resx resx = {}; 1355 1303 1356 1304 for (int i = 0; i < map_size; i++) { 1357 1305 bool match; ··· 1362 1310 if (map[i].flags & exclude) 1363 1311 continue; 1364 1312 1365 - if (map[i].flags & CALL_FUNC) 1366 - match = (map[i].flags & FIXED_VALUE) ? 1367 - map[i].fval(kvm, fixed_bits) : 1368 - map[i].match(kvm); 1313 + if (map[i].flags & FORCE_RESx) 1314 + match = false; 1315 + else if (map[i].flags & CALL_FUNC) 1316 + match = map[i].match(kvm); 1369 1317 else 1370 1318 match = idreg_feat_match(kvm, &map[i]); 1371 1319 1372 - if (!match || (map[i].flags & FIXED_VALUE)) 1373 - val |= reg_feat_map_bits(&map[i]); 1320 + if (map[i].flags & REQUIRES_E2H1) 1321 + match &= !e2h0; 1322 + 1323 + if (!match) { 1324 + u64 bits = reg_feat_map_bits(&map[i]); 1325 + 1326 + if ((map[i].flags & AS_RES1) || 1327 + (e2h0 && (map[i].flags & RES1_WHEN_E2H0)) || 1328 + (!e2h0 && (map[i].flags & RES1_WHEN_E2H1))) 1329 + resx.res1 |= bits; 1330 + else 1331 + resx.res0 |= bits; 1332 + } 1374 1333 } 1375 1334 1376 - return val; 1335 + return resx; 1377 1336 } 1378 1337 1379 - static u64 compute_res0_bits(struct kvm *kvm, 1380 - const struct reg_bits_to_feat_map *map, 1381 - int map_size, 1382 - unsigned long require, 1383 - unsigned long exclude) 1338 + static struct resx compute_reg_resx_bits(struct kvm *kvm, 1339 + const struct reg_feat_map_desc *r, 1340 + unsigned long require, 1341 + unsigned long exclude) 1384 1342 { 1385 - return __compute_fixed_bits(kvm, map, map_size, NULL, 1386 - require, exclude | FIXED_VALUE); 1387 - } 1343 + struct resx resx; 1388 1344 1389 - static u64 compute_reg_res0_bits(struct kvm *kvm, 1390 - const struct reg_feat_map_desc *r, 1391 - unsigned long require, unsigned long exclude) 1392 - 1393 - { 1394 - u64 res0; 1395 - 1396 - res0 = compute_res0_bits(kvm, r->bit_feat_map, r->bit_feat_map_sz, 1345 + resx = compute_resx_bits(kvm, r->bit_feat_map, r->bit_feat_map_sz, 1397 1346 require, exclude); 1398 1347 1399 - /* 1400 - * If computing FGUs, don't take RES0 or register existence 1401 - * into account -- we're not computing bits for the register 1402 - * itself. 1403 - */ 1404 - if (!(exclude & NEVER_FGU)) { 1405 - res0 |= compute_res0_bits(kvm, &r->feat_map, 1, require, exclude); 1406 - res0 |= ~reg_feat_map_bits(&r->feat_map); 1348 + if (r->feat_map.flags & MASKS_POINTER) { 1349 + resx.res0 |= r->feat_map.masks->res0; 1350 + resx.res1 |= r->feat_map.masks->res1; 1407 1351 } 1408 1352 1409 - return res0; 1353 + /* 1354 + * If the register itself was not valid, all the non-RESx bits are 1355 + * now considered RES0 (this matches the behaviour of registers such 1356 + * as SCTLR2 and TCR2). Weed out any potential (though unlikely) 1357 + * overlap with RES1 bits coming from the previous computation. 1358 + */ 1359 + resx.res0 |= compute_resx_bits(kvm, &r->feat_map, 1, require, exclude).res0; 1360 + resx.res1 &= ~resx.res0; 1361 + 1362 + return resx; 1410 1363 } 1411 1364 1412 - static u64 compute_reg_fixed_bits(struct kvm *kvm, 1413 - const struct reg_feat_map_desc *r, 1414 - u64 *fixed_bits, unsigned long require, 1415 - unsigned long exclude) 1365 + static u64 compute_fgu_bits(struct kvm *kvm, const struct reg_feat_map_desc *r) 1416 1366 { 1417 - return __compute_fixed_bits(kvm, r->bit_feat_map, r->bit_feat_map_sz, 1418 - fixed_bits, require | FIXED_VALUE, exclude); 1367 + struct resx resx; 1368 + 1369 + /* 1370 + * If computing FGUs, we collect the unsupported feature bits as 1371 + * RESx bits, but don't take the actual RESx bits or register 1372 + * existence into account -- we're not computing bits for the 1373 + * register itself. 1374 + */ 1375 + resx = compute_resx_bits(kvm, r->bit_feat_map, r->bit_feat_map_sz, 1376 + 0, NEVER_FGU); 1377 + 1378 + return resx.res0 | resx.res1; 1419 1379 } 1420 1380 1421 1381 void compute_fgu(struct kvm *kvm, enum fgt_group_id fgt) ··· 1436 1372 1437 1373 switch (fgt) { 1438 1374 case HFGRTR_GROUP: 1439 - val |= compute_reg_res0_bits(kvm, &hfgrtr_desc, 1440 - 0, NEVER_FGU); 1441 - val |= compute_reg_res0_bits(kvm, &hfgwtr_desc, 1442 - 0, NEVER_FGU); 1375 + val |= compute_fgu_bits(kvm, &hfgrtr_desc); 1376 + val |= compute_fgu_bits(kvm, &hfgwtr_desc); 1443 1377 break; 1444 1378 case HFGITR_GROUP: 1445 - val |= compute_reg_res0_bits(kvm, &hfgitr_desc, 1446 - 0, NEVER_FGU); 1379 + val |= compute_fgu_bits(kvm, &hfgitr_desc); 1447 1380 break; 1448 1381 case HDFGRTR_GROUP: 1449 - val |= compute_reg_res0_bits(kvm, &hdfgrtr_desc, 1450 - 0, NEVER_FGU); 1451 - val |= compute_reg_res0_bits(kvm, &hdfgwtr_desc, 1452 - 0, NEVER_FGU); 1382 + val |= compute_fgu_bits(kvm, &hdfgrtr_desc); 1383 + val |= compute_fgu_bits(kvm, &hdfgwtr_desc); 1453 1384 break; 1454 1385 case HAFGRTR_GROUP: 1455 - val |= compute_reg_res0_bits(kvm, &hafgrtr_desc, 1456 - 0, NEVER_FGU); 1386 + val |= compute_fgu_bits(kvm, &hafgrtr_desc); 1457 1387 break; 1458 1388 case HFGRTR2_GROUP: 1459 - val |= compute_reg_res0_bits(kvm, &hfgrtr2_desc, 1460 - 0, NEVER_FGU); 1461 - val |= compute_reg_res0_bits(kvm, &hfgwtr2_desc, 1462 - 0, NEVER_FGU); 1389 + val |= compute_fgu_bits(kvm, &hfgrtr2_desc); 1390 + val |= compute_fgu_bits(kvm, &hfgwtr2_desc); 1463 1391 break; 1464 1392 case HFGITR2_GROUP: 1465 - val |= compute_reg_res0_bits(kvm, &hfgitr2_desc, 1466 - 0, NEVER_FGU); 1393 + val |= compute_fgu_bits(kvm, &hfgitr2_desc); 1467 1394 break; 1468 1395 case HDFGRTR2_GROUP: 1469 - val |= compute_reg_res0_bits(kvm, &hdfgrtr2_desc, 1470 - 0, NEVER_FGU); 1471 - val |= compute_reg_res0_bits(kvm, &hdfgwtr2_desc, 1472 - 0, NEVER_FGU); 1396 + val |= compute_fgu_bits(kvm, &hdfgrtr2_desc); 1397 + val |= compute_fgu_bits(kvm, &hdfgwtr2_desc); 1473 1398 break; 1474 1399 default: 1475 1400 BUG(); ··· 1467 1414 kvm->arch.fgu[fgt] = val; 1468 1415 } 1469 1416 1470 - void get_reg_fixed_bits(struct kvm *kvm, enum vcpu_sysreg reg, u64 *res0, u64 *res1) 1417 + struct resx get_reg_fixed_bits(struct kvm *kvm, enum vcpu_sysreg reg) 1471 1418 { 1472 - u64 fixed = 0, mask; 1419 + struct resx resx; 1473 1420 1474 1421 switch (reg) { 1475 1422 case HFGRTR_EL2: 1476 - *res0 = compute_reg_res0_bits(kvm, &hfgrtr_desc, 0, 0); 1477 - *res1 = HFGRTR_EL2_RES1; 1423 + resx = compute_reg_resx_bits(kvm, &hfgrtr_desc, 0, 0); 1478 1424 break; 1479 1425 case HFGWTR_EL2: 1480 - *res0 = compute_reg_res0_bits(kvm, &hfgwtr_desc, 0, 0); 1481 - *res1 = HFGWTR_EL2_RES1; 1426 + resx = compute_reg_resx_bits(kvm, &hfgwtr_desc, 0, 0); 1482 1427 break; 1483 1428 case HFGITR_EL2: 1484 - *res0 = compute_reg_res0_bits(kvm, &hfgitr_desc, 0, 0); 1485 - *res1 = HFGITR_EL2_RES1; 1429 + resx = compute_reg_resx_bits(kvm, &hfgitr_desc, 0, 0); 1486 1430 break; 1487 1431 case HDFGRTR_EL2: 1488 - *res0 = compute_reg_res0_bits(kvm, &hdfgrtr_desc, 0, 0); 1489 - *res1 = HDFGRTR_EL2_RES1; 1432 + resx = compute_reg_resx_bits(kvm, &hdfgrtr_desc, 0, 0); 1490 1433 break; 1491 1434 case HDFGWTR_EL2: 1492 - *res0 = compute_reg_res0_bits(kvm, &hdfgwtr_desc, 0, 0); 1493 - *res1 = HDFGWTR_EL2_RES1; 1435 + resx = compute_reg_resx_bits(kvm, &hdfgwtr_desc, 0, 0); 1494 1436 break; 1495 1437 case HAFGRTR_EL2: 1496 - *res0 = compute_reg_res0_bits(kvm, &hafgrtr_desc, 0, 0); 1497 - *res1 = HAFGRTR_EL2_RES1; 1438 + resx = compute_reg_resx_bits(kvm, &hafgrtr_desc, 0, 0); 1498 1439 break; 1499 1440 case HFGRTR2_EL2: 1500 - *res0 = compute_reg_res0_bits(kvm, &hfgrtr2_desc, 0, 0); 1501 - *res1 = HFGRTR2_EL2_RES1; 1441 + resx = compute_reg_resx_bits(kvm, &hfgrtr2_desc, 0, 0); 1502 1442 break; 1503 1443 case HFGWTR2_EL2: 1504 - *res0 = compute_reg_res0_bits(kvm, &hfgwtr2_desc, 0, 0); 1505 - *res1 = HFGWTR2_EL2_RES1; 1444 + resx = compute_reg_resx_bits(kvm, &hfgwtr2_desc, 0, 0); 1506 1445 break; 1507 1446 case HFGITR2_EL2: 1508 - *res0 = compute_reg_res0_bits(kvm, &hfgitr2_desc, 0, 0); 1509 - *res1 = HFGITR2_EL2_RES1; 1447 + resx = compute_reg_resx_bits(kvm, &hfgitr2_desc, 0, 0); 1510 1448 break; 1511 1449 case HDFGRTR2_EL2: 1512 - *res0 = compute_reg_res0_bits(kvm, &hdfgrtr2_desc, 0, 0); 1513 - *res1 = HDFGRTR2_EL2_RES1; 1450 + resx = compute_reg_resx_bits(kvm, &hdfgrtr2_desc, 0, 0); 1514 1451 break; 1515 1452 case HDFGWTR2_EL2: 1516 - *res0 = compute_reg_res0_bits(kvm, &hdfgwtr2_desc, 0, 0); 1517 - *res1 = HDFGWTR2_EL2_RES1; 1453 + resx = compute_reg_resx_bits(kvm, &hdfgwtr2_desc, 0, 0); 1518 1454 break; 1519 1455 case HCRX_EL2: 1520 - *res0 = compute_reg_res0_bits(kvm, &hcrx_desc, 0, 0); 1521 - *res1 = __HCRX_EL2_RES1; 1456 + resx = compute_reg_resx_bits(kvm, &hcrx_desc, 0, 0); 1457 + resx.res1 |= __HCRX_EL2_RES1; 1522 1458 break; 1523 1459 case HCR_EL2: 1524 - mask = compute_reg_fixed_bits(kvm, &hcr_desc, &fixed, 0, 0); 1525 - *res0 = compute_reg_res0_bits(kvm, &hcr_desc, 0, 0); 1526 - *res0 |= (mask & ~fixed); 1527 - *res1 = HCR_EL2_RES1 | (mask & fixed); 1460 + resx = compute_reg_resx_bits(kvm, &hcr_desc, 0, 0); 1528 1461 break; 1529 1462 case SCTLR2_EL1: 1530 1463 case SCTLR2_EL2: 1531 - *res0 = compute_reg_res0_bits(kvm, &sctlr2_desc, 0, 0); 1532 - *res1 = SCTLR2_EL1_RES1; 1464 + resx = compute_reg_resx_bits(kvm, &sctlr2_desc, 0, 0); 1533 1465 break; 1534 1466 case TCR2_EL2: 1535 - *res0 = compute_reg_res0_bits(kvm, &tcr2_el2_desc, 0, 0); 1536 - *res1 = TCR2_EL2_RES1; 1467 + resx = compute_reg_resx_bits(kvm, &tcr2_el2_desc, 0, 0); 1537 1468 break; 1538 1469 case SCTLR_EL1: 1539 - *res0 = compute_reg_res0_bits(kvm, &sctlr_el1_desc, 0, 0); 1540 - *res1 = SCTLR_EL1_RES1; 1470 + resx = compute_reg_resx_bits(kvm, &sctlr_el1_desc, 0, 0); 1471 + break; 1472 + case SCTLR_EL2: 1473 + resx = compute_reg_resx_bits(kvm, &sctlr_el2_desc, 0, 0); 1541 1474 break; 1542 1475 case MDCR_EL2: 1543 - *res0 = compute_reg_res0_bits(kvm, &mdcr_el2_desc, 0, 0); 1544 - *res1 = MDCR_EL2_RES1; 1476 + resx = compute_reg_resx_bits(kvm, &mdcr_el2_desc, 0, 0); 1545 1477 break; 1546 1478 case VTCR_EL2: 1547 - *res0 = compute_reg_res0_bits(kvm, &vtcr_el2_desc, 0, 0); 1548 - *res1 = VTCR_EL2_RES1; 1479 + resx = compute_reg_resx_bits(kvm, &vtcr_el2_desc, 0, 0); 1549 1480 break; 1550 1481 default: 1551 1482 WARN_ON_ONCE(1); 1552 - *res0 = *res1 = 0; 1483 + resx = (typeof(resx)){}; 1553 1484 break; 1554 1485 } 1486 + 1487 + return resx; 1555 1488 } 1556 1489 1557 1490 static __always_inline struct fgt_masks *__fgt_reg_to_masks(enum vcpu_sysreg reg)
+1 -9
arch/arm64/kvm/emulate-nested.c
··· 2435 2435 2436 2436 static u64 kvm_get_sysreg_res0(struct kvm *kvm, enum vcpu_sysreg sr) 2437 2437 { 2438 - struct kvm_sysreg_masks *masks; 2439 - 2440 - /* Only handle the VNCR-backed regs for now */ 2441 - if (sr < __VNCR_START__) 2442 - return 0; 2443 - 2444 - masks = kvm->arch.sysreg_masks; 2445 - 2446 - return masks->mask[sr - __SANITISED_REG_START__].res0; 2438 + return kvm_get_sysreg_resx(kvm, sr).res0; 2447 2439 } 2448 2440 2449 2441 static bool check_fgt_bit(struct kvm_vcpu *vcpu, enum vcpu_sysreg sr,
+72 -79
arch/arm64/kvm/nested.c
··· 1505 1505 u64 orig_val = val; 1506 1506 1507 1507 switch (reg) { 1508 - case SYS_ID_AA64ISAR0_EL1: 1509 - /* Support everything but TME */ 1510 - val &= ~ID_AA64ISAR0_EL1_TME; 1511 - break; 1512 - 1513 1508 case SYS_ID_AA64ISAR1_EL1: 1514 1509 /* Support everything but LS64 and Spec Invalidation */ 1515 1510 val &= ~(ID_AA64ISAR1_EL1_LS64 | ··· 1664 1669 u64 kvm_vcpu_apply_reg_masks(const struct kvm_vcpu *vcpu, 1665 1670 enum vcpu_sysreg sr, u64 v) 1666 1671 { 1667 - struct kvm_sysreg_masks *masks; 1672 + struct resx resx; 1668 1673 1669 - masks = vcpu->kvm->arch.sysreg_masks; 1670 - 1671 - if (masks) { 1672 - sr -= __SANITISED_REG_START__; 1673 - 1674 - v &= ~masks->mask[sr].res0; 1675 - v |= masks->mask[sr].res1; 1676 - } 1674 + resx = kvm_get_sysreg_resx(vcpu->kvm, sr); 1675 + v &= ~resx.res0; 1676 + v |= resx.res1; 1677 1677 1678 1678 return v; 1679 1679 } 1680 1680 1681 - static __always_inline void set_sysreg_masks(struct kvm *kvm, int sr, u64 res0, u64 res1) 1681 + static __always_inline void set_sysreg_masks(struct kvm *kvm, int sr, struct resx resx) 1682 1682 { 1683 - int i = sr - __SANITISED_REG_START__; 1684 - 1685 1683 BUILD_BUG_ON(!__builtin_constant_p(sr)); 1686 1684 BUILD_BUG_ON(sr < __SANITISED_REG_START__); 1687 1685 BUILD_BUG_ON(sr >= NR_SYS_REGS); 1688 1686 1689 - kvm->arch.sysreg_masks->mask[i].res0 = res0; 1690 - kvm->arch.sysreg_masks->mask[i].res1 = res1; 1687 + kvm_set_sysreg_resx(kvm, sr, resx); 1691 1688 } 1692 1689 1693 1690 int kvm_init_nv_sysregs(struct kvm_vcpu *vcpu) 1694 1691 { 1695 1692 struct kvm *kvm = vcpu->kvm; 1696 - u64 res0, res1; 1693 + struct resx resx; 1697 1694 1698 1695 lockdep_assert_held(&kvm->arch.config_lock); 1699 1696 ··· 1698 1711 return -ENOMEM; 1699 1712 1700 1713 /* VTTBR_EL2 */ 1701 - res0 = res1 = 0; 1714 + resx = (typeof(resx)){}; 1702 1715 if (!kvm_has_feat_enum(kvm, ID_AA64MMFR1_EL1, VMIDBits, 16)) 1703 - res0 |= GENMASK(63, 56); 1716 + resx.res0 |= GENMASK(63, 56); 1704 1717 if (!kvm_has_feat(kvm, ID_AA64MMFR2_EL1, CnP, IMP)) 1705 - res0 |= VTTBR_CNP_BIT; 1706 - set_sysreg_masks(kvm, VTTBR_EL2, res0, res1); 1718 + resx.res0 |= VTTBR_CNP_BIT; 1719 + set_sysreg_masks(kvm, VTTBR_EL2, resx); 1707 1720 1708 1721 /* VTCR_EL2 */ 1709 - get_reg_fixed_bits(kvm, VTCR_EL2, &res0, &res1); 1710 - set_sysreg_masks(kvm, VTCR_EL2, res0, res1); 1722 + resx = get_reg_fixed_bits(kvm, VTCR_EL2); 1723 + set_sysreg_masks(kvm, VTCR_EL2, resx); 1711 1724 1712 1725 /* VMPIDR_EL2 */ 1713 - res0 = GENMASK(63, 40) | GENMASK(30, 24); 1714 - res1 = BIT(31); 1715 - set_sysreg_masks(kvm, VMPIDR_EL2, res0, res1); 1726 + resx.res0 = GENMASK(63, 40) | GENMASK(30, 24); 1727 + resx.res1 = BIT(31); 1728 + set_sysreg_masks(kvm, VMPIDR_EL2, resx); 1716 1729 1717 1730 /* HCR_EL2 */ 1718 - get_reg_fixed_bits(kvm, HCR_EL2, &res0, &res1); 1719 - set_sysreg_masks(kvm, HCR_EL2, res0, res1); 1731 + resx = get_reg_fixed_bits(kvm, HCR_EL2); 1732 + set_sysreg_masks(kvm, HCR_EL2, resx); 1720 1733 1721 1734 /* HCRX_EL2 */ 1722 - get_reg_fixed_bits(kvm, HCRX_EL2, &res0, &res1); 1723 - set_sysreg_masks(kvm, HCRX_EL2, res0, res1); 1735 + resx = get_reg_fixed_bits(kvm, HCRX_EL2); 1736 + set_sysreg_masks(kvm, HCRX_EL2, resx); 1724 1737 1725 1738 /* HFG[RW]TR_EL2 */ 1726 - get_reg_fixed_bits(kvm, HFGRTR_EL2, &res0, &res1); 1727 - set_sysreg_masks(kvm, HFGRTR_EL2, res0, res1); 1728 - get_reg_fixed_bits(kvm, HFGWTR_EL2, &res0, &res1); 1729 - set_sysreg_masks(kvm, HFGWTR_EL2, res0, res1); 1739 + resx = get_reg_fixed_bits(kvm, HFGRTR_EL2); 1740 + set_sysreg_masks(kvm, HFGRTR_EL2, resx); 1741 + resx = get_reg_fixed_bits(kvm, HFGWTR_EL2); 1742 + set_sysreg_masks(kvm, HFGWTR_EL2, resx); 1730 1743 1731 1744 /* HDFG[RW]TR_EL2 */ 1732 - get_reg_fixed_bits(kvm, HDFGRTR_EL2, &res0, &res1); 1733 - set_sysreg_masks(kvm, HDFGRTR_EL2, res0, res1); 1734 - get_reg_fixed_bits(kvm, HDFGWTR_EL2, &res0, &res1); 1735 - set_sysreg_masks(kvm, HDFGWTR_EL2, res0, res1); 1745 + resx = get_reg_fixed_bits(kvm, HDFGRTR_EL2); 1746 + set_sysreg_masks(kvm, HDFGRTR_EL2, resx); 1747 + resx = get_reg_fixed_bits(kvm, HDFGWTR_EL2); 1748 + set_sysreg_masks(kvm, HDFGWTR_EL2, resx); 1736 1749 1737 1750 /* HFGITR_EL2 */ 1738 - get_reg_fixed_bits(kvm, HFGITR_EL2, &res0, &res1); 1739 - set_sysreg_masks(kvm, HFGITR_EL2, res0, res1); 1751 + resx = get_reg_fixed_bits(kvm, HFGITR_EL2); 1752 + set_sysreg_masks(kvm, HFGITR_EL2, resx); 1740 1753 1741 1754 /* HAFGRTR_EL2 - not a lot to see here */ 1742 - get_reg_fixed_bits(kvm, HAFGRTR_EL2, &res0, &res1); 1743 - set_sysreg_masks(kvm, HAFGRTR_EL2, res0, res1); 1755 + resx = get_reg_fixed_bits(kvm, HAFGRTR_EL2); 1756 + set_sysreg_masks(kvm, HAFGRTR_EL2, resx); 1744 1757 1745 1758 /* HFG[RW]TR2_EL2 */ 1746 - get_reg_fixed_bits(kvm, HFGRTR2_EL2, &res0, &res1); 1747 - set_sysreg_masks(kvm, HFGRTR2_EL2, res0, res1); 1748 - get_reg_fixed_bits(kvm, HFGWTR2_EL2, &res0, &res1); 1749 - set_sysreg_masks(kvm, HFGWTR2_EL2, res0, res1); 1759 + resx = get_reg_fixed_bits(kvm, HFGRTR2_EL2); 1760 + set_sysreg_masks(kvm, HFGRTR2_EL2, resx); 1761 + resx = get_reg_fixed_bits(kvm, HFGWTR2_EL2); 1762 + set_sysreg_masks(kvm, HFGWTR2_EL2, resx); 1750 1763 1751 1764 /* HDFG[RW]TR2_EL2 */ 1752 - get_reg_fixed_bits(kvm, HDFGRTR2_EL2, &res0, &res1); 1753 - set_sysreg_masks(kvm, HDFGRTR2_EL2, res0, res1); 1754 - get_reg_fixed_bits(kvm, HDFGWTR2_EL2, &res0, &res1); 1755 - set_sysreg_masks(kvm, HDFGWTR2_EL2, res0, res1); 1765 + resx = get_reg_fixed_bits(kvm, HDFGRTR2_EL2); 1766 + set_sysreg_masks(kvm, HDFGRTR2_EL2, resx); 1767 + resx = get_reg_fixed_bits(kvm, HDFGWTR2_EL2); 1768 + set_sysreg_masks(kvm, HDFGWTR2_EL2, resx); 1756 1769 1757 1770 /* HFGITR2_EL2 */ 1758 - get_reg_fixed_bits(kvm, HFGITR2_EL2, &res0, &res1); 1759 - set_sysreg_masks(kvm, HFGITR2_EL2, res0, res1); 1771 + resx = get_reg_fixed_bits(kvm, HFGITR2_EL2); 1772 + set_sysreg_masks(kvm, HFGITR2_EL2, resx); 1760 1773 1761 1774 /* TCR2_EL2 */ 1762 - get_reg_fixed_bits(kvm, TCR2_EL2, &res0, &res1); 1763 - set_sysreg_masks(kvm, TCR2_EL2, res0, res1); 1775 + resx = get_reg_fixed_bits(kvm, TCR2_EL2); 1776 + set_sysreg_masks(kvm, TCR2_EL2, resx); 1764 1777 1765 1778 /* SCTLR_EL1 */ 1766 - get_reg_fixed_bits(kvm, SCTLR_EL1, &res0, &res1); 1767 - set_sysreg_masks(kvm, SCTLR_EL1, res0, res1); 1779 + resx = get_reg_fixed_bits(kvm, SCTLR_EL1); 1780 + set_sysreg_masks(kvm, SCTLR_EL1, resx); 1781 + 1782 + /* SCTLR_EL2 */ 1783 + resx = get_reg_fixed_bits(kvm, SCTLR_EL2); 1784 + set_sysreg_masks(kvm, SCTLR_EL2, resx); 1768 1785 1769 1786 /* SCTLR2_ELx */ 1770 - get_reg_fixed_bits(kvm, SCTLR2_EL1, &res0, &res1); 1771 - set_sysreg_masks(kvm, SCTLR2_EL1, res0, res1); 1772 - get_reg_fixed_bits(kvm, SCTLR2_EL2, &res0, &res1); 1773 - set_sysreg_masks(kvm, SCTLR2_EL2, res0, res1); 1787 + resx = get_reg_fixed_bits(kvm, SCTLR2_EL1); 1788 + set_sysreg_masks(kvm, SCTLR2_EL1, resx); 1789 + resx = get_reg_fixed_bits(kvm, SCTLR2_EL2); 1790 + set_sysreg_masks(kvm, SCTLR2_EL2, resx); 1774 1791 1775 1792 /* MDCR_EL2 */ 1776 - get_reg_fixed_bits(kvm, MDCR_EL2, &res0, &res1); 1777 - set_sysreg_masks(kvm, MDCR_EL2, res0, res1); 1793 + resx = get_reg_fixed_bits(kvm, MDCR_EL2); 1794 + set_sysreg_masks(kvm, MDCR_EL2, resx); 1778 1795 1779 1796 /* CNTHCTL_EL2 */ 1780 - res0 = GENMASK(63, 20); 1781 - res1 = 0; 1797 + resx.res0 = GENMASK(63, 20); 1798 + resx.res1 = 0; 1782 1799 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, RME, IMP)) 1783 - res0 |= CNTHCTL_CNTPMASK | CNTHCTL_CNTVMASK; 1800 + resx.res0 |= CNTHCTL_CNTPMASK | CNTHCTL_CNTVMASK; 1784 1801 if (!kvm_has_feat(kvm, ID_AA64MMFR0_EL1, ECV, CNTPOFF)) { 1785 - res0 |= CNTHCTL_ECV; 1802 + resx.res0 |= CNTHCTL_ECV; 1786 1803 if (!kvm_has_feat(kvm, ID_AA64MMFR0_EL1, ECV, IMP)) 1787 - res0 |= (CNTHCTL_EL1TVT | CNTHCTL_EL1TVCT | 1788 - CNTHCTL_EL1NVPCT | CNTHCTL_EL1NVVCT); 1804 + resx.res0 |= (CNTHCTL_EL1TVT | CNTHCTL_EL1TVCT | 1805 + CNTHCTL_EL1NVPCT | CNTHCTL_EL1NVVCT); 1789 1806 } 1790 1807 if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, VH, IMP)) 1791 - res0 |= GENMASK(11, 8); 1792 - set_sysreg_masks(kvm, CNTHCTL_EL2, res0, res1); 1808 + resx.res0 |= GENMASK(11, 8); 1809 + set_sysreg_masks(kvm, CNTHCTL_EL2, resx); 1793 1810 1794 1811 /* ICH_HCR_EL2 */ 1795 - res0 = ICH_HCR_EL2_RES0; 1796 - res1 = ICH_HCR_EL2_RES1; 1812 + resx.res0 = ICH_HCR_EL2_RES0; 1813 + resx.res1 = ICH_HCR_EL2_RES1; 1797 1814 if (!(kvm_vgic_global_state.ich_vtr_el2 & ICH_VTR_EL2_TDS)) 1798 - res0 |= ICH_HCR_EL2_TDIR; 1815 + resx.res0 |= ICH_HCR_EL2_TDIR; 1799 1816 /* No GICv4 is presented to the guest */ 1800 - res0 |= ICH_HCR_EL2_DVIM | ICH_HCR_EL2_vSGIEOICount; 1801 - set_sysreg_masks(kvm, ICH_HCR_EL2, res0, res1); 1817 + resx.res0 |= ICH_HCR_EL2_DVIM | ICH_HCR_EL2_vSGIEOICount; 1818 + set_sysreg_masks(kvm, ICH_HCR_EL2, resx); 1802 1819 1803 1820 /* VNCR_EL2 */ 1804 - set_sysreg_masks(kvm, VNCR_EL2, VNCR_EL2_RES0, VNCR_EL2_RES1); 1821 + resx.res0 = VNCR_EL2_RES0; 1822 + resx.res1 = VNCR_EL2_RES1; 1823 + set_sysreg_masks(kvm, VNCR_EL2, resx); 1805 1824 1806 1825 out: 1807 1826 for (enum vcpu_sysreg sr = __SANITISED_REG_START__; sr < NR_SYS_REGS; sr++)
+68
arch/arm64/kvm/sys_regs.c
··· 5056 5056 5057 5057 DEFINE_SEQ_ATTRIBUTE(idregs_debug); 5058 5058 5059 + static const struct sys_reg_desc *sr_resx_find(struct kvm *kvm, loff_t pos) 5060 + { 5061 + unsigned long i, sr_idx = 0; 5062 + 5063 + for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { 5064 + const struct sys_reg_desc *r = &sys_reg_descs[i]; 5065 + 5066 + if (r->reg < __SANITISED_REG_START__) 5067 + continue; 5068 + 5069 + if (sr_idx++ == pos) 5070 + return r; 5071 + } 5072 + 5073 + return NULL; 5074 + } 5075 + 5076 + static void *sr_resx_start(struct seq_file *s, loff_t *pos) 5077 + { 5078 + struct kvm *kvm = s->private; 5079 + 5080 + if (!kvm->arch.sysreg_masks) 5081 + return NULL; 5082 + 5083 + return (void *)sr_resx_find(kvm, *pos); 5084 + } 5085 + 5086 + static void *sr_resx_next(struct seq_file *s, void *v, loff_t *pos) 5087 + { 5088 + struct kvm *kvm = s->private; 5089 + 5090 + (*pos)++; 5091 + 5092 + return (void *)sr_resx_find(kvm, *pos); 5093 + } 5094 + 5095 + static void sr_resx_stop(struct seq_file *s, void *v) 5096 + { 5097 + } 5098 + 5099 + static int sr_resx_show(struct seq_file *s, void *v) 5100 + { 5101 + const struct sys_reg_desc *desc = v; 5102 + struct kvm *kvm = s->private; 5103 + struct resx resx; 5104 + 5105 + if (!desc) 5106 + return 0; 5107 + 5108 + resx = kvm_get_sysreg_resx(kvm, desc->reg); 5109 + 5110 + seq_printf(s, "%20s:\tRES0:%016llx\tRES1:%016llx\n", 5111 + desc->name, resx.res0, resx.res1); 5112 + 5113 + return 0; 5114 + } 5115 + 5116 + static const struct seq_operations sr_resx_sops = { 5117 + .start = sr_resx_start, 5118 + .next = sr_resx_next, 5119 + .stop = sr_resx_stop, 5120 + .show = sr_resx_show, 5121 + }; 5122 + 5123 + DEFINE_SEQ_ATTRIBUTE(sr_resx); 5124 + 5059 5125 void kvm_sys_regs_create_debugfs(struct kvm *kvm) 5060 5126 { 5061 5127 debugfs_create_file("idregs", 0444, kvm->debugfs_dentry, kvm, 5062 5128 &idregs_debug_fops); 5129 + debugfs_create_file("resx", 0444, kvm->debugfs_dentry, kvm, 5130 + &sr_resx_fops); 5063 5131 } 5064 5132 5065 5133 static void reset_vm_ftr_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *reg)
+72 -10
arch/arm64/tools/sysreg
··· 1856 1856 0b0000 NI 1857 1857 0b0001 IMP 1858 1858 EndEnum 1859 - UnsignedEnum 27:24 TME 1860 - 0b0000 NI 1861 - 0b0001 IMP 1862 - EndEnum 1859 + Res0 27:24 1863 1860 UnsignedEnum 23:20 ATOMIC 1864 1861 0b0000 NI 1865 1862 0b0010 IMP ··· 2430 2433 Field 56 EnALS 2431 2434 Field 55 EnAS0 2432 2435 Field 54 EnASR 2433 - Field 53 TME 2434 - Field 52 TME0 2435 - Field 51 TMT 2436 - Field 50 TMT0 2436 + Res0 53:50 2437 2437 Field 49:46 TWEDEL 2438 2438 Field 45 TWEDEn 2439 2439 Field 44 DSSBS ··· 3744 3750 EndEnum 3745 3751 EndSysreg 3746 3752 3753 + Sysreg SCTLR_EL2 3 4 1 0 0 3754 + Field 63 TIDCP 3755 + Field 62 SPINTMASK 3756 + Field 61 NMI 3757 + Field 60 EnTP2 3758 + Field 59 TCSO 3759 + Field 58 TCSO0 3760 + Field 57 EPAN 3761 + Field 56 EnALS 3762 + Field 55 EnAS0 3763 + Field 54 EnASR 3764 + Res0 53:50 3765 + Field 49:46 TWEDEL 3766 + Field 45 TWEDEn 3767 + Field 44 DSSBS 3768 + Field 43 ATA 3769 + Field 42 ATA0 3770 + Enum 41:40 TCF 3771 + 0b00 NONE 3772 + 0b01 SYNC 3773 + 0b10 ASYNC 3774 + 0b11 ASYMM 3775 + EndEnum 3776 + Enum 39:38 TCF0 3777 + 0b00 NONE 3778 + 0b01 SYNC 3779 + 0b10 ASYNC 3780 + 0b11 ASYMM 3781 + EndEnum 3782 + Field 37 ITFSB 3783 + Field 36 BT 3784 + Field 35 BT0 3785 + Field 34 EnFPM 3786 + Field 33 MSCEn 3787 + Field 32 CMOW 3788 + Field 31 EnIA 3789 + Field 30 EnIB 3790 + Field 29 LSMAOE 3791 + Field 28 nTLSMD 3792 + Field 27 EnDA 3793 + Field 26 UCI 3794 + Field 25 EE 3795 + Field 24 E0E 3796 + Field 23 SPAN 3797 + Field 22 EIS 3798 + Field 21 IESB 3799 + Field 20 TSCXT 3800 + Field 19 WXN 3801 + Field 18 nTWE 3802 + Res0 17 3803 + Field 16 nTWI 3804 + Field 15 UCT 3805 + Field 14 DZE 3806 + Field 13 EnDB 3807 + Field 12 I 3808 + Field 11 EOS 3809 + Field 10 EnRCTX 3810 + Res0 9 3811 + Field 8 SED 3812 + Field 7 ITD 3813 + Field 6 nAA 3814 + Field 5 CP15BEN 3815 + Field 4 SA0 3816 + Field 3 SA 3817 + Field 2 C 3818 + Field 1 A 3819 + Field 0 M 3820 + EndSysreg 3821 + 3747 3822 Sysreg HCR_EL2 3 4 1 1 0 3748 3823 Field 63:60 TWEDEL 3749 3824 Field 59 TWEDEn ··· 3835 3772 Field 42 NV 3836 3773 Field 41 API 3837 3774 Field 40 APK 3838 - Field 39 TME 3839 - Field 38 MIOCNCE 3775 + Res0 39:38 3840 3776 Field 37 TEA 3841 3777 Field 36 TERR 3842 3778 Field 35 TLOR
-6
tools/arch/arm64/include/asm/sysreg.h
··· 847 847 #define SCTLR_ELx_A (BIT(1)) 848 848 #define SCTLR_ELx_M (BIT(0)) 849 849 850 - /* SCTLR_EL2 specific flags. */ 851 - #define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \ 852 - (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \ 853 - (BIT(29))) 854 - 855 - #define SCTLR_EL2_BT (BIT(36)) 856 850 #ifdef CONFIG_CPU_BIG_ENDIAN 857 851 #define ENDIAN_SET_EL2 SCTLR_ELx_EE 858 852 #else
-1
tools/perf/Documentation/perf-arm-spe.txt
··· 176 176 bit 10 - Remote access (FEAT_SPEv1p4) 177 177 bit 11 - Misaligned access (FEAT_SPEv1p1) 178 178 bit 12-15 - IMPLEMENTATION DEFINED events (when implemented) 179 - bit 16 - Transaction (FEAT_TME) 180 179 bit 17 - Partial or empty SME or SVE predicate (FEAT_SPEv1p1) 181 180 bit 18 - Empty SME or SVE predicate (FEAT_SPEv1p1) 182 181 bit 19 - L2D access (FEAT_SPEv1p4)
-1
tools/testing/selftests/kvm/arm64/set_id_regs.c
··· 91 91 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SM3, 0), 92 92 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA3, 0), 93 93 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, RDM, 0), 94 - REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TME, 0), 95 94 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, ATOMIC, 0), 96 95 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, CRC32, 0), 97 96 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA2, 0),