tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/stm: ltdc: unify log system

DRM_ERROR and similar are deprecated. Use drm_dev based logging.

Link: https://lore.kernel.org/r/20250821130356.883553-1-raphael.gallais-pou@foss.st.com
Acked-by: Yannick Fertre <yannick.fertre@foss.st.com>
Link: https://lore.kernel.org/r/20250825132951.547899-1-raphael.gallais-pou@foss.st.com
Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>

Raphael Gallais-Pou 1e00a12d f315e030

+70 -69
+70 -69
drivers/gpu/drm/stm/ltdc.c
··· 641 641 break; 642 642 default: 643 643 /* RGB or not a YCbCr supported format */ 644 - DRM_ERROR("Unsupported pixel format: %u\n", drm_pix_fmt); 644 + drm_err(plane->dev, "Unsupported pixel format: %u\n", drm_pix_fmt); 645 645 return; 646 646 } 647 647 ··· 664 664 u32 lofs = plane->index * LAY_OFS; 665 665 666 666 if (enc != DRM_COLOR_YCBCR_BT601 && enc != DRM_COLOR_YCBCR_BT709) { 667 - DRM_ERROR("color encoding %d not supported, use bt601 by default\n", enc); 667 + drm_err(plane->dev, "color encoding %d not supported, use bt601 by default\n", enc); 668 668 /* set by default color encoding to DRM_COLOR_YCBCR_BT601 */ 669 669 enc = DRM_COLOR_YCBCR_BT601; 670 670 } 671 671 672 672 if (ran != DRM_COLOR_YCBCR_LIMITED_RANGE && ran != DRM_COLOR_YCBCR_FULL_RANGE) { 673 - DRM_ERROR("color range %d not supported, use limited range by default\n", ran); 673 + drm_err(plane->dev, 674 + "color range %d not supported, use limited range by default\n", ran); 674 675 /* set by default color range to DRM_COLOR_YCBCR_LIMITED_RANGE */ 675 676 ran = DRM_COLOR_YCBCR_LIMITED_RANGE; 676 677 } 677 678 678 - DRM_DEBUG_DRIVER("Color encoding=%d, range=%d\n", enc, ran); 679 + drm_err(plane->dev, "Color encoding=%d, range=%d\n", enc, ran); 679 680 regmap_write(ldev->regmap, LTDC_L1CYR0R + lofs, 680 681 ltdc_ycbcr2rgb_coeffs[enc][ran][0]); 681 682 regmap_write(ldev->regmap, LTDC_L1CYR1R + lofs, ··· 775 774 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 776 775 struct drm_device *ddev = crtc->dev; 777 776 778 - DRM_DEBUG_DRIVER("\n"); 777 + drm_dbg_driver(crtc->dev, "\n"); 779 778 780 779 pm_runtime_get_sync(ddev->dev); 781 780 ··· 799 798 struct drm_device *ddev = crtc->dev; 800 799 int layer_index = 0; 801 800 802 - DRM_DEBUG_DRIVER("\n"); 801 + drm_dbg_driver(crtc->dev, "\n"); 803 802 804 803 drm_crtc_vblank_off(crtc); 805 804 ··· 838 837 839 838 result = clk_round_rate(ldev->pixel_clk, target); 840 839 841 - DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result); 840 + drm_dbg_driver(crtc->dev, "clk rate target %d, available %d\n", target, result); 842 841 843 842 /* Filter modes according to the max frequency supported by the pads */ 844 843 if (result > ldev->caps.pad_max_freq_hz) ··· 873 872 int rate = mode->clock * 1000; 874 873 875 874 if (clk_set_rate(ldev->pixel_clk, rate) < 0) { 876 - DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate); 875 + drm_err(crtc->dev, "Cannot set rate (%dHz) for pixel clk\n", rate); 877 876 return false; 878 877 } 879 878 880 879 adjusted_mode->clock = clk_get_rate(ldev->pixel_clk) / 1000; 881 880 882 - DRM_DEBUG_DRIVER("requested clock %dkHz, adjusted clock %dkHz\n", 883 - mode->clock, adjusted_mode->clock); 881 + drm_dbg_driver(crtc->dev, "requested clock %dkHz, adjusted clock %dkHz\n", 882 + mode->clock, adjusted_mode->clock); 884 883 885 884 return true; 886 885 } ··· 935 934 if (!pm_runtime_active(ddev->dev)) { 936 935 ret = pm_runtime_get_sync(ddev->dev); 937 936 if (ret) { 938 - DRM_ERROR("Failed to set mode, cannot get sync\n"); 937 + drm_err(crtc->dev, "Failed to set mode, cannot get sync\n"); 939 938 return; 940 939 } 941 940 } 942 941 943 - DRM_DEBUG_DRIVER("CRTC:%d mode:%s\n", crtc->base.id, mode->name); 944 - DRM_DEBUG_DRIVER("Video mode: %dx%d", mode->hdisplay, mode->vdisplay); 945 - DRM_DEBUG_DRIVER(" hfp %d hbp %d hsl %d vfp %d vbp %d vsl %d\n", 946 - mode->hsync_start - mode->hdisplay, 947 - mode->htotal - mode->hsync_end, 948 - mode->hsync_end - mode->hsync_start, 949 - mode->vsync_start - mode->vdisplay, 950 - mode->vtotal - mode->vsync_end, 951 - mode->vsync_end - mode->vsync_start); 942 + drm_dbg_driver(crtc->dev, "CRTC:%d mode:%s\n", crtc->base.id, mode->name); 943 + drm_dbg_driver(crtc->dev, "Video mode: %dx%d", mode->hdisplay, mode->vdisplay); 944 + drm_dbg_driver(crtc->dev, " hfp %d hbp %d hsl %d vfp %d vbp %d vsl %d\n", 945 + mode->hsync_start - mode->hdisplay, 946 + mode->htotal - mode->hsync_end, 947 + mode->hsync_end - mode->hsync_start, 948 + mode->vsync_start - mode->vdisplay, 949 + mode->vtotal - mode->vsync_end, 950 + mode->vsync_end - mode->vsync_start); 952 951 953 952 /* Convert video timings to ltdc timings */ 954 953 hsync = mode->hsync_end - mode->hsync_start - 1; ··· 1034 1033 struct drm_device *ddev = crtc->dev; 1035 1034 struct drm_pending_vblank_event *event = crtc->state->event; 1036 1035 1037 - DRM_DEBUG_ATOMIC("\n"); 1036 + drm_dbg_atomic(crtc->dev, "\n"); 1038 1037 1039 1038 ltdc_crtc_update_clut(crtc); 1040 1039 ··· 1122 1121 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 1123 1122 struct drm_crtc_state *state = crtc->state; 1124 1123 1125 - DRM_DEBUG_DRIVER("\n"); 1124 + drm_dbg_driver(crtc->dev, "\n"); 1126 1125 1127 1126 if (state->enable) 1128 1127 regmap_set_bits(ldev->regmap, LTDC_IER, IER_LIE); ··· 1136 1135 { 1137 1136 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 1138 1137 1139 - DRM_DEBUG_DRIVER("\n"); 1138 + drm_dbg_driver(crtc->dev, "\n"); 1140 1139 regmap_clear_bits(ldev->regmap, LTDC_IER, IER_LIE); 1141 1140 } 1142 1141 ··· 1145 1144 struct ltdc_device *ldev; 1146 1145 int ret; 1147 1146 1148 - DRM_DEBUG_DRIVER("\n"); 1149 - 1150 1147 if (!crtc) 1151 1148 return -ENODEV; 1149 + 1150 + drm_dbg_driver(crtc->dev, "\n"); 1152 1151 1153 1152 ldev = crtc_to_ltdc(crtc); 1154 1153 ··· 1169 1168 static int ltdc_crtc_verify_crc_source(struct drm_crtc *crtc, 1170 1169 const char *source, size_t *values_cnt) 1171 1170 { 1172 - DRM_DEBUG_DRIVER("\n"); 1173 - 1174 1171 if (!crtc) 1175 1172 return -ENODEV; 1176 1173 1174 + drm_dbg_driver(crtc->dev, "\n"); 1175 + 1177 1176 if (source && strcmp(source, "auto") != 0) { 1178 - DRM_DEBUG_DRIVER("Unknown CRC source %s for %s\n", 1179 - source, crtc->name); 1177 + drm_dbg_driver(crtc->dev, "Unknown CRC source %s for %s\n", 1178 + source, crtc->name); 1180 1179 return -EINVAL; 1181 1180 } 1182 1181 ··· 1234 1233 struct drm_framebuffer *fb = new_plane_state->fb; 1235 1234 u32 src_w, src_h; 1236 1235 1237 - DRM_DEBUG_DRIVER("\n"); 1236 + drm_dbg_driver(plane->dev, "\n"); 1238 1237 1239 1238 if (!fb) 1240 1239 return 0; ··· 1245 1244 1246 1245 /* Reject scaling */ 1247 1246 if (src_w != new_plane_state->crtc_w || src_h != new_plane_state->crtc_h) { 1248 - DRM_DEBUG_DRIVER("Scaling is not supported"); 1247 + drm_dbg_driver(plane->dev, "Scaling is not supported"); 1249 1248 1250 1249 return -EINVAL; 1251 1250 } ··· 1271 1270 enum ltdc_pix_fmt pf; 1272 1271 1273 1272 if (!newstate->crtc || !fb) { 1274 - DRM_DEBUG_DRIVER("fb or crtc NULL"); 1273 + drm_dbg_driver(plane->dev, "fb or crtc NULL"); 1275 1274 return; 1276 1275 } 1277 1276 ··· 1281 1280 src_w = newstate->src_w >> 16; 1282 1281 src_h = newstate->src_h >> 16; 1283 1282 1284 - DRM_DEBUG_DRIVER("plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n", 1285 - plane->base.id, fb->base.id, 1286 - src_w, src_h, src_x, src_y, 1287 - newstate->crtc_w, newstate->crtc_h, 1288 - newstate->crtc_x, newstate->crtc_y); 1283 + drm_dbg_driver(plane->dev, "plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n", 1284 + plane->base.id, fb->base.id, 1285 + src_w, src_h, src_x, src_y, 1286 + newstate->crtc_w, newstate->crtc_h, 1287 + newstate->crtc_x, newstate->crtc_y); 1289 1288 1290 1289 regmap_read(ldev->regmap, LTDC_BPCR, &bpcr); 1291 1290 ··· 1313 1312 val = ltdc_set_flexible_pixel_format(plane, pf); 1314 1313 1315 1314 if (val == NB_PF) { 1316 - DRM_ERROR("Pixel format %.4s not supported\n", 1317 - (char *)&fb->format->format); 1315 + drm_err(fb->dev, "Pixel format %.4s not supported\n", 1316 + (char *)&fb->format->format); 1318 1317 val = 0; /* set by default ARGB 32 bits */ 1319 1318 } 1320 1319 regmap_write_bits(ldev->regmap, LTDC_L1PFCR + lofs, LXPFCR_PF, val); ··· 1351 1350 if (newstate->rotation & DRM_MODE_REFLECT_Y) 1352 1351 paddr += (fb->pitches[0] * (y1 - y0)); 1353 1352 1354 - DRM_DEBUG_DRIVER("fb: phys 0x%08x", paddr); 1353 + drm_dbg_driver(fb->dev, "fb: phys 0x%08x", paddr); 1355 1354 regmap_write(ldev->regmap, LTDC_L1CFBAR + lofs, paddr); 1356 1355 1357 1356 /* Configures the color frame buffer pitch in bytes & line length */ ··· 1518 1517 regmap_write_bits(ldev->regmap, LTDC_L1RCR + lofs, 1519 1518 LXRCR_IMR | LXRCR_VBR | LXRCR_GRMSK, LXRCR_VBR); 1520 1519 1521 - DRM_DEBUG_DRIVER("CRTC:%d plane:%d\n", 1522 - oldstate->crtc->base.id, plane->base.id); 1520 + drm_dbg_driver(plane->dev, "CRTC:%d plane:%d\n", 1521 + oldstate->crtc->base.id, plane->base.id); 1523 1522 } 1524 1523 1525 1524 static void ltdc_plane_atomic_print_state(struct drm_printer *p, ··· 1633 1632 1634 1633 drm_plane_create_alpha_property(plane); 1635 1634 1636 - DRM_DEBUG_DRIVER("plane:%d created\n", plane->base.id); 1635 + drm_dbg_driver(plane->dev, "plane:%d created\n", plane->base.id); 1637 1636 1638 1637 return plane; 1639 1638 } ··· 1648 1647 1649 1648 primary = ltdc_plane_create(ddev, DRM_PLANE_TYPE_PRIMARY, 0); 1650 1649 if (!primary) { 1651 - DRM_ERROR("Can not create primary plane\n"); 1650 + drm_err(ddev, "Can not create primary plane\n"); 1652 1651 return -EINVAL; 1653 1652 } 1654 1653 ··· 1669 1668 ret = drmm_crtc_init_with_planes(ddev, crtc, primary, NULL, 1670 1669 &ltdc_crtc_funcs, NULL); 1671 1670 if (ret) { 1672 - DRM_ERROR("Can not initialize CRTC\n"); 1671 + drm_err(ddev, "Can not initialize CRTC\n"); 1673 1672 return ret; 1674 1673 } 1675 1674 ··· 1678 1677 drm_mode_crtc_set_gamma_size(crtc, CLUT_SIZE); 1679 1678 drm_crtc_enable_color_mgmt(crtc, 0, false, CLUT_SIZE); 1680 1679 1681 - DRM_DEBUG_DRIVER("CRTC:%d created\n", crtc->base.id); 1680 + drm_dbg_driver(ddev, "CRTC:%d created\n", crtc->base.id); 1682 1681 1683 1682 /* Add planes. Note : the first layer is used by primary plane */ 1684 1683 for (i = 1; i < ldev->caps.nb_layers; i++) { 1685 1684 overlay = ltdc_plane_create(ddev, DRM_PLANE_TYPE_OVERLAY, i); 1686 1685 if (!overlay) { 1687 - DRM_ERROR("Can not create overlay plane %d\n", i); 1686 + drm_err(ddev, "Can not create overlay plane %d\n", i); 1688 1687 return -ENOMEM; 1689 1688 } 1690 1689 if (ldev->caps.dynamic_zorder) ··· 1705 1704 struct drm_device *ddev = encoder->dev; 1706 1705 struct ltdc_device *ldev = ddev->dev_private; 1707 1706 1708 - DRM_DEBUG_DRIVER("\n"); 1707 + drm_dbg_driver(encoder->dev, "\n"); 1709 1708 1710 1709 /* Disable LTDC */ 1711 1710 regmap_clear_bits(ldev->regmap, LTDC_GCR, GCR_LTDCEN); ··· 1719 1718 struct drm_device *ddev = encoder->dev; 1720 1719 struct ltdc_device *ldev = ddev->dev_private; 1721 1720 1722 - DRM_DEBUG_DRIVER("\n"); 1721 + drm_dbg_driver(encoder->dev, "\n"); 1723 1722 1724 1723 /* set fifo underrun threshold register */ 1725 1724 if (ldev->caps.fifo_threshold) ··· 1735 1734 { 1736 1735 struct drm_device *ddev = encoder->dev; 1737 1736 1738 - DRM_DEBUG_DRIVER("\n"); 1737 + drm_dbg_driver(encoder->dev, "\n"); 1739 1738 1740 1739 /* 1741 1740 * Set to default state the pinctrl only with DPI type. ··· 1771 1770 if (ret) 1772 1771 return ret; 1773 1772 1774 - DRM_DEBUG_DRIVER("Bridge encoder:%d created\n", encoder->base.id); 1773 + drm_dbg_driver(encoder->dev, "Bridge encoder:%d created\n", encoder->base.id); 1775 1774 1776 1775 return 0; 1777 1776 } ··· 1871 1870 { 1872 1871 struct ltdc_device *ldev = ddev->dev_private; 1873 1872 1874 - DRM_DEBUG_DRIVER("\n"); 1873 + drm_dbg_driver(ddev, "\n"); 1875 1874 clk_disable_unprepare(ldev->pixel_clk); 1876 1875 } 1877 1876 ··· 1880 1879 struct ltdc_device *ldev = ddev->dev_private; 1881 1880 int ret; 1882 1881 1883 - DRM_DEBUG_DRIVER("\n"); 1882 + drm_dbg_driver(ddev, "\n"); 1884 1883 1885 1884 ret = clk_prepare_enable(ldev->pixel_clk); 1886 1885 if (ret) { 1887 - DRM_ERROR("failed to enable pixel clock (%d)\n", ret); 1886 + drm_err(ddev, "failed to enable pixel clock (%d)\n", ret); 1888 1887 return ret; 1889 1888 } 1890 1889 ··· 1904 1903 int irq, i, nb_endpoints; 1905 1904 int ret = -ENODEV; 1906 1905 1907 - DRM_DEBUG_DRIVER("\n"); 1906 + drm_dbg_driver(ddev, "\n"); 1908 1907 1909 1908 /* Get number of endpoints */ 1910 1909 nb_endpoints = of_graph_get_endpoint_count(np); ··· 1914 1913 ldev->pixel_clk = devm_clk_get(dev, "lcd"); 1915 1914 if (IS_ERR(ldev->pixel_clk)) { 1916 1915 if (PTR_ERR(ldev->pixel_clk) != -EPROBE_DEFER) 1917 - DRM_ERROR("Unable to get lcd clock\n"); 1916 + drm_err(ddev, "Unable to get lcd clock\n"); 1918 1917 return PTR_ERR(ldev->pixel_clk); 1919 1918 } 1920 1919 1921 1920 if (clk_prepare_enable(ldev->pixel_clk)) { 1922 - DRM_ERROR("Unable to prepare pixel clock\n"); 1921 + drm_err(ddev, "Unable to prepare pixel clock\n"); 1923 1922 return -ENODEV; 1924 1923 } 1925 1924 ··· 1940 1939 if (panel) { 1941 1940 bridge = drmm_panel_bridge_add(ddev, panel); 1942 1941 if (IS_ERR(bridge)) { 1943 - DRM_ERROR("panel-bridge endpoint %d\n", i); 1942 + drm_err(ddev, "panel-bridge endpoint %d\n", i); 1944 1943 ret = PTR_ERR(bridge); 1945 1944 goto err; 1946 1945 } ··· 1950 1949 ret = ltdc_encoder_init(ddev, bridge); 1951 1950 if (ret) { 1952 1951 if (ret != -EPROBE_DEFER) 1953 - DRM_ERROR("init encoder endpoint %d\n", i); 1952 + drm_err(ddev, "init encoder endpoint %d\n", i); 1954 1953 goto err; 1955 1954 } 1956 1955 } ··· 1968 1967 1969 1968 ldev->regs = devm_platform_ioremap_resource(pdev, 0); 1970 1969 if (IS_ERR(ldev->regs)) { 1971 - DRM_ERROR("Unable to get ltdc registers\n"); 1970 + drm_err(ddev, "Unable to get ltdc registers\n"); 1972 1971 ret = PTR_ERR(ldev->regs); 1973 1972 goto err; 1974 1973 } 1975 1974 1976 1975 ldev->regmap = devm_regmap_init_mmio(&pdev->dev, ldev->regs, &stm32_ltdc_regmap_cfg); 1977 1976 if (IS_ERR(ldev->regmap)) { 1978 - DRM_ERROR("Unable to regmap ltdc registers\n"); 1977 + drm_err(ddev, "Unable to regmap ltdc registers\n"); 1979 1978 ret = PTR_ERR(ldev->regmap); 1980 1979 goto err; 1981 1980 } 1982 1981 1983 1982 ret = ltdc_get_caps(ddev); 1984 1983 if (ret) { 1985 - DRM_ERROR("hardware identifier (0x%08x) not supported!\n", 1986 - ldev->caps.hw_version); 1984 + drm_err(ddev, "hardware identifier (0x%08x) not supported!\n", 1985 + ldev->caps.hw_version); 1987 1986 goto err; 1988 1987 } 1989 1988 1990 1989 /* Disable all interrupts */ 1991 1990 regmap_clear_bits(ldev->regmap, LTDC_IER, IER_MASK); 1992 1991 1993 - DRM_DEBUG_DRIVER("ltdc hw version 0x%08x\n", ldev->caps.hw_version); 1992 + drm_dbg_driver(ddev, "ltdc hw version 0x%08x\n", ldev->caps.hw_version); 1994 1993 1995 1994 /* initialize default value for fifo underrun threshold & clear interrupt error counters */ 1996 1995 ldev->transfer_err = 0; ··· 2009 2008 ltdc_irq_thread, IRQF_ONESHOT, 2010 2009 dev_name(dev), ddev); 2011 2010 if (ret) { 2012 - DRM_ERROR("Failed to register LTDC interrupt\n"); 2011 + drm_err(ddev, "Failed to register LTDC interrupt\n"); 2013 2012 goto err; 2014 2013 } 2015 2014 } 2016 2015 2017 2016 crtc = drmm_kzalloc(ddev, sizeof(*crtc), GFP_KERNEL); 2018 2017 if (!crtc) { 2019 - DRM_ERROR("Failed to allocate crtc\n"); 2018 + drm_err(ddev, "Failed to allocate crtc\n"); 2020 2019 ret = -ENOMEM; 2021 2020 goto err; 2022 2021 } 2023 2022 2024 2023 ret = ltdc_crtc_init(ddev, crtc); 2025 2024 if (ret) { 2026 - DRM_ERROR("Failed to init crtc\n"); 2025 + drm_err(ddev, "Failed to init crtc\n"); 2027 2026 goto err; 2028 2027 } 2029 2028 2030 2029 ret = drm_vblank_init(ddev, NB_CRTC); 2031 2030 if (ret) { 2032 - DRM_ERROR("Failed calling drm_vblank_init()\n"); 2031 + drm_err(ddev, "Failed calling drm_vblank_init()\n"); 2033 2032 goto err; 2034 2033 } 2035 2034 ··· 2048 2047 2049 2048 void ltdc_unload(struct drm_device *ddev) 2050 2049 { 2051 - DRM_DEBUG_DRIVER("\n"); 2050 + drm_dbg_driver(ddev, "\n"); 2052 2051 2053 2052 pm_runtime_disable(ddev->dev); 2054 2053 }