drm/msm/a6xx: Update a6xx gpu coredump · tjh.dev/kernel@1e05bba

+18

drivers/gpu/drm/msm/adreno/a6xx.xml.h

··· 241 241 A6XX_HLSQ_FRONTEND_META = 97, 242 242 A6XX_HLSQ_INDIRECT_META = 98, 243 243 A6XX_HLSQ_BACKEND_META = 99, 244 + A6XX_SP_LB_6_DATA = 112, 245 + A6XX_SP_LB_7_DATA = 113, 246 + A6XX_HLSQ_INST_RAM_1 = 115, 244 247 }; 245 248 246 249 enum a6xx_debugbus_id { ··· 277 274 A6XX_DBGBUS_HLSQ_SPTP = 31, 278 275 A6XX_DBGBUS_RB_0 = 32, 279 276 A6XX_DBGBUS_RB_1 = 33, 277 + A6XX_DBGBUS_RB_2 = 34, 280 278 A6XX_DBGBUS_UCHE_WRAPPER = 36, 281 279 A6XX_DBGBUS_CCU_0 = 40, 282 280 A6XX_DBGBUS_CCU_1 = 41, 281 + A6XX_DBGBUS_CCU_2 = 42, 283 282 A6XX_DBGBUS_VFD_0 = 56, 284 283 A6XX_DBGBUS_VFD_1 = 57, 285 284 A6XX_DBGBUS_VFD_2 = 58, 286 285 A6XX_DBGBUS_VFD_3 = 59, 286 + A6XX_DBGBUS_VFD_4 = 60, 287 + A6XX_DBGBUS_VFD_5 = 61, 287 288 A6XX_DBGBUS_SP_0 = 64, 288 289 A6XX_DBGBUS_SP_1 = 65, 290 + A6XX_DBGBUS_SP_2 = 66, 289 291 A6XX_DBGBUS_TPL1_0 = 72, 290 292 A6XX_DBGBUS_TPL1_1 = 73, 291 293 A6XX_DBGBUS_TPL1_2 = 74, 292 294 A6XX_DBGBUS_TPL1_3 = 75, 295 + A6XX_DBGBUS_TPL1_4 = 76, 296 + A6XX_DBGBUS_TPL1_5 = 77, 297 + A6XX_DBGBUS_SPTP_0 = 88, 298 + A6XX_DBGBUS_SPTP_1 = 89, 299 + A6XX_DBGBUS_SPTP_2 = 90, 300 + A6XX_DBGBUS_SPTP_3 = 91, 301 + A6XX_DBGBUS_SPTP_4 = 92, 302 + A6XX_DBGBUS_SPTP_5 = 93, 293 303 }; 294 304 295 305 enum a6xx_cp_perfcounter_select { ··· 1086 1070 #define REG_A6XX_CP_SQE_INSTR_BASE 0x00000830 1087 1071 1088 1072 #define REG_A6XX_CP_MISC_CNTL 0x00000840 1073 + 1074 + #define REG_A6XX_CP_CHICKEN_DBG 0x00000841 1089 1075 1090 1076 #define REG_A6XX_CP_APRIV_CNTL 0x00000844 1091 1077

+49 -1

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c

··· 385 385 nr_debugbus_blocks = ARRAY_SIZE(a6xx_debugbus_blocks) + 386 386 (a6xx_has_gbif(to_adreno_gpu(gpu)) ? 1 : 0); 387 387 388 + if (adreno_is_a650_family(to_adreno_gpu(gpu))) 389 + nr_debugbus_blocks += ARRAY_SIZE(a650_debugbus_blocks); 390 + 388 391 a6xx_state->debugbus = state_kcalloc(a6xx_state, nr_debugbus_blocks, 389 392 sizeof(*a6xx_state->debugbus)); 390 393 ··· 413 410 &a6xx_state->debugbus[i]); 414 411 415 412 a6xx_state->nr_debugbus += 1; 413 + } 414 + 415 + 416 + if (adreno_is_a650_family(to_adreno_gpu(gpu))) { 417 + for (i = 0; i < ARRAY_SIZE(a650_debugbus_blocks); i++) 418 + a6xx_get_debugbus_block(gpu, 419 + a6xx_state, 420 + &a650_debugbus_blocks[i], 421 + &a6xx_state->debugbus[i]); 416 422 } 417 423 } 418 424 ··· 536 524 struct a6xx_gpu_state_obj *obj, 537 525 struct a6xx_crashdumper *dumper) 538 526 { 527 + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 539 528 u64 *in = dumper->ptr; 540 529 u64 out = dumper->iova + A6XX_CD_DATA_OFFSET; 541 530 size_t datasize; 542 531 int i, regcount = 0; 532 + u32 id = cluster->id; 533 + 534 + /* Skip registers that are not present on older generation */ 535 + if (!adreno_is_a660_family(adreno_gpu) && 536 + cluster->registers == a660_fe_cluster) 537 + return; 538 + 539 + if (adreno_is_a650_family(adreno_gpu) && 540 + cluster->registers == a6xx_ps_cluster) 541 + id = CLUSTER_VPC_PS; 543 542 544 543 /* Some clusters need a selector register to be programmed too */ 545 544 if (cluster->sel_reg) ··· 560 537 int j; 561 538 562 539 in += CRASHDUMP_WRITE(in, REG_A6XX_CP_APERTURE_CNTL_CD, 563 - (cluster->id << 8) | (i << 4) | i); 540 + (id << 8) | (i << 4) | i); 564 541 565 542 for (j = 0; j < cluster->count; j += 2) { 566 543 int count = RANGE(cluster->registers, j); ··· 710 687 u64 out = dumper->iova + A6XX_CD_DATA_OFFSET; 711 688 int i, regcount = 0; 712 689 690 + /* Skip unsupported registers on older generations */ 691 + if (!adreno_is_a660_family(to_adreno_gpu(gpu)) && 692 + (regs->registers == a660_registers)) 693 + return; 694 + 713 695 /* Some blocks might need to program a selector register first */ 714 696 if (regs->val0) 715 697 in += CRASHDUMP_WRITE(in, regs->val0, regs->val1); ··· 748 720 struct a6xx_gpu_state_obj *obj) 749 721 { 750 722 int i, regcount = 0, index = 0; 723 + 724 + /* Skip unsupported registers on older generations */ 725 + if (!adreno_is_a660_family(to_adreno_gpu(gpu)) && 726 + (regs->registers == a660_registers)) 727 + return; 751 728 752 729 for (i = 0; i < regs->count; i += 2) 753 730 regcount += RANGE(regs->registers, i); ··· 978 945 for (i = 0; i < ARRAY_SIZE(a6xx_indexed_reglist); i++) 979 946 a6xx_get_indexed_regs(gpu, a6xx_state, &a6xx_indexed_reglist[i], 980 947 &a6xx_state->indexed_regs[i]); 948 + 949 + if (adreno_is_a650_family(to_adreno_gpu(gpu))) { 950 + u32 val; 951 + 952 + val = gpu_read(gpu, REG_A6XX_CP_CHICKEN_DBG); 953 + gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, val | 4); 954 + 955 + /* Get the contents of the CP mempool */ 956 + a6xx_get_indexed_regs(gpu, a6xx_state, &a6xx_cp_mempool_indexed, 957 + &a6xx_state->indexed_regs[i]); 958 + 959 + gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, val); 960 + a6xx_state->nr_indexed_regs = count; 961 + return; 962 + } 981 963 982 964 /* Set the CP mempool size to 0 to stabilize it while dumping */ 983 965 mempool_size = gpu_read(gpu, REG_A6XX_CP_MEM_POOL_SIZE);

+41 -8

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h

··· 36 36 0xa00e, 0xa0ef, 0xa0f8, 0xa0f8, 37 37 }; 38 38 39 + static const u32 a660_fe_cluster[] = { 40 + 0x9807, 0x9807, 41 + }; 42 + 39 43 static const u32 a6xx_pc_vs_cluster[] = { 40 44 0x9100, 0x9108, 0x9300, 0x9306, 0x9980, 0x9981, 0x9b00, 0x9b07, 41 45 }; 42 46 43 - #define CLUSTER_FE 0 44 - #define CLUSTER_SP_VS 1 45 - #define CLUSTER_PC_VS 2 46 - #define CLUSTER_GRAS 3 47 - #define CLUSTER_SP_PS 4 48 - #define CLUSTER_PS 5 47 + #define CLUSTER_FE 0 48 + #define CLUSTER_SP_VS 1 49 + #define CLUSTER_PC_VS 2 50 + #define CLUSTER_GRAS 3 51 + #define CLUSTER_SP_PS 4 52 + #define CLUSTER_PS 5 53 + #define CLUSTER_VPC_PS 6 49 54 50 55 #define CLUSTER(_id, _reg, _sel_reg, _sel_val) \ 51 56 { .id = _id, .name = #_id,\ ··· 72 67 CLUSTER(CLUSTER_PS, a6xx_ps_cluster, 0, 0), 73 68 CLUSTER(CLUSTER_FE, a6xx_fe_cluster, 0, 0), 74 69 CLUSTER(CLUSTER_PC_VS, a6xx_pc_vs_cluster, 0, 0), 70 + CLUSTER(CLUSTER_FE, a660_fe_cluster, 0, 0), 75 71 }; 76 72 77 73 static const u32 a6xx_sp_vs_hlsq_cluster[] = { ··· 111 105 112 106 static const u32 a6xx_sp_ps_sp_cluster[] = { 113 107 0xa980, 0xa9a8, 0xa9b0, 0xa9bc, 0xa9d0, 0xa9d3, 0xa9e0, 0xa9f3, 114 - 0xaa00, 0xaa00, 0xaa30, 0xaa31, 108 + 0xaa00, 0xaa00, 0xaa30, 0xaa31, 0xaaf2, 0xaaf2, 115 109 }; 116 110 117 111 static const u32 a6xx_sp_ps_sp_2d_cluster[] = { ··· 235 229 SHADER(A6XX_HLSQ_DATAPATH_META, 0x40), 236 230 SHADER(A6XX_HLSQ_FRONTEND_META, 0x40), 237 231 SHADER(A6XX_HLSQ_INDIRECT_META, 0x40), 232 + SHADER(A6XX_SP_LB_6_DATA, 0x200), 233 + SHADER(A6XX_SP_LB_7_DATA, 0x200), 234 + SHADER(A6XX_HLSQ_INST_RAM_1, 0x200), 238 235 }; 239 236 240 237 static const u32 a6xx_rb_rac_registers[] = { ··· 260 251 0x0540, 0x0555, 261 252 /* CP */ 262 253 0x0800, 0x0808, 0x0810, 0x0813, 0x0820, 0x0821, 0x0823, 0x0824, 263 - 0x0826, 0x0827, 0x0830, 0x0833, 0x0840, 0x0843, 0x084f, 0x086f, 254 + 0x0826, 0x0827, 0x0830, 0x0833, 0x0840, 0x0845, 0x084f, 0x086f, 264 255 0x0880, 0x088a, 0x08a0, 0x08ab, 0x08c0, 0x08c4, 0x08d0, 0x08dd, 265 256 0x08f0, 0x08f3, 0x0900, 0x0903, 0x0908, 0x0911, 0x0928, 0x093e, 266 257 0x0942, 0x094d, 0x0980, 0x0984, 0x098d, 0x0996, 0x0998, 0x099e, ··· 283 274 /* VFD */ 284 275 0xa600, 0xa601, 0xa603, 0xa603, 0xa60a, 0xa60a, 0xa610, 0xa617, 285 276 0xa630, 0xa630, 277 + /* HLSQ */ 278 + 0xd002, 0xd003, 279 + }; 280 + 281 + static const u32 a660_registers[] = { 282 + /* UCHE */ 283 + 0x0e3c, 0x0e3c, 286 284 }; 287 285 288 286 #define REGS(_array, _sel_reg, _sel_val) \ ··· 298 282 299 283 static const struct a6xx_registers a6xx_reglist[] = { 300 284 REGS(a6xx_registers, 0, 0), 285 + REGS(a660_registers, 0, 0), 301 286 REGS(a6xx_rb_rac_registers, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0), 302 287 REGS(a6xx_rb_rbp_registers, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 9), 303 288 }; ··· 458 441 static const struct a6xx_debugbus_block a6xx_cx_debugbus_blocks[] = { 459 442 DEBUGBUS(A6XX_DBGBUS_GMU_CX, 0x100), 460 443 DEBUGBUS(A6XX_DBGBUS_CX, 0x100), 444 + }; 445 + 446 + static const struct a6xx_debugbus_block a650_debugbus_blocks[] = { 447 + DEBUGBUS(A6XX_DBGBUS_RB_2, 0x100), 448 + DEBUGBUS(A6XX_DBGBUS_CCU_2, 0x100), 449 + DEBUGBUS(A6XX_DBGBUS_VFD_4, 0x100), 450 + DEBUGBUS(A6XX_DBGBUS_VFD_5, 0x100), 451 + DEBUGBUS(A6XX_DBGBUS_SP_2, 0x100), 452 + DEBUGBUS(A6XX_DBGBUS_TPL1_4, 0x100), 453 + DEBUGBUS(A6XX_DBGBUS_TPL1_5, 0x100), 454 + DEBUGBUS(A6XX_DBGBUS_SPTP_0, 0x100), 455 + DEBUGBUS(A6XX_DBGBUS_SPTP_1, 0x100), 456 + DEBUGBUS(A6XX_DBGBUS_SPTP_2, 0x100), 457 + DEBUGBUS(A6XX_DBGBUS_SPTP_3, 0x100), 458 + DEBUGBUS(A6XX_DBGBUS_SPTP_4, 0x100), 459 + DEBUGBUS(A6XX_DBGBUS_SPTP_5, 0x100), 461 460 }; 462 461 463 462 #endif

Configure Feed

Configure Feed