Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'timers-clocksource-2025-03-26' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull clocksource/event updates from Thomas Gleixner:
- Add support for suspend/resume in the STM32 LP-Timer driver with a
follow up fix, which uses the proper method to setup the timer as a
optional wakeup source instead of trying to force it as mandatory
wakeup source.
- The usual device tree updates to enable new SoC models in existing
drivers.
- Trivial spelling, style and indentation fixes
* tag 'timers-clocksource-2025-03-26' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
dt-bindings: timer: Add SiFive CLINT2
clocksource/drivers/stm32-lptimer: Use wakeup capable instead of init wakeup
clocksource/drivers/exynos_mct: Fixed a spelling error
clocksource/drivers/stm32-lptimer: Add support for suspend / resume
dt-bindings: timer: exynos4210-mct: add samsung,exynos2200-mct-peris compatible
dt-bindings: timer: exynos4210-mct: Add samsung,exynos990-mct compatible
dt-bindings: timer: Correct indentation and style in DTS example
+115
-65
+3
-3
Documentation/devicetree/bindings/timer/arm,twd-timer.yaml
+3
-3
Documentation/devicetree/bindings/timer/arm,twd-timer.yaml
···
50
50
#include <dt-bindings/interrupt-controller/arm-gic.h>
51
51
52
52
timer@2c000600 {
53
-
compatible = "arm,arm11mp-twd-timer";
54
-
reg = <0x2c000600 0x20>;
55
-
interrupts = <GIC_PPI 13 0xf01>;
53
+
compatible = "arm,arm11mp-twd-timer";
54
+
reg = <0x2c000600 0x20>;
55
+
interrupts = <GIC_PPI 13 0xf01>;
56
56
};
+22
-22
Documentation/devicetree/bindings/timer/renesas,cmt.yaml
+22
-22
Documentation/devicetree/bindings/timer/renesas,cmt.yaml
···
178
178
#include <dt-bindings/interrupt-controller/arm-gic.h>
179
179
#include <dt-bindings/power/r8a7790-sysc.h>
180
180
cmt0: timer@ffca0000 {
181
-
compatible = "renesas,r8a7790-cmt0", "renesas,rcar-gen2-cmt0";
182
-
reg = <0xffca0000 0x1004>;
183
-
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
184
-
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
185
-
clocks = <&cpg CPG_MOD 124>;
186
-
clock-names = "fck";
187
-
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
188
-
resets = <&cpg 124>;
181
+
compatible = "renesas,r8a7790-cmt0", "renesas,rcar-gen2-cmt0";
182
+
reg = <0xffca0000 0x1004>;
183
+
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
184
+
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
185
+
clocks = <&cpg CPG_MOD 124>;
186
+
clock-names = "fck";
187
+
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
188
+
resets = <&cpg 124>;
189
189
};
190
190
191
191
cmt1: timer@e6130000 {
192
-
compatible = "renesas,r8a7790-cmt1", "renesas,rcar-gen2-cmt1";
193
-
reg = <0xe6130000 0x1004>;
194
-
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
195
-
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
196
-
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
197
-
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
198
-
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
199
-
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
200
-
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
201
-
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
202
-
clocks = <&cpg CPG_MOD 329>;
203
-
clock-names = "fck";
204
-
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
205
-
resets = <&cpg 329>;
192
+
compatible = "renesas,r8a7790-cmt1", "renesas,rcar-gen2-cmt1";
193
+
reg = <0xe6130000 0x1004>;
194
+
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
195
+
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
196
+
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
197
+
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
198
+
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
199
+
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
200
+
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
201
+
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
202
+
clocks = <&cpg CPG_MOD 329>;
203
+
clock-names = "fck";
204
+
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
205
+
resets = <&cpg 329>;
206
206
};
+5
-5
Documentation/devicetree/bindings/timer/renesas,em-sti.yaml
+5
-5
Documentation/devicetree/bindings/timer/renesas,em-sti.yaml
···
38
38
- |
39
39
#include <dt-bindings/interrupt-controller/arm-gic.h>
40
40
timer@e0180000 {
41
-
compatible = "renesas,em-sti";
42
-
reg = <0xe0180000 0x54>;
43
-
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
44
-
clocks = <&sti_sclk>;
45
-
clock-names = "sclk";
41
+
compatible = "renesas,em-sti";
42
+
reg = <0xe0180000 0x54>;
43
+
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
44
+
clocks = <&sti_sclk>;
45
+
clock-names = "sclk";
46
46
};
+7
-7
Documentation/devicetree/bindings/timer/renesas,mtu2.yaml
+7
-7
Documentation/devicetree/bindings/timer/renesas,mtu2.yaml
···
66
66
#include <dt-bindings/clock/r7s72100-clock.h>
67
67
#include <dt-bindings/interrupt-controller/arm-gic.h>
68
68
mtu2: timer@fcff0000 {
69
-
compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
70
-
reg = <0xfcff0000 0x400>;
71
-
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
72
-
interrupt-names = "tgi0a";
73
-
clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
74
-
clock-names = "fck";
75
-
power-domains = <&cpg_clocks>;
69
+
compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
70
+
reg = <0xfcff0000 0x400>;
71
+
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
72
+
interrupt-names = "tgi0a";
73
+
clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
74
+
clock-names = "fck";
75
+
power-domains = <&cpg_clocks>;
76
76
};
+5
-5
Documentation/devicetree/bindings/timer/renesas,ostm.yaml
+5
-5
Documentation/devicetree/bindings/timer/renesas,ostm.yaml
···
71
71
#include <dt-bindings/clock/r7s72100-clock.h>
72
72
#include <dt-bindings/interrupt-controller/arm-gic.h>
73
73
ostm0: timer@fcfec000 {
74
-
compatible = "renesas,r7s72100-ostm", "renesas,ostm";
75
-
reg = <0xfcfec000 0x30>;
76
-
interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
77
-
clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
78
-
power-domains = <&cpg_clocks>;
74
+
compatible = "renesas,r7s72100-ostm", "renesas,ostm";
75
+
reg = <0xfcfec000 0x30>;
76
+
interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
77
+
clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
78
+
power-domains = <&cpg_clocks>;
79
79
};
+11
-11
Documentation/devicetree/bindings/timer/renesas,tmu.yaml
+11
-11
Documentation/devicetree/bindings/timer/renesas,tmu.yaml
···
122
122
#include <dt-bindings/interrupt-controller/arm-gic.h>
123
123
#include <dt-bindings/power/r8a7779-sysc.h>
124
124
tmu0: timer@ffd80000 {
125
-
compatible = "renesas,tmu-r8a7779", "renesas,tmu";
126
-
reg = <0xffd80000 0x30>;
127
-
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
128
-
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
129
-
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
130
-
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
131
-
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
132
-
clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
133
-
clock-names = "fck";
134
-
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
135
-
#renesas,channels = <3>;
125
+
compatible = "renesas,tmu-r8a7779", "renesas,tmu";
126
+
reg = <0xffd80000 0x30>;
127
+
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
128
+
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
129
+
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
130
+
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
131
+
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
132
+
clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
133
+
clock-names = "fck";
134
+
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
135
+
#renesas,channels = <3>;
136
136
};
+4
-4
Documentation/devicetree/bindings/timer/renesas,tpu.yaml
+4
-4
Documentation/devicetree/bindings/timer/renesas,tpu.yaml
···
49
49
examples:
50
50
- |
51
51
tpu: tpu@ffffe0 {
52
-
compatible = "renesas,tpu";
53
-
reg = <0xffffe0 16>, <0xfffff0 12>;
54
-
clocks = <&pclk>;
55
-
clock-names = "fck";
52
+
compatible = "renesas,tpu";
53
+
reg = <0xffffe0 16>, <0xfffff0 12>;
54
+
clocks = <&pclk>;
55
+
clock-names = "fck";
56
56
};
+4
Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml
+4
Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml
···
27
27
- enum:
28
28
- axis,artpec8-mct
29
29
- google,gs101-mct
30
+
- samsung,exynos2200-mct-peris
30
31
- samsung,exynos3250-mct
31
32
- samsung,exynos5250-mct
32
33
- samsung,exynos5260-mct
···
35
34
- samsung,exynos5433-mct
36
35
- samsung,exynos850-mct
37
36
- samsung,exynos8895-mct
37
+
- samsung,exynos990-mct
38
38
- tesla,fsd-mct
39
39
- const: samsung,exynos4210-mct
40
40
···
132
130
enum:
133
131
- axis,artpec8-mct
134
132
- google,gs101-mct
133
+
- samsung,exynos2200-mct-peris
135
134
- samsung,exynos5260-mct
136
135
- samsung,exynos5420-mct
137
136
- samsung,exynos5433-mct
138
137
- samsung,exynos850-mct
139
138
- samsung,exynos8895-mct
139
+
- samsung,exynos990-mct
140
140
then:
141
141
properties:
142
142
interrupts:
+23
-1
Documentation/devicetree/bindings/timer/sifive,clint.yaml
+23
-1
Documentation/devicetree/bindings/timer/sifive,clint.yaml
···
37
37
- starfive,jh8100-clint # StarFive JH8100
38
38
- const: sifive,clint0 # SiFive CLINT v0 IP block
39
39
- items:
40
+
- {}
41
+
- const: sifive,clint2 # SiFive CLINT v2 IP block
42
+
description:
43
+
SiFive CLINT v2 is the HRT that supports the Zicntr. The control of sifive,clint2
44
+
differs from that of sifive,clint0, making them incompatible.
45
+
- items:
40
46
- enum:
41
47
- allwinner,sun20i-d1-clint
42
48
- sophgo,cv1800b-clint
···
68
62
minItems: 1
69
63
maxItems: 4095
70
64
65
+
sifive,fine-ctr-bits:
66
+
maximum: 15
67
+
description: The width in bits of the fine counter.
68
+
69
+
if:
70
+
properties:
71
+
compatible:
72
+
contains:
73
+
const: sifive,clint2
74
+
then:
75
+
required:
76
+
- sifive,fine-ctr-bits
77
+
else:
78
+
properties:
79
+
sifive,fine-ctr-bits: false
80
+
71
81
additionalProperties: false
72
82
73
83
required:
···
99
77
<&cpu2intc 3>, <&cpu2intc 7>,
100
78
<&cpu3intc 3>, <&cpu3intc 7>,
101
79
<&cpu4intc 3>, <&cpu4intc 7>;
102
-
reg = <0x2000000 0x10000>;
80
+
reg = <0x2000000 0x10000>;
103
81
};
104
82
...
+1
-1
drivers/clocksource/exynos_mct.c
+1
-1
drivers/clocksource/exynos_mct.c
···
238
238
static int __init exynos4_clocksource_init(bool frc_shared)
239
239
{
240
240
/*
241
-
* When the frc is shared, the main processer should have already
241
+
* When the frc is shared, the main processor should have already
242
242
* turned it on and we shouldn't be writing to TCON.
243
243
*/
244
244
if (frc_shared)
+30
-6
drivers/clocksource/timer-stm32-lp.c
+30
-6
drivers/clocksource/timer-stm32-lp.c
···
24
24
struct regmap *reg;
25
25
struct clock_event_device clkevt;
26
26
unsigned long period;
27
+
u32 psc;
27
28
struct device *dev;
29
+
struct clk *clk;
28
30
};
29
31
30
32
static struct stm32_lp_private*
···
122
120
/* Adjust rate and period given the prescaler value */
123
121
*rate = DIV_ROUND_CLOSEST(*rate, (1 << i));
124
122
priv->period = DIV_ROUND_UP(*rate, HZ);
123
+
priv->psc = i;
124
+
}
125
+
126
+
static void stm32_clkevent_lp_suspend(struct clock_event_device *clkevt)
127
+
{
128
+
struct stm32_lp_private *priv = to_priv(clkevt);
129
+
130
+
stm32_clkevent_lp_shutdown(clkevt);
131
+
132
+
/* balance clk_prepare_enable() from the probe */
133
+
clk_disable_unprepare(priv->clk);
134
+
}
135
+
136
+
static void stm32_clkevent_lp_resume(struct clock_event_device *clkevt)
137
+
{
138
+
struct stm32_lp_private *priv = to_priv(clkevt);
139
+
140
+
clk_prepare_enable(priv->clk);
141
+
142
+
/* restore prescaler */
143
+
regmap_write(priv->reg, STM32_LPTIM_CFGR, priv->psc << CFGR_PSC_OFFSET);
125
144
}
126
145
127
146
static void stm32_clkevent_lp_init(struct stm32_lp_private *priv,
···
157
134
priv->clkevt.set_state_oneshot = stm32_clkevent_lp_set_oneshot;
158
135
priv->clkevt.set_next_event = stm32_clkevent_lp_set_next_event;
159
136
priv->clkevt.rating = STM32_LP_RATING;
137
+
priv->clkevt.suspend = stm32_clkevent_lp_suspend;
138
+
priv->clkevt.resume = stm32_clkevent_lp_resume;
160
139
161
140
clockevents_config_and_register(&priv->clkevt, rate, 0x1,
162
141
STM32_LPTIM_MAX_ARR);
···
176
151
return -ENOMEM;
177
152
178
153
priv->reg = ddata->regmap;
179
-
ret = clk_prepare_enable(ddata->clk);
154
+
priv->clk = ddata->clk;
155
+
ret = clk_prepare_enable(priv->clk);
180
156
if (ret)
181
157
return -EINVAL;
182
158
183
-
rate = clk_get_rate(ddata->clk);
159
+
rate = clk_get_rate(priv->clk);
184
160
if (!rate) {
185
161
ret = -EINVAL;
186
162
goto out_clk_disable;
···
194
168
}
195
169
196
170
if (of_property_read_bool(pdev->dev.parent->of_node, "wakeup-source")) {
197
-
ret = device_init_wakeup(&pdev->dev, true);
198
-
if (ret)
199
-
goto out_clk_disable;
171
+
device_set_wakeup_capable(&pdev->dev, true);
200
172
201
173
ret = dev_pm_set_wake_irq(&pdev->dev, irq);
202
174
if (ret)
···
215
191
return 0;
216
192
217
193
out_clk_disable:
218
-
clk_disable_unprepare(ddata->clk);
194
+
clk_disable_unprepare(priv->clk);
219
195
return ret;
220
196
}
221
197