tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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RDMA/mlx5: Delete one-time used functions

Merge them into their callers, usually the only thing the caller did was
to call the one function, so this is clearer.

Link: https://lore.kernel.org/r/20200702081809.423482-7-leon@kernel.org
Signed-off-by: Leon Romanovsky <leonro@mellanox.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>

authored by

Leon Romanovsky and committed by
Jason Gunthorpe 1e2b5a90 d8b7515e

+198 -277
+198 -277
drivers/infiniband/hw/mlx5/main.c
··· 3023 3023 return __get_port_caps(dev, port); 3024 3024 } 3025 3025 3026 - static void destroy_umrc_res(struct mlx5_ib_dev *dev) 3027 - { 3028 - int err; 3029 - 3030 - err = mlx5_mr_cache_cleanup(dev); 3031 - if (err) 3032 - mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 3033 - 3034 - if (dev->umrc.qp) 3035 - mlx5_ib_destroy_qp(dev->umrc.qp, NULL); 3036 - if (dev->umrc.cq) 3037 - ib_free_cq(dev->umrc.cq); 3038 - if (dev->umrc.pd) 3039 - ib_dealloc_pd(dev->umrc.pd); 3040 - } 3041 - 3042 - enum { 3043 - MAX_UMR_WR = 128, 3044 - }; 3045 - 3046 - static int create_umr_res(struct mlx5_ib_dev *dev) 3047 - { 3048 - struct ib_qp_init_attr *init_attr = NULL; 3049 - struct ib_qp_attr *attr = NULL; 3050 - struct ib_pd *pd; 3051 - struct ib_cq *cq; 3052 - struct ib_qp *qp; 3053 - int ret; 3054 - 3055 - attr = kzalloc(sizeof(*attr), GFP_KERNEL); 3056 - init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 3057 - if (!attr || !init_attr) { 3058 - ret = -ENOMEM; 3059 - goto error_0; 3060 - } 3061 - 3062 - pd = ib_alloc_pd(&dev->ib_dev, 0); 3063 - if (IS_ERR(pd)) { 3064 - mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 3065 - ret = PTR_ERR(pd); 3066 - goto error_0; 3067 - } 3068 - 3069 - cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 3070 - if (IS_ERR(cq)) { 3071 - mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 3072 - ret = PTR_ERR(cq); 3073 - goto error_2; 3074 - } 3075 - 3076 - init_attr->send_cq = cq; 3077 - init_attr->recv_cq = cq; 3078 - init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 3079 - init_attr->cap.max_send_wr = MAX_UMR_WR; 3080 - init_attr->cap.max_send_sge = 1; 3081 - init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 3082 - init_attr->port_num = 1; 3083 - qp = mlx5_ib_create_qp(pd, init_attr, NULL); 3084 - if (IS_ERR(qp)) { 3085 - mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 3086 - ret = PTR_ERR(qp); 3087 - goto error_3; 3088 - } 3089 - qp->device = &dev->ib_dev; 3090 - qp->real_qp = qp; 3091 - qp->uobject = NULL; 3092 - qp->qp_type = MLX5_IB_QPT_REG_UMR; 3093 - qp->send_cq = init_attr->send_cq; 3094 - qp->recv_cq = init_attr->recv_cq; 3095 - 3096 - attr->qp_state = IB_QPS_INIT; 3097 - attr->port_num = 1; 3098 - ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 3099 - IB_QP_PORT, NULL); 3100 - if (ret) { 3101 - mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 3102 - goto error_4; 3103 - } 3104 - 3105 - memset(attr, 0, sizeof(*attr)); 3106 - attr->qp_state = IB_QPS_RTR; 3107 - attr->path_mtu = IB_MTU_256; 3108 - 3109 - ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 3110 - if (ret) { 3111 - mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 3112 - goto error_4; 3113 - } 3114 - 3115 - memset(attr, 0, sizeof(*attr)); 3116 - attr->qp_state = IB_QPS_RTS; 3117 - ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 3118 - if (ret) { 3119 - mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 3120 - goto error_4; 3121 - } 3122 - 3123 - dev->umrc.qp = qp; 3124 - dev->umrc.cq = cq; 3125 - dev->umrc.pd = pd; 3126 - 3127 - sema_init(&dev->umrc.sem, MAX_UMR_WR); 3128 - ret = mlx5_mr_cache_init(dev); 3129 - if (ret) { 3130 - mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 3131 - goto error_4; 3132 - } 3133 - 3134 - kfree(attr); 3135 - kfree(init_attr); 3136 - 3137 - return 0; 3138 - 3139 - error_4: 3140 - mlx5_ib_destroy_qp(qp, NULL); 3141 - dev->umrc.qp = NULL; 3142 - 3143 - error_3: 3144 - ib_free_cq(cq); 3145 - dev->umrc.cq = NULL; 3146 - 3147 - error_2: 3148 - ib_dealloc_pd(pd); 3149 - dev->umrc.pd = NULL; 3150 - 3151 - error_0: 3152 - kfree(attr); 3153 - kfree(init_attr); 3154 - return ret; 3155 - } 3156 - 3157 3026 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 3158 3027 { 3159 3028 switch (umr_fence_cap) { ··· 3035 3166 } 3036 3167 } 3037 3168 3038 - static int create_dev_resources(struct mlx5_ib_resources *devr) 3169 + static int mlx5_ib_dev_res_init(struct mlx5_ib_dev *dev) 3039 3170 { 3171 + struct mlx5_ib_resources *devr = &dev->devr; 3040 3172 struct ib_srq_init_attr attr; 3041 - struct mlx5_ib_dev *dev; 3042 3173 struct ib_device *ibdev; 3043 3174 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 3044 3175 int port; 3045 3176 int ret = 0; 3046 3177 3047 - dev = container_of(devr, struct mlx5_ib_dev, devr); 3048 3178 ibdev = &dev->ib_dev; 3049 3179 3050 3180 if (!MLX5_CAP_GEN(dev->mdev, xrc)) ··· 3159 3291 return ret; 3160 3292 } 3161 3293 3162 - static void destroy_dev_resources(struct mlx5_ib_resources *devr) 3294 + static void mlx5_ib_dev_res_cleanup(struct mlx5_ib_dev *dev) 3163 3295 { 3164 - struct mlx5_ib_dev *dev; 3296 + struct mlx5_ib_resources *devr = &dev->devr; 3165 3297 int port; 3166 - 3167 - dev = container_of(devr, struct mlx5_ib_dev, devr); 3168 3298 3169 3299 mlx5_ib_destroy_srq(devr->s1, NULL); 3170 3300 kfree(devr->s1); ··· 3372 3506 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params); 3373 3507 } 3374 3508 3375 - static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev) 3376 - { 3377 - if (!dev->delay_drop.dir_debugfs) 3378 - return; 3379 - debugfs_remove_recursive(dev->delay_drop.dir_debugfs); 3380 - dev->delay_drop.dir_debugfs = NULL; 3381 - } 3382 - 3383 - static void cancel_delay_drop(struct mlx5_ib_dev *dev) 3384 - { 3385 - if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 3386 - return; 3387 - 3388 - cancel_work_sync(&dev->delay_drop.delay_drop_work); 3389 - delay_drop_debugfs_cleanup(dev); 3390 - } 3391 - 3392 3509 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 3393 3510 size_t count, loff_t *pos) 3394 3511 { ··· 3410 3561 .write = delay_drop_timeout_write, 3411 3562 .read = delay_drop_timeout_read, 3412 3563 }; 3413 - 3414 - static void delay_drop_debugfs_init(struct mlx5_ib_dev *dev) 3415 - { 3416 - struct dentry *root; 3417 - 3418 - if (!mlx5_debugfs_root) 3419 - return; 3420 - 3421 - root = debugfs_create_dir("delay_drop", dev->mdev->priv.dbg_root); 3422 - dev->delay_drop.dir_debugfs = root; 3423 - 3424 - debugfs_create_atomic_t("num_timeout_events", 0400, root, 3425 - &dev->delay_drop.events_cnt); 3426 - debugfs_create_atomic_t("num_rqs", 0400, root, 3427 - &dev->delay_drop.rqs_cnt); 3428 - debugfs_create_file("timeout", 0600, root, &dev->delay_drop, 3429 - &fops_delay_drop_timeout); 3430 - } 3431 - 3432 - static void init_delay_drop(struct mlx5_ib_dev *dev) 3433 - { 3434 - if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 3435 - return; 3436 - 3437 - mutex_init(&dev->delay_drop.lock); 3438 - dev->delay_drop.dev = dev; 3439 - dev->delay_drop.activate = false; 3440 - dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 3441 - INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 3442 - atomic_set(&dev->delay_drop.rqs_cnt, 0); 3443 - atomic_set(&dev->delay_drop.events_cnt, 0); 3444 - 3445 - delay_drop_debugfs_init(dev); 3446 - } 3447 3564 3448 3565 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev, 3449 3566 struct mlx5_ib_multiport_info *mpi) ··· 4273 4458 .modify_wq = mlx5_ib_modify_wq, 4274 4459 }; 4275 4460 4276 - static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev) 4277 - { 4278 - u8 port_num; 4279 - 4280 - dev->ib_dev.uverbs_ex_cmd_mask |= 4281 - (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 4282 - (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 4283 - (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 4284 - (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 4285 - (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 4286 - ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops); 4287 - 4288 - port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4289 - 4290 - /* Register only for native ports */ 4291 - return mlx5_add_netdev_notifier(dev, port_num); 4292 - } 4293 - 4294 - static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev) 4295 - { 4296 - u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4297 - 4298 - mlx5_remove_netdev_notifier(dev, port_num); 4299 - } 4300 - 4301 - static int mlx5_ib_stage_raw_eth_roce_init(struct mlx5_ib_dev *dev) 4461 + static int mlx5_ib_roce_init(struct mlx5_ib_dev *dev) 4302 4462 { 4303 4463 struct mlx5_core_dev *mdev = dev->mdev; 4304 4464 enum rdma_link_layer ll; 4305 4465 int port_type_cap; 4306 - int err = 0; 4307 - 4308 - port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4309 - ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4310 - 4311 - if (ll == IB_LINK_LAYER_ETHERNET) 4312 - err = mlx5_ib_stage_common_roce_init(dev); 4313 - 4314 - return err; 4315 - } 4316 - 4317 - static void mlx5_ib_stage_raw_eth_roce_cleanup(struct mlx5_ib_dev *dev) 4318 - { 4319 - mlx5_ib_stage_common_roce_cleanup(dev); 4320 - } 4321 - 4322 - static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev) 4323 - { 4324 - struct mlx5_core_dev *mdev = dev->mdev; 4325 - enum rdma_link_layer ll; 4326 - int port_type_cap; 4466 + u8 port_num = 0; 4327 4467 int err; 4328 4468 4329 4469 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4330 4470 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4331 4471 4332 4472 if (ll == IB_LINK_LAYER_ETHERNET) { 4333 - err = mlx5_ib_stage_common_roce_init(dev); 4334 - if (err) 4473 + dev->ib_dev.uverbs_ex_cmd_mask |= 4474 + (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 4475 + (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 4476 + (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 4477 + (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 4478 + (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 4479 + ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops); 4480 + 4481 + port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4482 + 4483 + /* Register only for native ports */ 4484 + err = mlx5_add_netdev_notifier(dev, port_num); 4485 + if (err || dev->is_rep || !mlx5_is_roce_enabled(mdev)) 4486 + /* 4487 + * We don't enable ETH interface for 4488 + * 1. IB representors 4489 + * 2. User disabled ROCE through devlink interface 4490 + */ 4335 4491 return err; 4336 4492 4337 4493 err = mlx5_enable_eth(dev); ··· 4312 4526 4313 4527 return 0; 4314 4528 cleanup: 4315 - mlx5_ib_stage_common_roce_cleanup(dev); 4316 - 4529 + mlx5_remove_netdev_notifier(dev, port_num); 4317 4530 return err; 4318 4531 } 4319 4532 4320 - static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev) 4533 + static void mlx5_ib_roce_cleanup(struct mlx5_ib_dev *dev) 4321 4534 { 4322 4535 struct mlx5_core_dev *mdev = dev->mdev; 4323 4536 enum rdma_link_layer ll; 4324 4537 int port_type_cap; 4538 + u8 port_num; 4325 4539 4326 4540 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4327 4541 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4328 4542 4329 4543 if (ll == IB_LINK_LAYER_ETHERNET) { 4330 - mlx5_disable_eth(dev); 4331 - mlx5_ib_stage_common_roce_cleanup(dev); 4544 + if (!dev->is_rep) 4545 + mlx5_disable_eth(dev); 4546 + 4547 + port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4548 + mlx5_remove_netdev_notifier(dev, port_num); 4332 4549 } 4333 - } 4334 - 4335 - static int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev) 4336 - { 4337 - return create_dev_resources(&dev->devr); 4338 - } 4339 - 4340 - static void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev) 4341 - { 4342 - destroy_dev_resources(&dev->devr); 4343 - } 4344 - 4345 - static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev) 4346 - { 4347 - return mlx5_ib_odp_init_one(dev); 4348 - } 4349 - 4350 - static void mlx5_ib_stage_odp_cleanup(struct mlx5_ib_dev *dev) 4351 - { 4352 - mlx5_ib_odp_cleanup_one(dev); 4353 4550 } 4354 4551 4355 4552 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev) ··· 4394 4625 4395 4626 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev) 4396 4627 { 4397 - destroy_umrc_res(dev); 4628 + int err; 4629 + 4630 + err = mlx5_mr_cache_cleanup(dev); 4631 + if (err) 4632 + mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 4633 + 4634 + if (dev->umrc.qp) 4635 + mlx5_ib_destroy_qp(dev->umrc.qp, NULL); 4636 + if (dev->umrc.cq) 4637 + ib_free_cq(dev->umrc.cq); 4638 + if (dev->umrc.pd) 4639 + ib_dealloc_pd(dev->umrc.pd); 4398 4640 } 4399 4641 4400 4642 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev) ··· 4413 4633 ib_unregister_device(&dev->ib_dev); 4414 4634 } 4415 4635 4636 + enum { 4637 + MAX_UMR_WR = 128, 4638 + }; 4639 + 4416 4640 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev) 4417 4641 { 4418 - return create_umr_res(dev); 4642 + struct ib_qp_init_attr *init_attr = NULL; 4643 + struct ib_qp_attr *attr = NULL; 4644 + struct ib_pd *pd; 4645 + struct ib_cq *cq; 4646 + struct ib_qp *qp; 4647 + int ret; 4648 + 4649 + attr = kzalloc(sizeof(*attr), GFP_KERNEL); 4650 + init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 4651 + if (!attr || !init_attr) { 4652 + ret = -ENOMEM; 4653 + goto error_0; 4654 + } 4655 + 4656 + pd = ib_alloc_pd(&dev->ib_dev, 0); 4657 + if (IS_ERR(pd)) { 4658 + mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 4659 + ret = PTR_ERR(pd); 4660 + goto error_0; 4661 + } 4662 + 4663 + cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 4664 + if (IS_ERR(cq)) { 4665 + mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 4666 + ret = PTR_ERR(cq); 4667 + goto error_2; 4668 + } 4669 + 4670 + init_attr->send_cq = cq; 4671 + init_attr->recv_cq = cq; 4672 + init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 4673 + init_attr->cap.max_send_wr = MAX_UMR_WR; 4674 + init_attr->cap.max_send_sge = 1; 4675 + init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 4676 + init_attr->port_num = 1; 4677 + qp = mlx5_ib_create_qp(pd, init_attr, NULL); 4678 + if (IS_ERR(qp)) { 4679 + mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 4680 + ret = PTR_ERR(qp); 4681 + goto error_3; 4682 + } 4683 + qp->device = &dev->ib_dev; 4684 + qp->real_qp = qp; 4685 + qp->uobject = NULL; 4686 + qp->qp_type = MLX5_IB_QPT_REG_UMR; 4687 + qp->send_cq = init_attr->send_cq; 4688 + qp->recv_cq = init_attr->recv_cq; 4689 + 4690 + attr->qp_state = IB_QPS_INIT; 4691 + attr->port_num = 1; 4692 + ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 4693 + IB_QP_PORT, NULL); 4694 + if (ret) { 4695 + mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 4696 + goto error_4; 4697 + } 4698 + 4699 + memset(attr, 0, sizeof(*attr)); 4700 + attr->qp_state = IB_QPS_RTR; 4701 + attr->path_mtu = IB_MTU_256; 4702 + 4703 + ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 4704 + if (ret) { 4705 + mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 4706 + goto error_4; 4707 + } 4708 + 4709 + memset(attr, 0, sizeof(*attr)); 4710 + attr->qp_state = IB_QPS_RTS; 4711 + ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 4712 + if (ret) { 4713 + mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 4714 + goto error_4; 4715 + } 4716 + 4717 + dev->umrc.qp = qp; 4718 + dev->umrc.cq = cq; 4719 + dev->umrc.pd = pd; 4720 + 4721 + sema_init(&dev->umrc.sem, MAX_UMR_WR); 4722 + ret = mlx5_mr_cache_init(dev); 4723 + if (ret) { 4724 + mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 4725 + goto error_4; 4726 + } 4727 + 4728 + kfree(attr); 4729 + kfree(init_attr); 4730 + 4731 + return 0; 4732 + 4733 + error_4: 4734 + mlx5_ib_destroy_qp(qp, NULL); 4735 + dev->umrc.qp = NULL; 4736 + 4737 + error_3: 4738 + ib_free_cq(cq); 4739 + dev->umrc.cq = NULL; 4740 + 4741 + error_2: 4742 + ib_dealloc_pd(pd); 4743 + dev->umrc.pd = NULL; 4744 + 4745 + error_0: 4746 + kfree(attr); 4747 + kfree(init_attr); 4748 + return ret; 4419 4749 } 4420 4750 4421 4751 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev) 4422 4752 { 4423 - init_delay_drop(dev); 4753 + struct dentry *root; 4424 4754 4755 + if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4756 + return 0; 4757 + 4758 + mutex_init(&dev->delay_drop.lock); 4759 + dev->delay_drop.dev = dev; 4760 + dev->delay_drop.activate = false; 4761 + dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 4762 + INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 4763 + atomic_set(&dev->delay_drop.rqs_cnt, 0); 4764 + atomic_set(&dev->delay_drop.events_cnt, 0); 4765 + 4766 + if (!mlx5_debugfs_root) 4767 + return 0; 4768 + 4769 + root = debugfs_create_dir("delay_drop", dev->mdev->priv.dbg_root); 4770 + dev->delay_drop.dir_debugfs = root; 4771 + 4772 + debugfs_create_atomic_t("num_timeout_events", 0400, root, 4773 + &dev->delay_drop.events_cnt); 4774 + debugfs_create_atomic_t("num_rqs", 0400, root, 4775 + &dev->delay_drop.rqs_cnt); 4776 + debugfs_create_file("timeout", 0600, root, &dev->delay_drop, 4777 + &fops_delay_drop_timeout); 4425 4778 return 0; 4426 4779 } 4427 4780 4428 4781 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev) 4429 4782 { 4430 - cancel_delay_drop(dev); 4783 + if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4784 + return; 4785 + 4786 + cancel_work_sync(&dev->delay_drop.delay_drop_work); 4787 + if (!dev->delay_drop.dir_debugfs) 4788 + return; 4789 + 4790 + debugfs_remove_recursive(dev->delay_drop.dir_debugfs); 4791 + dev->delay_drop.dir_debugfs = NULL; 4431 4792 } 4432 4793 4433 4794 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev) ··· 4640 4719 mlx5_ib_stage_non_default_cb, 4641 4720 NULL), 4642 4721 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4643 - mlx5_ib_stage_roce_init, 4644 - mlx5_ib_stage_roce_cleanup), 4722 + mlx5_ib_roce_init, 4723 + mlx5_ib_roce_cleanup), 4645 4724 STAGE_CREATE(MLX5_IB_STAGE_QP, 4646 4725 mlx5_init_qp_table, 4647 4726 mlx5_cleanup_qp_table), ··· 4649 4728 mlx5_init_srq_table, 4650 4729 mlx5_cleanup_srq_table), 4651 4730 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4652 - mlx5_ib_stage_dev_res_init, 4653 - mlx5_ib_stage_dev_res_cleanup), 4731 + mlx5_ib_dev_res_init, 4732 + mlx5_ib_dev_res_cleanup), 4654 4733 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4655 4734 mlx5_ib_stage_dev_notifier_init, 4656 4735 mlx5_ib_stage_dev_notifier_cleanup), 4657 4736 STAGE_CREATE(MLX5_IB_STAGE_ODP, 4658 - mlx5_ib_stage_odp_init, 4659 - mlx5_ib_stage_odp_cleanup), 4737 + mlx5_ib_odp_init_one, 4738 + mlx5_ib_odp_cleanup_one), 4660 4739 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4661 4740 mlx5_ib_counters_init, 4662 4741 mlx5_ib_counters_cleanup), ··· 4703 4782 mlx5_ib_stage_raw_eth_non_default_cb, 4704 4783 NULL), 4705 4784 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4706 - mlx5_ib_stage_raw_eth_roce_init, 4707 - mlx5_ib_stage_raw_eth_roce_cleanup), 4785 + mlx5_ib_roce_init, 4786 + mlx5_ib_roce_cleanup), 4708 4787 STAGE_CREATE(MLX5_IB_STAGE_QP, 4709 4788 mlx5_init_qp_table, 4710 4789 mlx5_cleanup_qp_table), ··· 4712 4791 mlx5_init_srq_table, 4713 4792 mlx5_cleanup_srq_table), 4714 4793 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4715 - mlx5_ib_stage_dev_res_init, 4716 - mlx5_ib_stage_dev_res_cleanup), 4794 + mlx5_ib_dev_res_init, 4795 + mlx5_ib_dev_res_cleanup), 4717 4796 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4718 4797 mlx5_ib_stage_dev_notifier_init, 4719 4798 mlx5_ib_stage_dev_notifier_cleanup),