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dt-bindings: clock: qcom: Add SM8450 video clock controller
Add device tree bindings for the video clock controller on Qualcomm
SM8450 platform.
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230524140656.7076-2-quic_tdas@quicinc.com
authored by
Taniya Das
and committed by
Bjorn Andersson
1e910b2b
ac9a7868
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Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
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Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sm8450-videocc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Video Clock & Reset Controller on SM8450
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maintainers:
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- Taniya Das <quic_tdas@quicinc.com>
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description: |
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Qualcomm video clock control module provides the clocks, resets and power
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domains on SM8450.
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See also:: include/dt-bindings/clock/qcom,videocc-sm8450.h
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properties:
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compatible:
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const: qcom,sm8450-videocc
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reg:
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maxItems: 1
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clocks:
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items:
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- description: Board XO source
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- description: Video AHB clock from GCC
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power-domains:
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maxItems: 1
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description:
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MMCX power domain.
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required-opps:
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maxItems: 1
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description:
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A phandle to an OPP node describing required MMCX performance point.
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- power-domains
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- required-opps
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sm8450.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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videocc: clock-controller@aaf0000 {
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compatible = "qcom,sm8450-videocc";
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reg = <0x0aaf0000 0x10000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_VIDEO_AHB_CLK>;
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power-domains = <&rpmhpd SM8450_MMCX>;
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required-opps = <&rpmhpd_opp_low_svs>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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include/dt-bindings/clock/qcom,sm8450-videocc.h
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include/dt-bindings/clock/qcom,sm8450-videocc.h
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8450_H
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#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8450_H
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/* VIDEO_CC clocks */
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#define VIDEO_CC_MVS0_CLK 0
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#define VIDEO_CC_MVS0_CLK_SRC 1
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#define VIDEO_CC_MVS0_DIV_CLK_SRC 2
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#define VIDEO_CC_MVS0C_CLK 3
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#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 4
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#define VIDEO_CC_MVS1_CLK 5
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#define VIDEO_CC_MVS1_CLK_SRC 6
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#define VIDEO_CC_MVS1_DIV_CLK_SRC 7
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#define VIDEO_CC_MVS1C_CLK 8
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#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 9
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#define VIDEO_CC_PLL0 10
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#define VIDEO_CC_PLL1 11
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/* VIDEO_CC power domains */
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#define VIDEO_CC_MVS0C_GDSC 0
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#define VIDEO_CC_MVS0_GDSC 1
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#define VIDEO_CC_MVS1C_GDSC 2
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#define VIDEO_CC_MVS1_GDSC 3
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/* VIDEO_CC resets */
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#define CVP_VIDEO_CC_INTERFACE_BCR 0
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#define CVP_VIDEO_CC_MVS0_BCR 1
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#define CVP_VIDEO_CC_MVS0C_BCR 2
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#define CVP_VIDEO_CC_MVS1_BCR 3
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#define CVP_VIDEO_CC_MVS1C_BCR 4
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#define VIDEO_CC_MVS0C_CLK_ARES 5
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#define VIDEO_CC_MVS1C_CLK_ARES 6
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#endif