Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
dmaengine: fsl-edma: configure tcd attr with separate src and dst settings
Set the edma tcd transfer attribution settings for the src and dst based
on their respective dma_addr values, to remove the previous 32-byte
alignment limitation in the EDMA memcpy function.
Signed-off-by: Han Xu <han.xu@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20251119163255.502070-1-han.xu@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Han Xu
and committed by
Vinod Koul
1ecd8b60
cd3ba117
+33
-12
+33
-12
drivers/dma/fsl-edma-common.c
+33
-12
drivers/dma/fsl-edma-common.c
···
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mux_configure8(fsl_chan, muxaddr, ch_off, slot, enable);
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}
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-
static unsigned int fsl_edma_get_tcd_attr(enum dma_slave_buswidth addr_width)
209
+
static unsigned int fsl_edma_get_tcd_attr(enum dma_slave_buswidth src_addr_width,
210
+
enum dma_slave_buswidth dst_addr_width)
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{
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-
u32 val;
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+
u32 src_val, dst_val;
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-
if (addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
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-
addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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+
if (src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
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+
src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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+
if (dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
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+
dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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-
val = ffs(addr_width) - 1;
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-
return val | (val << 8);
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+
src_val = ffs(src_addr_width) - 1;
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+
dst_val = ffs(dst_addr_width) - 1;
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+
return dst_val | (src_val << 8);
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}
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void fsl_edma_free_desc(struct virt_dma_desc *vdesc)
···
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dma_buf_next = dma_addr;
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if (direction == DMA_MEM_TO_DEV) {
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+
if (!fsl_chan->cfg.src_addr_width)
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+
fsl_chan->cfg.src_addr_width = fsl_chan->cfg.dst_addr_width;
619
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fsl_chan->attr =
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-
fsl_edma_get_tcd_attr(fsl_chan->cfg.dst_addr_width);
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+
fsl_edma_get_tcd_attr(fsl_chan->cfg.src_addr_width,
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+
fsl_chan->cfg.dst_addr_width);
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nbytes = fsl_chan->cfg.dst_addr_width *
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fsl_chan->cfg.dst_maxburst;
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} else {
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+
if (!fsl_chan->cfg.dst_addr_width)
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+
fsl_chan->cfg.dst_addr_width = fsl_chan->cfg.src_addr_width;
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fsl_chan->attr =
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-
fsl_edma_get_tcd_attr(fsl_chan->cfg.src_addr_width);
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+
fsl_edma_get_tcd_attr(fsl_chan->cfg.src_addr_width,
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+
fsl_chan->cfg.dst_addr_width);
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nbytes = fsl_chan->cfg.src_addr_width *
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fsl_chan->cfg.src_maxburst;
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}
···
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fsl_desc->dirn = direction;
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if (direction == DMA_MEM_TO_DEV) {
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+
if (!fsl_chan->cfg.src_addr_width)
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+
fsl_chan->cfg.src_addr_width = fsl_chan->cfg.dst_addr_width;
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fsl_chan->attr =
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-
fsl_edma_get_tcd_attr(fsl_chan->cfg.dst_addr_width);
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+
fsl_edma_get_tcd_attr(fsl_chan->cfg.src_addr_width,
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+
fsl_chan->cfg.dst_addr_width);
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nbytes = fsl_chan->cfg.dst_addr_width *
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fsl_chan->cfg.dst_maxburst;
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} else {
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+
if (!fsl_chan->cfg.dst_addr_width)
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+
fsl_chan->cfg.dst_addr_width = fsl_chan->cfg.src_addr_width;
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fsl_chan->attr =
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-
fsl_edma_get_tcd_attr(fsl_chan->cfg.src_addr_width);
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+
fsl_edma_get_tcd_attr(fsl_chan->cfg.src_addr_width,
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+
fsl_chan->cfg.dst_addr_width);
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nbytes = fsl_chan->cfg.src_addr_width *
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fsl_chan->cfg.src_maxburst;
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}
···
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{
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struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
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struct fsl_edma_desc *fsl_desc;
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+
u32 src_bus_width, dst_bus_width;
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+
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+
src_bus_width = min_t(u32, DMA_SLAVE_BUSWIDTH_32_BYTES, 1 << (ffs(dma_src) - 1));
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+
dst_bus_width = min_t(u32, DMA_SLAVE_BUSWIDTH_32_BYTES, 1 << (ffs(dma_dst) - 1));
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786
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fsl_desc = fsl_edma_alloc_desc(fsl_chan, 1);
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if (!fsl_desc)
···
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/* To match with copy_align and max_seg_size so 1 tcd is enough */
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fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[0].vtcd, dma_src, dma_dst,
801
-
fsl_edma_get_tcd_attr(DMA_SLAVE_BUSWIDTH_32_BYTES),
802
-
32, len, 0, 1, 1, 32, 0, true, true, false);
781
+
fsl_edma_get_tcd_attr(src_bus_width, dst_bus_width),
782
+
src_bus_width, len, 0, 1, 1, dst_bus_width, 0, true,
783
+
true, false);
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return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags);
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}