+1 -3

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

reviewed

··· 753 753 754 754 void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev, bool reset) 755 755 { 756 756 - struct ras_err_data err_data = {0, 0, 0, NULL}; 757 757 - 758 758 - amdgpu_umc_poison_handler(adev, &err_data, reset); 756 756 + amdgpu_umc_poison_handler(adev, reset); 759 757 } 760 758 761 759 bool amdgpu_amdkfd_ras_query_utcl2_poison_status(struct amdgpu_device *adev)

+1 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

reviewed

··· 1561 1561 { 1562 1562 bool poison_stat = false; 1563 1563 struct amdgpu_device *adev = obj->adev; 1564 1564 - struct ras_err_data err_data = {0, 0, 0, NULL}; 1565 1564 struct amdgpu_ras_block_object *block_obj = 1566 1565 amdgpu_ras_get_ras_block(adev, obj->head.block, 0); 1567 1566 ··· 1583 1584 } 1584 1585 1585 1586 if (!adev->gmc.xgmi.connected_to_cpu) 1586 1586 - amdgpu_umc_poison_handler(adev, &err_data, false); 1587 1587 + amdgpu_umc_poison_handler(adev, false); 1587 1588 1588 1589 if (block_obj->hw_ops->handle_poison_consumption) 1589 1590 poison_stat = block_obj->hw_ops->handle_poison_consumption(adev);

+5 -8

drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c

reviewed

··· 165 165 return AMDGPU_RAS_SUCCESS; 166 166 } 167 167 168 168 - int amdgpu_umc_poison_handler(struct amdgpu_device *adev, 169 169 - void *ras_error_status, 170 170 - bool reset) 168 168 + int amdgpu_umc_poison_handler(struct amdgpu_device *adev, bool reset) 171 169 { 172 170 int ret = AMDGPU_RAS_SUCCESS; 173 171 174 172 if (!adev->gmc.xgmi.connected_to_cpu) { 175 175 - struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 173 173 + struct ras_err_data err_data = {0, 0, 0, NULL}; 176 174 struct ras_common_if head = { 177 175 .block = AMDGPU_RAS_BLOCK__UMC, 178 176 }; 179 177 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head); 180 178 181 181 - ret = 182 182 - amdgpu_umc_do_page_retirement(adev, ras_error_status, NULL, reset); 179 179 + ret = amdgpu_umc_do_page_retirement(adev, &err_data, NULL, reset); 183 180 184 181 if (ret == AMDGPU_RAS_SUCCESS && obj) { 185 185 - obj->err_data.ue_count += err_data->ue_count; 186 186 - obj->err_data.ce_count += err_data->ce_count; 182 182 + obj->err_data.ue_count += err_data.ue_count; 183 183 + obj->err_data.ce_count += err_data.ce_count; 187 184 } 188 185 } else if (reset) { 189 186 /* MCA poison handler is only responsible for GPU reset,

+1 -3

drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h

reviewed

··· 83 83 }; 84 84 85 85 int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block); 86 86 - int amdgpu_umc_poison_handler(struct amdgpu_device *adev, 87 87 - void *ras_error_status, 88 88 - bool reset); 86 86 + int amdgpu_umc_poison_handler(struct amdgpu_device *adev, bool reset); 89 87 int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev, 90 88 struct amdgpu_irq_src *source, 91 89 struct amdgpu_iv_entry *entry);