+1

drivers/gpu/drm/msm/Makefile

reviewed

··· 201 201 generated/a6xx_perfcntrs.xml.h \ 202 202 generated/a7xx_enums.xml.h \ 203 203 generated/a7xx_perfcntrs.xml.h \ 204 204 + generated/a8xx_enums.xml.h \ 204 205 generated/a6xx_gmu.xml.h \ 205 206 generated/adreno_common.xml.h \ 206 207 generated/adreno_pm4.xml.h \

+8 -8

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

reviewed

··· 238 238 OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BOTH); 239 239 240 240 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 241 241 - OUT_RING(ring, LRZ_FLUSH); 241 241 + OUT_RING(ring, LRZ_FLUSH_INVALIDATE); 242 242 243 243 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); 244 244 OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BR); ··· 381 381 rbmemptr_stats(ring, index, alwayson_end)); 382 382 383 383 /* Write the fence to the scratch register */ 384 384 - OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1); 384 384 + OUT_PKT4(ring, REG_A6XX_CP_SCRATCH(2), 1); 385 385 OUT_RING(ring, submit->seqno); 386 386 387 387 /* ··· 522 522 rbmemptr_stats(ring, index, alwayson_end)); 523 523 524 524 /* Write the fence to the scratch register */ 525 525 - OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1); 525 525 + OUT_PKT4(ring, REG_A6XX_CP_SCRATCH(2), 1); 526 526 OUT_RING(ring, submit->seqno); 527 527 528 528 OUT_PKT7(ring, CP_THREAD_CONTROL, 1); ··· 1305 1305 } 1306 1306 1307 1307 if (adreno_is_a660_family(adreno_gpu)) 1308 1308 - gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020); 1308 1308 + gpu_write(gpu, REG_A7XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020); 1309 1309 1310 1310 /* Setting the mem pool size */ 1311 1311 if (adreno_is_a610(adreno_gpu) || adreno_is_a612(adreno_gpu)) { ··· 1754 1754 const char *block = "unknown"; 1755 1755 1756 1756 u32 scratch[] = { 1757 1757 - gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)), 1758 1758 - gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)), 1759 1759 - gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)), 1760 1760 - gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)), 1757 1757 + gpu_read(gpu, REG_A6XX_CP_SCRATCH(4)), 1758 1758 + gpu_read(gpu, REG_A6XX_CP_SCRATCH(5)), 1759 1759 + gpu_read(gpu, REG_A6XX_CP_SCRATCH(6)), 1760 1760 + gpu_read(gpu, REG_A6XX_CP_SCRATCH(7)), 1761 1761 }; 1762 1762 1763 1763 if (info)

+4 -4

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h

reviewed

··· 71 71 u32 sel_val; 72 72 } a6xx_clusters[] = { 73 73 CLUSTER(CLUSTER_GRAS, a6xx_gras_cluster, 0, 0), 74 74 - CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rac, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0x0), 75 75 - CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rbp, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0x9), 74 74 + CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rac, REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 0x0), 75 75 + CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rbp, REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 0x9), 76 76 CLUSTER(CLUSTER_PS, a6xx_ps_cluster, 0, 0), 77 77 CLUSTER(CLUSTER_FE, a6xx_fe_cluster, 0, 0), 78 78 CLUSTER(CLUSTER_PC_VS, a6xx_pc_vs_cluster, 0, 0), ··· 303 303 static const struct a6xx_registers a6xx_reglist[] = { 304 304 REGS(a6xx_registers, 0, 0), 305 305 REGS(a660_registers, 0, 0), 306 306 - REGS(a6xx_rb_rac_registers, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0), 307 307 - REGS(a6xx_rb_rbp_registers, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 9), 306 306 + REGS(a6xx_rb_rac_registers, REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 0), 307 307 + REGS(a6xx_rb_rbp_registers, REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 9), 308 308 }; 309 309 310 310 static const u32 a6xx_ahb_registers[] = {

+4 -4

drivers/gpu/drm/msm/adreno/adreno_gen7_0_0_snapshot.h

reviewed

··· 691 691 static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_noncontext_pipe_lpac_registers), 8)); 692 692 693 693 static const struct gen7_sel_reg gen7_0_0_rb_rac_sel = { 694 694 - .host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST, 695 695 - .cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 694 694 + .host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST, 695 695 + .cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 696 696 .val = 0x0, 697 697 }; 698 698 699 699 static const struct gen7_sel_reg gen7_0_0_rb_rbp_sel = { 700 700 - .host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST, 701 701 - .cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 700 700 + .host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST, 701 701 + .cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 702 702 .val = 0x9, 703 703 }; 704 704

+4 -4

drivers/gpu/drm/msm/adreno/adreno_gen7_2_0_snapshot.h

reviewed

··· 478 478 static_assert(IS_ALIGNED(sizeof(gen7_2_0_sp_noncontext_pipe_lpac_hlsq_state_registers), 8)); 479 479 480 480 static const struct gen7_sel_reg gen7_2_0_rb_rac_sel = { 481 481 - .host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST, 482 482 - .cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 481 481 + .host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST, 482 482 + .cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 483 483 .val = 0x0, 484 484 }; 485 485 486 486 static const struct gen7_sel_reg gen7_2_0_rb_rbp_sel = { 487 487 - .host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST, 488 488 - .cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 487 487 + .host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST, 488 488 + .cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 489 489 .val = 0x9, 490 490 }; 491 491

+4 -4

drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h

reviewed

··· 1105 1105 static_assert(IS_ALIGNED(sizeof(gen7_9_0_tpl1_pipe_lpac_cluster_sp_ps_usptp_registers), 8)); 1106 1106 1107 1107 static const struct gen7_sel_reg gen7_9_0_rb_rac_sel = { 1108 1108 - .host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST, 1109 1109 - .cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 1108 1108 + .host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST, 1109 1109 + .cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 1110 1110 .val = 0, 1111 1111 }; 1112 1112 1113 1113 static const struct gen7_sel_reg gen7_9_0_rb_rbp_sel = { 1114 1114 - .host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST, 1115 1115 - .cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 1114 1114 + .host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST, 1115 1115 + .cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 1116 1116 .val = 0x9, 1117 1117 }; 1118 1118

+1635 -542

drivers/gpu/drm/msm/registers/adreno/a6xx.xml

reviewed

··· 7 7 <import file="adreno/adreno_pm4.xml"/> 8 8 <import file="adreno/a6xx_enums.xml"/> 9 9 <import file="adreno/a7xx_enums.xml"/> 10 10 + <import file="adreno/a8xx_enums.xml"/> 10 11 <import file="adreno/a6xx_perfcntrs.xml"/> 11 12 <import file="adreno/a7xx_perfcntrs.xml"/> 12 13 <import file="adreno/a6xx_descriptors.xml"/> 14 14 + <import file="adreno/a8xx_descriptors.xml"/> 13 15 14 16 <!-- 15 17 Each register that is actually being used by driver should have "usage" defined, ··· 86 84 <bitfield name="CP_ILLEGAL_INSTR_ERROR_BV" pos="17" type="boolean" variants="A7XX-"/> 87 85 </bitset> 88 86 87 87 + <bitset name="A8XX_CP_GLOBAL_INT_MASK" inline="no" varset="chip"> 88 88 + <bitfield name="HWFAULTBR" pos="0" type="boolean"/> 89 89 + <bitfield name="HWFAULTBV" pos="1" type="boolean"/> 90 90 + <bitfield name="HWFAULTLPAC" pos="2" type="boolean"/> 91 91 + <bitfield name="HWFAULTAQE0" pos="3" type="boolean"/> 92 92 + <bitfield name="HWFAULTAQE1" pos="4" type="boolean"/> 93 93 + <bitfield name="HWFAULTDDEBR" pos="5" type="boolean"/> 94 94 + <bitfield name="HWFAULTDDEBV" pos="6" type="boolean"/> 95 95 + <bitfield name="SWFAULTBR" pos="16" type="boolean"/> 96 96 + <bitfield name="SWFAULTBV" pos="17" type="boolean"/> 97 97 + <bitfield name="SWFAULTLPAC" pos="18" type="boolean"/> 98 98 + <bitfield name="SWFAULTAQE0" pos="19" type="boolean"/> 99 99 + <bitfield name="SWFAULTAQE1" pos="20" type="boolean"/> 100 100 + <bitfield name="SWFAULTDDEBR" pos="21" type="boolean"/> 101 101 + <bitfield name="SWFAULTDDEBV" pos="22" type="boolean"/> 102 102 + </bitset> 103 103 + 104 104 + <bitset name="A8XX_CP_INTERRUPT_STATUS_MASK_PIPE" inline="no" varset="chip"> 105 105 + <bitfield name="CSFRBWRAP" pos="0" type="boolean"/> 106 106 + <bitfield name="CSFIB1WRAP" pos="1" type="boolean"/> 107 107 + <bitfield name="CSFIB2WRAP" pos="2" type="boolean"/> 108 108 + <bitfield name="CSFIB3WRAP" pos="3" type="boolean"/> 109 109 + <bitfield name="CSFSDSWRAP" pos="4" type="boolean"/> 110 110 + <bitfield name="CSFMRBWRAP" pos="5" type="boolean"/> 111 111 + <bitfield name="CSFVSDWRAP" pos="6" type="boolean"/> 112 112 + <bitfield name="OPCODEERROR" pos="8" type="boolean"/> 113 113 + <bitfield name="VSDPARITYERROR" pos="9" type="boolean"/> 114 114 + <bitfield name="REGISTERPROTECTIONERROR" pos="10" type="boolean"/> 115 115 + <bitfield name="ILLEGALINSTRUCTION" pos="11" type="boolean"/> 116 116 + <bitfield name="SMMUFAULT" pos="12" type="boolean"/> 117 117 + <bitfield name="VBIFRESPCLIENT" pos="13" type="boolean"/> 118 118 + <bitfield name="VBIFRESPTYPE" pos="19" type="boolean"/> 119 119 + <bitfield name="VBIFRESPREAD" pos="21" type="boolean"/> 120 120 + <bitfield name="VBIFRESP" pos="22" type="boolean"/> 121 121 + <bitfield name="RTWROVF" pos="23" type="boolean"/> 122 122 + <bitfield name="LRZRTWROVF" pos="24" type="boolean"/> 123 123 + <bitfield name="LRZRTREFCNTOVF" pos="25" type="boolean"/> 124 124 + <bitfield name="LRZRTCLRRESMISS" pos="26" type="boolean"/> 125 125 + </bitset> 126 126 + 127 127 + <bitset name="A8XX_CP_HW_FAULT_STATUS_MASK_PIPE" inline="no" varset="chip"> 128 128 + <bitfield name="CSFRBFAULT" pos="0" type="boolean"/> 129 129 + <bitfield name="CSFIB1FAULT" pos="1" type="boolean"/> 130 130 + <bitfield name="CSFIB2FAULT" pos="2" type="boolean"/> 131 131 + <bitfield name="CSFIB3FAULT" pos="3" type="boolean"/> 132 132 + <bitfield name="CSFSDSFAULT" pos="4" type="boolean"/> 133 133 + <bitfield name="CSFMRBFAULT" pos="5" type="boolean"/> 134 134 + <bitfield name="CSFVSDFAULT" pos="6" type="boolean"/> 135 135 + <bitfield name="SQEREADBURSTOVF" pos="8" type="boolean"/> 136 136 + <bitfield name="EVENTENGINEOVF" pos="9" type="boolean"/> 137 137 + <bitfield name="UCODEERROR" pos="10" type="boolean"/> 138 138 + </bitset> 139 139 + 89 140 <reg64 offset="0x0800" name="CP_RB_BASE"/> 90 141 <reg32 offset="0x0802" name="CP_RB_CNTL"/> 142 142 + <reg32 offset="0x0803" name="CP_RB_RPTR_WR" variants="A7XX-"/> 91 143 <reg64 offset="0x0804" name="CP_RB_RPTR_ADDR"/> 92 144 <reg32 offset="0x0806" name="CP_RB_RPTR"/> 93 145 <reg32 offset="0x0807" name="CP_RB_WPTR"/> 94 94 - <reg32 offset="0x0808" name="CP_SQE_CNTL"/> 95 95 - <reg32 offset="0x0812" name="CP_CP2GMU_STATUS"> 146 146 + <reg32 offset="0x0808" name="CP_RB_RPTR_ADDR_BV" variants="A8XX-"/> 147 147 + <reg32 offset="0x080a" name="CP_RB_RPTR_BV" variants="A8XX-"/> 148 148 + <reg64 offset="0x080b" name="CP_RB_BASE_LPAC" variants="A8XX-"/> 149 149 + <reg32 offset="0x080d" name="CP_RB_CNTL_LPAC" variants="A8XX-"/> 150 150 + <reg32 offset="0x080e" name="CP_RB_RPTR_WR_LPAC" variants="A8XX-"/> 151 151 + <reg64 offset="0x080f" name="CP_RB_RPTR_ADDR_LPAC" variants="A8XX-"/> 152 152 + <reg32 offset="0x0811" name="CP_RB_RPTR_LPAC" variants="A8XX-"/> 153 153 + <reg32 offset="0x0812" name="CP_RB_WPTR_LPAC" variants="A8XX-"/> 154 154 + <reg32 offset="0x0814" name="CP_SMMU_STREAM_ID_LPAC" variants="A8XX-"/> 155 155 + <reg32 offset="0x0808" name="CP_SQE_CNTL" variants="A6XX-A7XX"/> 156 156 + <reg32 offset="0x0815" name="CP_SQE_CNTL" variants="A8XX-"/> 157 157 + <reg64 offset="0x0816" name="CP_SQE_INSTR_BASE" variants="A8XX-"/> 158 158 + <reg64 offset="0x0818" name="CP_AQE_INSTR_BASE_0" variants="A8XX-"/> 159 159 + <reg64 offset="0x081a" name="CP_AQE_INSTR_BASE_1" variants="A8XX-"/> 160 160 + <reg32 offset="0x0812" name="CP_CP2GMU_STATUS" variants="A6XX-A7XX"> 161 161 + <!-- Note, layout defined by microcode --> 96 162 <bitfield name="IFPC" pos="0" type="boolean"/> 97 163 </reg32> 98 98 - <reg32 offset="0x0821" name="CP_HW_FAULT"/> 99 99 - <reg32 offset="0x0823" name="CP_INTERRUPT_STATUS" type="A6XX_CP_INT"/> 100 100 - <reg32 offset="0x0824" name="CP_PROTECT_STATUS"/> 101 101 - <reg32 offset="0x0825" name="CP_STATUS_1"/> 102 102 - <reg64 offset="0x0830" name="CP_SQE_INSTR_BASE"/> 103 103 - <reg32 offset="0x0840" name="CP_MISC_CNTL"/> 104 104 - <reg32 offset="0x0844" name="CP_APRIV_CNTL"> 164 164 + <reg32 offset="0x0822" name="CP_CP2GMU_STATUS" variants="A8XX-"> 165 165 + <bitfield name="IFPC" pos="0" type="boolean"/> 166 166 + </reg32> 167 167 + <reg32 offset="0x0821" name="CP_HW_FAULT" variants="A6XX-A7XX"/> 168 168 + <reg32 offset="0x0823" name="CP_INTERRUPT_STATUS" type="A6XX_CP_INT" variants="A6XX-A7XX"/> 169 169 + 170 170 + <bitset name="a6xx_cp_protect_status" inline="yes"> 171 171 + <bitfield name="ADDR" low="0" high="17"/> 172 172 + <bitfield name="READ" pos="20" type="boolean"/> 173 173 + <bitfield name="CP_HALTED" pos="21" type="boolean"/> 174 174 + <bitfield name="ACCESS_VIOLATION" pos="22" type="boolean"/> 175 175 + </bitset> 176 176 + 177 177 + <reg32 offset="0x0824" name="CP_PROTECT_STATUS" type="a6xx_cp_protect_status" variants="A6XX-A7XX"/> 178 178 + <reg32 offset="0x084f" name="CP_PROTECT_STATUS_PIPE" type="a6xx_cp_protect_status" variants="A8XX-"/> 179 179 + <reg32 offset="0x0825" name="CP_STATUS_1" variants="A6XX-A7XX"/> 180 180 + 181 181 + <reg32 offset="0x0825" name="CP_SEMAPHORE_REG_0" variants="A8XX-"/> 182 182 + <array offset="0x082a" name="CP_SCRATCH_GLOBAL" stride="1" length="4" variants="A8XX-"> 183 183 + <reg32 offset="0x0" name="REG"/> 184 184 + </array> 185 185 + <array offset="0x0830" name="CP_SCRATCH_PIPE" stride="1" length="5" variants="A8XX-"> 186 186 + <reg32 offset="0x0" name="REG"/> 187 187 + </array> 188 188 + 189 189 + <reg32 offset="0x0840" name="CP_RL_ERROR_DETAILS_0" variants="A8XX-"/> 190 190 + <reg32 offset="0x0841" name="CP_RL_ERROR_DETAILS_1" variants="A8XX-"/> 191 191 + 192 192 + <reg64 offset="0x0830" name="CP_SQE_INSTR_BASE" variants="A6XX-A7XX"/> 193 193 + <reg32 offset="0x0840" name="CP_MISC_CNTL" variants="A6XX-A7XX"/> 194 194 + <reg32 offset="0x084c" name="CP_MISC_CNTL" variants="A8XX-"/> 195 195 + 196 196 + <reg32 offset="0x08b0" name="CP_SQE_ICACHE_CNTL_PIPE" variants="A8XX-"/> 197 197 + <reg32 offset="0x08b1" name="CP_SQE_DCACHE_CNTL_PIPE" variants="A8XX-"/> 198 198 + <reg32 offset="0x08b3" name="CP_HW_FAULT_STATUS_PIPE" variants="A8XX-"/> 199 199 + <reg32 offset="0x08b4" name="CP_HW_FAULT_STATUS_MASK_PIPE" variants="A8XX-"/> 200 200 + <reg32 offset="0x08b5" name="CP_INTERRUPT_STATUS_GLOBAL" type="A8XX_CP_GLOBAL_INT_MASK" variants="A8XX-"/> 201 201 + <reg32 offset="0x08b6" name="CP_INTERRUPT_STATUS_MASK_GLOBAL" type="A8XX_CP_GLOBAL_INT_MASK" variants="A8XX-"/> 202 202 + <reg32 offset="0x08b7" name="CP_INTERRUPT_STATUS_PIPE" type="A8XX_CP_INTERRUPT_STATUS_MASK_PIPE" variants="A8XX-"/> 203 203 + <reg32 offset="0x08b8" name="CP_INTERRUPT_STATUS_MASK_PIPE" variants="A8XX-"/> 204 204 + <reg32 offset="0x08b9" name="CP_PIPE_STATUS_PIPE" variants="A8XX-"/> 205 205 + <reg32 offset="0x08ba" name="CP_GPU_BATCH_ID_PIPE" variants="A8XX-"/> 206 206 + <reg32 offset="0x08bb" name="CP_SQE_STATUS_PIPE" variants="A8XX-"/> 207 207 + 208 208 + <bitset name="a6xx_cp_apriv_cntl" inline="yes"> 105 209 <!-- Crashdumper writes --> 106 210 <bitfield pos="6" name="CDWRITE" type="boolean"/> 107 211 <!-- Crashdumper reads --> 108 212 <bitfield pos="5" name="CDREAD" type="boolean"/> 109 109 - 110 110 - <!-- 4 is unknown --> 111 111 - 213 213 + <!-- CP Scratch reg copy to mem --> 214 214 + <bitfield pos="4" name="SCRATCHWT" type="boolean"/> 112 215 <!-- RPTR shadow writes --> 113 216 <bitfield pos="3" name="RBRPWB" type="boolean"/> 114 217 <!-- Memory accesses from PM4 packets in the ringbuffer --> ··· 222 115 <bitfield pos="1" name="RBFETCH" type="boolean"/> 223 116 <!-- Instruction cache fetches --> 224 117 <bitfield pos="0" name="ICACHE" type="boolean"/> 225 225 - </reg32> 118 118 + </bitset> 119 119 + 120 120 + <reg32 offset="0x0844" name="CP_APRIV_CNTL" type="a6xx_cp_apriv_cntl" variants="A6XX-A7XX"/> 121 121 + <reg32 offset="0x084d" name="CP_APRIV_CNTL_PIPE" type="a6xx_cp_apriv_cntl" variants="A8XX-"/> 122 122 + 226 123 <!-- Preemptions taking longer than this threshold increment PERF_CP_LONG_PREEMPTIONS: --> 227 227 - <reg32 offset="0x08C0" name="CP_PREEMPT_THRESHOLD"/> 124 124 + <reg32 offset="0x08c0" name="CP_PREEMPT_THRESHOLD" variants="A6XX-A7XX"/> 125 125 + <reg32 offset="0x08ec" name="CP_PREEMPT_THRESHOLD" variants="A8XX-"/> 228 126 <!-- all the threshold values seem to be in units of quad-dwords: --> 229 229 - <reg32 offset="0x08C1" name="CP_ROQ_THRESHOLDS_1"> 127 127 + <reg32 offset="0x08c1" name="CP_ROQ_THRESHOLDS_1" variants="A6XX"> 230 128 <doc> 231 129 b0..7 identifies where MRB data starts (and RB data ends) 232 130 b8.15 identifies where VSD data starts (and MRB data ends) ··· 243 131 <bitfield name="IB1_START" low="16" high="23" shr="2"/> 244 132 <bitfield name="IB2_START" low="24" high="31" shr="2"/> 245 133 </reg32> 246 246 - <reg32 offset="0x08C2" name="CP_ROQ_THRESHOLDS_2"> 134 134 + <reg32 offset="0x08c2" name="CP_ROQ_THRESHOLDS_2" variants="A6XX"> 247 135 <doc> 248 136 low bits identify where CP_SET_DRAW_STATE stateobj 249 137 processing starts (and IB2 data ends). I'm guessing ··· 259 147 <!-- total ROQ size: --> 260 148 <bitfield name="ROQ_SIZE" low="16" high="31" shr="2"/> 261 149 </reg32> 262 262 - <reg32 offset="0x08C3" name="CP_MEM_POOL_SIZE"/> 263 263 - <reg32 offset="0x0841" name="CP_CHICKEN_DBG"/> 264 264 - <reg32 offset="0x0842" name="CP_ADDR_MODE_CNTL" type="a5xx_address_mode"/> 265 265 - <reg32 offset="0x0843" name="CP_DBG_ECO_CNTL"/> 266 266 - <reg32 offset="0x084F" name="CP_PROTECT_CNTL"> 150 150 + <reg32 offset="0x08C3" name="CP_MEM_POOL_SIZE" variants="A6XX"/> 151 151 + <reg32 offset="0x0841" name="CP_CHICKEN_DBG" variants="A6XX-A7XX"/> 152 152 + <reg32 offset="0x08b2" name="CP_CHICKEN_DBG_PIPE" variants="A8XX-"/> 153 153 + <reg32 offset="0x0842" name="CP_ADDR_MODE_CNTL" type="a5xx_address_mode" variants="A6XX"/> 154 154 + <reg32 offset="0x0843" name="CP_DBG_ECO_CNTL" variants="A6XX-A7XX"/> 155 155 + <reg32 offset="0x084b" name="CP_DBG_ECO_CNTL" variants="A8XX-"/> 156 156 + 157 157 + <bitset name="a6xx_cp_protect_cntl" inline="yes"> 267 158 <bitfield pos="3" name="LAST_SPAN_INF_RANGE" type="boolean"/> 268 159 <bitfield pos="1" name="ACCESS_FAULT_ON_VIOL_EN" type="boolean"/> 269 160 <bitfield pos="0" name="ACCESS_PROT_EN" type="boolean"/> 270 270 - </reg32> 161 161 + </bitset> 271 162 272 272 - <array offset="0x0883" name="CP_SCRATCH" stride="1" length="8"> 163 163 + <reg32 offset="0x084f" name="CP_PROTECT_CNTL" type="a6xx_cp_protect_cntl" variants="A6XX-A7XX"/> 164 164 + <bitset name="a8xx_cp_protect_cntl" inline="yes"> 165 165 + <bitfield name="HALT_SQE_RANGE" low="16" high="31"/> 166 166 + <bitfield name="LAST_SPAN_INF_RANGE" pos="3" type="boolean"/> 167 167 + <bitfield name="ACCESS_FAULT_ON_VIOL_EN" pos="1" type="boolean"/> 168 168 + <bitfield name="ACCESS_PROT_EN" pos="0" type="boolean"/> 169 169 + </bitset> 170 170 + 171 171 + <reg32 offset="0x084e" name="CP_PROTECT_CNTL_PIPE" type="a8xx_cp_protect_cntl" variants="A8XX-"/> 172 172 + 173 173 + <array offset="0x0883" name="CP_SCRATCH" stride="1" length="8" variants="A6XX-A7XX"> 273 174 <reg32 offset="0x0" name="REG" type="uint"/> 274 175 </array> 275 275 - <array offset="0x0850" name="CP_PROTECT" stride="1" length="32"> 176 176 + <array offset="0x0850" name="CP_PROTECT" stride="1" length="32" variants="A6XX-A7XX"> 177 177 + <reg32 offset="0x0" name="REG" type="a6x_cp_protect"/> 178 178 + </array> 179 179 + <array offset="0x0850" name="CP_PROTECT_GLOBAL" stride="1" length="64" variants="A8XX-"> 180 180 + <reg32 offset="0x0" name="REG" type="a6x_cp_protect"/> 181 181 + </array> 182 182 + <array offset="0x08a0" name="CP_PROTECT_PIPE" stride="1" length="16" variants="A8XX-"> 276 183 <reg32 offset="0x0" name="REG" type="a6x_cp_protect"/> 277 184 </array> 278 185 279 279 - <reg32 offset="0x08A0" name="CP_CONTEXT_SWITCH_CNTL"> 186 186 + <bitset name="a6xx_cp_context_switch_cntl" inline="yes"> 280 187 <bitfield name="STOP" pos="0" type="boolean"/> 281 188 <bitfield name="LEVEL" low="6" high="7"/> 282 189 <bitfield name="USES_GMEM" pos="8" type="boolean"/> 283 190 <bitfield name="SKIP_SAVE_RESTORE" pos="9" type="boolean"/> 284 284 - </reg32> 285 285 - <reg64 offset="0x08A1" name="CP_CONTEXT_SWITCH_SMMU_INFO"/> 286 286 - <reg64 offset="0x08A3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR"/> 287 287 - <reg64 offset="0x08A5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR"/> 288 288 - <reg64 offset="0x08A7" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR"/> 289 289 - <reg32 offset="0x08ab" name="CP_CONTEXT_SWITCH_LEVEL_STATUS" variants="A7XX-"/> 290 290 - <array offset="0x08D0" name="CP_PERFCTR_CP_SEL" stride="1" length="14"/> 291 291 - <array offset="0x08e0" name="CP_BV_PERFCTR_CP_SEL" stride="1" length="7" variants="A7XX-"/> 292 292 - <reg64 offset="0x0900" name="CP_CRASH_DUMP_SCRIPT_BASE"/> 293 293 - <reg32 offset="0x0902" name="CP_CRASH_DUMP_CNTL"/> 294 294 - <reg32 offset="0x0903" name="CP_CRASH_DUMP_STATUS"/> 295 295 - <reg32 offset="0x0908" name="CP_SQE_STAT_ADDR"/> 296 296 - <reg32 offset="0x0909" name="CP_SQE_STAT_DATA"/> 297 297 - <reg32 offset="0x090A" name="CP_DRAW_STATE_ADDR"/> 298 298 - <reg32 offset="0x090B" name="CP_DRAW_STATE_DATA"/> 299 299 - <reg32 offset="0x090C" name="CP_ROQ_DBG_ADDR"/> 300 300 - <reg32 offset="0x090D" name="CP_ROQ_DBG_DATA"/> 301 301 - <reg32 offset="0x090E" name="CP_MEM_POOL_DBG_ADDR"/> 302 302 - <reg32 offset="0x090F" name="CP_MEM_POOL_DBG_DATA"/> 303 303 - <reg32 offset="0x0910" name="CP_SQE_UCODE_DBG_ADDR"/> 304 304 - <reg32 offset="0x0911" name="CP_SQE_UCODE_DBG_DATA"/> 305 305 - <reg64 offset="0x0928" name="CP_IB1_BASE"/> 306 306 - <reg32 offset="0x092A" name="CP_IB1_REM_SIZE"/> 307 307 - <reg64 offset="0x092B" name="CP_IB2_BASE"/> 308 308 - <reg32 offset="0x092D" name="CP_IB2_REM_SIZE"/> 191 191 + </bitset> 192 192 + 193 193 + <reg32 offset="0x08a0" name="CP_CONTEXT_SWITCH_CNTL" type="a6xx_cp_context_switch_cntl" variants="A6XX-A7XX"/> 194 194 + <reg32 offset="0x08c0" name="CP_CONTEXT_SWITCH_CNTL" type="a6xx_cp_context_switch_cntl" variants="A8XX-"/> 195 195 + 196 196 + <reg64 offset="0x08a1" name="CP_CONTEXT_SWITCH_SMMU_INFO" variants="A6XX-A7XX"/> 197 197 + <reg64 offset="0x08a3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR" variants="A6XX-A7XX"/> 198 198 + <reg64 offset="0x08a5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR" variants="A6XX-A7XX"/> 199 199 + <reg64 offset="0x08a7" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR" variants="A6XX-A7XX"/> 200 200 + <reg32 offset="0x08ab" name="CP_CONTEXT_SWITCH_LEVEL_STATUS" variants="A7XX"/> 201 201 + 202 202 + <reg64 offset="0x08c1" name="CP_CONTEXT_SWITCH_SMMU_INFO" variants="A8XX-"/> 203 203 + <reg64 offset="0x08c3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR" variants="A8XX-"/> 204 204 + <reg64 offset="0x08c5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR" variants="A8XX-"/> 205 205 + <reg64 offset="0x08c7" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR" variants="A8XX-"/> 206 206 + <reg32 offset="0x08cb" name="CP_CONTEXT_SWITCH_LEVEL_STATUS" variants="A8XX-"/> 207 207 + 208 208 + <array offset="0x08d0" name="CP_PERFCTR_CP_SEL" stride="1" length="14" variants="A6XX-A7XX"/> 209 209 + <array offset="0x08d0" name="CP_PERFCTR_CP_SEL" stride="1" length="21" variants="A8XX-"/> 210 210 + <array offset="0x08e0" name="CP_BV_PERFCTR_CP_SEL" stride="1" length="7" variants="A7XX"/> 211 211 + <reg64 offset="0x0900" name="CP_CRASH_DUMP_SCRIPT_BASE" variants="A6XX-A7XX"/> 212 212 + <reg32 offset="0x0902" name="CP_CRASH_DUMP_CNTL" variants="A6XX-A7XX"/> 213 213 + <reg32 offset="0x0903" name="CP_CRASH_DUMP_STATUS" variants="A6XX-A7XX"/> 214 214 + <reg64 offset="0x0842" name="CP_CRASH_DUMP_SCRIPT_BASE" variants="A8XX-"/> 215 215 + <reg32 offset="0x0844" name="CP_CRASH_DUMP_CNTL" variants="A8XX-"/> 216 216 + <reg32 offset="0x0845" name="CP_CRASH_DUMP_STATUS" variants="A8XX-"/> 217 217 + <reg32 offset="0x0908" name="CP_SQE_STAT_ADDR" variants="A6XX-A7XX"/> 218 218 + <reg32 offset="0x0909" name="CP_SQE_STAT_DATA" variants="A6XX-A7XX"/> 219 219 + <reg32 offset="0x090a" name="CP_DRAW_STATE_ADDR" variants="A6XX-A7XX"/> 220 220 + <reg32 offset="0x090b" name="CP_DRAW_STATE_DATA" variants="A6XX-A7XX"/> 221 221 + <reg32 offset="0x090c" name="CP_ROQ_DBG_ADDR" variants="A6XX-A7XX"/> 222 222 + <reg32 offset="0x090d" name="CP_ROQ_DBG_DATA" variants="A6XX-A7XX"/> 223 223 + <reg32 offset="0x090e" name="CP_MEM_POOL_DBG_ADDR" variants="A6XX-A7XX"/> 224 224 + <reg32 offset="0x090f" name="CP_MEM_POOL_DBG_DATA" variants="A6XX-A7XX"/> 225 225 + <reg32 offset="0x0910" name="CP_SQE_UCODE_DBG_ADDR" variants="A6XX-A7XX"/> 226 226 + <reg32 offset="0x0911" name="CP_SQE_UCODE_DBG_DATA" variants="A6XX-A7XX"/> 227 227 + 228 228 + <reg32 offset="0x08f0" name="CP_SQE_STAT_ADDR_PIPE" variants="A8XX-"/> 229 229 + <reg32 offset="0x08f1" name="CP_SQE_STAT_DATA_PIPE" variants="A8XX-"/> 230 230 + <reg32 offset="0x08f2" name="CP_DRAW_STATE_ADDR_PIPE" variants="A8XX-"/> 231 231 + <reg32 offset="0x08f3" name="CP_DRAW_STATE_DATA_PIPE" variants="A8XX-"/> 232 232 + <reg32 offset="0x08f4" name="CP_ROQ_DBG_ADDR_PIPE" variants="A8XX-"/> 233 233 + <reg32 offset="0x08f5" name="CP_ROQ_DBG_DATA_PIPE" variants="A8XX-"/> 234 234 + <reg32 offset="0x08f6" name="CP_MEM_POOL_DBG_ADDR_PIPE" variants="A8XX-"/> 235 235 + <reg32 offset="0x08f7" name="CP_MEM_POOL_DBG_DATA_PIPE" variants="A8XX-"/> 236 236 + <reg32 offset="0x08f8" name="CP_SQE_UCODE_DBG_ADDR_PIPE" variants="A8XX-"/> 237 237 + <reg32 offset="0x08f9" name="CP_SQE_UCODE_DBG_DATA_PIPE" variants="A8XX-"/> 238 238 + <reg32 offset="0x08fa" name="CP_RESOURCE_TABLE_DBG_ADDR_BV" variants="A8XX-"/> 239 239 + <reg32 offset="0x08fb" name="CP_RESOURCE_TABLE_DBG_DATA_BV" variants="A8XX-"/> 240 240 + <reg32 offset="0x08fc" name="CP_FIFO_DBG_ADDR_LPAC" variants="A8XX-"/> 241 241 + <reg32 offset="0x08fd" name="CP_FIFO_DBG_DATA_LPAC" variants="A8XX-"/> 242 242 + <reg32 offset="0x08fe" name="CP_FIFO_DBG_ADDR_DDE_PIPE" variants="A8XX-"/> 243 243 + <reg32 offset="0x08ff" name="CP_FIFO_DBG_DATA_DDE_PIPE" variants="A8XX-"/> 244 244 + 245 245 + <reg32 offset="0x0b00" name="CP_SLICE_MEM_POOL_DBG_ADDR_PIPE" variants="A8XX-"/> 246 246 + <reg32 offset="0x0b01" name="CP_SLICE_MEM_POOL_DBG_DATA_PIPE" variants="A8XX-"/> 247 247 + <reg32 offset="0x0b93" name="CP_SLICE_CHICKEN_DBG_PIPE" variants="A8XX-"/> 248 248 + 249 249 + <reg64 offset="0x0928" name="CP_IB1_BASE" variants="A6XX-A7XX"/> 250 250 + <reg32 offset="0x092a" name="CP_IB1_REM_SIZE" variants="A6XX-A7XX"/> 251 251 + <reg64 offset="0x092b" name="CP_IB2_BASE" variants="A6XX-A7XX"/> 252 252 + <reg32 offset="0x092d" name="CP_IB2_REM_SIZE" variants="A6XX-A7XX"/> 309 253 <!-- SDS == CP_SET_DRAW_STATE: --> 310 310 - <reg64 offset="0x092e" name="CP_SDS_BASE"/> 311 311 - <reg32 offset="0x0930" name="CP_SDS_REM_SIZE"/> 254 254 + <reg64 offset="0x092e" name="CP_SDS_BASE" variants="A6XX-A7XX"/> 255 255 + <reg32 offset="0x0930" name="CP_SDS_REM_SIZE" variants="A6XX-A7XX"/> 312 256 <!-- MRB == MEM_READ_ADDR/$addr in SQE firmware --> 313 313 - <reg64 offset="0x0931" name="CP_MRB_BASE"/> 314 314 - <reg32 offset="0x0933" name="CP_MRB_REM_SIZE"/> 257 257 + <reg64 offset="0x0931" name="CP_MRB_BASE" variants="A6XX-A7XX"/> 258 258 + <reg32 offset="0x0933" name="CP_MRB_REM_SIZE" variants="A6XX-A7XX"/> 315 259 <!-- 316 260 VSD == Visibility Stream Decode 317 261 This is used by CP to read the draw stream and skip empty draws 318 262 --> 319 319 - <reg64 offset="0x0934" name="CP_VSD_BASE"/> 263 263 + <reg64 offset="0x0934" name="CP_VSD_BASE" variants="A6XX-A7XX"/> 264 264 + 265 265 + <reg64 offset="0x0900" name="CP_IB1_BASE" variants="A8XX-"/> 266 266 + <reg32 offset="0x0902" name="CP_IB1_REM_SIZE" variants="A8XX-"/> 267 267 + <reg32 offset="0x0903" name="CP_IB1_INIT_SIZE" variants="A8XX-"/> 268 268 + <reg64 offset="0x0904" name="CP_IB2_BASE" variants="A8XX-"/> 269 269 + <reg32 offset="0x0906" name="CP_IB2_REM_SIZE" variants="A8XX-"/> 270 270 + <reg32 offset="0x0907" name="CP_IB2_INIT_SIZE" variants="A8XX-"/> 271 271 + <reg64 offset="0x0908" name="CP_IB3_BASE" variants="A8XX-"/> 272 272 + <reg32 offset="0x090a" name="CP_IB3_REM_SIZE" variants="A8XX-"/> 273 273 + <reg32 offset="0x090b" name="CP_IB3_INIT_SIZE" variants="A8XX-"/> 274 274 + <reg64 offset="0x090c" name="CP_SDS_BASE" variants="A8XX-"/> 275 275 + <reg32 offset="0x090e" name="CP_SDS_REM_SIZE" variants="A8XX-"/> 276 276 + <reg32 offset="0x090f" name="CP_SDS_INIT_SIZE" variants="A8XX-"/> 277 277 + <reg64 offset="0x0910" name="CP_MRB_BASE" variants="A8XX-"/> 278 278 + <reg32 offset="0x0912" name="CP_MRB_REM_SIZE" variants="A8XX-"/> 279 279 + <reg32 offset="0x0913" name="CP_MRB_INIT_SIZE" variants="A8XX-"/> 280 280 + <reg64 offset="0x0914" name="CP_VSD_BASE" variants="A8XX-"/> 281 281 + <reg32 offset="0x0916" name="CP_VSD_REM_SIZE" variants="A8XX-"/> 282 282 + <reg32 offset="0x0917" name="CP_VSD_INIT_SIZE" variants="A8XX-"/> 320 283 321 284 <bitset name="a6xx_roq_status" inline="yes"> 322 285 <bitfield name="RPTR" low="0" high="9"/> 323 286 <bitfield name="WPTR" low="16" high="25"/> 324 287 </bitset> 325 325 - <reg32 offset="0x0939" name="CP_ROQ_RB_STATUS" type="a6xx_roq_status"/> 326 326 - <reg32 offset="0x093a" name="CP_ROQ_IB1_STATUS" type="a6xx_roq_status"/> 327 327 - <reg32 offset="0x093b" name="CP_ROQ_IB2_STATUS" type="a6xx_roq_status"/> 328 328 - <reg32 offset="0x093c" name="CP_ROQ_SDS_STATUS" type="a6xx_roq_status"/> 329 329 - <reg32 offset="0x093d" name="CP_ROQ_MRB_STATUS" type="a6xx_roq_status"/> 330 330 - <reg32 offset="0x093e" name="CP_ROQ_VSD_STATUS" type="a6xx_roq_status"/> 288 288 + <reg32 offset="0x0939" name="CP_ROQ_RB_STATUS" type="a6xx_roq_status" variants="A6XX-A7XX"/> 289 289 + <reg32 offset="0x093a" name="CP_ROQ_IB1_STATUS" type="a6xx_roq_status" variants="A6XX-A7XX"/> 290 290 + <reg32 offset="0x093b" name="CP_ROQ_IB2_STATUS" type="a6xx_roq_status" variants="A6XX-A7XX"/> 291 291 + <reg32 offset="0x093c" name="CP_ROQ_SDS_STATUS" type="a6xx_roq_status" variants="A6XX-A7XX"/> 292 292 + <reg32 offset="0x093d" name="CP_ROQ_MRB_STATUS" type="a6xx_roq_status" variants="A6XX-A7XX"/> 293 293 + <reg32 offset="0x093e" name="CP_ROQ_VSD_STATUS" type="a6xx_roq_status" variants="A6XX-A7XX"/> 331 294 332 332 - <reg32 offset="0x0943" name="CP_IB1_INIT_SIZE"/> 333 333 - <reg32 offset="0x0944" name="CP_IB2_INIT_SIZE"/> 334 334 - <reg32 offset="0x0945" name="CP_SDS_INIT_SIZE"/> 335 335 - <reg32 offset="0x0946" name="CP_MRB_INIT_SIZE"/> 336 336 - <reg32 offset="0x0947" name="CP_VSD_INIT_SIZE"/> 295 295 + <reg32 offset="0x0920" name="CP_ROQ_RB_STATUS" type="a6xx_roq_status" variants="A8XX-"/> 296 296 + <reg32 offset="0x0921" name="CP_ROQ_IB1_STATUS" type="a6xx_roq_status" variants="A8XX-"/> 297 297 + <reg32 offset="0x0922" name="CP_ROQ_IB2_STATUS" type="a6xx_roq_status" variants="A8XX-"/> 298 298 + <reg32 offset="0x0923" name="CP_ROQ_IB3_STATUS" type="a6xx_roq_status" variants="A8XX-"/> 299 299 + <reg32 offset="0x0924" name="CP_ROQ_SDS_STATUS" type="a6xx_roq_status" variants="A8XX-"/> 300 300 + <reg32 offset="0x0925" name="CP_ROQ_MRB_STATUS" type="a6xx_roq_status" variants="A8XX-"/> 301 301 + <reg32 offset="0x0926" name="CP_ROQ_VSD_STATUS" type="a6xx_roq_status" variants="A8XX-"/> 337 302 338 338 - <reg32 offset="0x0948" name="CP_ROQ_AVAIL_RB"> 303 303 + <reg32 offset="0x0943" name="CP_IB1_INIT_SIZE" variants="A6XX-A7XX"/> 304 304 + <reg32 offset="0x0944" name="CP_IB2_INIT_SIZE" variants="A6XX-A7XX"/> 305 305 + <reg32 offset="0x0945" name="CP_SDS_INIT_SIZE" variants="A6XX-A7XX"/> 306 306 + <reg32 offset="0x0946" name="CP_MRB_INIT_SIZE" variants="A6XX-A7XX"/> 307 307 + <reg32 offset="0x0947" name="CP_VSD_INIT_SIZE" variants="A6XX-A7XX"/> 308 308 + 309 309 + <bitset name="a6xx_cp_roq_avail" inline="yes"> 339 310 <doc>number of remaining dwords incl current dword being consumed?</doc> 340 311 <bitfield name="REM" low="16" high="31"/> 341 341 - </reg32> 342 342 - <reg32 offset="0x0949" name="CP_ROQ_AVAIL_IB1"> 343 343 - <doc>number of remaining dwords incl current dword being consumed?</doc> 344 344 - <bitfield name="REM" low="16" high="31"/> 345 345 - </reg32> 346 346 - <reg32 offset="0x094a" name="CP_ROQ_AVAIL_IB2"> 347 347 - <doc>number of remaining dwords incl current dword being consumed?</doc> 348 348 - <bitfield name="REM" low="16" high="31"/> 349 349 - </reg32> 350 350 - <reg32 offset="0x094b" name="CP_ROQ_AVAIL_SDS"> 351 351 - <doc>number of remaining dwords incl current dword being consumed?</doc> 352 352 - <bitfield name="REM" low="16" high="31"/> 353 353 - </reg32> 354 354 - <reg32 offset="0x094c" name="CP_ROQ_AVAIL_MRB"> 355 355 - <doc>number of dwords that have already been read but haven't been consumed by $addr</doc> 356 356 - <bitfield name="REM" low="16" high="31"/> 357 357 - </reg32> 358 358 - <reg32 offset="0x094d" name="CP_ROQ_AVAIL_VSD"> 359 359 - <doc>number of remaining dwords incl current dword being consumed?</doc> 360 360 - <bitfield name="REM" low="16" high="31"/> 361 361 - </reg32> 312 312 + </bitset> 313 313 + 314 314 + <reg32 offset="0x0948" name="CP_ROQ_AVAIL_RB" type="a6xx_cp_roq_avail" variants="A6XX-A7XX"/> 315 315 + <reg32 offset="0x0949" name="CP_ROQ_AVAIL_IB1" type="a6xx_cp_roq_avail" variants="A6XX-A7XX"/> 316 316 + <reg32 offset="0x094a" name="CP_ROQ_AVAIL_IB2" type="a6xx_cp_roq_avail" variants="A6XX-A7XX"/> 317 317 + <reg32 offset="0x094b" name="CP_ROQ_AVAIL_SDS" type="a6xx_cp_roq_avail" variants="A6XX-A7XX"/> 318 318 + <reg32 offset="0x094c" name="CP_ROQ_AVAIL_MRB" type="a6xx_cp_roq_avail" variants="A6XX-A7XX"/> 319 319 + <reg32 offset="0x094d" name="CP_ROQ_AVAIL_VSD" type="a6xx_cp_roq_avail" variants="A6XX-A7XX"/> 320 320 + 321 321 + <reg32 offset="0x0918" name="CP_ROQ_AVAIL_RB" type="a6xx_cp_roq_avail" variants="A8XX-"/> 322 322 + <reg32 offset="0x0919" name="CP_ROQ_AVAIL_IB1" type="a6xx_cp_roq_avail" variants="A8XX-"/> 323 323 + <reg32 offset="0x091a" name="CP_ROQ_AVAIL_IB2" type="a6xx_cp_roq_avail" variants="A8XX-"/> 324 324 + <reg32 offset="0x091b" name="CP_ROQ_AVAIL_IB3" type="a6xx_cp_roq_avail" variants="A8XX-"/> 325 325 + <reg32 offset="0x091c" name="CP_ROQ_AVAIL_SDS" type="a6xx_cp_roq_avail" variants="A8XX-"/> 326 326 + <reg32 offset="0x091d" name="CP_ROQ_AVAIL_MRB" type="a6xx_cp_roq_avail" variants="A8XX-"/> 327 327 + <reg32 offset="0x091e" name="CP_ROQ_AVAIL_VSD" type="a6xx_cp_roq_avail" variants="A8XX-"/> 362 328 363 329 <bitset name="a7xx_aperture_cntl" inline="yes"> 364 330 <bitfield name="PIPE" low="12" high="13" type="adreno_pipe"/> 365 331 <bitfield name="CLUSTER" low="8" high="10" type="a7xx_cluster"/> 366 332 <bitfield name="CONTEXT" low="4" high="5"/> 367 333 </bitset> 368 368 - <reg64 offset="0x0980" name="CP_ALWAYS_ON_COUNTER"/> 369 369 - <reg32 offset="0x098D" name="CP_AHB_CNTL"/> 334 334 + <reg64 offset="0x0980" name="CP_ALWAYS_ON_COUNTER" variants="A6XX-A7XX"/> 335 335 + <reg64 offset="0x0982" name="CP_ALWAYS_ON_CONTEXT" variants="A6XX-A7XX"/> 336 336 + <reg64 offset="0x08e7" name="CP_ALWAYS_ON_COUNTER" variants="A8XX-"/> 337 337 + <reg64 offset="0x08e9" name="CP_ALWAYS_ON_CONTEXT" variants="A8XX-"/> 338 338 + <reg32 offset="0x098d" name="CP_AHB_CNTL" variants="A6XX-A7XX"/> 339 339 + <reg32 offset="0x0838" name="CP_AHB_CNTL" variants="A8XX-"/> 370 340 <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST" variants="A6XX"/> 371 371 - <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST" type="a7xx_aperture_cntl" variants="A7XX-"/> 341 341 + <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST" type="a7xx_aperture_cntl" variants="A7XX"/> 372 342 <reg32 offset="0x0A01" name="CP_APERTURE_CNTL_SQE" variants="A6XX"/> 373 343 <reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD" variants="A6XX"/> 374 374 - <reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD" type="a7xx_aperture_cntl" variants="A7XX-"/> 344 344 + <reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD" type="a7xx_aperture_cntl" variants="A7XX"/> 375 345 376 376 - <reg32 offset="0x0a61" name="CP_BV_PROTECT_STATUS" variants="A7XX-"/> 377 377 - <reg32 offset="0x0a64" name="CP_BV_HW_FAULT" variants="A7XX-"/> 378 378 - <reg32 offset="0x0a81" name="CP_BV_DRAW_STATE_ADDR" variants="A7XX-"/> 379 379 - <reg32 offset="0x0a82" name="CP_BV_DRAW_STATE_DATA" variants="A7XX-"/> 380 380 - <reg32 offset="0x0a83" name="CP_BV_ROQ_DBG_ADDR" variants="A7XX-"/> 381 381 - <reg32 offset="0x0a84" name="CP_BV_ROQ_DBG_DATA" variants="A7XX-"/> 382 382 - <reg32 offset="0x0a85" name="CP_BV_SQE_UCODE_DBG_ADDR" variants="A7XX-"/> 383 383 - <reg32 offset="0x0a86" name="CP_BV_SQE_UCODE_DBG_DATA" variants="A7XX-"/> 384 384 - <reg32 offset="0x0a87" name="CP_BV_SQE_STAT_ADDR" variants="A7XX-"/> 385 385 - <reg32 offset="0x0a88" name="CP_BV_SQE_STAT_DATA" variants="A7XX-"/> 386 386 - <reg32 offset="0x0a96" name="CP_BV_MEM_POOL_DBG_ADDR" variants="A7XX-"/> 387 387 - <reg32 offset="0x0a97" name="CP_BV_MEM_POOL_DBG_DATA" variants="A7XX-"/> 388 388 - <reg64 offset="0x0a98" name="CP_BV_RB_RPTR_ADDR" variants="A7XX-"/> 346 346 + <array offset="0x0a9c" name="CP_RESERVED_REG" stride="1" length="4" variants="A7XX"/> 347 347 + <array offset="0x0958" name="CP_RESERVED_REG" stride="1" length="4" variants="A8XX-"/> 389 348 390 390 - <reg32 offset="0x0a9a" name="CP_RESOURCE_TABLE_DBG_ADDR" variants="A7XX-"/> 391 391 - <reg32 offset="0x0a9b" name="CP_RESOURCE_TABLE_DBG_DATA" variants="A7XX-"/> 392 392 - <reg32 offset="0x0ad0" name="CP_BV_APRIV_CNTL" variants="A7XX-"/> 393 393 - <reg32 offset="0x0ada" name="CP_BV_CHICKEN_DBG" variants="A7XX-"/> 349 349 + <bitset name="a8xx_aperture_cntl" inline="yes"> 350 350 + <bitfield name="CONTEXTID3D" low="4" high="5"/> 351 351 + <bitfield name="CLUSTERID" low="8" high="11"/> 352 352 + <bitfield name="PIPEID" low="12" high="15"/> 353 353 + <bitfield name="SLICEID" low="16" high="18"/> 354 354 + <bitfield name="USESLICEID" pos="23" type="boolean"/> 355 355 + </bitset> 394 356 395 395 - <reg32 offset="0x0b0a" name="CP_LPAC_DRAW_STATE_ADDR" variants="A7XX-"/> 396 396 - <reg32 offset="0x0b0b" name="CP_LPAC_DRAW_STATE_DATA" variants="A7XX-"/> 397 397 - <reg32 offset="0x0b0c" name="CP_LPAC_ROQ_DBG_ADDR" variants="A7XX-"/> 398 398 - <reg32 offset="0x0b27" name="CP_SQE_AC_UCODE_DBG_ADDR" variants="A7XX-"/> 399 399 - <reg32 offset="0x0b28" name="CP_SQE_AC_UCODE_DBG_DATA" variants="A7XX-"/> 400 400 - <reg32 offset="0x0b29" name="CP_SQE_AC_STAT_ADDR" variants="A7XX-"/> 401 401 - <reg32 offset="0x0b2a" name="CP_SQE_AC_STAT_DATA" variants="A7XX-"/> 357 357 + <reg32 offset="0x081c" name="CP_APERTURE_CNTL_HOST" type="a8xx_aperture_cntl" variants="A8XX-"/> 358 358 + <reg32 offset="0x081d" name="CP_APERTURE_CNTL_GMU" type="a8xx_aperture_cntl" variants="A8XX-"/> 359 359 + <reg32 offset="0x081e" name="CP_APERTURE_CNTL_CD" type="a8xx_aperture_cntl" variants="A8XX-"/> 402 360 403 403 - <reg32 offset="0x0b31" name="CP_LPAC_APRIV_CNTL" variants="A7XX-"/> 404 404 - <reg32 offset="0x0B34" name="CP_LPAC_PROG_FIFO_SIZE"/> 405 405 - <reg32 offset="0x0b35" name="CP_LPAC_ROQ_DBG_DATA" variants="A7XX-"/> 406 406 - <reg32 offset="0x0b36" name="CP_LPAC_FIFO_DBG_DATA" variants="A7XX-"/> 407 407 - <reg32 offset="0x0b40" name="CP_LPAC_FIFO_DBG_ADDR" variants="A7XX-"/> 408 408 - <reg32 offset="0x0b81" name="CP_LPAC_SQE_CNTL"/> 409 409 - <reg64 offset="0x0b82" name="CP_LPAC_SQE_INSTR_BASE"/> 361 361 + <reg32 offset="0x0a61" name="CP_BV_PROTECT_STATUS" variants="A7XX"/> 362 362 + <reg32 offset="0x0a64" name="CP_BV_HW_FAULT" variants="A7XX"/> 363 363 + <reg32 offset="0x0a66" name="CP_BV_RB_RPTR" variants="A7XX"/> 364 364 + <reg64 offset="0x0a6d" name="CP_BV_IB1_BASE" variants="A7XX"/> 365 365 + <reg32 offset="0x0a70" name="CP_BV_IB1_REM_SIZE" variants="A7XX"/> 366 366 + <reg64 offset="0x0a71" name="CP_BV_IB2_BASE" variants="A7XX"/> 367 367 + <reg32 offset="0x0a74" name="CP_BV_IB2_REM_SIZE" variants="A7XX"/> 368 368 + <reg32 offset="0x0a81" name="CP_BV_DRAW_STATE_ADDR" variants="A7XX"/> 369 369 + <reg32 offset="0x0a82" name="CP_BV_DRAW_STATE_DATA" variants="A7XX"/> 370 370 + <reg32 offset="0x0a83" name="CP_BV_ROQ_DBG_ADDR" variants="A7XX"/> 371 371 + <reg32 offset="0x0a84" name="CP_BV_ROQ_DBG_DATA" variants="A7XX"/> 372 372 + <reg32 offset="0x0a85" name="CP_BV_SQE_UCODE_DBG_ADDR" variants="A7XX"/> 373 373 + <reg32 offset="0x0a86" name="CP_BV_SQE_UCODE_DBG_DATA" variants="A7XX"/> 374 374 + <reg32 offset="0x0a87" name="CP_BV_SQE_STAT_ADDR" variants="A7XX"/> 375 375 + <reg32 offset="0x0a88" name="CP_BV_SQE_STAT_DATA" variants="A7XX"/> 410 376 411 411 - <reg64 offset="0x0b70" name="CP_AQE_INSTR_BASE_0" variants="A7XX-"/> 412 412 - <reg64 offset="0x0b72" name="CP_AQE_INSTR_BASE_1" variants="A7XX-"/> 413 413 - <reg32 offset="0x0b78" name="CP_AQE_APRIV_CNTL" variants="A7XX-"/> 377 377 + <reg32 offset="0x0a8f" name="CP_BV_ROQ_AVAIL_RB" variants="A7XX"> 378 378 + <doc>number of remaining dwords incl current dword being consumed?</doc> 379 379 + <bitfield name="REM" low="16" high="31"/> 380 380 + </reg32> 381 381 + <reg32 offset="0x0a90" name="CP_BV_ROQ_AVAIL_IB1" variants="A7XX"> 382 382 + <doc>number of remaining dwords incl current dword being consumed?</doc> 383 383 + <bitfield name="REM" low="16" high="31"/> 384 384 + </reg32> 385 385 + <reg32 offset="0x0a91" name="CP_BV_ROQ_AVAIL_IB2" variants="A7XX"> 386 386 + <doc>number of remaining dwords incl current dword being consumed?</doc> 387 387 + <bitfield name="REM" low="16" high="31"/> 388 388 + </reg32> 414 389 415 415 - <reg32 offset="0x0ba8" name="CP_AQE_ROQ_DBG_ADDR_0" variants="A7XX-"/> 416 416 - <reg32 offset="0x0ba9" name="CP_AQE_ROQ_DBG_ADDR_1" variants="A7XX-"/> 417 417 - <reg32 offset="0x0bac" name="CP_AQE_ROQ_DBG_DATA_0" variants="A7XX-"/> 418 418 - <reg32 offset="0x0bad" name="CP_AQE_ROQ_DBG_DATA_1" variants="A7XX-"/> 419 419 - <reg32 offset="0x0bb0" name="CP_AQE_UCODE_DBG_ADDR_0" variants="A7XX-"/> 420 420 - <reg32 offset="0x0bb1" name="CP_AQE_UCODE_DBG_ADDR_1" variants="A7XX-"/> 421 421 - <reg32 offset="0x0bb4" name="CP_AQE_UCODE_DBG_DATA_0" variants="A7XX-"/> 422 422 - <reg32 offset="0x0bb5" name="CP_AQE_UCODE_DBG_DATA_1" variants="A7XX-"/> 423 423 - <reg32 offset="0x0bb8" name="CP_AQE_STAT_ADDR_0" variants="A7XX-"/> 424 424 - <reg32 offset="0x0bb9" name="CP_AQE_STAT_ADDR_1" variants="A7XX-"/> 425 425 - <reg32 offset="0x0bbc" name="CP_AQE_STAT_DATA_0" variants="A7XX-"/> 426 426 - <reg32 offset="0x0bbd" name="CP_AQE_STAT_DATA_1" variants="A7XX-"/> 390 390 + <reg32 offset="0x0a96" name="CP_BV_MEM_POOL_DBG_ADDR" variants="A7XX"/> 391 391 + <reg32 offset="0x0a97" name="CP_BV_MEM_POOL_DBG_DATA" variants="A7XX"/> 392 392 + <reg64 offset="0x0a98" name="CP_BV_RB_RPTR_ADDR" variants="A7XX"/> 427 393 428 428 - <reg32 offset="0x0C01" name="VSC_ADDR_MODE_CNTL" type="a5xx_address_mode"/> 429 429 - <reg32 offset="0x0018" name="RBBM_GPR0_CNTL"/> 430 430 - <reg32 offset="0x0201" name="RBBM_INT_0_STATUS" type="A6XX_RBBM_INT_0_MASK"/> 431 431 - <reg32 offset="0x0210" name="RBBM_STATUS"> 394 394 + <reg32 offset="0x0a9a" name="CP_RESOURCE_TABLE_DBG_ADDR" variants="A7XX"/> 395 395 + <reg32 offset="0x0a9b" name="CP_RESOURCE_TABLE_DBG_DATA" variants="A7XX"/> 396 396 + <reg32 offset="0x0ad0" name="CP_BV_APRIV_CNTL" variants="A7XX"/> 397 397 + <reg32 offset="0x0ada" name="CP_BV_CHICKEN_DBG" variants="A7XX"/> 398 398 + 399 399 + <reg32 offset="0x0b0a" name="CP_LPAC_DRAW_STATE_ADDR" variants="A7XX"/> 400 400 + <reg32 offset="0x0b0b" name="CP_LPAC_DRAW_STATE_DATA" variants="A7XX"/> 401 401 + <reg32 offset="0x0b0c" name="CP_LPAC_ROQ_DBG_ADDR" variants="A7XX"/> 402 402 + <reg32 offset="0x0b27" name="CP_SQE_AC_UCODE_DBG_ADDR" variants="A7XX"/> 403 403 + <reg32 offset="0x0b28" name="CP_SQE_AC_UCODE_DBG_DATA" variants="A7XX"/> 404 404 + <reg32 offset="0x0b29" name="CP_SQE_AC_STAT_ADDR" variants="A7XX"/> 405 405 + <reg32 offset="0x0b2a" name="CP_SQE_AC_STAT_DATA" variants="A7XX"/> 406 406 + 407 407 + <reg32 offset="0x0b31" name="CP_LPAC_APRIV_CNTL" variants="A7XX"/> 408 408 + <reg32 offset="0x0b34" name="CP_LPAC_PROG_FIFO_SIZE" variants="A7XX"/> 409 409 + <reg32 offset="0x0b35" name="CP_LPAC_ROQ_DBG_DATA" variants="A7XX"/> 410 410 + <reg32 offset="0x0b36" name="CP_LPAC_FIFO_DBG_DATA" variants="A7XX"/> 411 411 + <reg32 offset="0x0b40" name="CP_LPAC_FIFO_DBG_ADDR" variants="A7XX"/> 412 412 + <reg32 offset="0x0b81" name="CP_LPAC_SQE_CNTL" variants="A6XX-A7XX"/> 413 413 + <reg64 offset="0x0b82" name="CP_LPAC_SQE_INSTR_BASE" variants="A6XX-A7XX"/> 414 414 + 415 415 + <reg64 offset="0x0b70" name="CP_AQE_INSTR_BASE_0" variants="A7XX"/> 416 416 + <reg64 offset="0x0b72" name="CP_AQE_INSTR_BASE_1" variants="A7XX"/> 417 417 + <reg32 offset="0x0b78" name="CP_AQE_APRIV_CNTL" variants="A7XX"/> 418 418 + 419 419 + <reg32 offset="0x0ba8" name="CP_AQE_ROQ_DBG_ADDR_0" variants="A7XX"/> 420 420 + <reg32 offset="0x0ba9" name="CP_AQE_ROQ_DBG_ADDR_1" variants="A7XX"/> 421 421 + <reg32 offset="0x0bac" name="CP_AQE_ROQ_DBG_DATA_0" variants="A7XX"/> 422 422 + <reg32 offset="0x0bad" name="CP_AQE_ROQ_DBG_DATA_1" variants="A7XX"/> 423 423 + <reg32 offset="0x0bb0" name="CP_AQE_UCODE_DBG_ADDR_0" variants="A7XX"/> 424 424 + <reg32 offset="0x0bb1" name="CP_AQE_UCODE_DBG_ADDR_1" variants="A7XX"/> 425 425 + <reg32 offset="0x0bb4" name="CP_AQE_UCODE_DBG_DATA_0" variants="A7XX"/> 426 426 + <reg32 offset="0x0bb5" name="CP_AQE_UCODE_DBG_DATA_1" variants="A7XX"/> 427 427 + <reg32 offset="0x0bb8" name="CP_AQE_STAT_ADDR_0" variants="A7XX"/> 428 428 + <reg32 offset="0x0bb9" name="CP_AQE_STAT_ADDR_1" variants="A7XX"/> 429 429 + <reg32 offset="0x0bbc" name="CP_AQE_STAT_DATA_0" variants="A7XX"/> 430 430 + <reg32 offset="0x0bbd" name="CP_AQE_STAT_DATA_1" variants="A7XX"/> 431 431 + 432 432 + <reg32 offset="0x0C01" name="VSC_ADDR_MODE_CNTL" type="a5xx_address_mode" variants="A6XX"/> 433 433 + <reg32 offset="0x0018" name="RBBM_GPR0_CNTL" variants="A6XX"/> 434 434 + <reg32 offset="0x0201" name="RBBM_INT_0_STATUS" type="A6XX_RBBM_INT_0_MASK" variants="A6XX-A7XX"/> 435 435 + <reg32 offset="0x006a" name="RBBM_INT_0_STATUS" type="A6XX_RBBM_INT_0_MASK" variants="A8XX-"/> 436 436 + <reg32 offset="0x0210" name="RBBM_STATUS" variants="A6XX-A7XX"> 432 437 <bitfield pos="23" name="GPU_BUSY_IGN_AHB" type="boolean"/> 433 438 <bitfield pos="22" name="GPU_BUSY_IGN_AHB_CP" type="boolean"/> 434 439 <bitfield pos="21" name="HLSQ_BUSY" type="boolean"/> ··· 571 342 <bitfield pos="1" name="CP_AHB_BUSY_CP_MASTER" type="boolean"/> 572 343 <bitfield pos="0" name="CP_AHB_BUSY_CX_MASTER" type="boolean"/> 573 344 </reg32> 574 574 - <reg32 offset="0x0211" name="RBBM_STATUS1"/> 575 575 - <reg32 offset="0x0212" name="RBBM_STATUS2"/> 576 576 - <reg32 offset="0x0213" name="RBBM_STATUS3"> 345 345 + <reg32 offset="0x0211" name="RBBM_STATUS1" variants="A6XX-A7XX"/> 346 346 + <reg32 offset="0x0212" name="RBBM_STATUS2" variants="A6XX-A7XX"/> 347 347 + <reg32 offset="0x0213" name="RBBM_STATUS3" variants="A6XX-A7XX"> 577 348 <bitfield pos="24" name="SMMU_STALLED_ON_FAULT" type="boolean"/> 578 349 </reg32> 579 579 - <reg32 offset="0x0215" name="RBBM_VBIF_GX_RESET_STATUS"/> 580 350 581 581 - <reg32 offset="0x0260" name="RBBM_CLOCK_MODE_CP" variants="A7XX-"/> 582 582 - <reg32 offset="0x0284" name="RBBM_CLOCK_MODE_BV_LRZ" variants="A7XX-"/> 583 583 - <reg32 offset="0x0285" name="RBBM_CLOCK_MODE_BV_GRAS" variants="A7XX-"/> 584 584 - <reg32 offset="0x0286" name="RBBM_CLOCK_MODE2_GRAS" variants="A7XX-"/> 585 585 - <reg32 offset="0x0287" name="RBBM_CLOCK_MODE_BV_VFD" variants="A7XX-"/> 586 586 - <reg32 offset="0x0288" name="RBBM_CLOCK_MODE_BV_GPC" variants="A7XX-"/> 351 351 + <reg32 offset="0x012" name="RBBM_STATUS" variants="A8XX-"> 352 352 + <bitfield pos="23" name="GPU_BUSY_IGN_AHB" type="boolean"/> 353 353 + <bitfield pos="22" name="GPU_BUSY_IGN_AHB_CP" type="boolean"/> 354 354 + <bitfield pos="21" name="SLICE_BUSY_IGN_CP" type="boolean"/> 355 355 + <bitfield pos="20" name="CP_SLICE_BUSY" type="boolean"/> 356 356 + <bitfield pos="19" name="UNSLICE_BUSY_IGN_AHB" type="boolean"/> 357 357 + <bitfield pos="18" name="UNSLICE_BUSY_IGN_AHB_CP" type="boolean"/> 358 358 + <bitfield pos="17" name="CP_SLICE_RL_BUSY" type="boolean"/> 359 359 + <bitfield pos="14" name="UNSLICE_TOP_BUSY" type="boolean"/> 360 360 + <bitfield pos="13" name="UFC_BUSY" type="boolean"/> 361 361 + <bitfield pos="12" name="HLSQ_BUSY" type="boolean"/> 362 362 + <bitfield pos="11" name="VSC_BUSY" type="boolean"/> 363 363 + <bitfield pos="10" name="UCHE_BUSY" type="boolean"/> 364 364 + <bitfield pos="9" name="VPC_BUSY" type="boolean"/> 365 365 + <bitfield pos="8" name="PC_BUSY" type="boolean"/> 366 366 + <bitfield pos="7" name="CMP_BUSY" type="boolean"/> 367 367 + <bitfield pos="6" name="DCMP_BUSY" type="boolean"/> 368 368 + <bitfield pos="5" name="VBIF_GX_BUSY" type="boolean"/> 369 369 + <bitfield pos="4" name="DBGC_PERF_BUSY" type="boolean"/> 370 370 + <bitfield pos="3" name="GFX_DBGC_BUSY" type="boolean"/> 371 371 + <bitfield pos="2" name="CP_BUSY" type="boolean"/> 372 372 + <bitfield pos="1" name="CP_AHB_BUSY_CP_MASTER" type="boolean"/> 373 373 + <bitfield pos="0" name="CP_AHB_BUSY_CX_MASTER" type="boolean"/> 374 374 + </reg32> 375 375 + <reg32 offset="0x013" name="RBBM_STATUS1" variants="A8XX-"/> 376 376 + <reg32 offset="0x015" name="RBBM_GFX_STATUS" variants="A8XX-"/> 377 377 + <reg32 offset="0x016" name="RBBM_GFX_STATUS1" variants="A8XX-"/> 378 378 + <reg32 offset="0x018" name="RBBM_LPAC_STATUS" variants="A8XX-"/> 379 379 + <reg32 offset="0x01a" name="RBBM_GFX_BR_STATUS" variants="A8XX-"/> 380 380 + <reg32 offset="0x01c" name="RBBM_GFX_BV_STATUS" variants="A8XX-"/> 381 381 + <reg32 offset="0x01e" name="RBBM_MISC_STATUS" variants="A8XX-"> 382 382 + <bitfield pos="0" name="SMMU_STALLED_ON_FAULT" type="boolean"/> 383 383 + </reg32> 587 384 588 588 - <reg32 offset="0x02c0" name="RBBM_SW_FUSE_INT_STATUS" variants="A7XX-"/> 589 589 - <reg32 offset="0x02c1" name="RBBM_SW_FUSE_INT_MASK" variants="A7XX-"/> 385 385 + <reg32 offset="0x0215" name="RBBM_VBIF_GX_RESET_STATUS" variants="A6XX"/> 386 386 + 387 387 + <reg32 offset="0x0260" name="RBBM_CLOCK_MODE_CP" variants="A7XX"/> 388 388 + <reg32 offset="0x0284" name="RBBM_CLOCK_MODE_BV_LRZ" variants="A7XX"/> 389 389 + <reg32 offset="0x0285" name="RBBM_CLOCK_MODE_BV_GRAS" variants="A7XX"/> 390 390 + <reg32 offset="0x0286" name="RBBM_CLOCK_MODE2_GRAS" variants="A7XX"/> 391 391 + <reg32 offset="0x0287" name="RBBM_CLOCK_MODE_BV_VFD" variants="A7XX"/> 392 392 + <reg32 offset="0x0288" name="RBBM_CLOCK_MODE_BV_GPC" variants="A7XX"/> 393 393 + 394 394 + <reg32 offset="0x02c0" name="RBBM_SW_FUSE_INT_STATUS" variants="A7XX"/> 395 395 + <reg32 offset="0x02c1" name="RBBM_SW_FUSE_INT_MASK" variants="A7XX"/> 396 396 + <reg32 offset="0x0071" name="RBBM_SW_FUSE_INT_STATUS" variants="A8XX-"/> 397 397 + <reg32 offset="0x0072" name="RBBM_SW_FUSE_INT_MASK" variants="A8XX-"/> 590 398 591 399 <array offset="0x0400" name="RBBM_PERFCTR_CP" stride="2" length="14" variants="A6XX"/> 592 400 <array offset="0x041c" name="RBBM_PERFCTR_RBBM" stride="2" length="4" variants="A6XX"/> ··· 642 376 <array offset="0x04ea" name="RBBM_PERFCTR_LRZ" stride="2" length="4" variants="A6XX"/> 643 377 <array offset="0x04f2" name="RBBM_PERFCTR_CMP" stride="2" length="4" variants="A6XX"/> 644 378 645 645 - <array offset="0x0300" name="RBBM_PERFCTR_CP" stride="2" length="14" variants="A7XX-"/> 646 646 - <array offset="0x031c" name="RBBM_PERFCTR_RBBM" stride="2" length="4" variants="A7XX-"/> 647 647 - <array offset="0x0324" name="RBBM_PERFCTR_PC" stride="2" length="8" variants="A7XX-"/> 648 648 - <array offset="0x0334" name="RBBM_PERFCTR_VFD" stride="2" length="8" variants="A7XX-"/> 649 649 - <array offset="0x0344" name="RBBM_PERFCTR_HLSQ" stride="2" length="6" variants="A7XX-"/> 650 650 - <array offset="0x0350" name="RBBM_PERFCTR_VPC" stride="2" length="6" variants="A7XX-"/> 651 651 - <array offset="0x035c" name="RBBM_PERFCTR_CCU" stride="2" length="5" variants="A7XX-"/> 652 652 - <array offset="0x0366" name="RBBM_PERFCTR_TSE" stride="2" length="4" variants="A7XX-"/> 653 653 - <array offset="0x036e" name="RBBM_PERFCTR_RAS" stride="2" length="4" variants="A7XX-"/> 654 654 - <array offset="0x0376" name="RBBM_PERFCTR_UCHE" stride="2" length="12" variants="A7XX-"/> 655 655 - <array offset="0x038e" name="RBBM_PERFCTR_TP" stride="2" length="12" variants="A7XX-"/> 656 656 - <array offset="0x03a6" name="RBBM_PERFCTR_SP" stride="2" length="24" variants="A7XX-"/> 657 657 - <array offset="0x03d6" name="RBBM_PERFCTR_RB" stride="2" length="8" variants="A7XX-"/> 658 658 - <array offset="0x03e6" name="RBBM_PERFCTR_VSC" stride="2" length="2" variants="A7XX-"/> 659 659 - <array offset="0x03ea" name="RBBM_PERFCTR_LRZ" stride="2" length="4" variants="A7XX-"/> 660 660 - <array offset="0x03f2" name="RBBM_PERFCTR_CMP" stride="2" length="4" variants="A7XX-"/> 661 661 - <array offset="0x03fa" name="RBBM_PERFCTR_UFC" stride="2" length="4" variants="A7XX-"/> 662 662 - <array offset="0x0410" name="RBBM_PERFCTR2_HLSQ" stride="2" length="6" variants="A7XX-"/> 663 663 - <array offset="0x041c" name="RBBM_PERFCTR2_CP" stride="2" length="7" variants="A7XX-"/> 664 664 - <array offset="0x042a" name="RBBM_PERFCTR2_SP" stride="2" length="12" variants="A7XX-"/> 665 665 - <array offset="0x0442" name="RBBM_PERFCTR2_TP" stride="2" length="6" variants="A7XX-"/> 666 666 - <array offset="0x044e" name="RBBM_PERFCTR2_UFC" stride="2" length="2" variants="A7XX-"/> 667 667 - <array offset="0x0460" name="RBBM_PERFCTR_BV_PC" stride="2" length="8" variants="A7XX-"/> 668 668 - <array offset="0x0470" name="RBBM_PERFCTR_BV_VFD" stride="2" length="8" variants="A7XX-"/> 669 669 - <array offset="0x0480" name="RBBM_PERFCTR_BV_VPC" stride="2" length="6" variants="A7XX-"/> 670 670 - <array offset="0x048c" name="RBBM_PERFCTR_BV_TSE" stride="2" length="4" variants="A7XX-"/> 671 671 - <array offset="0x0494" name="RBBM_PERFCTR_BV_RAS" stride="2" length="4" variants="A7XX-"/> 672 672 - <array offset="0x049c" name="RBBM_PERFCTR_BV_LRZ" stride="2" length="4" variants="A7XX-"/> 379 379 + <array offset="0x0300" name="RBBM_PERFCTR_CP" stride="2" length="14" variants="A7XX"/> 380 380 + <array offset="0x031c" name="RBBM_PERFCTR_RBBM" stride="2" length="4" variants="A7XX"/> 381 381 + <array offset="0x0324" name="RBBM_PERFCTR_PC" stride="2" length="8" variants="A7XX"/> 382 382 + <array offset="0x0334" name="RBBM_PERFCTR_VFD" stride="2" length="8" variants="A7XX"/> 383 383 + <array offset="0x0344" name="RBBM_PERFCTR_HLSQ" stride="2" length="6" variants="A7XX"/> 384 384 + <array offset="0x0350" name="RBBM_PERFCTR_VPC" stride="2" length="6" variants="A7XX"/> 385 385 + <array offset="0x035c" name="RBBM_PERFCTR_CCU" stride="2" length="5" variants="A7XX"/> 386 386 + <array offset="0x0366" name="RBBM_PERFCTR_TSE" stride="2" length="4" variants="A7XX"/> 387 387 + <array offset="0x036e" name="RBBM_PERFCTR_RAS" stride="2" length="4" variants="A7XX"/> 388 388 + <array offset="0x0376" name="RBBM_PERFCTR_UCHE" stride="2" length="12" variants="A7XX"/> 389 389 + <array offset="0x038e" name="RBBM_PERFCTR_TP" stride="2" length="12" variants="A7XX"/> 390 390 + <array offset="0x03a6" name="RBBM_PERFCTR_SP" stride="2" length="24" variants="A7XX"/> 391 391 + <array offset="0x03d6" name="RBBM_PERFCTR_RB" stride="2" length="8" variants="A7XX"/> 392 392 + <array offset="0x03e6" name="RBBM_PERFCTR_VSC" stride="2" length="2" variants="A7XX"/> 393 393 + <array offset="0x03ea" name="RBBM_PERFCTR_LRZ" stride="2" length="4" variants="A7XX"/> 394 394 + <array offset="0x03f2" name="RBBM_PERFCTR_CMP" stride="2" length="4" variants="A7XX"/> 395 395 + <array offset="0x03fa" name="RBBM_PERFCTR_UFC" stride="2" length="4" variants="A7XX"/> 396 396 + <array offset="0x0410" name="RBBM_PERFCTR2_HLSQ" stride="2" length="6" variants="A7XX"/> 397 397 + <array offset="0x041c" name="RBBM_PERFCTR2_CP" stride="2" length="7" variants="A7XX"/> 398 398 + <array offset="0x042a" name="RBBM_PERFCTR2_SP" stride="2" length="12" variants="A7XX"/> 399 399 + <array offset="0x0442" name="RBBM_PERFCTR2_TP" stride="2" length="6" variants="A7XX"/> 400 400 + <array offset="0x044e" name="RBBM_PERFCTR2_UFC" stride="2" length="2" variants="A7XX"/> 401 401 + <array offset="0x0460" name="RBBM_PERFCTR_BV_PC" stride="2" length="8" variants="A7XX"/> 402 402 + <array offset="0x0470" name="RBBM_PERFCTR_BV_VFD" stride="2" length="8" variants="A7XX"/> 403 403 + <array offset="0x0480" name="RBBM_PERFCTR_BV_VPC" stride="2" length="6" variants="A7XX"/> 404 404 + <array offset="0x048c" name="RBBM_PERFCTR_BV_TSE" stride="2" length="4" variants="A7XX"/> 405 405 + <array offset="0x0494" name="RBBM_PERFCTR_BV_RAS" stride="2" length="4" variants="A7XX"/> 406 406 + <array offset="0x049c" name="RBBM_PERFCTR_BV_LRZ" stride="2" length="4" variants="A7XX"/> 673 407 674 674 - <reg32 offset="0x0500" name="RBBM_PERFCTR_CNTL"/> 675 675 - <reg32 offset="0x0501" name="RBBM_PERFCTR_LOAD_CMD0"/> 676 676 - <reg32 offset="0x0502" name="RBBM_PERFCTR_LOAD_CMD1"/> 677 677 - <reg32 offset="0x0503" name="RBBM_PERFCTR_LOAD_CMD2"/> 678 678 - <reg32 offset="0x0504" name="RBBM_PERFCTR_LOAD_CMD3"/> 679 679 - <reg32 offset="0x0505" name="RBBM_PERFCTR_LOAD_VALUE_LO"/> 680 680 - <reg32 offset="0x0506" name="RBBM_PERFCTR_LOAD_VALUE_HI"/> 681 681 - <array offset="0x0507" name="RBBM_PERFCTR_RBBM_SEL" stride="1" length="4"/> 682 682 - <reg32 offset="0x050B" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/> 683 683 - <reg32 offset="0x050e" name="RBBM_PERFCTR_SRAM_INIT_CMD"/> 684 684 - <reg32 offset="0x050f" name="RBBM_PERFCTR_SRAM_INIT_STATUS"/> 685 685 - <reg32 offset="0x0533" name="RBBM_ISDB_CNT"/> 686 686 - <reg32 offset="0x0534" name="RBBM_NC_MODE_CNTL"/> 687 687 - <reg32 offset="0x0535" name="RBBM_SNAPSHOT_STATUS" variants="A7XX-"/> 408 408 + <array offset="0x01b0" name="RBBM_PERFCTR_CP" stride="2" length="14" variants="A8XX"/> 409 409 + <array offset="0x01cc" name="RBBM_PERFCTR_RBBM" stride="2" length="4" variants="A8XX"/> 410 410 + <array offset="0x01d4" name="RBBM_PERFCTR_PC" stride="2" length="8" variants="A8XX"/> 411 411 + <array offset="0x01e4" name="RBBM_PERFCTR_VFD" stride="2" length="8" variants="A8XX"/> 412 412 + <array offset="0x01f4" name="RBBM_PERFCTR_HLSQ" stride="2" length="6" variants="A8XX"/> 413 413 + <array offset="0x0200" name="RBBM_PERFCTR_VPC" stride="2" length="6" variants="A8XX"/> 414 414 + <array offset="0x020c" name="RBBM_PERFCTR_CCU" stride="2" length="5" variants="A8XX"/> 415 415 + <array offset="0x0216" name="RBBM_PERFCTR_TSE" stride="2" length="4" variants="A8XX"/> 416 416 + <array offset="0x021e" name="RBBM_PERFCTR_RAS" stride="2" length="4" variants="A8XX"/> 417 417 + <array offset="0x0226" name="RBBM_PERFCTR_UCHE" stride="2" length="24" variants="A8XX"/> 418 418 + <array offset="0x0256" name="RBBM_PERFCTR_TP" stride="2" length="12" variants="A8XX"/> 419 419 + <array offset="0x026e" name="RBBM_PERFCTR_SP" stride="2" length="24" variants="A8XX"/> 420 420 + <array offset="0x029e" name="RBBM_PERFCTR_RB" stride="2" length="8" variants="A8XX"/> 421 421 + <array offset="0x02ae" name="RBBM_PERFCTR_VSC" stride="2" length="2" variants="A8XX"/> 422 422 + <array offset="0x02b2" name="RBBM_PERFCTR_LRZ" stride="2" length="4" variants="A8XX"/> 423 423 + <array offset="0x02ba" name="RBBM_PERFCTR_CMP" stride="2" length="4" variants="A8XX"/> 424 424 + <array offset="0x02c2" name="RBBM_PERFCTR_UFC" stride="2" length="4" variants="A8XX"/> 425 425 + <array offset="0x02e2" name="RBBM_PERFCTR2_HLSQ" stride="2" length="6" variants="A8XX"/> 426 426 + <array offset="0x02ee" name="RBBM_PERFCTR2_CP" stride="2" length="7" variants="A8XX"/> 427 427 + <array offset="0x02fc" name="RBBM_PERFCTR2_SP" stride="2" length="12" variants="A8XX"/> 428 428 + <array offset="0x0314" name="RBBM_PERFCTR2_TP" stride="2" length="8" variants="A8XX"/> 429 429 + <array offset="0x0324" name="RBBM_PERFCTR2_UFC" stride="2" length="2" variants="A8XX"/> 430 430 + <array offset="0x0328" name="RBBM_PERFCTR_BV_PC" stride="2" length="8" variants="A8XX"/> 431 431 + <array offset="0x0338" name="RBBM_PERFCTR_BV_VFD" stride="2" length="8" variants="A8XX"/> 432 432 + <array offset="0x0348" name="RBBM_PERFCTR_BV_VPC" stride="2" length="6" variants="A8XX"/> 433 433 + <array offset="0x0354" name="RBBM_PERFCTR_BV_TSE" stride="2" length="4" variants="A8XX"/> 434 434 + <array offset="0x035c" name="RBBM_PERFCTR_BV_RAS" stride="2" length="4" variants="A8XX"/> 435 435 + <array offset="0x0364" name="RBBM_PERFCTR_BV_LRZ" stride="2" length="4" variants="A8XX"/> 436 436 + <array offset="0x036c" name="RBBM_PERFCTR_BV_CCU" stride="2" length="3" variants="A8XX"/> 437 437 + <array offset="0x0372" name="RBBM_PERFCTR_BV_RB" stride="2" length="6" variants="A8XX"/> 438 438 + 439 439 + <reg32 offset="0x0500" name="RBBM_PERFCTR_CNTL" variants="A6XX-A7XX"/> 440 440 + <reg32 offset="0x0460" name="RBBM_PERFCTR_CNTL" variants="A8XX-"/> 441 441 + <reg32 offset="0x0501" name="RBBM_PERFCTR_LOAD_CMD0" variants="A6XX"/> 442 442 + <reg32 offset="0x0502" name="RBBM_PERFCTR_LOAD_CMD1" variants="A6XX"/> 443 443 + <reg32 offset="0x0503" name="RBBM_PERFCTR_LOAD_CMD2" variants="A6XX"/> 444 444 + <reg32 offset="0x0504" name="RBBM_PERFCTR_LOAD_CMD3" variants="A6XX"/> 445 445 + <reg64 offset="0x0505" name="RBBM_PERFCTR_LOAD_VALUE" variants="A6XX"/> 446 446 + <array offset="0x0507" name="RBBM_PERFCTR_RBBM_SEL" stride="1" length="4" variants="A6XX-A7XX"/> 447 447 + <array offset="0x0441" name="RBBM_PERFCTR_RBBM_SEL" stride="1" length="4" variants="A8XX-"/> 448 448 + <reg32 offset="0x050B" name="RBBM_PERFCTR_GPU_BUSY_MASKED" variants="A6XX-A7XX"/> 449 449 + <reg32 offset="0x019e" name="RBBM_PERFCTR_GPU_BUSY_MASKED" variants="A8XX-"/> 450 450 + <reg32 offset="0x050e" name="RBBM_PERFCTR_SRAM_INIT_CMD" variants="A6XX-A7XX"/> 451 451 + <reg32 offset="0x0449" name="RBBM_PERFCTR_SRAM_INIT_CMD" variants="A8XX-"/> 452 452 + <reg32 offset="0x050f" name="RBBM_PERFCTR_SRAM_INIT_STATUS" variants="A6XX-A7XX"/> 453 453 + <reg32 offset="0x019f" name="RBBM_PERFCTR_SRAM_INIT_STATUS" variants="A8XX-"/> 454 454 + <reg32 offset="0x01a1" name="RBBM_PERFCTR_FLUSH_HOST_STATUS" variants="A8XX-"/> 455 455 + <reg32 offset="0x044c" name="RBBM_PERFCTR_FLUSH_HOST_CMD" variants="A8XX-"/> 456 456 + <reg32 offset="0x0533" name="RBBM_ISDB_CNT" variants="A6XX-A7XX"/> 457 457 + <reg32 offset="0x002d" name="RBBM_ISDB_CNT" variants="A8XX-"/> 458 458 + <reg32 offset="0x0534" name="RBBM_NC_MODE_CNTL" variants="A6XX-A7XX"/> 459 459 + <reg32 offset="0x0440" name="RBBM_NC_MODE_CNTL" variants="A8XX-"/> 460 460 + <reg32 offset="0x0535" name="RBBM_SNAPSHOT_STATUS" variants="A7XX"/> 461 461 + <reg32 offset="0x002e" name="RBBM_SNAPSHOT_STATUS" variants="A8XX-"/> 462 462 + 463 463 + <reg32 offset="0x500" name="RBBM_SLICE_PERFCTR_CNTL" variants="A8XX-"/> 464 464 + <reg32 offset="0x58f" name="RBBM_SLICE_INTERFACE_HANG_INT_CNTL" variants="A8XX-"/> 465 465 + <array offset="0x5e0" name="RBBM_SLICE_PERFCTR_RBBM_SEL" stride="1" length="4" variants="A8XX-"/> 466 466 + <reg32 offset="0x5e8" name="RBBM_SLICE_PERFCTR_SRAM_INIT_CMD" variants="A8XX-"/> 467 467 + <reg32 offset="0x5eb" name="RBBM_SLICE_PERFCTR_FLUSH_HOST_CMD" variants="A8XX-"/> 468 468 + <reg32 offset="0x5ec" name="RBBM_SLICE_NC_MODE_CNTL" variants="A8XX-"/> 688 469 689 470 <!--- 690 471 This block of registers aren't tied to perf counters. They ··· 739 426 vertices in, number of primnitives assembled etc. 740 427 --> 741 428 742 742 - <reg64 offset="0x0540" name="RBBM_PIPESTAT_IAVERTICES"/> 743 743 - <reg64 offset="0x0542" name="RBBM_PIPESTAT_IAPRIMITIVES"/> 744 744 - <reg64 offset="0x0544" name="RBBM_PIPESTAT_VSINVOCATIONS"/> 745 745 - <reg64 offset="0x0546" name="RBBM_PIPESTAT_HSINVOCATIONS"/> 746 746 - <reg64 offset="0x0548" name="RBBM_PIPESTAT_DSINVOCATIONS"/> 747 747 - <reg64 offset="0x054a" name="RBBM_PIPESTAT_GSINVOCATIONS"/> 748 748 - <reg64 offset="0x054c" name="RBBM_PIPESTAT_GSPRIMITIVES"/> 749 749 - <reg64 offset="0x054e" name="RBBM_PIPESTAT_CINVOCATIONS"/> 750 750 - <reg64 offset="0x0550" name="RBBM_PIPESTAT_CPRIMITIVES"/> 751 751 - <reg64 offset="0x0552" name="RBBM_PIPESTAT_PSINVOCATIONS"/> 752 752 - <reg64 offset="0x0554" name="RBBM_PIPESTAT_CSINVOCATIONS"/> 429 429 + <reg64 offset="0x0540" name="RBBM_PIPESTAT_IAVERTICES" variants="A6XX-A7XX"/> 430 430 + <reg64 offset="0x0542" name="RBBM_PIPESTAT_IAPRIMITIVES" variants="A6XX-A7XX"/> 431 431 + <reg64 offset="0x0544" name="RBBM_PIPESTAT_VSINVOCATIONS" variants="A6XX-A7XX"/> 432 432 + <reg64 offset="0x0546" name="RBBM_PIPESTAT_HSINVOCATIONS" variants="A6XX-A7XX"/> 433 433 + <reg64 offset="0x0548" name="RBBM_PIPESTAT_DSINVOCATIONS" variants="A6XX-A7XX"/> 434 434 + <reg64 offset="0x054a" name="RBBM_PIPESTAT_GSINVOCATIONS" variants="A6XX-A7XX"/> 435 435 + <reg64 offset="0x054c" name="RBBM_PIPESTAT_GSPRIMITIVES" variants="A6XX-A7XX"/> 436 436 + <reg64 offset="0x054e" name="RBBM_PIPESTAT_CINVOCATIONS" variants="A6XX-A7XX"/> 437 437 + <reg64 offset="0x0550" name="RBBM_PIPESTAT_CPRIMITIVES" variants="A6XX-A7XX"/> 438 438 + <reg64 offset="0x0552" name="RBBM_PIPESTAT_PSINVOCATIONS" variants="A6XX-A7XX"/> 439 439 + <reg64 offset="0x0554" name="RBBM_PIPESTAT_CSINVOCATIONS" variants="A6XX-A7XX"/> 440 440 + 441 441 + <reg64 offset="0x0380" name="RBBM_PIPESTAT_IAVERTICES" variants="A8XX-"/> 442 442 + <reg64 offset="0x0382" name="RBBM_PIPESTAT_IAPRIMITIVES" variants="A8XX-"/> 443 443 + <reg64 offset="0x0384" name="RBBM_PIPESTAT_VSINVOCATIONS" variants="A8XX-"/> 444 444 + <reg64 offset="0x0386" name="RBBM_PIPESTAT_GSINVOCATIONS" variants="A8XX-"/> 445 445 + <reg64 offset="0x0388" name="RBBM_PIPESTAT_GSPRIMITIVES" variants="A8XX-"/> 446 446 + <reg64 offset="0x038a" name="RBBM_PIPESTAT_CINVOCATIONS" variants="A8XX-"/> 447 447 + <reg64 offset="0x038c" name="RBBM_PIPESTAT_CPRIMITIVES" variants="A8XX-"/> 448 448 + <reg64 offset="0x038e" name="RBBM_PIPESTAT_PSINVOCATIONS" variants="A8XX-"/> 449 449 + <reg64 offset="0x0390" name="RBBM_PIPESTAT_HSINVOCATIONS" variants="A8XX-"/> 450 450 + <reg64 offset="0x0392" name="RBBM_PIPESTAT_DSINVOCATIONS" variants="A8XX-"/> 451 451 + <reg64 offset="0x0394" name="RBBM_PIPESTAT_CSINVOCATIONS" variants="A8XX-"/> 452 452 + <reg64 offset="0x0396" name="RBBM_PIPESTAT_ASINVOCATIONS" variants="A8XX-"/> 453 453 + <reg64 offset="0x0398" name="RBBM_PIPESTAT_MSINVOCATIONS" variants="A8XX-"/> 454 454 + <reg64 offset="0x039a" name="RBBM_PIPESTAT_MSPRIMITIVES" variants="A8XX-"/> 753 455 754 456 <reg32 offset="0xF400" name="RBBM_SECVID_TRUST_CNTL"/> 755 457 <reg64 offset="0xF800" name="RBBM_SECVID_TSB_TRUSTED_BASE"/> 756 458 <reg32 offset="0xF802" name="RBBM_SECVID_TSB_TRUSTED_SIZE"/> 757 459 <reg32 offset="0xF803" name="RBBM_SECVID_TSB_CNTL"/> 758 758 - <reg32 offset="0xF810" name="RBBM_SECVID_TSB_ADDR_MODE_CNTL" type="a5xx_address_mode"/> 460 460 + <reg32 offset="0xF810" name="RBBM_SECVID_TSB_ADDR_MODE_CNTL" type="a5xx_address_mode" variants="A6XX"/> 759 461 <reg64 offset="0xfc00" name="RBBM_SECVID_TSB_STATUS" variants="A7XX-"/> 760 760 - <reg32 offset="0x00010" name="RBBM_VBIF_CLIENT_QOS_CNTL"/> 761 761 - <reg32 offset="0x00011" name="RBBM_GBIF_CLIENT_QOS_CNTL"/> 762 762 - <reg32 offset="0x00016" name="RBBM_GBIF_HALT"/> 763 763 - <reg32 offset="0x00017" name="RBBM_GBIF_HALT_ACK"/> 764 764 - <reg32 offset="0x0001c" name="RBBM_WAIT_FOR_GPU_IDLE_CMD"> 462 462 + <reg32 offset="0x00010" name="RBBM_VBIF_CLIENT_QOS_CNTL" variants="A6XX"/> 463 463 + <reg32 offset="0x00011" name="RBBM_GBIF_CLIENT_QOS_CNTL" variants="A6XX-A7XX"/> 464 464 + <reg32 offset="0x00008" name="RBBM_GBIF_CLIENT_QOS_CNTL" variants="A8XX-"/> 465 465 + <reg32 offset="0x00016" name="RBBM_GBIF_HALT" variants="A6XX-A7XX"/> 466 466 + <reg32 offset="0x0000a" name="RBBM_GBIF_HALT" variants="A8XX-"/> 467 467 + <reg32 offset="0x00017" name="RBBM_GBIF_HALT_ACK" variants="A6XX-A7XX"/> 468 468 + <reg32 offset="0x0000b" name="RBBM_GBIF_HALT_ACK" variants="A8XX-"/> 469 469 + <reg32 offset="0x0001c" name="RBBM_WAIT_FOR_GPU_IDLE_CMD" variants="A6XX"> 765 470 <bitfield pos="0" name="WAIT_GPU_IDLE" type="boolean"/> 766 471 </reg32> 767 472 768 768 - <reg32 offset="0x00016" name="RBBM_GBIF_HALT" variants="A7XX-"/> 769 769 - <reg32 offset="0x00017" name="RBBM_GBIF_HALT_ACK" variants="A7XX-"/> 770 770 - <reg32 offset="0x0001f" name="RBBM_INTERFACE_HANG_INT_CNTL"/> 771 771 - <reg32 offset="0x00037" name="RBBM_INT_CLEAR_CMD" type="A6XX_RBBM_INT_0_MASK"/> 772 772 - <reg32 offset="0x00038" name="RBBM_INT_0_MASK" type="A6XX_RBBM_INT_0_MASK"/> 773 773 - <reg32 offset="0x0003a" name="RBBM_INT_2_MASK" variants="A7XX-"/> 774 774 - <reg32 offset="0x00042" name="RBBM_SP_HYST_CNT"/> 775 775 - <reg32 offset="0x00043" name="RBBM_SW_RESET_CMD"/> 776 776 - <reg32 offset="0x00044" name="RBBM_RAC_THRESHOLD_CNT"/> 777 777 - <reg32 offset="0x00045" name="RBBM_BLOCK_SW_RESET_CMD"/> 778 778 - <reg32 offset="0x00046" name="RBBM_BLOCK_SW_RESET_CMD2"/> 779 779 - <reg32 offset="0x000ad" name="RBBM_CLOCK_CNTL_GLOBAL" variants="A7XX-"/> 780 780 - <reg32 offset="0x000ae" name="RBBM_CLOCK_CNTL"/> 781 781 - <reg32 offset="0x000b0" name="RBBM_CLOCK_CNTL_SP0"/> 782 782 - <reg32 offset="0x000b1" name="RBBM_CLOCK_CNTL_SP1"/> 783 783 - <reg32 offset="0x000b2" name="RBBM_CLOCK_CNTL_SP2"/> 784 784 - <reg32 offset="0x000b3" name="RBBM_CLOCK_CNTL_SP3"/> 785 785 - <reg32 offset="0x000b4" name="RBBM_CLOCK_CNTL2_SP0"/> 786 786 - <reg32 offset="0x000b5" name="RBBM_CLOCK_CNTL2_SP1"/> 787 787 - <reg32 offset="0x000b6" name="RBBM_CLOCK_CNTL2_SP2"/> 788 788 - <reg32 offset="0x000b7" name="RBBM_CLOCK_CNTL2_SP3"/> 789 789 - <reg32 offset="0x000b8" name="RBBM_CLOCK_DELAY_SP0"/> 790 790 - <reg32 offset="0x000b9" name="RBBM_CLOCK_DELAY_SP1"/> 791 791 - <reg32 offset="0x000ba" name="RBBM_CLOCK_DELAY_SP2"/> 792 792 - <reg32 offset="0x000bb" name="RBBM_CLOCK_DELAY_SP3"/> 793 793 - <reg32 offset="0x000bc" name="RBBM_CLOCK_HYST_SP0"/> 794 794 - <reg32 offset="0x000bd" name="RBBM_CLOCK_HYST_SP1"/> 795 795 - <reg32 offset="0x000be" name="RBBM_CLOCK_HYST_SP2"/> 796 796 - <reg32 offset="0x000bf" name="RBBM_CLOCK_HYST_SP3"/> 797 797 - <reg32 offset="0x000c0" name="RBBM_CLOCK_CNTL_TP0"/> 798 798 - <reg32 offset="0x000c1" name="RBBM_CLOCK_CNTL_TP1"/> 799 799 - <reg32 offset="0x000c2" name="RBBM_CLOCK_CNTL_TP2"/> 800 800 - <reg32 offset="0x000c3" name="RBBM_CLOCK_CNTL_TP3"/> 801 801 - <reg32 offset="0x000c4" name="RBBM_CLOCK_CNTL2_TP0"/> 802 802 - <reg32 offset="0x000c5" name="RBBM_CLOCK_CNTL2_TP1"/> 803 803 - <reg32 offset="0x000c6" name="RBBM_CLOCK_CNTL2_TP2"/> 804 804 - <reg32 offset="0x000c7" name="RBBM_CLOCK_CNTL2_TP3"/> 805 805 - <reg32 offset="0x000c8" name="RBBM_CLOCK_CNTL3_TP0"/> 806 806 - <reg32 offset="0x000c9" name="RBBM_CLOCK_CNTL3_TP1"/> 807 807 - <reg32 offset="0x000ca" name="RBBM_CLOCK_CNTL3_TP2"/> 808 808 - <reg32 offset="0x000cb" name="RBBM_CLOCK_CNTL3_TP3"/> 809 809 - <reg32 offset="0x000cc" name="RBBM_CLOCK_CNTL4_TP0"/> 810 810 - <reg32 offset="0x000cd" name="RBBM_CLOCK_CNTL4_TP1"/> 811 811 - <reg32 offset="0x000ce" name="RBBM_CLOCK_CNTL4_TP2"/> 812 812 - <reg32 offset="0x000cf" name="RBBM_CLOCK_CNTL4_TP3"/> 813 813 - <reg32 offset="0x000d0" name="RBBM_CLOCK_DELAY_TP0"/> 814 814 - <reg32 offset="0x000d1" name="RBBM_CLOCK_DELAY_TP1"/> 815 815 - <reg32 offset="0x000d2" name="RBBM_CLOCK_DELAY_TP2"/> 816 816 - <reg32 offset="0x000d3" name="RBBM_CLOCK_DELAY_TP3"/> 817 817 - <reg32 offset="0x000d4" name="RBBM_CLOCK_DELAY2_TP0"/> 818 818 - <reg32 offset="0x000d5" name="RBBM_CLOCK_DELAY2_TP1"/> 819 819 - <reg32 offset="0x000d6" name="RBBM_CLOCK_DELAY2_TP2"/> 820 820 - <reg32 offset="0x000d7" name="RBBM_CLOCK_DELAY2_TP3"/> 821 821 - <reg32 offset="0x000d8" name="RBBM_CLOCK_DELAY3_TP0"/> 822 822 - <reg32 offset="0x000d9" name="RBBM_CLOCK_DELAY3_TP1"/> 823 823 - <reg32 offset="0x000da" name="RBBM_CLOCK_DELAY3_TP2"/> 824 824 - <reg32 offset="0x000db" name="RBBM_CLOCK_DELAY3_TP3"/> 825 825 - <reg32 offset="0x000dc" name="RBBM_CLOCK_DELAY4_TP0"/> 826 826 - <reg32 offset="0x000dd" name="RBBM_CLOCK_DELAY4_TP1"/> 827 827 - <reg32 offset="0x000de" name="RBBM_CLOCK_DELAY4_TP2"/> 828 828 - <reg32 offset="0x000df" name="RBBM_CLOCK_DELAY4_TP3"/> 829 829 - <reg32 offset="0x000e0" name="RBBM_CLOCK_HYST_TP0"/> 830 830 - <reg32 offset="0x000e1" name="RBBM_CLOCK_HYST_TP1"/> 831 831 - <reg32 offset="0x000e2" name="RBBM_CLOCK_HYST_TP2"/> 832 832 - <reg32 offset="0x000e3" name="RBBM_CLOCK_HYST_TP3"/> 833 833 - <reg32 offset="0x000e4" name="RBBM_CLOCK_HYST2_TP0"/> 834 834 - <reg32 offset="0x000e5" name="RBBM_CLOCK_HYST2_TP1"/> 835 835 - <reg32 offset="0x000e6" name="RBBM_CLOCK_HYST2_TP2"/> 836 836 - <reg32 offset="0x000e7" name="RBBM_CLOCK_HYST2_TP3"/> 837 837 - <reg32 offset="0x000e8" name="RBBM_CLOCK_HYST3_TP0"/> 838 838 - <reg32 offset="0x000e9" name="RBBM_CLOCK_HYST3_TP1"/> 839 839 - <reg32 offset="0x000ea" name="RBBM_CLOCK_HYST3_TP2"/> 840 840 - <reg32 offset="0x000eb" name="RBBM_CLOCK_HYST3_TP3"/> 841 841 - <reg32 offset="0x000ec" name="RBBM_CLOCK_HYST4_TP0"/> 842 842 - <reg32 offset="0x000ed" name="RBBM_CLOCK_HYST4_TP1"/> 843 843 - <reg32 offset="0x000ee" name="RBBM_CLOCK_HYST4_TP2"/> 844 844 - <reg32 offset="0x000ef" name="RBBM_CLOCK_HYST4_TP3"/> 845 845 - <reg32 offset="0x000f0" name="RBBM_CLOCK_CNTL_RB0"/> 846 846 - <reg32 offset="0x000f1" name="RBBM_CLOCK_CNTL_RB1"/> 847 847 - <reg32 offset="0x000f2" name="RBBM_CLOCK_CNTL_RB2"/> 848 848 - <reg32 offset="0x000f3" name="RBBM_CLOCK_CNTL_RB3"/> 849 849 - <reg32 offset="0x000f4" name="RBBM_CLOCK_CNTL2_RB0"/> 850 850 - <reg32 offset="0x000f5" name="RBBM_CLOCK_CNTL2_RB1"/> 851 851 - <reg32 offset="0x000f6" name="RBBM_CLOCK_CNTL2_RB2"/> 852 852 - <reg32 offset="0x000f7" name="RBBM_CLOCK_CNTL2_RB3"/> 853 853 - <reg32 offset="0x000f8" name="RBBM_CLOCK_CNTL_CCU0"/> 854 854 - <reg32 offset="0x000f9" name="RBBM_CLOCK_CNTL_CCU1"/> 855 855 - <reg32 offset="0x000fa" name="RBBM_CLOCK_CNTL_CCU2"/> 856 856 - <reg32 offset="0x000fb" name="RBBM_CLOCK_CNTL_CCU3"/> 857 857 - <reg32 offset="0x00100" name="RBBM_CLOCK_HYST_RB_CCU0"/> 858 858 - <reg32 offset="0x00101" name="RBBM_CLOCK_HYST_RB_CCU1"/> 859 859 - <reg32 offset="0x00102" name="RBBM_CLOCK_HYST_RB_CCU2"/> 860 860 - <reg32 offset="0x00103" name="RBBM_CLOCK_HYST_RB_CCU3"/> 861 861 - <reg32 offset="0x00104" name="RBBM_CLOCK_CNTL_RAC"/> 862 862 - <reg32 offset="0x00105" name="RBBM_CLOCK_CNTL2_RAC"/> 863 863 - <reg32 offset="0x00106" name="RBBM_CLOCK_DELAY_RAC"/> 864 864 - <reg32 offset="0x00107" name="RBBM_CLOCK_HYST_RAC"/> 865 865 - <reg32 offset="0x00108" name="RBBM_CLOCK_CNTL_TSE_RAS_RBBM"/> 866 866 - <reg32 offset="0x00109" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/> 867 867 - <reg32 offset="0x0010a" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/> 868 868 - <reg32 offset="0x0010b" name="RBBM_CLOCK_CNTL_UCHE"/> 869 869 - <reg32 offset="0x0010c" name="RBBM_CLOCK_CNTL2_UCHE"/> 870 870 - <reg32 offset="0x0010d" name="RBBM_CLOCK_CNTL3_UCHE"/> 871 871 - <reg32 offset="0x0010e" name="RBBM_CLOCK_CNTL4_UCHE"/> 872 872 - <reg32 offset="0x0010f" name="RBBM_CLOCK_DELAY_UCHE"/> 873 873 - <reg32 offset="0x00110" name="RBBM_CLOCK_HYST_UCHE"/> 874 874 - <reg32 offset="0x00111" name="RBBM_CLOCK_MODE_VFD"/> 875 875 - <reg32 offset="0x00112" name="RBBM_CLOCK_DELAY_VFD"/> 876 876 - <reg32 offset="0x00113" name="RBBM_CLOCK_HYST_VFD"/> 877 877 - <reg32 offset="0x00114" name="RBBM_CLOCK_MODE_GPC"/> 878 878 - <reg32 offset="0x00115" name="RBBM_CLOCK_DELAY_GPC"/> 879 879 - <reg32 offset="0x00116" name="RBBM_CLOCK_HYST_GPC"/> 880 880 - <reg32 offset="0x00117" name="RBBM_CLOCK_DELAY_HLSQ_2"/> 881 881 - <reg32 offset="0x00118" name="RBBM_CLOCK_CNTL_GMU_GX"/> 882 882 - <reg32 offset="0x00119" name="RBBM_CLOCK_DELAY_GMU_GX"/> 883 883 - <reg32 offset="0x0011a" name="RBBM_CLOCK_HYST_GMU_GX"/> 884 884 - <reg32 offset="0x0011b" name="RBBM_CLOCK_MODE_HLSQ"/> 885 885 - <reg32 offset="0x0011c" name="RBBM_CLOCK_DELAY_HLSQ"/> 886 886 - <reg32 offset="0x0011d" name="RBBM_CLOCK_HYST_HLSQ"/> 887 887 - <reg32 offset="0x0011e" name="RBBM_CGC_GLOBAL_LOAD_CMD" variants="A7XX-"/> 888 888 - <reg32 offset="0x0011f" name="RBBM_CGC_P2S_TRIG_CMD" variants="A7XX-"/> 889 889 - <reg32 offset="0x00120" name="RBBM_CLOCK_CNTL_TEX_FCHE"/> 890 890 - <reg32 offset="0x00121" name="RBBM_CLOCK_DELAY_TEX_FCHE"/> 473 473 + <reg32 offset="0x01a" name="RBBM_WAIT_IDLE_CLOCKS_CNTL" variants="A6XX-A7XX"/> 474 474 + <reg32 offset="0x01b" name="RBBM_WAIT_IDLE_CLOCKS_CNTL2" variants="A6XX-A7XX"/> 475 475 + <reg32 offset="0x010" name="RBBM_WAIT_IDLE_CLOCKS_CNTL" variants="A8XX-"/> 476 476 + <reg32 offset="0x011" name="RBBM_WAIT_IDLE_CLOCKS_CNTL2" variants="A8XX-"/> 477 477 + 478 478 + <reg32 offset="0x0001f" name="RBBM_INTERFACE_HANG_INT_CNTL" variants="A6XX-A7XX"/> 479 479 + <reg32 offset="0x0002f" name="RBBM_INTERFACE_HANG_INT_CNTL" variants="A8XX-"/> 480 480 + <reg32 offset="0x00037" name="RBBM_INT_CLEAR_CMD" type="A6XX_RBBM_INT_0_MASK" variants="A6XX-A7XX"/> 481 481 + <reg32 offset="0x00061" name="RBBM_INT_CLEAR_CMD" type="A6XX_RBBM_INT_0_MASK" variants="A8XX-"/> 482 482 + <reg32 offset="0x00038" name="RBBM_INT_0_MASK" type="A6XX_RBBM_INT_0_MASK" variants="A6XX-A7XX"/> 483 483 + <reg32 offset="0x00062" name="RBBM_INT_0_MASK" type="A6XX_RBBM_INT_0_MASK" variants="A8XX-"/> 484 484 + <reg32 offset="0x0003a" name="RBBM_INT_2_MASK" variants="A7XX"/> 485 485 + <reg32 offset="0x00064" name="RBBM_INT_2_MASK" variants="A8XX-"/> 486 486 + <reg32 offset="0x00042" name="RBBM_SP_HYST_CNT" variants="A6XX-A7XX"/> 487 487 + <reg32 offset="0x00043" name="RBBM_SW_RESET_CMD" variants="A6XX-A7XX"/> 488 488 + <reg32 offset="0x00073" name="RBBM_SW_RESET_CMD" variants="A8XX-"/> 489 489 + <reg32 offset="0x00044" name="RBBM_RAC_THRESHOLD_CNT" variants="A6XX-A7XX"/> 490 490 + <reg32 offset="0x00029" name="RBBM_RAC_THRESHOLD_CNT" variants="A8XX-"/> 491 491 + <reg32 offset="0x00045" name="RBBM_BLOCK_SW_RESET_CMD" variants="A6XX"/> 492 492 + <reg32 offset="0x00046" name="RBBM_BLOCK_SW_RESET_CMD2" variants="A6XX"/> 493 493 + <reg32 offset="0x000ad" name="RBBM_CLOCK_CNTL_GLOBAL" variants="A7XX"/> 494 494 + <reg32 offset="0x0009a" name="RBBM_CLOCK_CNTL_GLOBAL" variants="A8XX-"/> 495 495 + <reg32 offset="0x07d" name="RBBM_POWER_UP_RESET_SW_OVERRIDE" variants="A8XX-"/> 496 496 + <reg32 offset="0x07e" name="RBBM_POWER_UP_RESET_SW_BV_OVERRIDE" variants="A8XX-"/> 497 497 + <reg32 offset="0x000ae" name="RBBM_CLOCK_CNTL" variants="A6XX-A7XX"/> 498 498 + <reg32 offset="0x000b0" name="RBBM_CLOCK_CNTL_SP0" variants="A6XX-A7XX"/> 499 499 + <reg32 offset="0x000b1" name="RBBM_CLOCK_CNTL_SP1" variants="A6XX-A7XX"/> 500 500 + <reg32 offset="0x000b2" name="RBBM_CLOCK_CNTL_SP2" variants="A6XX-A7XX"/> 501 501 + <reg32 offset="0x000b3" name="RBBM_CLOCK_CNTL_SP3" variants="A6XX-A7XX"/> 502 502 + <reg32 offset="0x000b4" name="RBBM_CLOCK_CNTL2_SP0" variants="A6XX-A7XX"/> 503 503 + <reg32 offset="0x000b5" name="RBBM_CLOCK_CNTL2_SP1" variants="A6XX-A7XX"/> 504 504 + <reg32 offset="0x000b6" name="RBBM_CLOCK_CNTL2_SP2" variants="A6XX-A7XX"/> 505 505 + <reg32 offset="0x000b7" name="RBBM_CLOCK_CNTL2_SP3" variants="A6XX-A7XX"/> 506 506 + <reg32 offset="0x000b8" name="RBBM_CLOCK_DELAY_SP0" variants="A6XX-A7XX"/> 507 507 + <reg32 offset="0x000b9" name="RBBM_CLOCK_DELAY_SP1" variants="A6XX-A7XX"/> 508 508 + <reg32 offset="0x000ba" name="RBBM_CLOCK_DELAY_SP2" variants="A6XX-A7XX"/> 509 509 + <reg32 offset="0x000bb" name="RBBM_CLOCK_DELAY_SP3" variants="A6XX-A7XX"/> 510 510 + <reg32 offset="0x000bc" name="RBBM_CLOCK_HYST_SP0" variants="A6XX-A7XX"/> 511 511 + <reg32 offset="0x000bd" name="RBBM_CLOCK_HYST_SP1" variants="A6XX-A7XX"/> 512 512 + <reg32 offset="0x000be" name="RBBM_CLOCK_HYST_SP2" variants="A6XX-A7XX"/> 513 513 + <reg32 offset="0x000bf" name="RBBM_CLOCK_HYST_SP3" variants="A6XX-A7XX"/> 514 514 + <reg32 offset="0x000c0" name="RBBM_CLOCK_CNTL_TP0" variants="A6XX-A7XX"/> 515 515 + <reg32 offset="0x000c1" name="RBBM_CLOCK_CNTL_TP1" variants="A6XX-A7XX"/> 516 516 + <reg32 offset="0x000c2" name="RBBM_CLOCK_CNTL_TP2" variants="A6XX-A7XX"/> 517 517 + <reg32 offset="0x000c3" name="RBBM_CLOCK_CNTL_TP3" variants="A6XX-A7XX"/> 518 518 + <reg32 offset="0x000c4" name="RBBM_CLOCK_CNTL2_TP0" variants="A6XX-A7XX"/> 519 519 + <reg32 offset="0x000c5" name="RBBM_CLOCK_CNTL2_TP1" variants="A6XX-A7XX"/> 520 520 + <reg32 offset="0x000c6" name="RBBM_CLOCK_CNTL2_TP2" variants="A6XX-A7XX"/> 521 521 + <reg32 offset="0x000c7" name="RBBM_CLOCK_CNTL2_TP3" variants="A6XX-A7XX"/> 522 522 + <reg32 offset="0x000c8" name="RBBM_CLOCK_CNTL3_TP0" variants="A6XX-A7XX"/> 523 523 + <reg32 offset="0x000c9" name="RBBM_CLOCK_CNTL3_TP1" variants="A6XX-A7XX"/> 524 524 + <reg32 offset="0x000ca" name="RBBM_CLOCK_CNTL3_TP2" variants="A6XX-A7XX"/> 525 525 + <reg32 offset="0x000cb" name="RBBM_CLOCK_CNTL3_TP3" variants="A6XX-A7XX"/> 526 526 + <reg32 offset="0x000cc" name="RBBM_CLOCK_CNTL4_TP0" variants="A6XX-A7XX"/> 527 527 + <reg32 offset="0x000cd" name="RBBM_CLOCK_CNTL4_TP1" variants="A6XX-A7XX"/> 528 528 + <reg32 offset="0x000ce" name="RBBM_CLOCK_CNTL4_TP2" variants="A6XX-A7XX"/> 529 529 + <reg32 offset="0x000cf" name="RBBM_CLOCK_CNTL4_TP3" variants="A6XX-A7XX"/> 530 530 + <reg32 offset="0x000d0" name="RBBM_CLOCK_DELAY_TP0" variants="A6XX-A7XX"/> 531 531 + <reg32 offset="0x000d1" name="RBBM_CLOCK_DELAY_TP1" variants="A6XX-A7XX"/> 532 532 + <reg32 offset="0x000d2" name="RBBM_CLOCK_DELAY_TP2" variants="A6XX-A7XX"/> 533 533 + <reg32 offset="0x000d3" name="RBBM_CLOCK_DELAY_TP3" variants="A6XX-A7XX"/> 534 534 + <reg32 offset="0x000d4" name="RBBM_CLOCK_DELAY2_TP0" variants="A6XX-A7XX"/> 535 535 + <reg32 offset="0x000d5" name="RBBM_CLOCK_DELAY2_TP1" variants="A6XX-A7XX"/> 536 536 + <reg32 offset="0x000d6" name="RBBM_CLOCK_DELAY2_TP2" variants="A6XX-A7XX"/> 537 537 + <reg32 offset="0x000d7" name="RBBM_CLOCK_DELAY2_TP3" variants="A6XX-A7XX"/> 538 538 + <reg32 offset="0x000d8" name="RBBM_CLOCK_DELAY3_TP0" variants="A6XX-A7XX"/> 539 539 + <reg32 offset="0x000d9" name="RBBM_CLOCK_DELAY3_TP1" variants="A6XX-A7XX"/> 540 540 + <reg32 offset="0x000da" name="RBBM_CLOCK_DELAY3_TP2" variants="A6XX-A7XX"/> 541 541 + <reg32 offset="0x000db" name="RBBM_CLOCK_DELAY3_TP3" variants="A6XX-A7XX"/> 542 542 + <reg32 offset="0x000dc" name="RBBM_CLOCK_DELAY4_TP0" variants="A6XX-A7XX"/> 543 543 + <reg32 offset="0x000dd" name="RBBM_CLOCK_DELAY4_TP1" variants="A6XX-A7XX"/> 544 544 + <reg32 offset="0x000de" name="RBBM_CLOCK_DELAY4_TP2" variants="A6XX-A7XX"/> 545 545 + <reg32 offset="0x000df" name="RBBM_CLOCK_DELAY4_TP3" variants="A6XX-A7XX"/> 546 546 + <reg32 offset="0x000e0" name="RBBM_CLOCK_HYST_TP0" variants="A6XX-A7XX"/> 547 547 + <reg32 offset="0x000e1" name="RBBM_CLOCK_HYST_TP1" variants="A6XX-A7XX"/> 548 548 + <reg32 offset="0x000e2" name="RBBM_CLOCK_HYST_TP2" variants="A6XX-A7XX"/> 549 549 + <reg32 offset="0x000e3" name="RBBM_CLOCK_HYST_TP3" variants="A6XX-A7XX"/> 550 550 + <reg32 offset="0x000e4" name="RBBM_CLOCK_HYST2_TP0" variants="A6XX-A7XX"/> 551 551 + <reg32 offset="0x000e5" name="RBBM_CLOCK_HYST2_TP1" variants="A6XX-A7XX"/> 552 552 + <reg32 offset="0x000e6" name="RBBM_CLOCK_HYST2_TP2" variants="A6XX-A7XX"/> 553 553 + <reg32 offset="0x000e7" name="RBBM_CLOCK_HYST2_TP3" variants="A6XX-A7XX"/> 554 554 + <reg32 offset="0x000e8" name="RBBM_CLOCK_HYST3_TP0" variants="A6XX-A7XX"/> 555 555 + <reg32 offset="0x000e9" name="RBBM_CLOCK_HYST3_TP1" variants="A6XX-A7XX"/> 556 556 + <reg32 offset="0x000ea" name="RBBM_CLOCK_HYST3_TP2" variants="A6XX-A7XX"/> 557 557 + <reg32 offset="0x000eb" name="RBBM_CLOCK_HYST3_TP3" variants="A6XX-A7XX"/> 558 558 + <reg32 offset="0x000ec" name="RBBM_CLOCK_HYST4_TP0" variants="A6XX-A7XX"/> 559 559 + <reg32 offset="0x000ed" name="RBBM_CLOCK_HYST4_TP1" variants="A6XX-A7XX"/> 560 560 + <reg32 offset="0x000ee" name="RBBM_CLOCK_HYST4_TP2" variants="A6XX-A7XX"/> 561 561 + <reg32 offset="0x000ef" name="RBBM_CLOCK_HYST4_TP3" variants="A6XX-A7XX"/> 562 562 + <reg32 offset="0x000f0" name="RBBM_CLOCK_CNTL_RB0" variants="A6XX-A7XX"/> 563 563 + <reg32 offset="0x000f1" name="RBBM_CLOCK_CNTL_RB1" variants="A6XX-A7XX"/> 564 564 + <reg32 offset="0x000f2" name="RBBM_CLOCK_CNTL_RB2" variants="A6XX-A7XX"/> 565 565 + <reg32 offset="0x000f3" name="RBBM_CLOCK_CNTL_RB3" variants="A6XX-A7XX"/> 566 566 + <reg32 offset="0x000f4" name="RBBM_CLOCK_CNTL2_RB0" variants="A6XX-A7XX"/> 567 567 + <reg32 offset="0x000f5" name="RBBM_CLOCK_CNTL2_RB1" variants="A6XX-A7XX"/> 568 568 + <reg32 offset="0x000f6" name="RBBM_CLOCK_CNTL2_RB2" variants="A6XX-A7XX"/> 569 569 + <reg32 offset="0x000f7" name="RBBM_CLOCK_CNTL2_RB3" variants="A6XX-A7XX"/> 570 570 + <reg32 offset="0x000f8" name="RBBM_CLOCK_CNTL_CCU0" variants="A6XX-A7XX"/> 571 571 + <reg32 offset="0x000f9" name="RBBM_CLOCK_CNTL_CCU1" variants="A6XX-A7XX"/> 572 572 + <reg32 offset="0x000fa" name="RBBM_CLOCK_CNTL_CCU2" variants="A6XX-A7XX"/> 573 573 + <reg32 offset="0x000fb" name="RBBM_CLOCK_CNTL_CCU3" variants="A6XX-A7XX"/> 574 574 + <reg32 offset="0x00100" name="RBBM_CLOCK_HYST_RB_CCU0" variants="A6XX-A7XX"/> 575 575 + <reg32 offset="0x00101" name="RBBM_CLOCK_HYST_RB_CCU1" variants="A6XX-A7XX"/> 576 576 + <reg32 offset="0x00102" name="RBBM_CLOCK_HYST_RB_CCU2" variants="A6XX-A7XX"/> 577 577 + <reg32 offset="0x00103" name="RBBM_CLOCK_HYST_RB_CCU3" variants="A6XX-A7XX"/> 578 578 + <reg32 offset="0x00104" name="RBBM_CLOCK_CNTL_RAC" variants="A6XX-A7XX"/> 579 579 + <reg32 offset="0x00105" name="RBBM_CLOCK_CNTL2_RAC" variants="A6XX-A7XX"/> 580 580 + <reg32 offset="0x00106" name="RBBM_CLOCK_DELAY_RAC" variants="A6XX-A7XX"/> 581 581 + <reg32 offset="0x00107" name="RBBM_CLOCK_HYST_RAC" variants="A6XX-A7XX"/> 582 582 + <reg32 offset="0x00108" name="RBBM_CLOCK_CNTL_TSE_RAS_RBBM" variants="A6XX-A7XX"/> 583 583 + <reg32 offset="0x00109" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM" variants="A6XX-A7XX"/> 584 584 + <reg32 offset="0x0010a" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM" variants="A6XX-A7XX"/> 585 585 + <reg32 offset="0x0010b" name="RBBM_CLOCK_CNTL_UCHE" variants="A6XX-A7XX"/> 586 586 + <reg32 offset="0x0010c" name="RBBM_CLOCK_CNTL2_UCHE" variants="A6XX-A7XX"/> 587 587 + <reg32 offset="0x0010d" name="RBBM_CLOCK_CNTL3_UCHE" variants="A6XX-A7XX"/> 588 588 + <reg32 offset="0x0010e" name="RBBM_CLOCK_CNTL4_UCHE" variants="A6XX-A7XX"/> 589 589 + <reg32 offset="0x0010f" name="RBBM_CLOCK_DELAY_UCHE" variants="A6XX-A7XX"/> 590 590 + <reg32 offset="0x00110" name="RBBM_CLOCK_HYST_UCHE" variants="A6XX-A7XX"/> 591 591 + <reg32 offset="0x00111" name="RBBM_CLOCK_MODE_VFD" variants="A6XX-A7XX"/> 592 592 + <reg32 offset="0x00112" name="RBBM_CLOCK_DELAY_VFD" variants="A6XX-A7XX"/> 593 593 + <reg32 offset="0x00113" name="RBBM_CLOCK_HYST_VFD" variants="A6XX-A7XX"/> 594 594 + <reg32 offset="0x00114" name="RBBM_CLOCK_MODE_GPC" variants="A6XX-A7XX"/> 595 595 + <reg32 offset="0x00115" name="RBBM_CLOCK_DELAY_GPC" variants="A6XX-A7XX"/> 596 596 + <reg32 offset="0x00116" name="RBBM_CLOCK_HYST_GPC" variants="A6XX-A7XX"/> 597 597 + <reg32 offset="0x00117" name="RBBM_CLOCK_DELAY_HLSQ_2" variants="A6XX-A7XX"/> 598 598 + <reg32 offset="0x00118" name="RBBM_CLOCK_CNTL_GMU_GX" variants="A6XX-A7XX"/> 599 599 + <reg32 offset="0x00119" name="RBBM_CLOCK_DELAY_GMU_GX" variants="A6XX-A7XX"/> 600 600 + <reg32 offset="0x0011a" name="RBBM_CLOCK_HYST_GMU_GX" variants="A6XX-A7XX"/> 601 601 + <reg32 offset="0x0011b" name="RBBM_CLOCK_MODE_HLSQ" variants="A6XX-A7XX"/> 602 602 + <reg32 offset="0x0011c" name="RBBM_CLOCK_DELAY_HLSQ" variants="A6XX-A7XX"/> 603 603 + <reg32 offset="0x0011d" name="RBBM_CLOCK_HYST_HLSQ" variants="A6XX-A7XX"/> 604 604 + <reg32 offset="0x0011e" name="RBBM_CGC_GLOBAL_LOAD_CMD" variants="A7XX"/> 605 605 + <reg32 offset="0x0009b" name="RBBM_CGC_GLOBAL_LOAD_CMD" variants="A8XX-"/> 606 606 + <reg32 offset="0x0011f" name="RBBM_CGC_P2S_TRIG_CMD" variants="A7XX"/> 607 607 + <reg32 offset="0x0009c" name="RBBM_CGC_P2S_TRIG_CMD" variants="A8XX-"/> 608 608 + <reg32 offset="0x00120" name="RBBM_CGC_P2S_CNTL" variants="A7XX"/> 609 609 + <reg32 offset="0x0009d" name="RBBM_CGC_P2S_CNTL" variants="A8XX-"/> 610 610 + <reg32 offset="0x00120" name="RBBM_CLOCK_CNTL_TEX_FCHE" variants="A6XX"/> 611 611 + <reg32 offset="0x00121" name="RBBM_CLOCK_DELAY_TEX_FCHE" variants="A6XX-A7XX"/> 891 612 <reg32 offset="0x00122" name="RBBM_CLOCK_HYST_TEX_FCHE" variants="A6XX"/> 892 892 - <reg32 offset="0x00122" name="RBBM_CGC_P2S_STATUS" variants="A7XX-"> 613 613 + <reg32 offset="0x00122" name="RBBM_CGC_P2S_STATUS" variants="A7XX"> 893 614 <bitfield name="TXDONE" pos="0" type="boolean"/> 894 615 </reg32> 895 895 - <reg32 offset="0x00123" name="RBBM_CLOCK_CNTL_FCHE"/> 896 896 - <reg32 offset="0x00124" name="RBBM_CLOCK_DELAY_FCHE"/> 897 897 - <reg32 offset="0x00125" name="RBBM_CLOCK_HYST_FCHE"/> 898 898 - <reg32 offset="0x00126" name="RBBM_CLOCK_CNTL_MHUB"/> 899 899 - <reg32 offset="0x00127" name="RBBM_CLOCK_DELAY_MHUB"/> 900 900 - <reg32 offset="0x00128" name="RBBM_CLOCK_HYST_MHUB"/> 901 901 - <reg32 offset="0x00129" name="RBBM_CLOCK_DELAY_GLC"/> 902 902 - <reg32 offset="0x0012a" name="RBBM_CLOCK_HYST_GLC"/> 903 903 - <reg32 offset="0x0012b" name="RBBM_CLOCK_CNTL_GLC"/> 904 904 - <reg32 offset="0x0012f" name="RBBM_CLOCK_HYST2_VFD" variants="A7XX-"/> 905 905 - <reg32 offset="0x005ff" name="RBBM_LPAC_GBIF_CLIENT_QOS_CNTL"/> 616 616 + <reg32 offset="0x09f" name="RBBM_CGC_P2S_STATUS" variants="A8XX-"> 617 617 + <bitfield name="TXDONE" pos="0" type="boolean"/> 618 618 + </reg32> 619 619 + <reg32 offset="0x00123" name="RBBM_CLOCK_CNTL_FCHE" variants="A6XX-A7XX"/> 620 620 + <reg32 offset="0x00124" name="RBBM_CLOCK_DELAY_FCHE" variants="A6XX-A7XX"/> 621 621 + <reg32 offset="0x00125" name="RBBM_CLOCK_HYST_FCHE" variants="A6XX-A7XX"/> 622 622 + <reg32 offset="0x00126" name="RBBM_CLOCK_CNTL_MHUB" variants="A6XX-A7XX"/> 623 623 + <reg32 offset="0x00127" name="RBBM_CLOCK_DELAY_MHUB" variants="A6XX-A7XX"/> 624 624 + <reg32 offset="0x00128" name="RBBM_CLOCK_HYST_MHUB" variants="A6XX-A7XX"/> 625 625 + <reg32 offset="0x00129" name="RBBM_CLOCK_DELAY_GLC" variants="A6XX-A7XX"/> 626 626 + <reg32 offset="0x0012a" name="RBBM_CLOCK_HYST_GLC" variants="A6XX-A7XX"/> 627 627 + <reg32 offset="0x0012b" name="RBBM_CLOCK_CNTL_GLC" variants="A6XX-A7XX"/> 628 628 + <reg32 offset="0x0012f" name="RBBM_CLOCK_HYST2_VFD" variants="A7XX"/> 629 629 + <reg32 offset="0x00195" name="RBBM_CGC_0_PC" variants="A7XX"/> 630 630 + <reg32 offset="0x0010b" name="RBBM_CGC_0_PC" variants="A8XX-"/> 631 631 + 632 632 + <reg32 offset="0x005ff" name="RBBM_LPAC_GBIF_CLIENT_QOS_CNTL" variants="A6XX-A7XX"/> 633 633 + <reg32 offset="0x00009" name="RBBM_LPAC_GBIF_CLIENT_QOS_CNTL" variants="A8XX-"/> 906 634 907 635 <reg32 offset="0x0600" name="DBGC_CFG_DBGBUS_SEL_A"/> 908 636 <reg32 offset="0x0601" name="DBGC_CFG_DBGBUS_SEL_B"/> ··· 964 610 <reg32 offset="0x0605" name="DBGC_CFG_DBGBUS_CNTLM"> 965 611 <bitfield high="27" low="24" name="ENABLE"/> 966 612 </reg32> 613 613 + <reg32 offset="0x0606" name="DBGC_CFG_DBGBUS_OPL"/> 614 614 + <reg32 offset="0x0607" name="DBGC_CFG_DBGBUS_OPE"/> 967 615 <reg32 offset="0x0608" name="DBGC_CFG_DBGBUS_IVTL_0"/> 968 616 <reg32 offset="0x0609" name="DBGC_CFG_DBGBUS_IVTL_1"/> 969 617 <reg32 offset="0x060a" name="DBGC_CFG_DBGBUS_IVTL_2"/> ··· 994 638 <bitfield high="27" low="24" name="BYTEL14"/> 995 639 <bitfield high="31" low="28" name="BYTEL15"/> 996 640 </reg32> 641 641 + <reg32 offset="0x0612" name="DBGC_CFG_DBGBUS_IVTE_0"/> 642 642 + <reg32 offset="0x0613" name="DBGC_CFG_DBGBUS_IVTE_1"/> 643 643 + <reg32 offset="0x0614" name="DBGC_CFG_DBGBUS_IVTE_2"/> 644 644 + <reg32 offset="0x0615" name="DBGC_CFG_DBGBUS_IVTE_3"/> 645 645 + <reg32 offset="0x0616" name="DBGC_CFG_DBGBUS_MASKE_0"/> 646 646 + <reg32 offset="0x0617" name="DBGC_CFG_DBGBUS_MASKE_1"/> 647 647 + <reg32 offset="0x0618" name="DBGC_CFG_DBGBUS_MASKE_2"/> 648 648 + <reg32 offset="0x0619" name="DBGC_CFG_DBGBUS_MASKE_3"/> 649 649 + <reg32 offset="0x061a" name="DBGC_CFG_DBGBUS_NIBBLEE"/> 650 650 + <reg32 offset="0x061b" name="DBGC_CFG_DBGBUS_PTRC0"/> 651 651 + <reg32 offset="0x061c" name="DBGC_CFG_DBGBUS_PTRC1"/> 652 652 + <reg32 offset="0x061d" name="DBGC_CFG_DBGBUS_LOADREG"/> 653 653 + <reg32 offset="0x061e" name="DBGC_CFG_DBGBUS_IDX"/> 654 654 + <reg32 offset="0x061f" name="DBGC_CFG_DBGBUS_CLRC"/> 655 655 + <reg32 offset="0x0620" name="DBGC_CFG_DBGBUS_LOADIVT"/> 656 656 + <reg32 offset="0x0621" name="DBGC_VBIF_DBG_CNTL"/> 657 657 + <reg32 offset="0x0622" name="DBGC_DBG_LO_HI_GPIO"/> 658 658 + <reg32 offset="0x0623" name="DBGC_EXT_TRACE_BUS_CNTL"/> 659 659 + <reg32 offset="0x0624" name="DBGC_READ_AHB_THROUGH_DBG"/> 660 660 + <reg32 offset="0x0625" name="DBGC_CFG_DBGBUS_EVENT_LOGIC"/> 661 661 + <reg32 offset="0x0626" name="DBGC_CFG_DBGBUS_OVER"/> 662 662 + <reg32 offset="0x0627" name="DBGC_CFG_DBGBUS_COUNT0"/> 663 663 + <reg32 offset="0x0628" name="DBGC_CFG_DBGBUS_COUNT1"/> 664 664 + <reg32 offset="0x0629" name="DBGC_CFG_DBGBUS_COUNT2"/> 665 665 + <reg32 offset="0x062a" name="DBGC_CFG_DBGBUS_COUNT3"/> 666 666 + <reg32 offset="0x062b" name="DBGC_CFG_DBGBUS_COUNT4"/> 667 667 + <reg32 offset="0x062c" name="DBGC_CFG_DBGBUS_COUNT5"/> 668 668 + <reg32 offset="0x062d" name="DBGC_CFG_DBGBUS_TRACE_ADDR"/> 669 669 + <reg32 offset="0x062e" name="DBGC_CFG_DBGBUS_TRACE_BUF0"/> 997 670 <reg32 offset="0x062f" name="DBGC_CFG_DBGBUS_TRACE_BUF1"/> 998 671 <reg32 offset="0x0630" name="DBGC_CFG_DBGBUS_TRACE_BUF2"/> 999 999 - <array offset="0x0CD8" name="VSC_PERFCTR_VSC_SEL" stride="1" length="2" variants="A6XX"/> 1000 1000 - <reg32 offset="0x0CD8" name="VSC_UNKNOWN_0CD8" variants="A7XX"> 1001 1001 - <doc> 1002 1002 - Set to true when binning, isn't changed afterwards 1003 1003 - </doc> 1004 1004 - <bitfield name="BINNING" pos="0" type="boolean"/> 1005 1005 - </reg32> 672 672 + <reg32 offset="0x0631" name="DBGC_CFG_DBGBUS_TRACE_BUF3"/> 673 673 + <reg32 offset="0x0632" name="DBGC_CFG_DBGBUS_TRACE_BUF4"/> 674 674 + <reg32 offset="0x0633" name="DBGC_CFG_DBGBUS_MISR0"/> 675 675 + <reg32 offset="0x0634" name="DBGC_CFG_DBGBUS_MISR1"/> 676 676 + <reg32 offset="0x0635" name="DBGC_EVT_CFG"/> 677 677 + <reg32 offset="0x0636" name="DBGC_EVT_INTF_SEL_0"/> 678 678 + <reg32 offset="0x0637" name="DBGC_EVT_INTF_SEL_1"/> 679 679 + <reg32 offset="0x0638" name="DBGC_EVT_SLICE_CFG"/> 680 680 + <reg32 offset="0x0639" name="DBGC_QDSS_TIMESTAMP_0"/> 681 681 + <reg32 offset="0x063a" name="DBGC_QDSS_TIMESTAMP_1"/> 682 682 + <reg32 offset="0x063b" name="DBGC_ECO_CNTL"/> 683 683 + <reg32 offset="0x063c" name="DBGC_AHB_DBG_CNTL"/> 684 684 + <reg32 offset="0x063d" name="DBGC_EVT_INTF_SEL_2"/> 685 685 + <reg32 offset="0x0640" name="DBGC_CFG_DBGBUS_PONG_SEL_A"/> 686 686 + <reg32 offset="0x0641" name="DBGC_CFG_DBGBUS_PONG_SEL_B"/> 687 687 + <reg32 offset="0x0642" name="DBGC_CFG_DBGBUS_PONG_SEL_C"/> 688 688 + <reg32 offset="0x0643" name="DBGC_CFG_DBGBUS_PONG_SEL_D"/> 689 689 + <reg32 offset="0x0644" name="DBGC_CFG_DBGBUS_MISC_MODE"/> 690 690 + <reg32 offset="0x0650" name="DBGC_EVT_INTF_SEL_3_0"/> 691 691 + <reg32 offset="0x0651" name="DBGC_EVT_INTF_SEL_3_1"/> 692 692 + <reg32 offset="0x0652" name="DBGC_EVT_INTF_SEL_3_2"/> 693 693 + <reg32 offset="0x0653" name="DBGC_EVT_INTF_SEL_3_3"/> 694 694 + <reg32 offset="0x0654" name="DBGC_EVT_INTF_SEL_3_4"/> 695 695 + <reg32 offset="0x0655" name="DBGC_EVT_INTF_SEL_3_5"/> 696 696 + <reg32 offset="0x0660" name="DBGC_TRACE_BUFFER_STATUS"/> 697 697 + <reg32 offset="0x0661" name="DBGC_TRACE_BUFFER_CMD"/> 698 698 + <reg32 offset="0x0662" name="DBGC_DBG_TRACE_BUFFER_RD_ADDR"/> 699 699 + <reg32 offset="0x0663" name="DBGC_DBG_TRACE_BUFFER_RD_DATA"/> 700 700 + <reg32 offset="0x0664" name="DBGC_TRACE_BUFFER_ATB_RD_STATUS"/> 701 701 + <reg32 offset="0x0665" name="DBGC_SMMU_FAULT_BLOCK_HALT_CFG"/> 702 702 + <reg32 offset="0x0666" name="DBGC_DBG_LOPC_SB_RD_ADDR"/> 703 703 + <reg32 offset="0x0667" name="DBGC_DBG_LOPC_SB_RD_DATA"/> 704 704 + <reg32 offset="0x0668" name="DBGC_DBG_LOPC_SB_WR_ADDR"/> 705 705 + <reg32 offset="0x0669" name="DBGC_DBG_LOPC_SB_WR_DATA"/> 706 706 + <reg32 offset="0x066a" name="DBGC_INTERRUPT_STATUS"/> 707 707 + <reg64 offset="0x0680" name="DBGC_GBIF_DBG_BASE"/> 708 708 + <reg32 offset="0x0682" name="DBGC_GBIF_DBG_BUFF_SIZE"/> 709 709 + <reg32 offset="0x0683" name="DBGC_GBIF_DBG_CNTL"/> 710 710 + <reg32 offset="0x0684" name="DBGC_GBIF_DBG_CMD"/> 711 711 + <reg32 offset="0x0685" name="DBGC_GBIF_DBG_STATUS"/> 712 712 + 713 713 + <reg32 offset="0x0700" name="DBGC_SCOPE_PERF_COUNTER_CFG_US" variants="A8XX-"/> 714 714 + <reg32 offset="0x0701" name="DBGC_CFG_PERF_TRIG_CLUSTER_FE_US" variants="A8XX-"/> 715 715 + <reg32 offset="0x0702" name="DBGC_CFG_PERF_TRIG_CLUSTER_VPC_US" variants="A8XX-"/> 716 716 + <reg32 offset="0x0703" name="DBGC_CFG_PERF_TRIG_CLUSTER_SP_VS_US" variants="A8XX-"/> 717 717 + <reg32 offset="0x0704" name="DBGC_CFG_PERF_TRIG_CLUSTER_SP_PS_US" variants="A8XX-"/> 718 718 + <reg32 offset="0x0707" name="DBGC_CFG_PERF_TRIG_CLUSTER_NONE_US" variants="A8XX-"/> 719 719 + <reg32 offset="0x0708" name="DBGC_CFG_BV_PERF_TRIG_CLUSTER_FE_US" variants="A8XX-"/> 720 720 + <reg32 offset="0x0709" name="DBGC_CFG_BV_PERF_TRIG_CLUSTER_VPC_US" variants="A8XX-"/> 721 721 + <reg32 offset="0x070a" name="DBGC_CFG_BV_PERF_TRIG_CLUSTER_SP_VS_US" variants="A8XX-"/> 722 722 + <reg32 offset="0x070f" name="DBGC_CFG_BV_PERF_TRIG_CLUSTER_NONE_US" variants="A8XX-"/> 723 723 + <reg32 offset="0x0710" name="DBGC_CFG_PERF_COUNTER_SEL_FE_US" variants="A8XX-"/> 724 724 + <reg32 offset="0x0711" name="DBGC_CFG_PERF_COUNTER_SEL_FE_US_1" variants="A8XX-"/> 725 725 + <reg32 offset="0x0712" name="DBGC_CFG_PERF_COUNTER_SEL_FE_US_2" variants="A8XX-"/> 726 726 + <reg32 offset="0x0713" name="DBGC_CFG_PERF_COUNTER_SEL_VPC_US" variants="A8XX-"/> 727 727 + <reg32 offset="0x0714" name="DBGC_CFG_PERF_COUNTER_SEL_VPC_US_1" variants="A8XX-"/> 728 728 + <reg32 offset="0x0715" name="DBGC_CFG_PERF_COUNTER_SEL_SP_VS_US" variants="A8XX-"/> 729 729 + <reg32 offset="0x0716" name="DBGC_CFG_PERF_COUNTER_SEL_SP_PS_US" variants="A8XX-"/> 730 730 + <reg32 offset="0x0720" name="DBGC_CFG_PERF_COUNTER_SEL_NONE_US" variants="A8XX-"/> 731 731 + <reg32 offset="0x0721" name="DBGC_CFG_PERF_COUNTER_SEL_NONE_US_1" variants="A8XX-"/> 732 732 + <reg32 offset="0x0722" name="DBGC_CFG_BV_PERF_COUNTER_SEL_FE_US" variants="A8XX-"/> 733 733 + <reg32 offset="0x0723" name="DBGC_CFG_BV_PERF_COUNTER_SEL_FE_US_1" variants="A8XX-"/> 734 734 + <reg32 offset="0x0724" name="DBGC_CFG_BV_PERF_COUNTER_SEL_FE_US_2" variants="A8XX-"/> 735 735 + <reg32 offset="0x0730" name="DBGC_CFG_BV_PERF_COUNTER_SEL_VPC_US" variants="A8XX-"/> 736 736 + <reg32 offset="0x0731" name="DBGC_CFG_BV_PERF_COUNTER_SEL_VPC_US_1" variants="A8XX-"/> 737 737 + <reg32 offset="0x0732" name="DBGC_CFG_BV_PERF_COUNTER_SEL_SP_VS_US" variants="A8XX-"/> 738 738 + <reg32 offset="0x0740" name="DBGC_CFG_BV_PERF_COUNTER_SEL_NONE_US" variants="A8XX-"/> 739 739 + <reg32 offset="0x0742" name="DBGC_CFG_PERF_TIMESTAMP_TRIG_SEL_US" variants="A8XX-"/> 740 740 + <reg32 offset="0x0743" name="DBGC_CFG_BV_PERF_TIMESTAMP_TRIG_SEL_US" variants="A8XX-"/> 741 741 + <reg64 offset="0x0744" name="DBGC_CFG_GBIF_BR_PERF_CNTR_BASE" variants="A8XX-"/> 742 742 + <reg32 offset="0x0746" name="DBGC_CFG_GBIF_BR_BUFFER_SIZE" variants="A8XX-"/> 743 743 + <reg64 offset="0x0747" name="DBGC_CFG_GBIF_BV_PERF_CNTR_BASE" variants="A8XX-"/> 744 744 + <reg32 offset="0x0749" name="DBGC_CFG_GBIF_BV_BUFFER_SIZE" variants="A8XX-"/> 745 745 + <reg32 offset="0x074a" name="DBGC_CFG_GBIF_QOS_CTRL" variants="A8XX-"/> 746 746 + <reg32 offset="0x0750" name="DBGC_GBIF_BR_PERF_CNTR_WRITE_POINTER" variants="A8XX-"/> 747 747 + <reg32 offset="0x0751" name="DBGC_GBIF_BV_PERF_CNTR_WRITE_POINTER" variants="A8XX-"/> 748 748 + <reg32 offset="0x0752" name="DBGC_PERF_COUNTER_FE_LOCAL_BATCH_ID" variants="A8XX-"/> 749 749 + <reg32 offset="0x0753" name="DBGC_CFG_PERF_WAIT_IDLE_CLOCKS_CNTL" variants="A8XX-"/> 750 750 + <reg32 offset="0x0754" name="DBGC_PERF_COUNTER_SCOPING_CMD_US" variants="A8XX-"/> 751 751 + <reg32 offset="0x0755" name="DBGC_PERF_SKEW_BUFFER_INIT_CMD" variants="A8XX-"/> 752 752 + <reg32 offset="0x0759" name="DBGC_LOPC_INTERRUPT_STATUS" variants="A8XX-"/> 753 753 + <reg32 offset="0x075a" name="DBGC_LOPC_BUFFER_PTR_STATUS" variants="A8XX-"/> 754 754 + <reg32 offset="0x075b" name="DBGC_PERF_SCOPING_STATUS" variants="A8XX-"/> 755 755 + <reg32 offset="0x075c" name="DBGC_PERF_COUNTER_PKT_STATUS" variants="A8XX-"/> 756 756 + <reg32 offset="0x0760" name="DBGC_GC_LIVE_MBX_PKT_STATUS" variants="A8XX-"/> 757 757 + <reg32 offset="0x0761" name="DBGC_GC_ALW_MBX_PKT_STATUS" variants="A8XX-"/> 758 758 + <reg32 offset="0x0762" name="DBGC_AO_CNTR_LO_STATUS" variants="A8XX-"/> 759 759 + <reg32 offset="0x0763" name="DBGC_AO_CNTR_HI_STATUS" variants="A8XX-"/> 760 760 + <reg32 offset="0x0770" name="DBGC_LOPC_GC_SB_DEPTH_STATUS" variants="A8XX-"/> 761 761 + <reg32 offset="0x0780" name="DBGC_LPAC_SCOPE_PERF_COUNTER_CFG_US" variants="A8XX-"/> 762 762 + <reg32 offset="0x0781" name="DBGC_CFG_PERF_TRIG_LPAC_US" variants="A8XX-"/> 763 763 + <reg32 offset="0x0782" name="DBGC_CFG_PERF_COUNTER_SEL_LPAC_US" variants="A8XX-"/> 764 764 + <reg32 offset="0x0783" name="DBGC_CFG_PERF_COUNTER_SEL_LPAC_US_1" variants="A8XX-"/> 765 765 + <reg32 offset="0x0784" name="DBGC_CFG_PERF_COUNTER_SEL_LPAC_US_2" variants="A8XX-"/> 766 766 + <reg32 offset="0x0785" name="DBGC_CFG_PERF_TIMESTAMP_TRIG_SEL_LPAC_US" variants="A8XX-"/> 767 767 + <reg64 offset="0x0786" name="DBGC_CFG_GBIF_LPAC_PERF_CNTR_BASE" variants="A8XX-"/> 768 768 + <reg32 offset="0x0788" name="DBGC_CFG_GBIF_LPAC_BUFFER_SIZE" variants="A8XX-"/> 769 769 + <reg32 offset="0x0789" name="DBGC_GBIF_LPAC_PERF_CNTR_WRITE_POINTER" variants="A8XX-"/> 770 770 + <reg32 offset="0x078a" name="DBGC_CFG_LPAC_PERF_WAIT_IDLE_CLOCKS_CNTL" variants="A8XX-"/> 771 771 + <reg32 offset="0x078b" name="DBGC_LPAC_PERF_COUNTER_SCOPING_CMD_US" variants="A8XX-"/> 772 772 + <reg32 offset="0x078c" name="DBGC_LPAC_MBX_PKT_STATUS" variants="A8XX-"/> 773 773 + <reg32 offset="0x078d" name="DBGC_LPAC_PERF_SCOPING_STATUS" variants="A8XX-"/> 774 774 + <reg32 offset="0x0790" name="DBGC_LOPC_LPAC_SB_DEPTH_STATUS" variants="A8XX-"/> 775 775 + <reg32 offset="0x07a0" name="DBGC_SCOPE_PERF_COUNTER_CFG_S" variants="A8XX-"/> 776 776 + <reg32 offset="0x07a1" name="DBGC_CFG_PERF_TRIG_CLUSTER_FE_S" variants="A8XX-"/> 777 777 + <reg32 offset="0x07a2" name="DBGC_CFG_PERF_TRIG_CLUSTER_SP_VS" variants="A8XX-"/> 778 778 + <reg32 offset="0x07a3" name="DBGC_CFG_PERF_TRIG_CLUSTER_VPC_VS" variants="A8XX-"/> 779 779 + <reg32 offset="0x07a4" name="DBGC_CFG_PERF_TRIG_CLUSTER_GRAS" variants="A8XX-"/> 780 780 + <reg32 offset="0x07a5" name="DBGC_CFG_PERF_TRIG_CLUSTER_SP_PS" variants="A8XX-"/> 781 781 + <reg32 offset="0x07a6" name="DBGC_CFG_PERF_TRIG_CLUSTER_VPC_PS" variants="A8XX-"/> 782 782 + <reg32 offset="0x07a7" name="DBGC_CFG_PERF_TRIG_CLUSTER_PS" variants="A8XX-"/> 783 783 + <reg32 offset="0x07a8" name="DBGC_CFG_BV_PERF_TRIG_CLUSTER_FE_S" variants="A8XX-"/> 784 784 + <reg32 offset="0x07a9" name="DBGC_CFG_BV_PERF_TRIG_CLUSTER_SP_VS" variants="A8XX-"/> 785 785 + <reg32 offset="0x07aa" name="DBGC_CFG_BV_PERF_TRIG_CLUSTER_VPC_VS" variants="A8XX-"/> 786 786 + <reg32 offset="0x07ab" name="DBGC_CFG_BV_PERF_TRIG_CLUSTER_GRAS" variants="A8XX-"/> 787 787 + <reg32 offset="0x07ac" name="DBGC_CFG_BV_PERF_TRIG_CLUSTER_VPC_PS" variants="A8XX-"/> 788 788 + <reg32 offset="0x07ad" name="DBGC_CFG_PERF_COUNTER_SEL_FE_S" variants="A8XX-"/> 789 789 + <reg32 offset="0x07ae" name="DBGC_CFG_PERF_COUNTER_SEL_FE_S_1" variants="A8XX-"/> 790 790 + <reg32 offset="0x07af" name="DBGC_CFG_PERF_COUNTER_SEL_FE_S_2" variants="A8XX-"/> 791 791 + <reg32 offset="0x07b0" name="DBGC_CFG_PERF_COUNTER_SEL_FE_S_3" variants="A8XX-"/> 792 792 + <reg32 offset="0x07b1" name="DBGC_CFG_PERF_COUNTER_SEL_SP_VS" variants="A8XX-"/> 793 793 + <reg32 offset="0x07b2" name="DBGC_CFG_PERF_COUNTER_SEL_SP_VS_1" variants="A8XX-"/> 794 794 + <reg32 offset="0x07b3" name="DBGC_CFG_PERF_COUNTER_SEL_SP_VS_2" variants="A8XX-"/> 795 795 + <reg32 offset="0x07b4" name="DBGC_CFG_PERF_COUNTER_SEL_SP_VS_3" variants="A8XX-"/> 796 796 + <reg32 offset="0x07b5" name="DBGC_CFG_PERF_COUNTER_SEL_VPC_VS" variants="A8XX-"/> 797 797 + <reg32 offset="0x07b6" name="DBGC_CFG_PERF_COUNTER_SEL_VPC_VS_1" variants="A8XX-"/> 798 798 + <reg32 offset="0x07b7" name="DBGC_CFG_PERF_COUNTER_SEL_GRAS" variants="A8XX-"/> 799 799 + <reg32 offset="0x07b8" name="DBGC_CFG_PERF_COUNTER_SEL_GRAS_1" variants="A8XX-"/> 800 800 + <reg32 offset="0x07b9" name="DBGC_CFG_PERF_COUNTER_SEL_GRAS_2" variants="A8XX-"/> 801 801 + <reg32 offset="0x07ba" name="DBGC_CFG_PERF_COUNTER_SEL_SP_PS" variants="A8XX-"/> 802 802 + <reg32 offset="0x07bb" name="DBGC_CFG_PERF_COUNTER_SEL_SP_PS_1" variants="A8XX-"/> 803 803 + <reg32 offset="0x07bc" name="DBGC_CFG_PERF_COUNTER_SEL_SP_PS_2" variants="A8XX-"/> 804 804 + <reg32 offset="0x07bd" name="DBGC_CFG_PERF_COUNTER_SEL_SP_PS_3" variants="A8XX-"/> 805 805 + <reg32 offset="0x07be" name="DBGC_CFG_PERF_COUNTER_SEL_VPC_PS" variants="A8XX-"/> 806 806 + <reg32 offset="0x07bf" name="DBGC_CFG_PERF_COUNTER_SEL_VPC_PS_1" variants="A8XX-"/> 807 807 + <reg32 offset="0x07c0" name="DBGC_CFG_PERF_COUNTER_SEL_PS" variants="A8XX-"/> 808 808 + <reg32 offset="0x07c1" name="DBGC_CFG_PERF_COUNTER_SEL_PS_1" variants="A8XX-"/> 809 809 + <reg32 offset="0x07c2" name="DBGC_CFG_PERF_COUNTER_SEL_PS_2" variants="A8XX-"/> 810 810 + <reg32 offset="0x07c3" name="DBGC_CFG_PERF_COUNTER_SEL_PS_3" variants="A8XX-"/> 811 811 + <reg32 offset="0x07c4" name="DBGC_CFG_PERF_TIMESTAMP_TRIG_SEL_S" variants="A8XX-"/> 812 812 + <reg32 offset="0x07c5" name="DBGC_CFG_BV_PERF_COUNTER_SEL_FE_S" variants="A8XX-"/> 813 813 + <reg32 offset="0x07c6" name="DBGC_CFG_BV_PERF_COUNTER_SEL_FE_S_1" variants="A8XX-"/> 814 814 + <reg32 offset="0x07c7" name="DBGC_CFG_BV_PERF_COUNTER_SEL_FE_S_2" variants="A8XX-"/> 815 815 + <reg32 offset="0x07c8" name="DBGC_CFG_BV_PERF_COUNTER_SEL_FE_S_3" variants="A8XX-"/> 816 816 + <reg32 offset="0x07c9" name="DBGC_CFG_BV_PERF_COUNTER_SEL_SP_VS" variants="A8XX-"/> 817 817 + <reg32 offset="0x07ca" name="DBGC_CFG_BV_PERF_COUNTER_SEL_SP_VS_1" variants="A8XX-"/> 818 818 + <reg32 offset="0x07cb" name="DBGC_CFG_BV_PERF_COUNTER_SEL_SP_VS_2" variants="A8XX-"/> 819 819 + <reg32 offset="0x07cc" name="DBGC_CFG_BV_PERF_COUNTER_SEL_SP_VS_3" variants="A8XX-"/> 820 820 + <reg32 offset="0x07cd" name="DBGC_CFG_BV_PERF_COUNTER_SEL_VPC_VS" variants="A8XX-"/> 821 821 + <reg32 offset="0x07ce" name="DBGC_CFG_BV_PERF_COUNTER_SEL_VPC_VS_1" variants="A8XX-"/> 822 822 + <reg32 offset="0x07cf" name="DBGC_CFG_BV_PERF_COUNTER_SEL_GRAS" variants="A8XX-"/> 823 823 + <reg32 offset="0x07d0" name="DBGC_CFG_BV_PERF_COUNTER_SEL_GRAS_1" variants="A8XX-"/> 824 824 + <reg32 offset="0x07d1" name="DBGC_CFG_BV_PERF_COUNTER_SEL_GRAS_2" variants="A8XX-"/> 825 825 + <reg32 offset="0x07d2" name="DBGC_CFG_BV_PERF_COUNTER_SEL_VPC_PS" variants="A8XX-"/> 826 826 + <reg32 offset="0x07d3" name="DBGC_CFG_BV_PERF_COUNTER_SEL_VPC_PS_1" variants="A8XX-"/> 827 827 + <reg32 offset="0x07d4" name="DBGC_CFG_BV_PERF_TIMESTAMP_TRIG_SEL_S" variants="A8XX-"/> 828 828 + <reg32 offset="0x07d5" name="DBGC_PERF_COUNTER_SCOPING_CMD_S" variants="A8XX-"/> 829 829 + <reg32 offset="0x07e0" name="DBGC_LPAC_SCOPE_PERF_COUNTER_CFG_S" variants="A8XX-"/> 830 830 + <reg32 offset="0x07e1" name="DBGC_CFG_PERF_TRIG_LPAC_S" variants="A8XX-"/> 831 831 + <reg32 offset="0x07e2" name="DBGC_CFG_PERF_COUNTER_SEL_LPAC_S" variants="A8XX-"/> 832 832 + <reg32 offset="0x07e3" name="DBGC_CFG_PERF_COUNTER_SEL_LPAC_S_1" variants="A8XX-"/> 833 833 + <reg32 offset="0x07e4" name="DBGC_CFG_PERF_COUNTER_SEL_LPAC_S_2" variants="A8XX-"/> 834 834 + <reg32 offset="0x07e5" name="DBGC_CFG_PERF_TIMESTAMP_TRIG_SEL_LPAC_S" variants="A8XX-"/> 835 835 + <reg32 offset="0x07e6" name="DBGC_LPAC_PERF_COUNTER_SCOPING_CMD_S" variants="A8XX-"/> 836 836 + 837 837 + <array offset="0x0CD8" name="VSC_PERFCTR_VSC_SEL" stride="1" length="2"/> 1006 838 <reg32 offset="0xC800" name="HLSQ_DBG_AHB_READ_APERTURE"/> 1007 839 <reg32 offset="0xD000" name="HLSQ_DBG_READ_SEL"/> 1008 1008 - <reg32 offset="0x0E00" name="UCHE_ADDR_MODE_CNTL" type="a5xx_address_mode"/> 840 840 + <reg32 offset="0x0E00" name="UCHE_ADDR_MODE_CNTL" type="a5xx_address_mode" variants="A6XX"/> 1009 841 <reg32 offset="0x0E01" name="UCHE_MODE_CNTL"/> 1010 1010 - <reg64 offset="0x0E05" name="UCHE_WRITE_RANGE_MAX"/> 1011 1011 - <reg64 offset="0x0E07" name="UCHE_WRITE_THRU_BASE"/> 1012 1012 - <reg64 offset="0x0E09" name="UCHE_TRAP_BASE"/> 1013 1013 - <reg64 offset="0x0E0B" name="UCHE_GMEM_RANGE_MIN"/> 1014 1014 - <reg64 offset="0x0E0D" name="UCHE_GMEM_RANGE_MAX"/> 1015 1015 - <reg32 offset="0x0E17" name="UCHE_CACHE_WAYS" usage="cmd"/> 842 842 + <reg64 offset="0x0E05" name="UCHE_WRITE_RANGE_MAX" variants="A6XX"/> 843 843 + <reg64 offset="0x0E07" name="UCHE_WRITE_THRU_BASE" variants="A6XX-A7XX"/> 844 844 + <reg64 offset="0x0E06" name="UCHE_WRITE_THRU_BASE" variants="A8XX-"/> 845 845 + <reg64 offset="0x0E09" name="UCHE_TRAP_BASE" variants="A6XX-A7XX"/> 846 846 + <reg64 offset="0x0E08" name="UCHE_TRAP_BASE" variants="A8XX-"/> 847 847 + <reg64 offset="0x0E0B" name="UCHE_GMEM_RANGE_MIN" variants="A6XX-A7XX"/> 848 848 + <reg64 offset="0x0E0D" name="UCHE_GMEM_RANGE_MAX" variants="A6XX-A7XX"/> 849 849 + <reg32 offset="0x0e17" name="UCHE_CACHE_WAYS" variants="A6XX-A7XX" usage="init"/> 850 850 + <reg32 offset="0x0e04" name="UCHE_CACHE_WAYS" variants="A8XX-"/> 1016 851 <reg32 offset="0x0E18" name="UCHE_FILTER_CNTL"/> 1017 1017 - <reg32 offset="0x0E19" name="UCHE_CLIENT_PF" usage="cmd"> 852 852 + <reg32 offset="0x0e19" name="UCHE_CLIENT_PF" variants="A6XX-A7XX" usage="init"> 1018 853 <bitfield high="7" low="0" name="PERFSEL"/> 1019 854 </reg32> 1020 1020 - <array offset="0x0E1C" name="UCHE_PERFCTR_UCHE_SEL" stride="1" length="12"/> 1021 1021 - <reg32 offset="0x0e3a" name="UCHE_GBIF_GX_CONFIG"/> 1022 1022 - <reg32 offset="0x0e3c" name="UCHE_CMDQ_CONFIG"/> 855 855 + <array offset="0x0e1c" name="UCHE_PERFCTR_UCHE_SEL" stride="1" length="12" variants="A6XX-A7XX"/> 856 856 + <array offset="0x0e20" name="UCHE_PERFCTR_UCHE_SEL" stride="1" length="24" variants="A8XX-"/> 857 857 + <reg32 offset="0x0e3a" name="UCHE_GBIF_GX_CONFIG" variants="A6XX-A7XX"/> 858 858 + <reg32 offset="0x0e12" name="UCHE_GBIF_GX_CONFIG" variants="A8XX-"/> 859 859 + <reg32 offset="0x0e3c" name="UCHE_CMDQ_CONFIG" variants="A6XX-A7XX"/> 1023 860 1024 1024 - <reg32 offset="0x3000" name="VBIF_VERSION"/> 1025 1025 - <reg32 offset="0x3001" name="VBIF_CLKON"> 861 861 + <reg32 offset="0x0f01" name="UCHE_CCHE_MODE_CNTL" variants="A8XX-"/> 862 862 + <reg32 offset="0x0f02" name="UCHE_CCHE_CACHE_WAYS" variants="A8XX-"/> 863 863 + <reg64 offset="0x0f04" name="UCHE_CCHE_WRITE_THRU_BASE" variants="A8XX-"/> 864 864 + <reg64 offset="0x0f06" name="UCHE_CCHE_TRAP_BASE" variants="A8XX-"/> 865 865 + <reg64 offset="0x0f08" name="UCHE_CCHE_GC_GMEM_RANGE_MIN" variants="A8XX-"/> 866 866 + <reg64 offset="0x0f0a" name="UCHE_CCHE_LPAC_GMEM_RANGE_MIN" variants="A8XX-"/> 867 867 + <reg32 offset="0x0f0c" name="UCHE_CCHE_HW_DBG_CNTL" variants="A8XX-"/> 868 868 + 869 869 + <!-- VBIF only existed on early a6xx, and was later replaced with GBIF --> 870 870 + 871 871 + <reg32 offset="0x3000" name="VBIF_VERSION" variants="A6XX"/> 872 872 + <reg32 offset="0x3001" name="VBIF_CLKON" variants="A6XX"> 1026 873 <bitfield pos="1" name="FORCE_ON_TESTBUS" type="boolean"/> 1027 874 </reg32> 1028 1028 - <reg32 offset="0x302A" name="VBIF_GATE_OFF_WRREQ_EN"/> 1029 1029 - <reg32 offset="0x3080" name="VBIF_XIN_HALT_CTRL0"/> 1030 1030 - <reg32 offset="0x3081" name="VBIF_XIN_HALT_CTRL1"/> 1031 1031 - <reg32 offset="0x3084" name="VBIF_TEST_BUS_OUT_CTRL"/> 1032 1032 - <reg32 offset="0x3085" name="VBIF_TEST_BUS1_CTRL0"/> 1033 1033 - <reg32 offset="0x3086" name="VBIF_TEST_BUS1_CTRL1"> 875 875 + <reg32 offset="0x302A" name="VBIF_GATE_OFF_WRREQ_EN" variants="A6XX"/> 876 876 + <reg32 offset="0x3080" name="VBIF_XIN_HALT_CTRL0" variants="A6XX"/> 877 877 + <reg32 offset="0x3081" name="VBIF_XIN_HALT_CTRL1" variants="A6XX"/> 878 878 + <reg32 offset="0x3084" name="VBIF_TEST_BUS_OUT_CTRL" variants="A6XX"/> 879 879 + <reg32 offset="0x3085" name="VBIF_TEST_BUS1_CTRL0" variants="A6XX"/> 880 880 + <reg32 offset="0x3086" name="VBIF_TEST_BUS1_CTRL1" variants="A6XX"> 1034 881 <bitfield low="0" high="3" name="DATA_SEL"/> 1035 882 </reg32> 1036 1036 - <reg32 offset="0x3087" name="VBIF_TEST_BUS2_CTRL0"/> 1037 1037 - <reg32 offset="0x3088" name="VBIF_TEST_BUS2_CTRL1"> 883 883 + <reg32 offset="0x3087" name="VBIF_TEST_BUS2_CTRL0" variants="A6XX"/> 884 884 + <reg32 offset="0x3088" name="VBIF_TEST_BUS2_CTRL1" variants="A6XX"> 1038 885 <bitfield low="0" high="8" name="DATA_SEL"/> 1039 886 </reg32> 1040 1040 - <reg32 offset="0x308c" name="VBIF_TEST_BUS_OUT"/> 1041 1041 - <reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0"/> 1042 1042 - <reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1"/> 1043 1043 - <reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2"/> 1044 1044 - <reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3"/> 1045 1045 - <reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0"/> 1046 1046 - <reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1"/> 1047 1047 - <reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2"/> 1048 1048 - <reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3"/> 1049 1049 - <reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0"/> 1050 1050 - <reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1"/> 1051 1051 - <reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2"/> 1052 1052 - <reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3"/> 1053 1053 - <reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0"/> 1054 1054 - <reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1"/> 1055 1055 - <reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2"/> 1056 1056 - <reg32 offset="0x3110" name="VBIF_PERF_PWR_CNT_LOW0"/> 1057 1057 - <reg32 offset="0x3111" name="VBIF_PERF_PWR_CNT_LOW1"/> 1058 1058 - <reg32 offset="0x3112" name="VBIF_PERF_PWR_CNT_LOW2"/> 1059 1059 - <reg32 offset="0x3118" name="VBIF_PERF_PWR_CNT_HIGH0"/> 1060 1060 - <reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1"/> 1061 1061 - <reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2"/> 887 887 + <reg32 offset="0x308c" name="VBIF_TEST_BUS_OUT" variants="A6XX"/> 888 888 + <reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0" variants="A6XX"/> 889 889 + <reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1" variants="A6XX"/> 890 890 + <reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2" variants="A6XX"/> 891 891 + <reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3" variants="A6XX"/> 892 892 + <reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0" variants="A6XX"/> 893 893 + <reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1" variants="A6XX"/> 894 894 + <reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2" variants="A6XX"/> 895 895 + <reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3" variants="A6XX"/> 896 896 + <reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0" variants="A6XX"/> 897 897 + <reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1" variants="A6XX"/> 898 898 + <reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2" variants="A6XX"/> 899 899 + <reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3" variants="A6XX"/> 900 900 + <reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0" variants="A6XX"/> 901 901 + <reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1" variants="A6XX"/> 902 902 + <reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2" variants="A6XX"/> 903 903 + <reg32 offset="0x3110" name="VBIF_PERF_PWR_CNT_LOW0" variants="A6XX"/> 904 904 + <reg32 offset="0x3111" name="VBIF_PERF_PWR_CNT_LOW1" variants="A6XX"/> 905 905 + <reg32 offset="0x3112" name="VBIF_PERF_PWR_CNT_LOW2" variants="A6XX"/> 906 906 + <reg32 offset="0x3118" name="VBIF_PERF_PWR_CNT_HIGH0" variants="A6XX"/> 907 907 + <reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1" variants="A6XX"/> 908 908 + <reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2" variants="A6XX"/> 1062 909 910 910 + <reg32 offset="0x3c00" name="GBIF_CX_CONFIG" variants="A8XX-"/> 1063 911 <reg32 offset="0x3c01" name="GBIF_SCACHE_CNTL0"/> 1064 912 <reg32 offset="0x3c02" name="GBIF_SCACHE_CNTL1"/> 1065 913 <reg32 offset="0x3c03" name="GBIF_QSB_SIDE0"/> ··· 1272 712 <reg32 offset="0x3c06" name="GBIF_QSB_SIDE3"/> 1273 713 <reg32 offset="0x3c45" name="GBIF_HALT"/> 1274 714 <reg32 offset="0x3c46" name="GBIF_HALT_ACK"/> 715 715 + <reg32 offset="0x3c49" name="GBIF_REINIT_ENABLE" variants="A8XX-"/> 716 716 + <reg32 offset="0x3c4a" name="GBIF_REINIT_DONE" variants="A8XX-"/> 1275 717 <reg32 offset="0x3cc0" name="GBIF_PERF_PWR_CNT_EN"/> 1276 718 <reg32 offset="0x3cc1" name="GBIF_PERF_PWR_CNT_CLR"/> 1277 719 <reg32 offset="0x3cc2" name="GBIF_PERF_CNT_SEL"/> 1278 1278 - <reg32 offset="0x3cc3" name="GBIF_PERF_PWR_CNT_SEL"/> 1279 1279 - <reg32 offset="0x3cc4" name="GBIF_PERF_CNT_LOW0"/> 1280 1280 - <reg32 offset="0x3cc5" name="GBIF_PERF_CNT_LOW1"/> 1281 1281 - <reg32 offset="0x3cc6" name="GBIF_PERF_CNT_LOW2"/> 1282 1282 - <reg32 offset="0x3cc7" name="GBIF_PERF_CNT_LOW3"/> 1283 1283 - <reg32 offset="0x3cc8" name="GBIF_PERF_CNT_HIGH0"/> 1284 1284 - <reg32 offset="0x3cc9" name="GBIF_PERF_CNT_HIGH1"/> 1285 1285 - <reg32 offset="0x3cca" name="GBIF_PERF_CNT_HIGH2"/> 1286 1286 - <reg32 offset="0x3ccb" name="GBIF_PERF_CNT_HIGH3"/> 1287 1287 - <reg32 offset="0x3ccc" name="GBIF_PWR_CNT_LOW0"/> 1288 1288 - <reg32 offset="0x3ccd" name="GBIF_PWR_CNT_LOW1"/> 1289 1289 - <reg32 offset="0x3cce" name="GBIF_PWR_CNT_LOW2"/> 1290 1290 - <reg32 offset="0x3ccf" name="GBIF_PWR_CNT_HIGH0"/> 1291 1291 - <reg32 offset="0x3cd0" name="GBIF_PWR_CNT_HIGH1"/> 1292 1292 - <reg32 offset="0x3cd1" name="GBIF_PWR_CNT_HIGH2"/> 720 720 + <reg32 offset="0x3cc3" name="GBIF_PERF_CNT_SEL_1" variants="A8XX-"/> 721 721 + 722 722 + <reg32 offset="0x3cc3" name="GBIF_PERF_PWR_CNT_SEL" variants="A6XX-A7XX"/> 723 723 + <reg32 offset="0x3cc4" name="GBIF_PERF_CNT_LOW0" variants="A6XX-A7XX"/> 724 724 + <reg32 offset="0x3cc5" name="GBIF_PERF_CNT_LOW1" variants="A6XX-A7XX"/> 725 725 + <reg32 offset="0x3cc6" name="GBIF_PERF_CNT_LOW2" variants="A6XX-A7XX"/> 726 726 + <reg32 offset="0x3cc7" name="GBIF_PERF_CNT_LOW3" variants="A6XX-A7XX"/> 727 727 + <reg32 offset="0x3cc8" name="GBIF_PERF_CNT_HIGH0" variants="A6XX-A7XX"/> 728 728 + <reg32 offset="0x3cc9" name="GBIF_PERF_CNT_HIGH1" variants="A6XX-A7XX"/> 729 729 + <reg32 offset="0x3cca" name="GBIF_PERF_CNT_HIGH2" variants="A6XX-A7XX"/> 730 730 + <reg32 offset="0x3ccb" name="GBIF_PERF_CNT_HIGH3" variants="A6XX-A7XX"/> 731 731 + <reg32 offset="0x3ccc" name="GBIF_PWR_CNT_LOW0" variants="A6XX-A7XX"/> 732 732 + <reg32 offset="0x3ccd" name="GBIF_PWR_CNT_LOW1" variants="A6XX-A7XX"/> 733 733 + <reg32 offset="0x3cce" name="GBIF_PWR_CNT_LOW2" variants="A6XX-A7XX"/> 734 734 + <reg32 offset="0x3ccf" name="GBIF_PWR_CNT_HIGH0" variants="A6XX-A7XX"/> 735 735 + <reg32 offset="0x3cd0" name="GBIF_PWR_CNT_HIGH1" variants="A6XX-A7XX"/> 736 736 + <reg32 offset="0x3cd1" name="GBIF_PWR_CNT_HIGH2" variants="A6XX-A7XX"/> 737 737 + 738 738 + <reg32 offset="0x3cc4" name="GBIF_PWR_CNT_SEL" variants="A8XX"/> 739 739 + <reg32 offset="0x3cc6" name="GBIF_PERF_CNT_LO_0" variants="A8XX"/> 740 740 + <reg32 offset="0x3cc7" name="GBIF_PERF_CNT_HI_0" variants="A8XX"/> 741 741 + <reg32 offset="0x3cc8" name="GBIF_PERF_CNT_LO_1" variants="A8XX"/> 742 742 + <reg32 offset="0x3cc9" name="GBIF_PERF_CNT_HI_1" variants="A8XX"/> 743 743 + <reg32 offset="0x3cca" name="GBIF_PERF_CNT_LO_2" variants="A8XX"/> 744 744 + <reg32 offset="0x3ccb" name="GBIF_PERF_CNT_HI_2" variants="A8XX"/> 745 745 + <reg32 offset="0x3ccc" name="GBIF_PERF_CNT_LO_3" variants="A8XX"/> 746 746 + <reg32 offset="0x3ccd" name="GBIF_PERF_CNT_HI_3" variants="A8XX"/> 747 747 + <reg32 offset="0x3cce" name="GBIF_PERF_CNT_LO_4" variants="A8XX"/> 748 748 + <reg32 offset="0x3ccf" name="GBIF_PERF_CNT_HI_4" variants="A8XX"/> 749 749 + <reg32 offset="0x3cd0" name="GBIF_PERF_CNT_LO_5" variants="A8XX"/> 750 750 + <reg32 offset="0x3cd1" name="GBIF_PERF_CNT_HI_5" variants="A8XX"/> 751 751 + <reg32 offset="0x3cd2" name="GBIF_PERF_CNT_LO_6" variants="A8XX"/> 752 752 + <reg32 offset="0x3cd3" name="GBIF_PERF_CNT_HI_6" variants="A8XX"/> 753 753 + <reg32 offset="0x3cd4" name="GBIF_PERF_CNT_LO_7" variants="A8XX"/> 754 754 + <reg32 offset="0x3cd5" name="GBIF_PERF_CNT_HI_7" variants="A8XX"/> 755 755 + <reg32 offset="0x3ce0" name="GBIF_PWR_CNT_LO_0" variants="A8XX"/> 756 756 + <reg32 offset="0x3ce1" name="GBIF_PWR_CNT_LO_1" variants="A8XX"/> 757 757 + <reg32 offset="0x3ce2" name="GBIF_PWR_CNT_LO_2" variants="A8XX"/> 758 758 + <reg32 offset="0x3ce3" name="GBIF_PWR_CNT_HI_0" variants="A8XX"/> 759 759 + <reg32 offset="0x3ce4" name="GBIF_PWR_CNT_HI_1" variants="A8XX"/> 760 760 + <reg32 offset="0x3ce5" name="GBIF_PWR_CNT_HI_2" variants="A8XX"/> 1293 761 1294 762 <reg32 offset="0x0c00" name="VSC_DBG_ECO_CNTL"/> 1295 1295 - <reg32 offset="0x0c02" name="VSC_BIN_SIZE" usage="rp_blit"> 1296 1296 - <bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/> 1297 1297 - <bitfield name="HEIGHT" low="8" high="16" shr="4" type="uint"/> 763 763 + <reg32 offset="0x0df0" name="VSC_KMD_DBG_ECO_CNTL" variants="A8XX-"/> 764 764 + <reg32 offset="0x0c02" name="VSC_BIN_SIZE" usage="rp_blit" variants="A6XX-A7XX"> 765 765 + <bitfield name="BINW" low="0" high="7" shr="5" type="uint"/> 766 766 + <bitfield name="BINH" low="8" high="16" shr="4" type="uint"/> 1298 767 </reg32> 768 768 + 769 769 + <bitset name="a8xx_bin_size" inline="yes"> 770 770 + <bitfield name="BINW" low="0" high="9" shr="5" type="uint"/> 771 771 + <bitfield name="BINH" low="16" high="26" shr="4" type="uint"/> 772 772 + </bitset> 773 773 + 774 774 + <reg32 offset="0x0c02" name="VSC_BIN_SIZE" type="a8xx_bin_size" usage="rp_blit" variants="A8XX"/> 1299 775 <reg64 offset="0x0c03" name="VSC_SIZE_BASE" type="waddress" usage="cmd"/> 1300 776 <reg32 offset="0x0c06" name="VSC_EXPANDED_BIN_CNTL" usage="rp_blit"> 1301 777 <bitfield name="NX" low="1" high="10" type="uint"/> ··· 1399 803 1400 804 <reg32 offset="0x0d08" name="VSC_UNKNOWN_0D08" variants="A7XX-" usage="rp_blit"/> 1401 805 1402 1402 - <reg32 offset="0x0E10" name="UCHE_UNKNOWN_0E10" variants="A7XX-" usage="cmd"/> 1403 1403 - <reg32 offset="0x0E11" name="UCHE_UNKNOWN_0E11" variants="A7XX-" usage="cmd"/> 806 806 + <reg32 offset="0x0e10" name="UCHE_UNKNOWN_0E10" variants="A7XX" usage="init"/> 807 807 + <reg32 offset="0x0e10" name="UCHE_VARB_IDLE_TIMEOUT" variants="A8XX-"/> 808 808 + <reg32 offset="0x0e11" name="UCHE_UNKNOWN_0E11" variants="A7XX" usage="init"/> 809 809 + <reg32 offset="0x0e11" name="UCHE_CLIENT_PF" variants="A8XX-"/> 1404 810 <!-- always 0x03200000 ? --> 1405 1405 - <reg32 offset="0x0e12" name="UCHE_UNKNOWN_0E12" usage="cmd"/> 811 811 + <reg32 offset="0x0e12" name="UCHE_UNKNOWN_0E12" variants="A6XX-A7XX" usage="init"/> 812 812 + <reg32 offset="0x0e15" name="UCHE_DBG_ECO_CNTL_0" variants="A8XX-"/> 813 813 + <reg32 offset="0x0e16" name="UCHE_HW_DBG_CNTL" variants="A8XX-"/> 1406 814 1407 815 <!-- adreno_reg_xy has 15 bits per coordinate, but a6xx registers only have 14 --> 1408 816 <bitset name="a6xx_reg_xy" inline="yes"> ··· 1429 829 </bitset> 1430 830 1431 831 <reg32 offset="0x8000" name="GRAS_CL_CNTL" type="a6xx_gras_cl_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 832 832 + <reg32 offset="0x8200" name="GRAS_CL_CNTL" type="a6xx_gras_cl_cntl" variants="A8XX-" usage="rp_blit"/> 1432 833 1433 834 <bitset name="a6xx_gras_xs_clip_cull_distance" inline="yes"> 1434 835 <bitfield name="CLIP_MASK" low="0" high="7"/> ··· 1439 838 <reg32 offset="0x8002" name="GRAS_CL_DS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="rp_blit" variants="A6XX-A7XX" /> 1440 839 <reg32 offset="0x8003" name="GRAS_CL_GS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="rp_blit" variants="A6XX-A7XX" /> 1441 840 <reg32 offset="0x8004" name="GRAS_CL_ARRAY_SIZE" low="0" high="10" type="uint" usage="rp_blit" variants="A6XX-A7XX" /> 841 841 + 842 842 + <reg32 offset="0x8201" name="GRAS_CL_VS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="rp_blit" variants="A8XX" /> 843 843 + <reg32 offset="0x8202" name="GRAS_CL_DS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="rp_blit" variants="A8XX" /> 844 844 + <reg32 offset="0x8203" name="GRAS_CL_GS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="rp_blit" variants="A8XX" /> 845 845 + <reg32 offset="0x8204" name="GRAS_CL_ARRAY_SIZE" low="0" high="10" type="uint" usage="rp_blit" variants="A8XX" /> 846 846 + 847 847 + <reg32 offset="0x8228" name="GRAS_UNKNOWN_8228" variants="A8XX-"/> 848 848 + <reg32 offset="0x8229" name="GRAS_UNKNOWN_8229" variants="A8XX-"/> 849 849 + <reg32 offset="0x822a" name="GRAS_UNKNOWN_822A" variants="A8XX-"/> 850 850 + <reg32 offset="0x822b" name="GRAS_UNKNOWN_822B" variants="A8XX-"/> 851 851 + <reg32 offset="0x822c" name="GRAS_UNKNOWN_822C" variants="A8XX-"/> 852 852 + <reg32 offset="0x822d" name="GRAS_UNKNOWN_822D" variants="A8XX-"/> 1442 853 1443 854 <bitset name="a6xx_gras_cl_interp_cntl" inline="yes"> 1444 855 <!-- see also RB_INTERP_CNTL --> ··· 1466 853 </bitset> 1467 854 1468 855 <reg32 offset="0x8005" name="GRAS_CL_INTERP_CNTL" type="a6xx_gras_cl_interp_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 856 856 + <reg32 offset="0x8080" name="GRAS_CL_INTERP_CNTL" type="a6xx_gras_cl_interp_cntl" variants="A8XX-" usage="rp_blit"/> 1469 857 1470 858 <bitset name="a6xx_gras_cl_guardband_clip_adj" inline="true"> 1471 859 <bitfield name="HORZ" low="0" high="8" type="uint"/> ··· 1474 860 </bitset> 1475 861 1476 862 <reg32 offset="0x8006" name="GRAS_CL_GUARDBAND_CLIP_ADJ" type="a6xx_gras_cl_guardband_clip_adj" variants="A6XX-A7XX" usage="rp_blit"/> 1477 1477 - 1478 1478 - <!-- Something connected to depth-stencil attachment size --> 1479 1479 - <reg32 offset="0x8007" name="GRAS_UNKNOWN_8007" variants="A7XX-" usage="rp_blit"/> 863 863 + <reg32 offset="0x8205" name="GRAS_CL_GUARDBAND_CLIP_ADJ" type="a6xx_gras_cl_guardband_clip_adj" variants="A8XX-" usage="rp_blit"/> 1480 864 1481 865 <!-- the scale/offset is per view, with up to 6 views --> 1482 866 <bitset name="a6xx_gras_bin_foveat" inline="yes"> ··· 1499 887 </bitset> 1500 888 1501 889 <reg32 offset="0x8008" name="GRAS_BIN_FOVEAT" type="a6xx_gras_bin_foveat" variants="A7XX" usage="cmd"/> 890 890 + <reg32 offset="0x8206" name="GRAS_BIN_FOVEAT" type="a6xx_gras_bin_foveat" variants="A8XX-" usage="cmd"/> 1502 891 1503 892 <reg32 offset="0x8009" name="GRAS_BIN_FOVEAT_OFFSET_0" variants="A7XX-" usage="cmd"> 1504 893 <bitfield name="XOFFSET_0" low="0" high="9" shr="2" type="uint"/> ··· 1534 921 <reg32 offset="5" name="ZSCALE" type="float"/> 1535 922 </array> 1536 923 924 924 + <array offset="0x82d0" name="GRAS_CL_VIEWPORT" stride="6" length="16" variants="A8XX-" usage="rp_blit"> 925 925 + <reg32 offset="0" name="XOFFSET" type="float"/> 926 926 + <reg32 offset="1" name="XSCALE" type="float"/> 927 927 + <reg32 offset="2" name="YOFFSET" type="float"/> 928 928 + <reg32 offset="3" name="YSCALE" type="float"/> 929 929 + <reg32 offset="4" name="ZOFFSET" type="float"/> 930 930 + <reg32 offset="5" name="ZSCALE" type="float"/> 931 931 + </array> 932 932 + 1537 933 <array offset="0x8070" name="GRAS_CL_VIEWPORT_ZCLAMP" stride="2" length="16" variants="A6XX-A7XX" usage="rp_blit"> 934 934 + <reg32 offset="0" name="MIN" type="float"/> 935 935 + <reg32 offset="1" name="MAX" type="float"/> 936 936 + </array> 937 937 + <array offset="0x80c0" name="GRAS_CL_VIEWPORT_ZCLAMP" stride="2" length="16" variants="A8XX-" usage="rp_blit"> 1538 938 <reg32 offset="0" name="MIN" type="float"/> 1539 939 <reg32 offset="1" name="MAX" type="float"/> 1540 940 </array> ··· 1577 951 <bitfield name="UNK20" low="20" high="22" variants="A6XX-A7XX"/> 1578 952 </bitset> 1579 953 <reg32 offset="0x8090" name="GRAS_SU_CNTL" type="a6xx_gras_su_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 954 954 + <reg32 offset="0x8209" name="GRAS_SU_CNTL" type="a6xx_gras_su_cntl" variants="A8XX-" usage="rp_blit"/> 955 955 + 956 956 + <!-- Fields moved from GRAS_SU_CNTL on earlier gens: --> 957 957 + <reg32 offset="0x820c" name="GRAS_SU_STEREO_CNTL" variants="A8XX-" usage="rp_blit"> 958 958 + <bitfield name="RENDERTARGETINDEXINCR" pos="18" type="boolean"/> 959 959 + <bitfield name="VIEWPORTINDEXINCR" pos="19" type="boolean"/> 960 960 + </reg32> 1580 961 1581 962 <bitset name="a6xx_gras_su_point_minmax" inline="yes"> 1582 963 <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/> ··· 1591 958 </bitset> 1592 959 1593 960 <reg32 offset="0x8091" name="GRAS_SU_POINT_MINMAX" type="a6xx_gras_su_point_minmax" variants="A6XX-A7XX" usage="rp_blit"/> 961 961 + <reg32 offset="0x820a" name="GRAS_SU_POINT_MINMAX" type="a6xx_gras_su_point_minmax" variants="A8XX-" usage="rp_blit"/> 962 962 + 1594 963 <reg32 offset="0x8092" name="GRAS_SU_POINT_SIZE" low="0" high="15" type="fixed" radix="4" variants="A6XX-A7XX" usage="rp_blit"/> 964 964 + <reg32 offset="0x820b" name="GRAS_SU_POINT_SIZE" low="0" high="15" type="fixed" radix="4" variants="A8XX-" usage="rp_blit"/> 1595 965 1596 966 <bitset name="a6xx_gras_su_depth_cntl" inline="yes"> 1597 967 <bitfield name="Z_TEST_ENABLE" pos="0" type="boolean"/> 1598 968 </bitset> 1599 969 1600 970 <reg32 offset="0x8114" name="GRAS_SU_DEPTH_CNTL" variants="A6XX-A7XX" type="a6xx_gras_su_depth_cntl" usage="rp_blit"/> 971 971 + <reg32 offset="0x8086" name="GRAS_SU_DEPTH_CNTL" variants="A8XX-" type="a6xx_gras_su_depth_cntl" usage="rp_blit"/> 1601 972 1602 973 <bitset name="a6xx_gras_su_stencil_cntl" inline="yes"> 1603 974 <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/> 1604 975 </bitset> 1605 976 1606 977 <reg32 offset="0x8115" name="GRAS_SU_STENCIL_CNTL" type="a6xx_gras_su_stencil_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 978 978 + <reg32 offset="0x8087" name="GRAS_SU_STENCIL_CNTL" type="a6xx_gras_su_stencil_cntl" variants="A8XX-" usage="rp_blit"/> 1607 979 1608 980 <bitset name="a6xx_gras_su_render_cntl" inline="yes"> 1609 981 <bitfield name="FS_DISABLE" pos="7" type="boolean"/> 1610 982 </bitset> 1611 983 1612 984 <reg32 offset="0x8116" name="GRAS_SU_RENDER_CNTL" type="a6xx_gras_su_render_cntl" variants="A7XX" usage="rp_blit"/> 985 985 + <reg32 offset="0x8088" name="GRAS_SU_RENDER_CNTL" type="a6xx_gras_su_render_cntl" variants="A8XX-" usage="rp_blit"/> 1613 986 1614 987 <!-- 0x8093 invalid --> 1615 988 <bitset name="a6xx_depth_plane_cntl" inline="yes"> ··· 1623 984 </bitset> 1624 985 1625 986 <reg32 offset="0x8094" name="GRAS_SU_DEPTH_PLANE_CNTL" type="a6xx_depth_plane_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 987 987 + <reg32 offset="0x8089" name="GRAS_SU_DEPTH_PLANE_CNTL" type="a6xx_depth_plane_cntl" variants="A8XX-" usage="rp_blit"/> 988 988 + 1626 989 <reg32 offset="0x8095" name="GRAS_SU_POLY_OFFSET_SCALE" type="float" variants="A6XX-A7XX" usage="rp_blit"/> 990 990 + <reg32 offset="0x808a" name="GRAS_SU_POLY_OFFSET_SCALE" type="float" variants="A8XX-" usage="rp_blit"/> 991 991 + 1627 992 <reg32 offset="0x8096" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float" variants="A6XX-A7XX" usage="rp_blit"/> 993 993 + <reg32 offset="0x808b" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float" variants="A8XX-" usage="rp_blit"/> 994 994 + 1628 995 <reg32 offset="0x8097" name="GRAS_SU_POLY_OFFSET_OFFSET_CLAMP" type="float" variants="A6XX-A7XX" usage="rp_blit"/> 996 996 + <reg32 offset="0x808c" name="GRAS_SU_POLY_OFFSET_OFFSET_CLAMP" type="float" variants="A8XX-" usage="rp_blit"/> 997 997 + 1629 998 <bitset name="a6xx_depth_buffer_info" inline="yes"> 1630 999 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/> 1631 1631 - <bitfield name="UNK3" pos="3"/> 1000 1000 + <bitfield name="READ_ONLY" pos="3" type="boolean"/> 1632 1001 </bitset> 1633 1002 1634 1003 <!-- duplicates RB_DEPTH_BUFFER_INFO: --> 1635 1004 <reg32 offset="0x8098" name="GRAS_SU_DEPTH_BUFFER_INFO" type="a6xx_depth_buffer_info" variants="A6XX-A7XX" usage="rp_blit"/> 1005 1005 + <reg32 offset="0x808d" name="GRAS_SU_DEPTH_BUFFER_INFO" type="a6xx_depth_buffer_info" variants="A8XX-" usage="rp_blit"/> 1636 1006 1637 1007 <bitset name="a6xx_gras_su_conservative_ras_cntl" inline="yes"> 1638 1008 <bitfield name="CONSERVATIVERASEN" pos="0" type="boolean"/> ··· 1656 1008 </bitset> 1657 1009 1658 1010 <reg32 offset="0x8099" name="GRAS_SU_CONSERVATIVE_RAS_CNTL" type="a6xx_gras_su_conservative_ras_cntl" variants="A6XX-A7XX" usage="cmd"/> 1011 1011 + <reg32 offset="0x820d" name="GRAS_SU_CONSERVATIVE_RAS_CNTL" type="a6xx_gras_su_conservative_ras_cntl" variants="A8XX-" usage="cmd"/> 1659 1012 1660 1013 <reg32 offset="0x809a" name="GRAS_SU_PATH_RENDERING_CNTL"> 1661 1014 <bitfield name="UNK0" pos="0" type="boolean"/> ··· 1671 1022 <reg32 offset="0x809c" name="GRAS_SU_GS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1672 1023 <reg32 offset="0x809d" name="GRAS_SU_DS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1673 1024 1025 1025 + <reg32 offset="0x820e" name="GRAS_SU_VS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" variants="A8XX" usage="rp_blit"/> 1026 1026 + <reg32 offset="0x820f" name="GRAS_SU_GS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" variants="A8XX" usage="rp_blit"/> 1027 1027 + <reg32 offset="0x8210" name="GRAS_SU_DS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" variants="A8XX" usage="rp_blit"/> 1028 1028 + 1674 1029 <bitset name="a6xx_rast_cntl" inline="yes"> 1675 1030 <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/> 1676 1031 </bitset> 1032 1032 + 1033 1033 + <reg32 offset="0x8211" name="GRAS_RAST_CNTL" type="a6xx_rast_cntl" variants="A8XX-" usage="rp_blit"/> 1677 1034 1678 1035 <enum name="a6xx_sequenced_thread_dist"> 1679 1036 <value value="0x0" name="DIST_SCREEN_COORD"/> ··· 1728 1073 </enum> 1729 1074 1730 1075 <bitset name="a6xx_gras_sc_cntl" inline="yes"> 1731 1731 - <bitfield name="CCUSINGLECACHELINESIZE" low="0" high="2"/> 1732 1076 <bitfield name="SINGLE_PRIM_MODE" low="3" high="4" type="a6xx_single_prim_mode"/> 1733 1077 <bitfield name="RASTER_MODE" pos="5" type="a6xx_raster_mode"/> 1734 1078 <bitfield name="RASTER_DIRECTION" low="6" high="7" type="a6xx_raster_direction"/> ··· 1738 1084 <bitfield name="EARLYVIZOUTEN" pos="12" type="boolean"/> 1739 1085 </bitset> 1740 1086 1741 1741 - <reg32 offset="0x80a0" name="GRAS_SC_CNTL" type="a6xx_gras_sc_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1087 1087 + <reg32 offset="0x80a0" name="GRAS_SC_CNTL" type="a6xx_gras_sc_cntl" variants="A6XX-A7XX" usage="rp_blit"> 1088 1088 + <bitfield name="CCUSINGLECACHELINESIZE" low="0" high="2" variants="A6XX-A7XX"/> 1089 1089 + </reg32> 1090 1090 + <reg32 offset="0x8230" name="GRAS_SC_CNTL" type="a6xx_gras_sc_cntl" variants="A8XX-" usage="rp_blit"/> 1742 1091 1743 1092 <enum name="a6xx_render_mode"> 1744 1093 <value value="0x0" name="RENDERING_PASS"/> ··· 1780 1123 1781 1124 <reg32 offset="0x80a1" name="GRAS_SC_BIN_CNTL" type="a6xx_bin_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1782 1125 1126 1126 + <!-- Common fields for RB_CNTL and GRAS_SC_BIN_CNTL --> 1127 1127 + <bitset name="a8xx_bin_cntl" inline="yes"> 1128 1128 + <bitfield name="BINW" low="0" high="9" shr="5" type="uint"/> 1129 1129 + <bitfield name="BINH" low="16" high="26" shr="4" type="uint"/> 1130 1130 + <bitfield name="RENDER_MODE" low="11" high="13" type="a6xx_render_mode"/> 1131 1131 + <doc> 1132 1132 + Allows draws that don't have GRAS_LRZ_CNTL.LRZ_WRITE but have 1133 1133 + GRAS_LRZ_CNTL.ENABLE to contribute to LRZ during RENDERING pass. 1134 1134 + In sysmem mode GRAS_LRZ_CNTL.LRZ_WRITE is not considered. 1135 1135 + </doc> 1136 1136 + <bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="28" high="30" type="a6xx_lrz_feedback_mask"/> 1137 1137 + <doc>Disable LRZ feedback writes</doc> 1138 1138 + <bitfield name="FORCE_LRZ_WRITE_DIS" pos="31" type="boolean"/> 1139 1139 + </bitset> 1140 1140 + 1141 1141 + <reg32 offset="0x8231" name="GRAS_SC_BIN_CNTL" type="a8xx_bin_cntl" variants="A8XX-" usage="rp_blit"> 1142 1142 + <bitfield name="CONS_VIS_IN_BINNING" pos="10" type="boolean"/> 1143 1143 + <bitfield name="FORCE_BI_DIR_LRZ_DISABLE" pos="14" type="boolean"/> 1144 1144 + <bitfield name="FORCE_LRZ_DIS" pos="15" type="boolean"/> 1145 1145 + <bitfield name="BIN_VRS_DIS" pos="27" type="boolean"/> 1146 1146 + </reg32> 1147 1147 + 1783 1148 <bitset name="a6xx_gras_sc_ras_msaa_cntl" inline="yes"> 1784 1149 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> 1785 1150 <bitfield name="UNK2" pos="2"/> ··· 1809 1130 </bitset> 1810 1131 1811 1132 <reg32 offset="0x80a2" name="GRAS_SC_RAS_MSAA_CNTL" type="a6xx_gras_sc_ras_msaa_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1133 1133 + <reg32 offset="0x8232" name="GRAS_SC_RAS_MSAA_CNTL" type="a6xx_gras_sc_ras_msaa_cntl" variants="A8XX-" usage="rp_blit"/> 1812 1134 1813 1135 <bitset name="a6xx_gras_sc_dest_msaa_cntl" inline="yes"> 1814 1136 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> ··· 1817 1137 </bitset> 1818 1138 1819 1139 <reg32 offset="0x80a3" name="GRAS_SC_DEST_MSAA_CNTL" type="a6xx_gras_sc_dest_msaa_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1140 1140 + <reg32 offset="0x8233" name="GRAS_SC_DEST_MSAA_CNTL" type="a6xx_gras_sc_dest_msaa_cntl" variants="A8XX-" usage="rp_blit"/> 1820 1141 1821 1142 <bitset name="a6xx_msaa_sample_pos_cntl" inline="yes"> 1822 1143 <bitfield name="UNK0" pos="0"/> ··· 1839 1158 <reg32 offset="0x80a5" name="GRAS_SC_PROGRAMMABLE_MSAA_POS_0" type="a6xx_programmable_msaa_pos" variants="A6XX-A7XX" usage="rp_blit"/> 1840 1159 <reg32 offset="0x80a6" name="GRAS_SC_PROGRAMMABLE_MSAA_POS_1" type="a6xx_programmable_msaa_pos" variants="A6XX-A7XX" usage="rp_blit"/> 1841 1160 1161 1161 + <reg32 offset="0x8237" name="GRAS_SC_MSAA_SAMPLE_POS_CNTL" type="a6xx_msaa_sample_pos_cntl" variants="A8XX-" usage="rp_blit"/> 1162 1162 + <reg32 offset="0x8238" name="GRAS_SC_PROGRAMMABLE_MSAA_POS_0" type="a6xx_programmable_msaa_pos" variants="A8XX-" usage="rp_blit"/> 1163 1163 + <reg32 offset="0x8239" name="GRAS_SC_PROGRAMMABLE_MSAA_POS_1" type="a6xx_programmable_msaa_pos" variants="A8XX-" usage="rp_blit"/> 1164 1164 + <reg32 offset="0x823a" name="GRAS_SC_PROGRAMMABLE_MSAA_POS_2" type="a6xx_programmable_msaa_pos" variants="A8XX-" usage="rp_blit"/> 1165 1165 + <reg32 offset="0x823b" name="GRAS_SC_PROGRAMMABLE_MSAA_POS_3" type="a6xx_programmable_msaa_pos" variants="A8XX-" usage="rp_blit"/> 1166 1166 + 1842 1167 <reg32 offset="0x80a7" name="GRAS_ROTATION_CNTL" variants="A7XX" usage="cmd"/> 1168 1168 + <reg32 offset="0x8207" name="GRAS_ROTATION_CNTL" variants="A8XX-" usage="cmd"/> 1843 1169 1844 1170 <bitset name="a6xx_screen_scissor_cntl" inline="yes"> 1845 1171 <bitfield name="SCISSOR_DISABLE" pos="0" type="boolean"/> 1846 1172 </bitset> 1847 1173 1848 1174 <reg32 offset="0x80af" name="GRAS_SC_SCREEN_SCISSOR_CNTL" type="a6xx_screen_scissor_cntl" variants="A6XX-A7XX" pos="0" usage="cmd"/> 1175 1175 + <reg32 offset="0x8234" name="GRAS_SC_SCREEN_SCISSOR_CNTL" type="a6xx_screen_scissor_cntl" variants="A8XX-" pos="0" usage="cmd"/> 1849 1176 1850 1177 <bitset name="a6xx_scissor_xy" inline="yes"> 1851 1178 <bitfield name="X" low="0" high="15" type="uint"/> ··· 1865 1176 <reg32 offset="1" name="BR" type="a6xx_scissor_xy"/> 1866 1177 </array> 1867 1178 1179 1179 + <array offset="0x8240" name="GRAS_SC_SCREEN_SCISSOR" stride="2" length="16" variants="A8XX-" usage="rp_blit"> 1180 1180 + <reg32 offset="0" name="TL" type="a6xx_scissor_xy"/> 1181 1181 + <reg32 offset="1" name="BR" type="a6xx_scissor_xy"/> 1182 1182 + </array> 1183 1183 + 1868 1184 <array offset="0x80d0" name="GRAS_SC_VIEWPORT_SCISSOR" stride="2" length="16" variants="A6XX-A7XX" usage="rp_blit"> 1185 1185 + <reg32 offset="0" name="TL" type="a6xx_scissor_xy"/> 1186 1186 + <reg32 offset="1" name="BR" type="a6xx_scissor_xy"/> 1187 1187 + </array> 1188 1188 + <array offset="0x8270" name="GRAS_SC_VIEWPORT_SCISSOR" stride="2" length="16" variants="A8XX-" usage="rp_blit"> 1869 1189 <reg32 offset="0" name="TL" type="a6xx_scissor_xy"/> 1870 1190 <reg32 offset="1" name="BR" type="a6xx_scissor_xy"/> 1871 1191 </array> 1872 1192 1873 1193 <reg32 offset="0x80f0" name="GRAS_SC_WINDOW_SCISSOR_TL" type="a6xx_reg_xy" variants="A6XX-A7XX" usage="rp_blit"/> 1874 1194 <reg32 offset="0x80f1" name="GRAS_SC_WINDOW_SCISSOR_BR" type="a6xx_reg_xy" variants="A6XX-A7XX" usage="rp_blit"/> 1195 1195 + 1196 1196 + <reg32 offset="0x8235" name="GRAS_SC_WINDOW_SCISSOR_TL" type="a6xx_reg_xy" variants="A8XX-" usage="rp_blit"/> 1197 1197 + <reg32 offset="0x8236" name="GRAS_SC_WINDOW_SCISSOR_BR" type="a6xx_reg_xy" variants="A8XX-" usage="rp_blit"/> 1875 1198 1876 1199 <enum name="a6xx_fsr_combiner"> 1877 1200 <value value="0" name="FSR_COMBINER_OP_KEEP"/> ··· 1904 1203 </bitset> 1905 1204 1906 1205 <reg32 offset="0x80f4" name="GRAS_VRS_CONFIG" type="a6xx_gras_vrs_config" variants="A7XX" usage="rp_blit"/> 1206 1206 + <reg32 offset="0x8208" name="GRAS_VRS_CONFIG" type="a6xx_gras_vrs_config" variants="A8XX-" usage="rp_blit"/> 1907 1207 1908 1208 <bitset name="a6xx_gras_quality_buffer_info" inline="yes"> 1909 1209 <bitfield name="LAYERED" pos="0" type="boolean"/> ··· 1912 1210 </bitset> 1913 1211 1914 1212 <reg32 offset="0x80f5" name="GRAS_QUALITY_BUFFER_INFO" type="a6xx_gras_quality_buffer_info" variants="A7XX" usage="rp_blit"/> 1213 1213 + <reg32 offset="0x808e" name="GRAS_QUALITY_BUFFER_INFO" type="a6xx_gras_quality_buffer_info" variants="A8XX-" usage="rp_blit"/> 1915 1214 1916 1215 <bitset name="a6xx_gras_quality_buffer_dimension" inline="yes"> 1917 1216 <bitfield name="WIDTH" low="0" high="15" type="uint"/> ··· 1920 1217 </bitset> 1921 1218 1922 1219 <reg32 offset="0x80f6" name="GRAS_QUALITY_BUFFER_DIMENSION" type="a6xx_gras_quality_buffer_dimension" variants="A7XX" usage="rp_blit"/> 1220 1220 + <reg32 offset="0x808f" name="GRAS_QUALITY_BUFFER_DIMENSION" type="a6xx_gras_quality_buffer_dimension" variants="A8XX-" usage="rp_blit"/> 1923 1221 1924 1222 <reg64 offset="0x80f8" name="GRAS_QUALITY_BUFFER_BASE" variants="A7XX" type="waddress" usage="rp_blit"/> 1223 1223 + <reg64 offset="0x8090" name="GRAS_QUALITY_BUFFER_BASE" variants="A8XX-" type="waddress" usage="rp_blit"/> 1925 1224 1926 1225 <bitset name="a6xx_gras_quality_buffer_pitch" inline="yes"> 1927 1226 <bitfield name="PITCH" shr="6" low="0" high="7" type="uint"/> ··· 1931 1226 </bitset> 1932 1227 1933 1228 <reg32 offset="0x80fa" name="GRAS_QUALITY_BUFFER_PITCH" type="a6xx_gras_quality_buffer_pitch" variants="A7XX" usage="rp_blit"/> 1229 1229 + <reg32 offset="0x8092" name="GRAS_QUALITY_BUFFER_PITCH" type="a6xx_gras_quality_buffer_pitch" variants="A8XX-" usage="rp_blit"/> 1934 1230 1935 1231 <enum name="a6xx_lrz_dir_status"> 1936 1232 <value value="0x1" name="LRZ_DIR_LE"/> ··· 1950 1244 - 0.0 if GREATER 1951 1245 - 1.0 if LESS 1952 1246 </doc> 1953 1953 - <bitfield name="FC_ENABLE" pos="3" type="boolean" variants="A6XX"/> 1954 1247 <!-- set when depth-test + depth-write enabled --> 1955 1248 <bitfield name="Z_WRITE_ENABLE" pos="4" type="boolean"/> 1956 1249 <bitfield name="Z_BOUNDS_ENABLE" pos="5" type="boolean"/> ··· 1963 1258 Disable LRZ based on previous direction and the current one. 1964 1259 If DIR_WRITE is not enabled - there is no write to direction buffer. 1965 1260 </doc> 1966 1966 - <bitfield name="DISABLE_ON_WRONG_DIR" pos="9" type="boolean" variants="A6XX"/> 1967 1261 <bitfield name="Z_FUNC" low="11" high="13" type="adreno_compare_func" variants="A7XX-"/> 1968 1262 </bitset> 1969 1263 1970 1970 - <reg32 offset="0x8100" name="GRAS_LRZ_CNTL" type="a6xx_gras_lrz_cntl" usage="rp_blit" variants="A6XX-A7XX"/> 1264 1264 + <reg32 offset="0x8100" name="GRAS_LRZ_CNTL" type="a6xx_gras_lrz_cntl" usage="rp_blit" variants="A6XX"> 1265 1265 + <bitfield name="FC_ENABLE" pos="3" type="boolean" variants="A6XX"/> 1266 1266 + <bitfield name="DISABLE_ON_WRONG_DIR" pos="9" type="boolean" variants="A6XX"/> 1267 1267 + </reg32> 1268 1268 + <reg32 offset="0x8100" name="GRAS_LRZ_CNTL" type="a6xx_gras_lrz_cntl" usage="rp_blit" variants="A7XX"/> 1269 1269 + <reg32 offset="0x8212" name="GRAS_LRZ_CNTL" type="a6xx_gras_lrz_cntl" usage="rp_blit" variants="A8XX-"/> 1270 1270 + 1271 1271 + <reg32 offset="0x8007" name="GRAS_LRZ_CB_CNTL" variants="A7XX" usage="rp_blit"> 1272 1272 + <doc> 1273 1273 + The total size of the LRZ image array (not including 1274 1274 + fast clear buffer), used as a stride for double 1275 1275 + buffering used with concurrent binning. 1276 1276 + </doc> 1277 1277 + <bitfield name="DOUBLE_BUFFER_STRIDE" low="8" high="31" shr="8"/> 1278 1278 + </reg32> 1279 1279 + <reg32 offset="0x8101" name="GRAS_LRZ_CB_CNTL" usage="rp_blit" variants="A8XX-"> 1280 1280 + <bitfield name="DOUBLE_BUFFER_PITCH" low="8" high="31" shr="8"/> 1281 1281 + </reg32> 1971 1282 1972 1283 <enum name="a6xx_fragcoord_sample_mode"> 1973 1284 <value value="0" name="FRAGCOORD_CENTER"/> ··· 1996 1275 </bitset> 1997 1276 1998 1277 <reg32 offset="0x8101" name="GRAS_LRZ_PS_INPUT_CNTL" type="a6xx_gras_lrz_ps_input_cntl" usage="rp_blit" variants="A6XX-A7XX"/> 1278 1278 + <reg32 offset="0x8102" name="GRAS_LRZ_PS_INPUT_CNTL" type="a6xx_gras_lrz_ps_input_cntl" usage="rp_blit" variants="A8XX-"/> 1999 1279 2000 1280 <bitset name="a6xx_gras_lrz_mrt_buffer_info_0" inline="yes"> 2001 1281 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/> 2002 1282 </bitset> 2003 1283 2004 1284 <reg32 offset="0x8102" name="GRAS_LRZ_MRT_BUFFER_INFO_0" type="a6xx_gras_lrz_mrt_buffer_info_0" usage="rp_blit" variants="A6XX-A7XX"/> 1285 1285 + <reg32 offset="0x8103" name="GRAS_LRZ_MRT_BUFFER_INFO_0" type="a6xx_gras_lrz_mrt_buffer_info_0" usage="rp_blit" variants="A8XX-"/> 2005 1286 2006 1287 <reg64 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE" align="256" type="waddress" usage="rp_blit" variants="A6XX-A7XX"/> 1288 1288 + <reg64 offset="0x8104" name="GRAS_LRZ_BUFFER_BASE" align="256" type="waddress" usage="rp_blit" variants="A8XX-"/> 2007 1289 2008 1290 <bitset name="a6xx_gras_lrz_buffer_pitch" inline="yes"> 2009 1291 <bitfield name="PITCH" low="0" high="7" shr="5" type="uint"/> ··· 2014 1290 </bitset> 2015 1291 2016 1292 <reg32 offset="0x8105" name="GRAS_LRZ_BUFFER_PITCH" type="a6xx_gras_lrz_buffer_pitch" usage="rp_blit" variants="A6XX-A7XX"/> 1293 1293 + <reg32 offset="0x8108" name="GRAS_LRZ_BUFFER_PITCH" type="a6xx_gras_lrz_buffer_pitch" usage="rp_blit" variants="A8XX-"/> 1294 1294 + 1295 1295 + <reg32 offset="0x810e" name="GRAS_LRZ_BUFFER_STRIDE" usage="rp_blit" low="0" high="16" shr="12" variants="A8XX-"/> 2017 1296 2018 1297 <!-- 2019 1298 The LRZ "fast clear" buffer is initialized to zero's by blob, and ··· 2073 1346 2074 1347 <!-- 0x810c-0x810f invalid --> 2075 1348 1349 1349 + <reg32 offset="0x8110" name="GRAS_LRZ_BUFFER_SLICE_PITCH" low="0" high="31" shr="8" type="uint" variants="A8XX-"/> 1350 1350 + 2076 1351 <reg32 offset="0x8110" name="GRAS_MODE_CNTL" low="0" high="1" variants="A6XX-A7XX" usage="cmd"/> 1352 1352 + <reg32 offset="0x8213" name="GRAS_MODE_CNTL" low="0" high="1" variants="A8XX-" usage="cmd"/> 2077 1353 2078 1354 <!-- A bit tentative but it's a color and it is followed by LRZ_CLEAR --> 2079 1355 <reg32 offset="0x8111" name="GRAS_LRZ_DEPTH_CLEAR" type="float" variants="A7XX"/> 1356 1356 + <reg32 offset="0x810d" name="GRAS_LRZ_DEPTH_CLEAR" type="float" variants="A8XX-"/> 2080 1357 2081 2081 - <bitset name="a6xx_gras_lrz_depth_buffer_info" inline="yes"> 2082 2082 - <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/> 2083 2083 - <bitfield name="UNK3" pos="3"/> 2084 2084 - </bitset> 2085 2085 - 2086 2086 - <reg32 offset="0x8113" name="GRAS_LRZ_DEPTH_BUFFER_INFO" type="a6xx_gras_lrz_depth_buffer_info" variants="A7XX" usage="rp_blit"/> 1358 1358 + <reg32 offset="0x8113" name="GRAS_LRZ_DEPTH_BUFFER_INFO" type="a6xx_depth_buffer_info" variants="A7XX" usage="rp_blit"/> 1359 1359 + <reg32 offset="0x810f" name="GRAS_LRZ_DEPTH_BUFFER_INFO" type="a6xx_depth_buffer_info" variants="A8XX" usage="rp_blit"/> 2087 1360 2088 1361 <doc>LUT used to convert quality buffer values to HW shading rate values. An array of 4-bit values.</doc> 2089 2089 - <array offset="0x8120" name="GRAS_LRZ_QUALITY_LOOKUP_TABLE" variants="A7XX-" stride="1" length="2"/> 1362 1362 + <array offset="0x8120" name="GRAS_LRZ_QUALITY_LOOKUP_TABLE" variants="A7XX" stride="1" length="2"/> 1363 1363 + <array offset="0x8130" name="GRAS_LRZ_QUALITY_LOOKUP_TABLE" variants="A8XX-" stride="1" length="2"/> 2090 1364 2091 2091 - <!-- 0x8112-0x83ff invalid --> 1365 1365 + <reg32 offset="0x810c" name="GRAS_LRZ_COLOR_COMP_MASK" variants="A8XX-"> 1366 1366 + <bitfield name="MRT0" low="0" high="3"/> 1367 1367 + <bitfield name="MRT1" low="4" high="7"/> 1368 1368 + <bitfield name="MRT2" low="8" high="11"/> 1369 1369 + <bitfield name="MRT3" low="12" high="15"/> 1370 1370 + <bitfield name="MRT4" low="16" high="19"/> 1371 1371 + <bitfield name="MRT5" low="20" high="23"/> 1372 1372 + <bitfield name="MRT6" low="24" high="27"/> 1373 1373 + <bitfield name="MRT7" low="28" high="31"/> 1374 1374 + </reg32> 2092 1375 2093 1376 <enum name="a6xx_rotation"> 2094 1377 <value value="0x0" name="ROTATE_0"/> ··· 2109 1372 <value value="0x5" name="ROTATE_VFLIP"/> 2110 1373 </enum> 2111 1374 2112 2112 - <bitset name="a6xx_a2d_bit_cntl" inline="yes"> 1375 1375 + <bitset name="a6xx_a2d_blt_cntl" inline="yes"> 2113 1376 <bitfield name="ROTATE" low="0" high="2" type="a6xx_rotation"/> 2114 1377 <bitfield name="OVERWRITEEN" pos="3" type="boolean"/> 2115 1378 <bitfield name="UNK4" low="4" high="6"/> ··· 2128 1391 <bitfield name="COPY" pos="30" type="boolean" variants="A7XX-"/> 2129 1392 </bitset> 2130 1393 2131 2131 - <reg32 offset="0x8400" name="GRAS_A2D_BLT_CNTL" type="a6xx_a2d_bit_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1394 1394 + <reg32 offset="0x8400" name="GRAS_A2D_BLT_CNTL" type="a6xx_a2d_blt_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2132 1395 <!-- note: the low 8 bits for src coords are valid, probably fixed point 2133 1396 it would be a bit weird though, since we subtract 1 from BR coords 2134 1397 apparently signed, gallium driver uses negative coords and it works? ··· 2145 1408 <reg32 offset="0x840a" name="GRAS_A2D_SCISSOR_TL" type="a6xx_reg_xy" variants="A6XX-A7XX" usage="rp_blit"/> 2146 1409 <reg32 offset="0x840b" name="GRAS_A2D_SCISSOR_BR" type="a6xx_reg_xy" variants="A6XX-A7XX" usage="rp_blit"/> 2147 1410 1411 1411 + <reg32 offset="0x8500" name="GRAS_A2D_BLT_CNTL" type="a6xx_a2d_blt_cntl" variants="A8XX-" usage="rp_blit"/> 1412 1412 + <reg32 offset="0x8501" name="GRAS_A2D_SRC_XMIN" low="8" high="24" type="int" variants="A8XX-" usage="rp_blit"/> 1413 1413 + <reg32 offset="0x8502" name="GRAS_A2D_SRC_XMAX" low="8" high="24" type="int" variants="A8XX-" usage="rp_blit"/> 1414 1414 + <reg32 offset="0x8503" name="GRAS_A2D_SRC_YMIN" low="8" high="24" type="int" variants="A8XX-" usage="rp_blit"/> 1415 1415 + <reg32 offset="0x8504" name="GRAS_A2D_SRC_YMAX" low="8" high="24" type="int" variants="A8XX-" usage="rp_blit"/> 1416 1416 + <reg32 offset="0x8505" name="GRAS_A2D_DEST_TL" type="a6xx_reg_xy" variants="A8XX-" usage="rp_blit"/> 1417 1417 + <reg32 offset="0x8506" name="GRAS_A2D_DEST_BR" type="a6xx_reg_xy" variants="A8XX-" usage="rp_blit"/> 1418 1418 + <reg32 offset="0x8507" name="GRAS_A2D_SCISSOR_TL" type="a6xx_reg_xy" variants="A8XX-" usage="rp_blit"/> 1419 1419 + <reg32 offset="0x8508" name="GRAS_A2D_SCISSOR_BR" type="a6xx_reg_xy" variants="A8XX-" usage="rp_blit"/> 1420 1420 + 2148 1421 <!-- always 0x880 ? (and 0 in a640/a650 traces?) --> 2149 2149 - <reg32 offset="0x8600" name="GRAS_DBG_ECO_CNTL" usage="cmd"> 1422 1422 + <reg32 offset="0x8600" name="GRAS_DBG_ECO_CNTL" usage="init" variants="A6XX-A7XX"> 2150 1423 <bitfield name="UNK7" pos="7" type="boolean"/> 2151 1424 <bitfield name="LRZCACHELOCKDIS" pos="11" type="boolean"/> 2152 1425 </reg32> 2153 2153 - <reg32 offset="0x8601" name="GRAS_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/> 2154 2154 - <reg32 offset="0x8602" name="GRAS_NC_MODE_CNTL" variants="A7XX-"/> 2155 2155 - <array offset="0x8610" name="GRAS_PERFCTR_TSE_SEL" stride="1" length="4"/> 2156 2156 - <array offset="0x8614" name="GRAS_PERFCTR_RAS_SEL" stride="1" length="4"/> 2157 2157 - <array offset="0x8618" name="GRAS_PERFCTR_LRZ_SEL" stride="1" length="4"/> 1426 1426 + <reg32 offset="0x8600" name="GRAS_TSEFE_DBG_ECO_CNTL" variants="A8XX-"/> 1427 1427 + <reg32 offset="0x8702" name="GRAS_DBG_ECO_CNTL" variants="A8XX"/> 1428 1428 + <reg32 offset="0x8601" name="GRAS_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode" variants="A6XX"/> 1429 1429 + <reg32 offset="0x8602" name="GRAS_NC_MODE_CNTL" variants="A7XX"/> 1430 1430 + <reg32 offset="0x8700" name="GRAS_NC_MODE_CNTL" variants="A8XX-"/> 1431 1431 + <array offset="0x8610" name="GRAS_PERFCTR_TSE_SEL" stride="1" length="4" variants="A6XX-A7XX"/> 1432 1432 + <array offset="0x8614" name="GRAS_PERFCTR_RAS_SEL" stride="1" length="4" variants="A6XX-A7XX"/> 1433 1433 + <array offset="0x8618" name="GRAS_PERFCTR_LRZ_SEL" stride="1" length="4" variants="A6XX-A7XX"/> 1434 1434 + 1435 1435 + <array offset="0x8610" name="GRAS_PERFCTR_TSEFE_SEL" stride="1" length="6" variants="A8XX-"/> 1436 1436 + <array offset="0x8710" name="GRAS_PERFCTR_TSE_SEL" stride="1" length="6" variants="A8XX-"/> 1437 1437 + <array offset="0x8720" name="GRAS_PERFCTR_RAS_SEL" stride="1" length="4" variants="A8XX-"/> 1438 1438 + <array offset="0x8730" name="GRAS_PERFCTR_LRZ_SEL" stride="1" length="6" variants="A8XX-"/> 1439 1439 + 2158 1440 2159 1441 <!-- note 0x8620-0x87ff are not all invalid 2160 1442 (in particular, 0x8631/0x8632 have 0x3fff3fff mask and would be xy coords) ··· 2181 1425 2182 1426 <!-- same as GRAS_BIN_CONTROL, but without bit 27: --> 2183 1427 <reg32 offset="0x8800" name="RB_CNTL" variants="A6XX-A7XX" type="a6xx_bin_cntl" usage="rp_blit"/> 1428 1428 + <reg32 offset="0x8800" name="RB_CNTL" variants="A8XX-" type="a8xx_bin_cntl" usage="rp_blit"/> 2184 1429 2185 1430 <reg32 offset="0x8801" name="RB_RENDER_CNTL" variants="A6XX" usage="rp_blit"> 2186 1431 <bitfield name="CCUSINGLECACHELINESIZE" low="3" high="5"/> ··· 2219 1462 <reg32 offset="0x8804" name="RB_MSAA_SAMPLE_POS_CNTL" type="a6xx_msaa_sample_pos_cntl" usage="rp_blit"/> 2220 1463 <reg32 offset="0x8805" name="RB_PROGRAMMABLE_MSAA_POS_0" type="a6xx_programmable_msaa_pos" usage="rp_blit"/> 2221 1464 <reg32 offset="0x8806" name="RB_PROGRAMMABLE_MSAA_POS_1" type="a6xx_programmable_msaa_pos" usage="rp_blit"/> 2222 2222 - <!-- 0x8807-0x8808 invalid --> 1465 1465 + <reg32 offset="0x8807" name="RB_PROGRAMMABLE_MSAA_POS_2" type="a6xx_programmable_msaa_pos" usage="rp_blit" variants="A8XX-"/> 1466 1466 + <reg32 offset="0x8808" name="RB_PROGRAMMABLE_MSAA_POS_3" type="a6xx_programmable_msaa_pos" usage="rp_blit" variants="A8XX-"/> 2223 1467 <!-- 2224 1468 note: maybe not actually called RB_RENDER_CONTROLn (since RB_RENDER_CNTL 2225 1469 name comes from kernel and is probably right) ··· 2234 1476 <bitfield name="IJ_LINEAR_CENTROID" pos="4" type="boolean"/> 2235 1477 <bitfield name="IJ_LINEAR_SAMPLE" pos="5" type="boolean"/> 2236 1478 <bitfield name="COORD_MASK" low="6" high="9" type="hex"/> 2237 2237 - <bitfield name="UNK10" pos="10" type="boolean"/> 1479 1479 + <bitfield name="INTERP_EN" pos="10" type="boolean"/> 2238 1480 </reg32> 2239 1481 <reg32 offset="0x880a" name="RB_PS_INPUT_CNTL" usage="rp_blit"> 2240 1482 <!-- enable bits for various FS sysvalue regs: --> ··· 2292 1534 <reg32 offset="0x8810" name="RB_PS_SAMPLEFREQ_CNTL" usage="rp_blit"> 2293 1535 <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/> 2294 1536 </reg32> 2295 2295 - <reg32 offset="0x8811" name="RB_UNKNOWN_8811" low="4" high="6" usage="cmd"/> 2296 2296 - <reg32 offset="0x8812" name="RB_UNKNOWN_8812" variants="A7XX-" usage="rp_blit"/> 1537 1537 + <reg32 offset="0x8811" name="RB_MODE_CNTL" low="4" high="6" usage="cmd"/> 1538 1538 + <reg32 offset="0x8812" name="RB_BUFFER_CNTL" variants="A7XX-" usage="rp_blit"> 1539 1539 + <bitfield name="Z_SYSMEM" pos="0" type="boolean"/> 1540 1540 + <bitfield name="S_SYSMEM" pos="1" type="boolean"/> 1541 1541 + <bitfield name="RT0_SYSMEM" pos="2" type="boolean"/> 1542 1542 + <bitfield name="RT1_SYSMEM" pos="3" type="boolean"/> 1543 1543 + <bitfield name="RT2_SYSMEM" pos="4" type="boolean"/> 1544 1544 + <bitfield name="RT3_SYSMEM" pos="5" type="boolean"/> 1545 1545 + <bitfield name="RT4_SYSMEM" pos="6" type="boolean"/> 1546 1546 + <bitfield name="RT5_SYSMEM" pos="7" type="boolean"/> 1547 1547 + <bitfield name="RT6_SYSMEM" pos="8" type="boolean"/> 1548 1548 + <bitfield name="RT7_SYSMEM" pos="9" type="boolean"/> 1549 1549 + <bitfield name="Z_FULL_IN_GMEM" pos="10" type="boolean" variants="A8XX-"/> 1550 1550 + <bitfield name="S_FULL_IN_GMEM" pos="11" type="boolean" variants="A8XX-"/> 1551 1551 + <bitfield name="RT0_FULL_IN_GMEM" pos="12" type="boolean" variants="A8XX-"/> 1552 1552 + <bitfield name="RT1_FULL_IN_GMEM" pos="13" type="boolean" variants="A8XX-"/> 1553 1553 + <bitfield name="RT2_FULL_IN_GMEM" pos="14" type="boolean" variants="A8XX-"/> 1554 1554 + <bitfield name="RT3_FULL_IN_GMEM" pos="15" type="boolean" variants="A8XX-"/> 1555 1555 + <bitfield name="RT4_FULL_IN_GMEM" pos="16" type="boolean" variants="A8XX-"/> 1556 1556 + <bitfield name="RT5_FULL_IN_GMEM" pos="17" type="boolean" variants="A8XX-"/> 1557 1557 + <bitfield name="RT6_FULL_IN_GMEM" pos="18" type="boolean" variants="A8XX-"/> 1558 1558 + <bitfield name="RT7_FULL_IN_GMEM" pos="19" type="boolean" variants="A8XX-"/> 1559 1559 + </reg32> 1560 1560 + 1561 1561 + <reg32 offset="0x8816" name="RB_RESOLVE_CR_CNTL" variants="A8XX-" usage="rp_blit"/> 1562 1562 + 2297 1563 <!-- 0x8813-0x8817 invalid --> 2298 1564 <!-- always 0x0 ? --> 2299 1565 <reg32 offset="0x8818" name="RB_UNKNOWN_8818" low="0" high="6" usage="cmd"/> ··· 2328 1546 <reg32 offset="0x881c" name="RB_UNKNOWN_881C" usage="cmd"/> 2329 1547 <reg32 offset="0x881d" name="RB_UNKNOWN_881D" usage="cmd"/> 2330 1548 <reg32 offset="0x881e" name="RB_UNKNOWN_881E" usage="cmd"/> 2331 2331 - <!-- 0x881f invalid --> 1549 1549 + 1550 1550 + <!-- Duplicates fields from SP_PS_CNTL_0 --> 1551 1551 + <reg32 offset="0x881f" name="RB_PS_CNTL" variants="A8XX-" usage="rp_blit"> 1552 1552 + <bitfield name="PIXLODENABLE" pos="0" type="boolean"/> 1553 1553 + <bitfield name="LODPIXMASK" pos="1" type="boolean"/> 1554 1554 + </reg32> 1555 1555 + 2332 1556 <array offset="0x8820" name="RB_MRT" stride="8" length="8" usage="rp_blit"> 2333 1557 <reg32 offset="0x0" name="CONTROL"> 2334 2334 - <bitfield name="BLEND" pos="0" type="boolean"/> 2335 2335 - <bitfield name="BLEND2" pos="1" type="boolean"/> 1558 1558 + <bitfield name="COLOR_BLEND_EN" pos="0" type="boolean"/> 1559 1559 + <bitfield name="ALPHA_BLEND_EN" pos="1" type="boolean"/> 2336 1560 <bitfield name="ROP_ENABLE" pos="2" type="boolean"/> 2337 1561 <bitfield name="ROP_CODE" low="3" high="6" type="a3xx_rop_code"/> 2338 1562 <bitfield name="COMPONENT_ENABLE" low="7" high="10" type="hex"/> ··· 2401 1613 <bitfield name="ALPHA_TO_ONE" pos="11" type="boolean"/> 2402 1614 <bitfield name="SAMPLE_MASK" low="16" high="31"/> 2403 1615 </reg32> 2404 2404 - <!-- 0x8866-0x886f invalid --> 1616 1616 + <reg32 offset="0x8866" name="RB_LB_PARAM_LIMIT" variants="A8XX-" usage="rp_blit"> 1617 1617 + <bitfield name="PRIMALLOCTHRESHOLD" low="0" high="2" type="uint"/> 1618 1618 + </reg32> 2405 1619 <reg32 offset="0x8870" name="RB_DEPTH_PLANE_CNTL" type="a6xx_depth_plane_cntl" usage="rp_blit"/> 2406 1620 2407 1621 <reg32 offset="0x8871" name="RB_DEPTH_CNTL" usage="rp_blit"> ··· 2417 1627 </doc> 2418 1628 <bitfield name="Z_READ_ENABLE" pos="6" type="boolean"/> 2419 1629 <bitfield name="Z_BOUNDS_ENABLE" pos="7" type="boolean"/> 1630 1630 + <!-- clamp shader depth out to [0, 1] (instead of RB_VIEWPORT_ZCLAMP_MIN/MAX)--> 1631 1631 + <bitfield name="O_DEPTH_01_CLAMP_EN" pos="8" type="boolean" variants="A8XX-"/> 2420 1632 </reg32> 2421 1633 2422 1634 <!-- duplicates GRAS_SU_DEPTH_BUFFER_INFO: --> 2423 1635 <reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO" variants="A6XX" type="a6xx_depth_buffer_info" usage="rp_blit"/> 2424 1636 <!-- first 4 bits duplicates GRAS_SU_DEPTH_BUFFER_INFO --> 2425 2425 - <reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO" variants="A7XX-" usage="rp_blit"> 2426 2426 - <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/> 2427 2427 - <bitfield name="UNK3" low="3" high="4"/> 1637 1637 + <reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO" type="a6xx_depth_buffer_info" variants="A7XX-" usage="rp_blit"> 1638 1638 + <bitfield name="PRT" low="3" high="4"/> 2428 1639 <bitfield name="TILEMODE" low="5" high="6" type="a6xx_tile_mode"/> 2429 1640 <bitfield name="LOSSLESSCOMPEN" pos="7" type="boolean"/> 2430 1641 </reg32> ··· 2493 1702 <reg32 offset="0x8898" name="RB_LRZ_CNTL" usage="rp_blit"> 2494 1703 <bitfield name="ENABLE" pos="0" type="boolean"/> 2495 1704 </reg32> 2496 2496 - <reg32 offset="0x8899" name="RB_UNKNOWN_8899" variants="A7XX-" usage="cmd"/> 1705 1705 + <reg32 offset="0x8899" name="RB_LRZ_CNTL2" variants="A7XX-" usage="cmd"> 1706 1706 + <bitfield name="ENABLE_BIDIRECTIONAL_LRZ" pos="0" type="boolean"/> 1707 1707 + </reg32> 2497 1708 <!-- 0x8899-0x88bf invalid --> 2498 1709 <!-- clamps depth value for depth test/write --> 2499 1710 <reg32 offset="0x88c0" name="RB_VIEWPORT_ZCLAMP_MIN" type="float" usage="rp_blit" variants="A6XX-A7XX"/> 2500 1711 <reg32 offset="0x88c1" name="RB_VIEWPORT_ZCLAMP_MAX" type="float" usage="rp_blit" variants="A6XX-A7XX"/> 1712 1712 + 1713 1713 + <!-- todo allow type="float" on an <array/> --> 1714 1714 + <array offset="0x88b0" name="RB_VIEWPORT_ZCLAMP_MIN" stride="1" length="16" usage="rp_blit" variants="A8XX-"> 1715 1715 + <reg32 offset="0" name="REG" type="float"/> 1716 1716 + </array> 1717 1717 + <array offset="0x88c0" name="RB_VIEWPORT_ZCLAMP_MAX" stride="1" length="16" usage="rp_blit" variants="A8XX-"> 1718 1718 + <reg32 offset="0" name="REG" type="float"/> 1719 1719 + </array> 2501 1720 2502 1721 <!-- 0x88c2-0x88cf invalid--> 2503 1722 <reg32 offset="0x88d0" name="RB_RESOLVE_CNTL_0" usage="rp_blit"> ··· 2521 1720 <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/> 2522 1721 <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/> 2523 1722 </reg32> 1723 1723 + 1724 1724 + <reg32 offset="0x88d3" name="RB_RESOLVE_CNTL_3" type="a8xx_bin_size" variants="A8XX-" usage="rp_blit"/> 1725 1725 + <reg32 offset="0x88f0" name="RB_RESOLVE_CNTL_4" variants="A8XX-" usage="rp_blit"/> 1726 1726 + <reg32 offset="0x88f1" name="RB_RESOLVE_CNTL_5" variants="A8XX-" usage="rp_blit"/> 1727 1727 + 2524 1728 <reg32 offset="0x88d4" name="RB_RESOLVE_WINDOW_OFFSET" type="a6xx_reg_xy" usage="rp_blit"/> 2525 1729 <reg32 offset="0x88d5" name="RB_RESOLVE_GMEM_BUFFER_INFO" usage="rp_blit"> 2526 1730 <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/> ··· 2604 1798 <value value="0x1" name="CCU_CACHE_SIZE_HALF"/> 2605 1799 <value value="0x2" name="CCU_CACHE_SIZE_QUARTER"/> 2606 1800 <value value="0x3" name="CCU_CACHE_SIZE_EIGHTH"/> 1801 1801 + <!-- for DEPTH_CACHE_SIZE 3 == THREE_QUARTER from KNP --> 1802 1802 + <value value="0x3" name="CCU_CACHE_SIZE_THREE_QUARTER"/> 2607 1803 </enum> 2608 2608 - <reg32 offset="0x88e5" name="RB_CCU_CACHE_CNTL" variants="A7XX-" usage="cmd"> 1804 1804 + <reg32 offset="0x88e5" name="RB_CCU_CACHE_CNTL" variants="A7XX" usage="cmd"> 2609 1805 <bitfield name="DEPTH_OFFSET_HI" pos="0" type="hex"/> 2610 1806 <bitfield name="COLOR_OFFSET_HI" pos="2" type="hex"/> 2611 1807 <bitfield name="DEPTH_CACHE_SIZE" low="10" high="11" type="a6xx_ccu_cache_size"/> ··· 2622 1814 --> 2623 1815 <bitfield name="COLOR_OFFSET" low="23" high="31" shr="12" type="hex"/> 2624 1816 </reg32> 2625 2625 - <!-- 0x88e6-0x88ef invalid --> 1817 1817 + 1818 1818 + <reg32 offset="0x88e5" name="RB_CCU_CACHE_CNTL" variants="A8XX-" usage="cmd"> 1819 1819 + <!-- 1820 1820 + For color cache, full is 128KB per CCU. For depth cache, 1821 1821 + full is 256KB per CCU. 1822 1822 + 1823 1823 + For attr/pos caches (see VPC_{ATTR,POS,BV_POS}_BUF_GMEM_SIZE), 1824 1824 + the sizes are per CCU 1825 1825 + --> 1826 1826 + <bitfield name="COLOR_OFFSET" low="0" high="13" shr="12" type="hex"/> 1827 1827 + <bitfield name="COLOR_CACHE_SIZE" low="14" high="15" type="a6xx_ccu_cache_size"/> 1828 1828 + <bitfield name="DEPTH_OFFSET" low="16" high="29" shr="12" type="hex"/> 1829 1829 + <bitfield name="DEPTH_CACHE_SIZE" low="30" high="31" type="a6xx_ccu_cache_size"/> 1830 1830 + </reg32> 1831 1831 + 1832 1832 + <reg32 offset="0x88e6" name="RB_RESOLVE_GMEM_BUFFER_CNTL" variants="A8XX-"> 1833 1833 + <bitfield name="FULL_IN_GMEM" pos="0" type="boolean"/> 1834 1834 + </reg32> 1835 1835 + 2626 1836 <!-- always 0x0 ? --> 2627 2627 - <reg32 offset="0x88f0" name="RB_UNKNOWN_88F0" low="0" high="11" usage="cmd"/> 1837 1837 + <reg32 offset="0x88f0" name="RB_UNKNOWN_88F0" low="0" high="11" variants="A6XX" usage="cmd"/> 2628 1838 <!-- could be for separate stencil? (or may not be a flag buffer at all) --> 2629 2629 - <reg64 offset="0x88f1" name="RB_UNK_FLAG_BUFFER_BASE" type="waddress" align="64"/> 2630 2630 - <reg32 offset="0x88f3" name="RB_UNK_FLAG_BUFFER_PITCH" type="a6xx_flag_buffer_pitch"/> 1839 1839 + <reg64 offset="0x88f1" name="RB_UNK_FLAG_BUFFER_BASE" type="waddress" align="64" variants="A6XX"/> 1840 1840 + <reg32 offset="0x88f3" name="RB_UNK_FLAG_BUFFER_PITCH" type="a6xx_flag_buffer_pitch" variants="A6XX"/> 2631 1841 2632 1842 <reg32 offset="0x88f4" name="RB_VRS_CONFIG" usage="rp_blit"> 2633 1843 <bitfield name="UNK2" pos="2" type="boolean"/> ··· 2675 1849 the address is specified through CP_EVENT_WRITE7::WRITE_SAMPLE_COUNT. 2676 1850 </doc> 2677 1851 <reg64 offset="0x8927" name="RB_SAMPLE_COUNTER_BASE" type="waddress" align="16" usage="cmd"/> 2678 2678 - <!-- 0x8929-0x89ff invalid --> 2679 1852 2680 2680 - <!-- TODO: there are some registers in the 0x8a00-0x8bff range --> 1853 1853 + <bitset name="a8xx_gmem_dimension" inline="yes"> 1854 1854 + <bitfield name="WIDTH" low="0" high="14" type="uint"/> 1855 1855 + <bitfield name="HEIGHT" low="16" high="30" type="uint"/> 1856 1856 + </bitset> 1857 1857 + 1858 1858 + <reg32 offset="0x8813" name="RB_DEPTH_GMEM_DIMENSION" type="a8xx_gmem_dimension" variants="A8XX-"/> 1859 1859 + <reg32 offset="0x8814" name="RB_STENCIL_GMEM_DIMENSION" type="a8xx_gmem_dimension" variants="A8XX-"/> 1860 1860 + <reg32 offset="0x8815" name="RB_RESOLVE_GMEM_DIMENSION" type="a8xx_gmem_dimension" variants="A8XX-"/> 1861 1861 + 1862 1862 + <array offset="0x8930" name="RB_MRT_GMEM_DIMENSION" variants="A8XX-" stride="1" length="8"> 1863 1863 + <reg32 offset="0" name="REG" type="a8xx_gmem_dimension"/> 1864 1864 + </array> 2681 1865 2682 1866 <!-- 2683 1867 These show up in a6xx gen3+ but so far haven't found an example of ··· 2698 1862 <reg32 offset="0x8a20" name="RB_UNKNOWN_8A20" variants="A6XX" usage="rp_blit"/> 2699 1863 <reg32 offset="0x8a30" name="RB_UNKNOWN_8A30" variants="A6XX" usage="rp_blit"/> 2700 1864 2701 2701 - <reg32 offset="0x8c00" name="RB_A2D_BLT_CNTL" type="a6xx_a2d_bit_cntl" usage="rp_blit"/> 1865 1865 + <reg32 offset="0x8c00" name="RB_A2D_BLT_CNTL" type="a6xx_a2d_blt_cntl" usage="rp_blit"/> 2702 1866 <reg32 offset="0x8c01" name="RB_A2D_PIXEL_CNTL" low="0" high="31" usage="rp_blit"/> 2703 1867 2704 1868 <bitset name="a6xx_a2d_src_texture_info" inline="yes"> ··· 2757 1921 <!-- 0x8c35-0x8dff invalid --> 2758 1922 2759 1923 <!-- always 0x1 ? either doesn't exist for a650 or write-only: --> 2760 2760 - <reg32 offset="0x8e01" name="RB_UNKNOWN_8E01" usage="cmd"/> 1924 1924 + <reg32 offset="0x8e01" name="RB_RBP_CNTL" usage="cmd"/> 2761 1925 <!-- 0x8e00-0x8e03 invalid --> 2762 1926 <reg32 offset="0x8e04" name="RB_DBG_ECO_CNTL" usage="cmd"/> <!-- TODO: valid mask 0xfffffeff --> 2763 2763 - <reg32 offset="0x8e05" name="RB_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/> 1927 1927 + <reg32 offset="0x8e05" name="RB_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode" variants="A6XX"/> 2764 1928 <!-- 0x02080000 in GMEM, zero otherwise? --> 2765 1929 <reg32 offset="0x8e06" name="RB_CCU_DBG_ECO_CNTL" variants="A7XX-" usage="cmd"/> 2766 1930 ··· 2799 1963 <bitfield name="CONCURRENT_UNRESOLVE_MODE" low="5" high="6" type="a7xx_concurrent_unresolve_mode"/> 2800 1964 <!-- rest of the bits were moved to RB_CCU_CACHE_CNTL --> 2801 1965 </reg32> 2802 2802 - <reg32 offset="0x8e08" name="RB_NC_MODE_CNTL"> 1966 1966 + <reg32 offset="0x8e08" name="RB_NC_MODE_CNTL" variants="A6XX-A7XX"> 2803 1967 <bitfield name="MODE" pos="0" type="boolean"/> 2804 1968 <bitfield name="LOWER_BIT" low="1" high="2" type="uint"/> 2805 1969 <bitfield name="MIN_ACCESS_LENGTH" pos="3" type="boolean"/> <!-- true=64b false=32b --> ··· 2808 1972 <bitfield name="RGB565_PREDICATOR" pos="11" type="boolean"/> 2809 1973 <bitfield name="UNK12" low="12" high="13"/> 2810 1974 </reg32> 2811 2811 - <reg32 offset="0x8e09" name="RB_UNKNOWN_8E09" variants="A7XX-" usage="cmd"/> 1975 1975 + <reg32 offset="0x8e08" name="RB_CCU_NC_MODE_CNTL" variants="A8XX-"/> 1976 1976 + 1977 1977 + <reg32 offset="0x8e09" name="RB_UNKNOWN_8E09" variants="A7XX" usage="cmd"/> 1978 1978 + <reg32 offset="0x8e09" name="RB_GC_GMEM_PROTECT" variants="A8XX-"/> 1979 1979 + <reg32 offset="0x8e0a" name="RB_LPAC_GMEM_PROTECT" variants="A8XX-"/> 2812 1980 <!-- 0x8e09-0x8e0f invalid --> 2813 1981 <array offset="0x8e10" name="RB_PERFCTR_RB_SEL" stride="1" length="8"/> 2814 1982 <array offset="0x8e18" name="RB_PERFCTR_CCU_SEL" stride="1" length="5"/> 2815 1983 <!-- 0x8e1d-0x8e1f invalid --> 2816 1984 <!-- 0x8e20-0x8e25 more perfcntr sel? --> 2817 1985 <!-- 0x8e26-0x8e27 invalid --> 2818 2818 - <reg32 offset="0x8e28" name="RB_CMP_DBG_ECO_CNTL"/> 1986 1986 + 1987 1987 + <reg32 offset="0x8f00" name="RB_CMP_NC_MODE_CNTL" variants="A8XX-"/> 1988 1988 + <reg32 offset="0x8f01" name="RB_RESOLVE_PREFETCH_CNTL" variants="A8XX-"/> 1989 1989 + <reg32 offset="0x8f02" name="RB_CMP_DBG_ECO_CNTL" variants="A8XX-"/> 1990 1990 + 1991 1991 + <reg32 offset="0x8f03" name="RB_UNSLICE_STATUS" variants="A8XX-"/> 1992 1992 + <reg32 offset="0x8e28" name="RB_CMP_DBG_ECO_CNTL" variants="A6XX-A7XX"/> 2819 1993 <!-- 0x8e29-0x8e2b invalid --> 2820 2820 - <array offset="0x8e2c" name="RB_PERFCTR_CMP_SEL" stride="1" length="4"/> 2821 2821 - <array offset="0x8e30" name="RB_PERFCTR_UFC_SEL" stride="1" length="6" variants="A7XX-"/> 2822 2822 - <reg32 offset="0x8e3b" name="RB_RB_SUB_BLOCK_SEL_CNTL_HOST"/> 2823 2823 - <reg32 offset="0x8e3d" name="RB_RB_SUB_BLOCK_SEL_CNTL_CD"/> 1994 1994 + <array offset="0x8e2c" name="RB_PERFCTR_CMP_SEL" stride="1" length="4" variants="A6XX-A7XX"/> 1995 1995 + <array offset="0x8e30" name="RB_PERFCTR_UFC_SEL" stride="1" length="6" variants="A7XX"/> 1996 1996 + <array offset="0x8f04" name="RB_PERFCTR_CMP_SEL" stride="1" length="4" variants="A8XX-"/> 1997 1997 + <array offset="0x8f10" name="RB_PERFCTR_UFC_SEL" stride="1" length="6" variants="A8XX-"/> 1998 1998 + <reg32 offset="0x8e3b" name="RB_SUB_BLOCK_SEL_CNTL_HOST"/> 1999 1999 + <reg32 offset="0x8e3d" name="RB_SUB_BLOCK_SEL_CNTL_CD"/> 2000 2000 + <reg32 offset="0x8f29" name="RB_UFC_DBG_CNTL" variants="A8XX-"/> 2824 2001 <!-- 0x8e3e-0x8e4f invalid --> 2825 2002 <!-- GMEM save/restore for preemption: --> 2826 2003 <reg32 offset="0x8e50" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE" pos="0" type="boolean"/> 2827 2004 <!-- address for GMEM save/restore? --> 2828 2005 <reg32 offset="0x8e51" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ADDR" type="waddress" align="1"/> 2829 2829 - <!-- 0x8e53-0x8e7f invalid --> 2830 2830 - <reg32 offset="0x8e79" name="RB_UNKNOWN_8E79" variants="A7XX-" usage="cmd"/> 2006 2006 + <reg32 offset="0x8e77" name="RB_SLICE_UFC_PREFETCH_CNTL" variants="A8XX-"/> 2007 2007 + <reg32 offset="0x8e78" name="RB_SLICE_UFC_DBG_CNTL" variants="A8XX-"/> 2008 2008 + <reg32 offset="0x8e79" name="RB_UNKNOWN_8E79" variants="A7XX" usage="init"/> 2831 2009 <!-- 0x8e80-0x8e83 are valid --> 2832 2010 <!-- 0x8e84-0x90ff invalid --> 2833 2011 ··· 2864 2014 <reg32 offset="0x9102" name="VPC_GS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2865 2015 <reg32 offset="0x9103" name="VPC_DS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2866 2016 2017 2017 + <reg32 offset="0x9307" name="VPC_VS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" variants="A8XX" usage="rp_blit"/> 2018 2018 + <reg32 offset="0x9308" name="VPC_GS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" variants="A8XX" usage="rp_blit"/> 2019 2019 + <reg32 offset="0x9309" name="VPC_DS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" variants="A8XX" usage="rp_blit"/> 2020 2020 + 2867 2021 <reg32 offset="0x9311" name="VPC_VS_CLIP_CULL_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2868 2022 <reg32 offset="0x9312" name="VPC_GS_CLIP_CULL_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2869 2023 <reg32 offset="0x9313" name="VPC_DS_CLIP_CULL_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" variants="A6XX-A7XX" usage="rp_blit"/> ··· 2882 2028 <reg32 offset="0x9105" name="VPC_GS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2883 2029 <reg32 offset="0x9106" name="VPC_DS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2884 2030 2031 2031 + <reg32 offset="0x930a" name="VPC_VS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" variants="A8XX-" usage="rp_blit"/> 2032 2032 + <reg32 offset="0x930b" name="VPC_GS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" variants="A8XX-" usage="rp_blit"/> 2033 2033 + <reg32 offset="0x930c" name="VPC_DS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" variants="A8XX-" usage="rp_blit"/> 2885 2034 2886 2035 <reg32 offset="0x9314" name="VPC_VS_SIV_CNTL_V2" type="a6xx_vpc_xs_siv_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2887 2036 <reg32 offset="0x9315" name="VPC_GS_SIV_CNTL_V2" type="a6xx_vpc_xs_siv_cntl" variants="A6XX-A7XX" usage="rp_blit"/> ··· 2899 2042 2900 2043 <reg32 offset="0x9980" name="VPC_RAST_STREAM_CNTL" type="a6xx_vpc_rast_stream_cntl" variants="A6XX" usage="rp_blit"/> 2901 2044 <reg32 offset="0x9107" name="VPC_RAST_STREAM_CNTL" type="a6xx_vpc_rast_stream_cntl" variants="A7XX" usage="rp_blit"/> 2045 2045 + <reg32 offset="0x930d" name="VPC_RAST_STREAM_CNTL" type="a6xx_vpc_rast_stream_cntl" variants="A8XX-" usage="rp_blit"/> 2902 2046 <reg32 offset="0x9317" name="VPC_RAST_STREAM_CNTL_V2" type="a6xx_vpc_rast_stream_cntl" variants="A7XX" usage="rp_blit"/> 2903 2047 2904 2048 <reg32 offset="0x9107" name="VPC_UNKNOWN_9107" variants="A6XX" usage="rp_blit"> ··· 2909 2051 </reg32> 2910 2052 2911 2053 <reg32 offset="0x9108" name="VPC_RAST_CNTL" type="a6xx_rast_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2054 2054 + <reg32 offset="0x930e" name="VPC_RAST_CNTL" type="a6xx_rast_cntl" variants="A8XX-" usage="rp_blit"/> 2912 2055 <bitset name="a6xx_pc_cntl" inline="yes"> 2913 2056 <bitfield name="PRIMITIVE_RESTART" pos="0" type="boolean"/> 2914 2057 <bitfield name="PROVOKING_VTX_LAST" pos="1" type="boolean"/> ··· 2950 2091 </bitset> 2951 2092 2952 2093 <reg32 offset="0x9109" name="VPC_PC_CNTL" type="a6xx_pc_cntl" variants="A7XX" usage="rp_blit"/> 2094 2094 + <reg32 offset="0x930f" name="VPC_PC_CNTL" type="a6xx_pc_cntl" variants="A8XX-" usage="rp_blit"/> 2953 2095 <reg32 offset="0x910a" name="VPC_GS_PARAM_0" type="a6xx_gs_param_0" variants="A7XX" usage="rp_blit"/> 2096 2096 + <reg32 offset="0x90c0" name="VPC_GS_PARAM_0" type="a6xx_gs_param_0" variants="A8XX-" usage="rp_blit"/> 2954 2097 <reg32 offset="0x910b" name="VPC_STEREO_RENDERING_VIEWMASK" type="hex" low="0" high="15" variants="A7XX" usage="rp_blit"/> 2098 2098 + <reg32 offset="0x90c1" name="VPC_STEREO_RENDERING_VIEWMASK" type="hex" low="0" high="15" variants="A8XX-" usage="rp_blit"/> 2955 2099 <reg32 offset="0x910c" name="VPC_STEREO_RENDERING_CNTL" type="a6xx_stereo_rendering_cntl" variants="A7XX" usage="rp_blit"/> 2100 2100 + <reg32 offset="0x931a" name="VPC_STEREO_RENDERING_CNTL" type="a6xx_stereo_rendering_cntl" variants="A8XX-" usage="rp_blit"/> 2956 2101 2957 2102 <enum name="a6xx_varying_interp_mode"> 2958 2103 <value value="0" name="INTERP_SMOOTH"/> ··· 2982 2119 <reg32 offset="0x0" name="MODE"/> 2983 2120 </array> 2984 2121 2122 2122 + <array offset="0x9240" name="VPC_VARYING_INTERP_MODE" stride="1" length="8" variants="A8XX-" usage="rp_blit"> 2123 2123 + <doc>Packed array of a6xx_varying_interp_mode</doc> 2124 2124 + <reg32 offset="0x0" name="MODE"/> 2125 2125 + </array> 2126 2126 + <array offset="0x9248" name="VPC_VARYING_REPLACE_MODE" stride="1" length="8" variants="A8XX-" usage="rp_blit"> 2127 2127 + <doc>Packed array of a6xx_varying_ps_repl_mode</doc> 2128 2128 + <reg32 offset="0x0" name="MODE"/> 2129 2129 + </array> 2130 2130 + 2985 2131 <!-- always 0x0 --> 2986 2132 <reg32 offset="0x9210" name="VPC_UNKNOWN_9210" low="0" high="31" variants="A6XX" usage="cmd"/> 2987 2133 <reg32 offset="0x9211" name="VPC_UNKNOWN_9211" low="0" high="31" variants="A6XX" usage="cmd"/> 2988 2134 2989 2135 <array offset="0x9212" name="VPC_VARYING_LM_TRANSFER_CNTL" stride="1" length="4" variants="A6XX-A7XX" usage="rp_blit"> 2136 2136 + <!-- one bit per varying component: --> 2137 2137 + <reg32 offset="0" name="DISABLE"/> 2138 2138 + </array> 2139 2139 + 2140 2140 + <array offset="0x9252" name="VPC_VARYING_LM_TRANSFER_CNTL" stride="1" length="4" variants="A8XX-" usage="rp_blit"> 2990 2141 <!-- one bit per varying component: --> 2991 2142 <reg32 offset="0" name="DISABLE"/> 2992 2143 </array> ··· 3035 2158 </bitset> 3036 2159 3037 2160 <reg32 offset="0x9216" name="VPC_SO_MAPPING_WPTR" type="a6xx_vpc_so_mapping_wptr" variants="A6XX-A7XX" usage="rp_blit"/> 2161 2161 + <reg32 offset="0x9180" name="VPC_SO_MAPPING_WPTR" type="a6xx_vpc_so_mapping_wptr" variants="A8XX-" usage="rp_blit"/> 3038 2162 3039 2163 <bitset name="a6xx_vpc_so_mapping_port" inline="yes"> 3040 2164 <bitfield name="A_BUF" low="0" high="1" type="uint"/> ··· 3048 2170 3049 2171 <!-- special register, write multiple times to load SO program (not readable) --> 3050 2172 <reg32 offset="0x9217" name="VPC_SO_MAPPING_PORT" type="a6xx_vpc_so_mapping_port" variants="A6XX-A7XX" usage="rp_blit"/> 2173 2173 + <reg32 offset="0x9181" name="VPC_SO_MAPPING_PORT" type="a6xx_vpc_so_mapping_port" variants="A8XX-" usage="rp_blit"/> 3051 2174 3052 2175 <reg64 offset="0x9218" name="VPC_SO_QUERY_BASE" type="waddress" align="32" variants="A6XX-A7XX" usage="cmd"/> 2176 2176 + <reg64 offset="0x9182" name="VPC_SO_QUERY_BASE" type="waddress" align="32" variants="A8XX-" usage="cmd"/> 3053 2177 3054 2178 <array offset="0x921a" name="VPC_SO" stride="7" length="4" variants="A6XX-A7XX" usage="cmd"> 2179 2179 + <reg64 offset="0" name="BUFFER_BASE" type="waddress" align="32"/> 2180 2180 + <reg32 offset="2" name="BUFFER_SIZE" low="2" high="31" shr="2"/> 2181 2181 + <reg32 offset="3" name="BUFFER_STRIDE" low="0" high="9" shr="2"/> 2182 2182 + <reg32 offset="4" name="BUFFER_OFFSET" low="2" high="31" shr="2"/> 2183 2183 + <reg64 offset="5" name="FLUSH_BASE" type="waddress" align="32"/> 2184 2184 + </array> 2185 2185 + 2186 2186 + <array offset="0x9184" name="VPC_SO" stride="7" length="4" variants="A8XX-" usage="cmd"> 3055 2187 <reg64 offset="0" name="BUFFER_BASE" type="waddress" align="32"/> 3056 2188 <reg32 offset="2" name="BUFFER_SIZE" low="2" high="31" shr="2"/> 3057 2189 <reg32 offset="3" name="BUFFER_STRIDE" low="0" high="9" shr="2"/> ··· 3074 2186 </bitset> 3075 2187 3076 2188 <reg32 offset="0x9236" name="VPC_REPLACE_MODE_CNTL" type="a6xx_vpc_replace_mode_cntl" variants="A6XX-A7XX" usage="cmd"/> 2189 2189 + <reg32 offset="0x9310" name="VPC_REPLACE_MODE_CNTL" type="a6xx_vpc_replace_mode_cntl" variants="A8XX-" usage="cmd"/> 3077 2190 3078 2191 <reg32 offset="0x9300" name="VPC_ROTATION_CNTL" low="0" high="2" variants="A6XX-A7XX" usage="cmd"/> 2192 2192 + <reg32 offset="0x9312" name="VPC_ROTATION_CNTL" low="0" high="2" variants="A8XX-" usage="cmd"/> 3079 2193 3080 2194 <bitset name="a6xx_vpc_xs_cntl" inline="yes"> 3081 2195 <doc> ··· 3101 2211 <reg32 offset="0x9302" name="VPC_GS_CNTL" type="a6xx_vpc_xs_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 3102 2212 <reg32 offset="0x9303" name="VPC_DS_CNTL" type="a6xx_vpc_xs_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 3103 2213 2214 2214 + <reg32 offset="0x9300" name="VPC_VS_CNTL" type="a6xx_vpc_xs_cntl" variants="A8XX-" usage="rp_blit"/> 2215 2215 + <reg32 offset="0x9301" name="VPC_GS_CNTL" type="a6xx_vpc_xs_cntl" variants="A8XX-" usage="rp_blit"/> 2216 2216 + <reg32 offset="0x9302" name="VPC_DS_CNTL" type="a6xx_vpc_xs_cntl" variants="A8XX-" usage="rp_blit"/> 2217 2217 + 3104 2218 <bitset name="a6xx_vpc_ps_cntl" inline="yes"> 3105 2219 <bitfield name="NUMNONPOSVAR" low="0" high="7" type="uint"/> 3106 2220 <!-- for fixed-function (i.e. no GS) gl_PrimitiveID in FS --> ··· 3125 2231 </bitset> 3126 2232 3127 2233 <reg32 offset="0x9304" name="VPC_PS_CNTL" type="a6xx_vpc_ps_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2234 2234 + <reg32 offset="0x9303" name="VPC_PS_CNTL" type="a6xx_vpc_ps_cntl" variants="A8XX-" usage="rp_blit"/> 3128 2235 3129 2236 <bitset name="a6xx_vpc_so_cntl" inline="yes"> 3130 2237 <!-- ··· 3139 2244 </bitset> 3140 2245 3141 2246 <reg32 offset="0x9305" name="VPC_SO_CNTL" type="a6xx_vpc_so_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2247 2247 + <reg32 offset="0x9304" name="VPC_SO_CNTL" type="a6xx_vpc_so_cntl" variants="A8XX-" usage="rp_blit"/> 3142 2248 3143 2249 <bitset name="a6xx_so_override" inline="yes"> 3144 2250 <bitfield name="DISABLE" pos="0" type="boolean"/> 3145 2251 </bitset> 3146 2252 3147 2253 <reg32 offset="0x9306" name="VPC_SO_OVERRIDE" type="a6xx_so_override" variants="A6XX-A7XX" usage="rp_blit"/> 2254 2254 + <reg32 offset="0x9305" name="VPC_SO_OVERRIDE" type="a6xx_so_override" variants="A8XX-" usage="rp_blit"/> 3148 2255 3149 2256 <reg32 offset="0x9807" name="PC_DGEN_SO_OVERRIDE" type="a6xx_so_override" variants="A7XX" usage="rp_blit"/> 2257 2257 + <reg32 offset="0x9b0a" name="PC_DGEN_SO_OVERRIDE" type="a6xx_so_override" variants="A8XX-" usage="rp_blit"/> 3150 2258 3151 2259 <reg32 offset="0x9307" name="VPC_PS_RAST_CNTL" type="a6xx_rast_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2260 2260 + <reg32 offset="0x9306" name="VPC_PS_RAST_CNTL" type="a6xx_rast_cntl" variants="A8XX-" usage="rp_blit"/> 3152 2261 3153 3153 - <reg32 offset="0x9308" name="VPC_ATTR_BUF_GMEM_SIZE" variants="A7XX" type="uint" usage="rp_blit"/> 3154 3154 - <reg32 offset="0x9309" name="VPC_ATTR_BUF_GMEM_BASE" variants="A7XX" type="uint" usage="rp_blit"/> 2262 2262 + <reg32 offset="0x9308" name="VPC_ATTR_BUF_GMEM_SIZE" variants="A7XX" type="uint" usage="cmd"/> 2263 2263 + <reg32 offset="0x9309" name="VPC_ATTR_BUF_GMEM_BASE" variants="A7XX" type="hex" usage="cmd"/> 3155 2264 3156 3156 - <reg32 offset="0x9b09" name="PC_ATTR_BUF_GMEM_SIZE" variants="A7XX" type="uint" usage="rp_blit"/> 2265 2265 + <reg32 offset="0x9314" name="VPC_ATTR_BUF_GMEM_SIZE" variants="A8XX-" type="uint" usage="cmd"/> 2266 2266 + <reg32 offset="0x9315" name="VPC_ATTR_BUF_GMEM_BASE" variants="A8XX-" type="hex" usage="cmd"/> 2267 2267 + 2268 2268 + <reg32 offset="0x9316" name="VPC_POS_BUF_GMEM_SIZE" variants="A8XX-" type="uint" usage="cmd"/> 2269 2269 + <reg32 offset="0x9317" name="VPC_POS_BUF_GMEM_BASE" variants="A8XX-" type="hex" usage="cmd"/> 2270 2270 + 2271 2271 + <reg32 offset="0x9318" name="VPC_BV_POS_BUF_GMEM_SIZE" variants="A8XX-" type="uint" usage="cmd"/> 2272 2272 + <reg32 offset="0x9319" name="VPC_BV_POS_BUF_GMEM_BASE" variants="A8XX-" type="hex" usage="cmd"/> 2273 2273 + 2274 2274 + <reg32 offset="0x9b09" name="PC_ATTR_BUF_GMEM_SIZE" variants="A7XX" type="uint" usage="cmd"/> 2275 2275 + <reg32 offset="0x9b16" name="PC_ATTR_BUF_GMEM_SIZE" variants="A8XX-" type="uint" usage="cmd"/> 2276 2276 + 2277 2277 + <reg32 offset="0x9b17" name="PC_POS_BUF_GMEM_SIZE" variants="A8XX-" type="uint" usage="cmd"/> 2278 2278 + <reg32 offset="0x9b18" name="PC_BV_POS_BUF_GMEM_SIZE" variants="A8XX-" type="uint" usage="cmd"/> 3157 2279 3158 2280 <reg32 offset="0x930a" name="VPC_UNKNOWN_930A" variants="A7XX"/> 3159 2281 2282 2282 + <reg32 offset="0x9313" name="VPC_UNKNOWN_9313" variants="A8XX-"/> 2283 2283 + <reg32 offset="0x9e17" name="PC_UNKNOWN_9E17" variants="A8XX-"/> 2284 2284 + 3160 2285 <reg32 offset="0x960a" name="VPC_FLATSHADE_MODE_CNTL" variants="A7XX"/> 2286 2286 + <reg32 offset="0x9741" name="VPC_FLATSHADE_MODE_CNTL" variants="A8XX-"/> 3161 2287 3162 2288 <!-- 0x9307-0x95ff invalid --> 3163 2289 3164 2290 <!-- TODO: 0x9600-0x97ff range --> 3165 3165 - <reg32 offset="0x9600" name="VPC_DBG_ECO_CNTL" usage="cmd"/> <!-- always 0x0 ? TODO: 0x1fbf37ff valid mask --> 3166 3166 - <reg32 offset="0x9601" name="VPC_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode" usage="cmd"/> 3167 3167 - <reg32 offset="0x9602" name="VPC_UNKNOWN_9602" pos="0" usage="cmd"/> <!-- always 0x0 ? --> 3168 3168 - <reg32 offset="0x9603" name="VPC_UNKNOWN_9603" low="0" high="26"/> 2291 2291 + <reg32 offset="0x9600" name="VPC_DBG_ECO_CNTL" variants="A6XX-A7XX" usage="cmd"/> <!-- always 0x0 ? TODO: 0x1fbf37ff valid mask --> 2292 2292 + <reg32 offset="0x9601" name="VPC_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode" usage="cmd" variants="A6XX"/> 2293 2293 + <reg32 offset="0x9680" name="VPC_DBG_ECO_CNTL" variants="A8XX-"/> 2294 2294 + <reg32 offset="0x9604" name="VPC_DBG_ECO_CNTL_2" variants="A8XX-"/> 2295 2295 + <reg32 offset="0x9742" name="VPC_DBG_ECO_CNTL_1" variants="A8XX-"/> 2296 2296 + <reg32 offset="0x9745" name="VPC_DBG_ECO_CNTL_3" variants="A8XX-"/> 2297 2297 + <reg32 offset="0x9602" name="VPC_LB_MODE_CNTL" pos="0" variants="A6XX-A7XX" usage="init"/> <!-- always 0x0 ? --> 2298 2298 + <reg32 offset="0x9740" name="VPC_LB_MODE_CNTL" pos="0" variants="A8XX-"/> 2299 2299 + <reg32 offset="0x9603" name="VPC_STATUS" low="0" high="26" variants="A6XX-A7XX"/> 2300 2300 + <reg32 offset="0x9600" name="VPC_STATUS" low="0" high="26" variants="A8XX-"/> 3169 2301 <array offset="0x9604" name="VPC_PERFCTR_VPC_SEL" stride="1" length="6" variants="A6XX"/> 3170 3170 - <array offset="0x960b" name="VPC_PERFCTR_VPC_SEL" stride="1" length="12" variants="A7XX-"/> 3171 3171 - <!-- 0x960a-0x9623 invalid --> 3172 3172 - <!-- TODO: regs from 0x9624-0x963a --> 3173 3173 - <!-- 0x963b-0x97ff invalid --> 2302 2302 + <array offset="0x960b" name="VPC_PERFCTR_VPC_SEL" stride="1" length="12" variants="A7XX"/> 2303 2303 + <array offset="0x9670" name="VPC_PERFCTR_VPC_SEL_2" stride="1" length="12" variants="A8XX-"/> 2304 2304 + <array offset="0x9690" name="VPC_PERFCTR_VPC_SEL" stride="1" length="12" variants="A8XX-"/> 2305 2305 + <array offset="0x9750" name="VPC_PERFCTR_VPC_SEL_1" stride="1" length="12" variants="A8XX-"/> 2306 2306 + 2307 2307 + <reg64 offset="0x9634" name="VPC_CONTEXT_SWITCH_SO_SAVE_ADDR" type="waddress" variants="A6XX-A7XX"/> 2308 2308 + <reg64 offset="0x9602" name="VPC_CONTEXT_SWITCH_SO_SAVE_ADDR" type="waddress" variants="A8XX-"/> 2309 2309 + 2310 2310 + <reg32 offset="0x980b" name="PC_UNKNOWN_980B" variants="A8XX-"/> 3174 2311 3175 2312 <reg32 offset="0x9800" name="PC_HS_PARAM_0" low="0" high="5" type="uint" variants="A6XX-A7XX" usage="rp_blit"/> 2313 2313 + <reg32 offset="0x9b10" name="PC_HS_PARAM_0" low="0" high="5" type="uint" variants="A8XX-" usage="rp_blit"/> 3176 2314 3177 2315 <bitset name="a6xx_pc_hs_param_1" inline="yes"> 3178 2316 <bitfield name="SIZE" low="0" high="10" type="uint"/> ··· 3213 2285 </bitset> 3214 2286 3215 2287 <reg32 offset="0x9801" name="PC_HS_PARAM_1" type="a6xx_pc_hs_param_1" variants="A6XX-A7XX" usage="rp_blit"/> 2288 2288 + <reg32 offset="0x9b11" name="PC_HS_PARAM_1" type="a6xx_pc_hs_param_1" variants="A8XX-" usage="rp_blit"/> 3216 2289 3217 2290 <bitset name="a6xx_pc_ds_param" inline="yes"> 3218 2291 <bitfield name="SPACING" low="0" high="1" type="a6xx_tess_spacing"/> ··· 3221 2292 </bitset> 3222 2293 3223 2294 <reg32 offset="0x9802" name="PC_DS_PARAM" type="a6xx_pc_ds_param" variants="A6XX-A7XX" usage="rp_blit"/> 2295 2295 + <reg32 offset="0x9b12" name="PC_DS_PARAM" type="a6xx_pc_ds_param" variants="A8XX-" usage="rp_blit"/> 3224 2296 3225 2297 <reg32 offset="0x9803" name="PC_RESTART_INDEX" low="0" high="31" type="uint" variants="A6XX-A7XX" usage="rp_blit"/> 2298 2298 + <reg32 offset="0x9b15" name="PC_RESTART_INDEX" low="0" high="31" type="uint" variants="A8XX-" usage="rp_blit"/> 3226 2299 3227 2300 <reg32 offset="0x9804" name="PC_MODE_CNTL" low="0" high="7" variants="A6XX-A7XX" usage="rp_blit"/> 2301 2301 + <reg32 offset="0x9b00" name="PC_MODE_CNTL" low="0" high="14" variants="A8XX" usage="rp_blit"/> 3228 2302 3229 2303 <reg32 offset="0x9805" name="PC_POWER_CNTL" low="0" high="2" usage="rp_blit"/> 3230 2304 ··· 3236 2304 </bitset> 3237 2305 3238 2306 <reg32 offset="0x9806" name="PC_PS_CNTL" type="a6xx_pc_ps_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2307 2307 + <reg32 offset="0x9b06" name="PC_PS_CNTL" type="a6xx_pc_ps_cntl" variants="A8XX-" usage="rp_blit"/> 3239 2308 3240 2309 <bitset name="a6xx_pc_dgen_so_cntl" inline="yes"> 3241 2310 <bitfield name="STREAM_ENABLE" low="15" high="18" type="hex"/> ··· 3244 2311 3245 2312 <!-- New in a6xx gen3+ --> 3246 2313 <reg32 offset="0x9808" name="PC_DGEN_SO_CNTL" type="a6xx_pc_dgen_so_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2314 2314 + <reg32 offset="0x9b0b" name="PC_DGEN_SO_CNTL" type="a6xx_pc_dgen_so_cntl" variants="A8XX-" usage="rp_blit"/> 3247 2315 3248 2316 <bitset name="a6xx_pc_dgen_su_conservative_ras_cntl" inline="yes"> 3249 2317 <bitfield name="CONSERVATIVERASEN" pos="0" type="boolean"/> 3250 2318 </bitset> 3251 2319 3252 2320 <reg32 offset="0x980a" name="PC_DGEN_SU_CONSERVATIVE_RAS_CNTL" type="a6xx_pc_dgen_su_conservative_ras_cntl" variants="A6XX-A7XX"/> 2321 2321 + <reg32 offset="0x9b08" name="PC_DGEN_SU_CONSERVATIVE_RAS_CNTL" type="a6xx_pc_dgen_su_conservative_ras_cntl" variants="A8XX-"/> 2322 2322 + 2323 2323 + <reg32 offset="0x9b0c" name="PC_VS_INPUT_CNTL" variants="A8XX-" usage="rp_blit"> 2324 2324 + <bitfield name="INSTR_CNT" low="0" high="5" type="uint"/> 2325 2325 + <bitfield name="SIDEBAND_CNT" low="6" high="8" type="uint"/> 2326 2326 + </reg32> 3253 2327 3254 2328 <!-- 0x9840 - 0x9842 are not readable --> 3255 2329 <bitset name="a6xx_draw_initiator" inline="yes"> ··· 3266 2326 <reg32 offset="0x9840" name="PC_DRAW_INITIATOR" type="a6xx_draw_initiator" variants="A6XX-A7XX"/> 3267 2327 <reg32 offset="0x9841" name="PC_KERNEL_INITIATOR" type="a6xx_draw_initiator" variants="A6XX-A7XX"/> 3268 2328 2329 2329 + <reg32 offset="0x9800" name="PC_DRAW_INITIATOR" type="a6xx_draw_initiator" variants="A8XX-"/> 2330 2330 + <reg32 offset="0x9801" name="PC_KERNEL_INITIATOR" type="a6xx_draw_initiator" variants="A8XX-"/> 2331 2331 + 3269 2332 <bitset name="a6xx_event_initiator" inline="yes"> 3270 2333 <!-- I think only the low bit is actually used? --> 3271 2334 <bitfield name="STATE_ID" low="16" high="23"/> ··· 3276 2333 </bitset> 3277 2334 3278 2335 <reg32 offset="0x9842" name="PC_EVENT_INITIATOR" type="a6xx_event_initiator" variants="A6XX-A7XX"/> 2336 2336 + <reg32 offset="0x9802" name="PC_EVENT_INITIATOR" type="a6xx_event_initiator" variants="A8XX-"/> 3279 2337 3280 2338 <!-- 3281 2339 0x9880 written in a lot of places by SQE, same value gets written ··· 3289 2345 3290 2346 <reg32 offset="0x9981" name="PC_DGEN_RAST_CNTL" type="a6xx_rast_cntl" variants="A6XX" usage="rp_blit"/> 3291 2347 <reg32 offset="0x9809" name="PC_DGEN_RAST_CNTL" type="a6xx_rast_cntl" variants="A7XX" usage="rp_blit"/> 2348 2348 + <reg32 offset="0x9812" name="PC_DGEN_RAST_CNTL" type="a6xx_rast_cntl" variants="A8XX" usage="rp_blit"/> 3292 2349 3293 2350 <!-- Both are a750+. 3294 2351 Probably needed to correctly overlap execution of several draws. 3295 2352 --> 3296 2353 <reg32 offset="0x9885" name="PC_HS_BUFFER_SIZE" variants="A7XX" usage="cmd"/> 2354 2354 + <reg32 offset="0x9814" name="PC_HS_BUFFER_SIZE" variants="A8XX-" usage="cmd"/> 3297 2355 <!-- Blob adds a bit more space {0x10, 0x20, 0x30, 0x40} bytes, but the meaning of 3298 2356 this additional space is not known. 3299 2357 --> 3300 2358 <reg32 offset="0x9886" name="PC_TF_BUFFER_SIZE" variants="A7XX" usage="cmd"/> 2359 2359 + <reg32 offset="0x9815" name="PC_TF_BUFFER_SIZE" variants="A8XX-" usage="cmd"/> 3301 2360 3302 2361 <!-- 0x9982-0x9aff invalid --> 3303 2362 3304 2363 <reg32 offset="0x9b00" name="PC_CNTL" type="a6xx_pc_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2364 2364 + <reg32 offset="0x9b01" name="PC_CNTL" type="a6xx_pc_cntl" variants="A8XX-" usage="rp_blit"/> 3305 2365 3306 2366 <bitset name="a6xx_pc_xs_cntl" inline="yes"> 3307 2367 <doc> ··· 3329 2381 <reg32 offset="0x9b03" name="PC_HS_CNTL" type="a6xx_pc_xs_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 3330 2382 <reg32 offset="0x9b04" name="PC_DS_CNTL" type="a6xx_pc_xs_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 3331 2383 2384 2384 + <reg32 offset="0x9b02" name="PC_VS_CNTL" type="a6xx_pc_xs_cntl" variants="A8XX-" usage="rp_blit"/> 2385 2385 + <reg32 offset="0x9b03" name="PC_GS_CNTL" type="a6xx_pc_xs_cntl" variants="A8XX-" usage="rp_blit"/> 2386 2386 + <reg32 offset="0x9b04" name="PC_HS_CNTL" type="a6xx_pc_xs_cntl" variants="A8XX-" usage="rp_blit"/> 2387 2387 + <reg32 offset="0x9b05" name="PC_DS_CNTL" type="a6xx_pc_xs_cntl" variants="A8XX-" usage="rp_blit"/> 2388 2388 + 3332 2389 <reg32 offset="0x9b05" name="PC_GS_PARAM_0" type="a6xx_gs_param_0" variants="A6XX-A7XX" usage="rp_blit"/> 2390 2390 + <reg32 offset="0x9b13" name="PC_GS_PARAM_0" type="a6xx_gs_param_0" variants="A8XX-" usage="rp_blit"/> 3333 2391 3334 2392 <reg32 offset="0x9b06" name="PC_PRIMITIVE_CNTL_6" variants="A6XX" usage="rp_blit"> 3335 2393 <doc> ··· 3345 2391 </reg32> 3346 2392 3347 2393 <reg32 offset="0x9b07" name="PC_STEREO_RENDERING_CNTL" type="a6xx_stereo_rendering_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2394 2394 + <reg32 offset="0x9b09" name="PC_STEREO_RENDERING_CNTL" type="a6xx_stereo_rendering_cntl" variants="A8XX-" usage="rp_blit"/> 3348 2395 <!-- mask of enabled views, doesn't exist on A630 --> 3349 2396 <reg32 offset="0x9b08" name="PC_STEREO_RENDERING_VIEWMASK" type="hex" low="0" high="15" variants="A6XX-A7XX" usage="rp_blit"/> 2397 2397 + <reg32 offset="0x9b0d" name="PC_STEREO_RENDERING_VIEWMASK" type="hex" low="0" high="15" variants="A8XX-" usage="rp_blit"/> 3350 2398 <!-- 0x9b09-0x9bff invalid --> 3351 2399 <reg32 offset="0x9c00" name="PC_2D_EVENT_CMD"> 3352 2400 <!-- special register (but note first 8 bits can be written/read) --> 3353 2401 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/> 3354 2402 <bitfield name="STATE_ID" low="8" high="15"/> 3355 2403 </reg32> 3356 3356 - <!-- 0x9c01-0x9dff invalid --> 3357 3357 - <!-- TODO: 0x9e00-0xa000 range incomplete --> 3358 3358 - <reg32 offset="0x9e00" name="PC_DBG_ECO_CNTL"/> 3359 3359 - <reg32 offset="0x9e01" name="PC_ADDR_MODE_CNTL" type="a5xx_address_mode"/> 2404 2404 + 2405 2405 + <reg32 offset="0x9e50" name="PC_CHICKEN_BITS_1" variants="A8XX-"/> 2406 2406 + <reg32 offset="0x9f20" name="PC_CHICKEN_BITS_2" variants="A8XX-"/> 2407 2407 + <reg32 offset="0x9e22" name="PC_CHICKEN_BITS_3" variants="A8XX-"/> 2408 2408 + <reg32 offset="0x9e23" name="PC_CHICKEN_BITS_4" variants="A8XX-"/> 2409 2409 + <reg32 offset="0x9f23" name="PC_CHICKEN_BITS_5" variants="A8XX-"/> 2410 2410 + 2411 2411 + <reg32 offset="0x9e00" name="PC_DBG_ECO_CNTL" variants="A6XX-A7XX"/> 2412 2412 + <reg32 offset="0x9e53" name="PC_DBG_ECO_CNTL" variants="A8XX-"/> 2413 2413 + <reg32 offset="0x9e01" name="PC_ADDR_MODE_CNTL" type="a5xx_address_mode" variants="A6XX"/> 3360 2414 <reg64 offset="0x9e04" name="PC_DMA_BASE" type="address" variants="A6XX-A7XX"/> 3361 2415 <reg32 offset="0x9e06" name="PC_DMA_OFFSET" type="uint" variants="A6XX-A7XX"/> 3362 2416 <reg32 offset="0x9e07" name="PC_DMA_SIZE" type="uint" variants="A6XX-A7XX"/> 3363 2417 2418 2418 + <reg64 offset="0x9e06" name="PC_DMA_BASE" type="address" variants="A8XX-"/> 2419 2419 + <reg32 offset="0x9e08" name="PC_DMA_OFFSET" type="uint" variants="A8XX-"/> 2420 2420 + <reg32 offset="0x9e09" name="PC_DMA_SIZE" type="uint" variants="A8XX-"/> 2421 2421 + 3364 2422 <reg64 offset="0x9e08" name="PC_TESS_BASE" variants="A6XX" type="waddress" align="32" usage="cmd"/> 3365 2423 <reg64 offset="0x9810" name="PC_TESS_BASE" variants="A7XX" type="waddress" align="32" usage="cmd"/> 2424 2424 + <reg64 offset="0x9816" name="PC_TESS_BASE" variants="A8XX-" type="waddress" align="32" usage="cmd"/> 3366 2425 3367 2426 <reg32 offset="0x9e0b" name="PC_DRAWCALL_CNTL" type="vgt_draw_initiator_a4xx" variants="A6XX-A7XX"> 3368 2427 <doc> ··· 3385 2418 </reg32> 3386 2419 <reg32 offset="0x9e0c" name="PC_DRAWCALL_INSTANCE_NUM" type="uint" variants="A6XX-A7XX"/> 3387 2420 <reg32 offset="0x9e0d" name="PC_DRAWCALL_SIZE" type="uint" variants="A6XX-A7XX"/> 2421 2421 + 2422 2422 + <reg32 offset="0x9e00" name="PC_DRAWCALL_CNTL" type="vgt_draw_initiator_a4xx" variants="A8XX-"/> 2423 2423 + <reg32 offset="0x9e01" name="PC_DRAWCALL_INSTANCE_NUM" type="uint" variants="A8XX-"/> 2424 2424 + <reg32 offset="0x9e02" name="PC_DRAWCALL_SIZE" type="uint" variants="A8XX-"/> 3388 2425 3389 2426 <!-- These match the contents of CP_SET_BIN_DATA (not written directly) --> 3390 2427 <bitset name="a6xx_pc_vis_stream_cntl" inline="yes"> ··· 3401 2430 <reg64 offset="0x9e12" name="PC_PVIS_STREAM_BIN_BASE" type="waddress" align="32" variants="A6XX-A7XX"/> 3402 2431 <reg64 offset="0x9e14" name="PC_DVIS_STREAM_BIN_BASE" type="waddress" align="32" variants="A6XX-A7XX"/> 3403 2432 2433 2433 + <reg32 offset="0x9e0a" name="PC_AUTO_VERTEX_STRIDE"/> 2434 2434 + <reg32 offset="0x9e0d" name="PC_VIS_STREAM_CNTL" type="a6xx_pc_vis_stream_cntl" variants="A8XX-"/> 2435 2435 + <reg64 offset="0x9e0e" name="PC_PVIS_STREAM_BIN_BASE" type="waddress" align="32" variants="A8XX-"/> 2436 2436 + <reg64 offset="0x9e10" name="PC_DVIS_STREAM_BIN_BASE" type="waddress" align="32" variants="A8XX-"/> 2437 2437 + 3404 2438 <bitset name="a6xx_pc_drawcall_cntl_override" inline="yes"> 3405 2439 <doc>Written by CP_SET_VISIBILITY_OVERRIDE handler</doc> 3406 2440 <bitfield name="OVERRIDE" pos="0" type="boolean"/> 3407 2441 </bitset> 3408 2442 3409 2443 <reg32 offset="0x9e1c" name="PC_DRAWCALL_CNTL_OVERRIDE" type="a6xx_pc_drawcall_cntl_override" variants="A6XX-A7XX"/> 2444 2444 + <reg32 offset="0x9e04" name="PC_DRAWCALL_CNTL_OVERRIDE" type="a6xx_pc_drawcall_cntl_override" variants="A8XX-"/> 3410 2445 3411 3411 - <reg32 offset="0x9e24" name="PC_UNKNOWN_9E24" variants="A7XX-" usage="cmd"/> 2446 2446 + <reg32 offset="0x9e24" name="PC_UNKNOWN_9E24" variants="A7XX-" usage="init"/> 3412 2447 3413 2448 <array offset="0x9e34" name="PC_PERFCTR_PC_SEL" stride="1" length="8" variants="A6XX"/> 3414 3414 - <array offset="0x9e42" name="PC_PERFCTR_PC_SEL" stride="1" length="16" variants="A7XX-"/> 2449 2449 + <array offset="0x9e42" name="PC_PERFCTR_PC_SEL" stride="1" length="16" variants="A7XX"/> 2450 2450 + <array offset="0x9e30" name="PC_PERFCTR_PC_SEL" stride="1" length="16" variants="A8XX-"/> 2451 2451 + <array offset="0x9f00" name="PC_SLICE_PERFCTR_PC_SEL" stride="1" length="16" variants="A8XX-"/> 3415 2452 3416 2453 <!-- always 0x0 --> 3417 3417 - <reg32 offset="0x9e72" name="PC_UNKNOWN_9E72" usage="cmd"/> 2454 2454 + <reg32 offset="0x9e72" name="PC_CONTEXT_SWITCH_GFX_PREEMPTION_MODE" variants="A6XX-A7XX" usage="init"/> 2455 2455 + <reg32 offset="0x9e63" name="PC_CONTEXT_SWITCH_GFX_PREEMPTION_MODE" variants="A8XX-"/> 2456 2456 + <reg32 offset="0x9e64" name="PC_CONTEXT_SWITCH_STABILIZE_CNTL_1" variants="A8XX-"/> 3418 2457 3419 2458 <reg32 offset="0xa000" name="VFD_CNTL_0" usage="rp_blit"> 3420 2459 <bitfield name="FETCH_CNT" low="0" high="5" type="uint"/> ··· 3511 2530 3512 2531 <reg32 offset="0xa0f8" name="VFD_POWER_CNTL" low="0" high="2" usage="rp_blit"/> 3513 2532 3514 3514 - <reg32 offset="0xa600" name="VFD_DBG_ECO_CNTL" variants="A7XX-" usage="cmd"/> 2533 2533 + <reg32 offset="0xa600" name="VFD_DBG_ECO_CNTL" variants="A7XX-" usage="init"/> 3515 2534 3516 3516 - <reg32 offset="0xa601" name="VFD_ADDR_MODE_CNTL" type="a5xx_address_mode"/> 2535 2535 + <reg32 offset="0xa601" name="VFD_ADDR_MODE_CNTL" type="a5xx_address_mode" variants="A6XX"/> 3517 2536 <array offset="0xa610" name="VFD_PERFCTR_VFD_SEL" stride="1" length="8" variants="A6XX"/> 3518 2537 <array offset="0xa610" name="VFD_PERFCTR_VFD_SEL" stride="1" length="16" variants="A7XX-"/> 2538 2538 + <reg32 offset="0xa639" name="VFD_CB_BV_THRESHOLD" variants="A8XX-"/> 2539 2539 + <reg32 offset="0xa63a" name="VFD_CB_BR_THRESHOLD" variants="A8XX-"/> 2540 2540 + <reg32 offset="0xa63b" name="VFD_CB_BUSY_REQ_CNT" variants="A8XX-"/> 2541 2541 + <reg32 offset="0xa63c" name="VFD_CB_LP_REQ_CNT" variants="A8XX-"/> 3519 2542 3520 2543 <!-- 3521 2544 Note: this seems to always be paired with another bit in another ··· 3578 2593 <bitset name="a6xx_sp_xs_output_cntl" inline="yes"> 3579 2594 <!-- # of VS outputs including pos/psize --> 3580 2595 <bitfield name="OUT" low="0" high="5" type="uint"/> 3581 3581 - <!-- FLAGS_REGID only for GS --> 3582 3582 - <bitfield name="FLAGS_REGID" low="6" high="13" type="a3xx_regid"/> 3583 2596 </bitset> 3584 2597 3585 2598 <reg32 offset="0xa800" name="SP_VS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="rp_blit"> ··· 3703 2720 <bitfield name="OFFSET" low="0" high="18" shr="11"/> 3704 2721 </bitset> 3705 2722 2723 2723 + <bitset name="a6xx_sp_xs_hysteresis" inline="yes"> 2724 2724 + <doc>Same on a6xx/a7xx, UMD should not need to write this</doc> 2725 2725 + </bitset> 2726 2726 + 2727 2727 + <bitset name="a8xx_sp_xs_hysteresis" inline="yes"> 2728 2728 + <doc>UMD needs to write in some cases</doc> 2729 2729 + <!-- seen 0x400, 0xc00, 0x1000, 0x1c00, 0x1000, 0x2000, 0x3000 --> 2730 2730 + </bitset> 2731 2731 + 3706 2732 <reg32 offset="0xa81b" name="SP_VS_PROGRAM_COUNTER_OFFSET" type="uint" usage="rp_blit"/> 3707 2733 <reg64 offset="0xa81c" name="SP_VS_BASE" type="address" align="32" usage="rp_blit"/> 3708 2734 <reg32 offset="0xa81e" name="SP_VS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/> ··· 3721 2729 <reg32 offset="0xa823" name="SP_VS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/> 3722 2730 <reg32 offset="0xa824" name="SP_VS_INSTR_SIZE" low="0" high="27" type="uint" usage="rp_blit"/> 3723 2731 <reg32 offset="0xa825" name="SP_VS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="rp_blit"/> 2732 2732 + <reg32 offset="0xa826" name="SP_VS_HYSTERESIS" type="a6xx_sp_xs_hysteresis" variants="A6XX-A7XX"/> 2733 2733 + <reg32 offset="0xa826" name="SP_VS_HYSTERESIS" type="a8xx_sp_xs_hysteresis" variants="A8XX-"/> 3724 2734 <reg32 offset="0xa82d" name="SP_VS_VGS_CNTL" variants="A7XX-" usage="cmd"/> 3725 2735 3726 2736 <reg32 offset="0xa830" name="SP_HS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="rp_blit"> ··· 3748 2754 <reg32 offset="0xa83b" name="SP_HS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/> 3749 2755 <reg32 offset="0xa83c" name="SP_HS_INSTR_SIZE" low="0" high="27" type="uint" usage="rp_blit"/> 3750 2756 <reg32 offset="0xa83d" name="SP_HS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="rp_blit"/> 2757 2757 + <reg32 offset="0xa83e" name="SP_HS_HYSTERESIS" type="a6xx_sp_xs_hysteresis" variants="A6XX-A7XX"/> 2758 2758 + <reg32 offset="0xa83e" name="SP_HS_HYSTERESIS" type="a8xx_sp_xs_hysteresis" variants="A8XX-"/> 3751 2759 <reg32 offset="0xa82f" name="SP_HS_VGS_CNTL" variants="A7XX-" usage="cmd"/> 3752 2760 3753 2761 <reg32 offset="0xa840" name="SP_DS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="rp_blit"> ··· 3787 2791 <reg32 offset="0xa863" name="SP_DS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/> 3788 2792 <reg32 offset="0xa864" name="SP_DS_INSTR_SIZE" low="0" high="27" type="uint" usage="rp_blit"/> 3789 2793 <reg32 offset="0xa865" name="SP_DS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="rp_blit"/> 2794 2794 + <reg32 offset="0xa866" name="SP_DS_HYSTERESIS" type="a6xx_sp_xs_hysteresis" variants="A6XX-A7XX"/> 2795 2795 + <reg32 offset="0xa866" name="SP_DS_HYSTERESIS" type="a8xx_sp_xs_hysteresis" variants="A8XX-"/> 3790 2796 <reg32 offset="0xa868" name="SP_DS_VGS_CNTL" variants="A7XX-" usage="cmd"/> 3791 2797 3792 2798 <reg32 offset="0xa870" name="SP_GS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="rp_blit"> ··· 3812 2814 <reg32 offset="0xa872" name="SP_GS_BOOLEAN_CF_MASK" type="hex" usage="rp_blit"/> 3813 2815 3814 2816 <!-- TODO: exact same layout as 0xa802-0xa81a --> 3815 3815 - <reg32 offset="0xa873" name="SP_GS_OUTPUT_CNTL" type="a6xx_sp_xs_output_cntl" usage="rp_blit"/> 2817 2817 + <reg32 offset="0xa873" name="SP_GS_OUTPUT_CNTL" type="a6xx_sp_xs_output_cntl" usage="rp_blit"> 2818 2818 + <!-- FLAGS_REGID only for GS --> 2819 2819 + <bitfield name="FLAGS_REGID" low="6" high="13" type="a3xx_regid"/> 2820 2820 + </reg32> 3816 2821 <array offset="0xa874" name="SP_GS_OUTPUT" stride="1" length="16" usage="rp_blit"> 3817 2822 <reg32 offset="0x0" name="REG"> 3818 2823 <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/> ··· 3844 2843 <reg32 offset="0xa894" name="SP_GS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/> 3845 2844 <reg32 offset="0xa895" name="SP_GS_INSTR_SIZE" low="0" high="27" type="uint" usage="rp_blit"/> 3846 2845 <reg32 offset="0xa896" name="SP_GS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="rp_blit"/> 2846 2846 + <reg32 offset="0xa897" name="SP_GS_HYSTERESIS" type="a6xx_sp_xs_hysteresis" variants="A6XX-A7XX"/> 2847 2847 + <reg32 offset="0xa897" name="SP_GS_HYSTERESIS" type="a8xx_sp_xs_hysteresis" variants="A8XX-"/> 3847 2848 <reg32 offset="0xa899" name="SP_GS_VGS_CNTL" variants="A7XX-" usage="cmd"/> 3848 2849 3849 2850 <reg64 offset="0xa8a0" name="SP_VS_SAMPLER_BASE" type="address" align="16" usage="cmd"/> ··· 3889 2886 <reg64 offset="0xa986" name="SP_PS_PVT_MEM_BASE" type="waddress" align="32" usage="rp_blit"/> 3890 2887 <reg32 offset="0xa988" name="SP_PS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/> 3891 2888 3892 3892 - <reg32 offset="0xa989" name="SP_BLEND_CNTL" usage="rp_blit"> 2889 2889 + <bitset name="a6xx_sp_blend_cntl" inline="yes"> 3893 2890 <!-- per-mrt enable bit --> 3894 2891 <bitfield name="ENABLE_BLEND" low="0" high="7"/> 3895 3895 - <bitfield name="UNK8" pos="8" type="boolean"/> 2892 2892 + <bitfield name="INDEPENDENT_BLEND_EN" pos="8" type="boolean"/> 3896 2893 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/> 3897 2894 <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/> 2895 2895 + </bitset> 2896 2896 + 2897 2897 + <reg32 offset="0xa989" name="SP_BLEND_CNTL" type="a6xx_sp_blend_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2898 2898 + <reg32 offset="0xa989" name="SP_BLEND_CNTL" type="a6xx_sp_blend_cntl" variants="A8XX-" usage="rp_blit"> 2899 2899 + <bitfield name="ALPHA_TO_ONE" pos="11" type="boolean" variants="A8XX-"/> 3898 2900 </reg32> 2901 2901 + 3899 2902 <reg32 offset="0xa98a" name="SP_SRGB_CNTL" usage="rp_blit"> 3900 2903 <!-- Same as RB_SRGB_CNTL --> 3901 2904 <bitfield name="SRGB_MRT0" pos="0" type="boolean"/> ··· 4002 2993 <reg32 offset="0xa9a7" name="SP_PS_TSIZE" low="0" high="7" type="uint" usage="rp_blit"/> 4003 2994 <reg32 offset="0xa9a8" name="SP_UNKNOWN_A9A8" low="0" high="16" usage="cmd"/> <!-- always 0x0 ? --> 4004 2995 <reg32 offset="0xa9a9" name="SP_PS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="rp_blit"/> 4005 4005 - <reg32 offset="0xa9ab" name="SP_PS_UNKNOWN_A9AB" variants="A7XX-" usage="cmd"/> 2996 2996 + <reg32 offset="0xa9ab" name="SP_PS_HYSTERESIS" type="a6xx_sp_xs_hysteresis" variants="A6XX-A7XX"/> 2997 2997 + <reg32 offset="0xa9ab" name="SP_PS_HYSTERESIS" type="a8xx_sp_xs_hysteresis" variants="A8XX-"/> 4006 2998 4007 2999 <!-- TODO: unknown bool register at 0xa9aa, likely same as 0xa8c0-0xa8c3 but for FS --> 4008 4008 - 4009 4009 - 4010 4010 - 4011 3000 4012 3001 <reg32 offset="0xa9b0" name="SP_CS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="cmd"> 4013 3002 <bitfield name="THREADSIZE" pos="20" type="a6xx_threadsize"/> ··· 4043 3036 must be at least the actual CONSTLEN. 4044 3037 </doc> 4045 3038 </bitfield> 3039 3039 + <bitfield name="ALT_LM_ENCODE" pos="26" type="boolean"/> 4046 3040 </reg32> 4047 3041 <reg32 offset="0xa9b2" name="SP_CS_BOOLEAN_CF_MASK" type="hex" usage="cmd"/> 4048 3042 <reg32 offset="0xa9b3" name="SP_CS_PROGRAM_COUNTER_OFFSET" type="uint" usage="cmd"/> ··· 4055 3047 <reg32 offset="0xa9bb" name="SP_CS_CONFIG" type="a6xx_sp_xs_config" usage="cmd"/> 4056 3048 <reg32 offset="0xa9bc" name="SP_CS_INSTR_SIZE" low="0" high="27" type="uint" usage="cmd"/> 4057 3049 <reg32 offset="0xa9bd" name="SP_CS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="cmd"/> 4058 4058 - <reg32 offset="0xa9be" name="SP_CS_UNKNOWN_A9BE" variants="A7XX-" usage="cmd"/> 3050 3050 + <reg32 offset="0xa9be" name="SP_CS_HYSTERESIS" type="a6xx_sp_xs_hysteresis" variants="A6XX-A7XX"/> 3051 3051 + <reg32 offset="0xa9be" name="SP_CS_HYSTERESIS" type="a8xx_sp_xs_hysteresis" variants="A8XX-"/> 4059 3052 <reg32 offset="0xa9c5" name="SP_CS_VGS_CNTL" variants="A7XX-" usage="cmd"/> 4060 3053 4061 3054 <!-- new in a6xx gen4, matches SP_CS_CONST_CONFIG_0 --> ··· 4167 3158 <bitfield name="RT7" low="28" high="31"/> 4168 3159 </reg32> 4169 3160 3161 3161 + <array offset="0xaa04" name="SP_MRT_BLEND_CNTL" stride="1" length="8" variants="A8XX-"> 3162 3162 + <reg32 offset="0" name="REG"> 3163 3163 + <bitfield name="COLOR_BLEND_EN" pos="0" type="boolean"/> 3164 3164 + <bitfield name="ALPHA_BLEND_EN" pos="1" type="boolean"/> 3165 3165 + <bitfield name="COMPONENT_WRITE_MASK" low="7" high="10"/> 3166 3166 + </reg32> 3167 3167 + </array> 3168 3168 + 3169 3169 + <reg32 offset="0xaa0c" name="SP_ALPHA_TEST_CNTL" variants="A8XX-"> 3170 3170 + <bitfield name="ALPHA_TEST" pos="8" type="boolean"/> 3171 3171 + </reg32> 3172 3172 + 4170 3173 <reg32 offset="0xaaf2" name="SP_UNKNOWN_AAF2" type="uint" usage="cmd"/> 4171 3174 4172 3175 <!-- ··· 4203 3182 --> 4204 3183 <bitfield name="CONSTANT_DEMOTION_ENABLE" pos="0" type="boolean"/> 4205 3184 <bitfield name="ISAMMODE" low="1" high="2" type="a6xx_isam_mode"/> 4206 4206 - <bitfield name="SHARED_CONSTS_ENABLE" pos="3" type="boolean"/> <!-- see HLSQ_SHARED_CONSTS --> 3185 3185 + <bitfield name="SHARED_CONSTS_ENABLE" pos="3" type="boolean"/> <!-- see SP_SHARED_CONSTANT --> 4207 3186 </reg32> 4208 3187 4209 3188 <reg32 offset="0xab01" name="SP_UNKNOWN_AB01" variants="A7XX-" usage="cmd"/> 4210 4210 - <reg32 offset="0xab02" name="SP_UNKNOWN_AB02" variants="A7XX-" usage="cmd"/> 3189 3189 + <reg32 offset="0xab02" name="SP_HLSQ_MODE_CNTL" variants="A7XX-" usage="cmd"> 3190 3190 + <bitfield name="SHARED_CONSTS_ENABLE" pos="0" type="boolean"/> <!-- see SP_SHARED_CONSTANT --> 3191 3191 + </reg32> 4211 3192 4212 3193 <reg32 offset="0xab04" name="SP_PS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/> 4213 3194 <reg32 offset="0xab05" name="SP_PS_INSTR_SIZE" low="0" high="27" type="uint" usage="rp_blit"/> 3195 3195 + 3196 3196 + <reg32 offset="0xab06" name="SP_BIN_SIZE" type="a8xx_bin_size" variants="A8XX-" usage="rp_blit"/> 4214 3197 4215 3198 <array offset="0xab10" name="SP_GFX_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="rp_blit"> 4216 3199 <reg64 offset="0" name="DESCRIPTOR" variants="A6XX"> ··· 4235 3210 --> 4236 3211 <reg64 offset="0xab1a" name="SP_GFX_UAV_BASE" type="address" align="16" usage="cmd"/> 4237 3212 <reg32 offset="0xab20" name="SP_GFX_USIZE" low="0" high="6" type="uint" variants="A6XX-A7XX" usage="cmd"/> 3213 3213 + <reg32 offset="0xab09" name="SP_GFX_USIZE" low="0" high="6" type="uint" variants="A8XX-" usage="cmd"/> 4238 3214 4239 3215 <reg32 offset="0xab22" name="SP_UNKNOWN_AB22" variants="A7XX" usage="cmd"/> 3216 3216 + 3217 3217 + <reg32 offset="0xab23" name="SP_UNKNOWN_AB23" variants="A8XX-"/> 4240 3218 4241 3219 <enum name="a6xx_sp_a2d_output_ifmt_type"> 4242 3220 <value name="OUTPUT_IFMT_2D_FLOAT" value="0"/> ··· 4262 3234 <reg32 offset="0xacc0" name="SP_A2D_OUTPUT_INFO" type="a6xx_sp_a2d_output_info" variants="A6XX" usage="rp_blit"/> 4263 3235 <reg32 offset="0xa9bf" name="SP_A2D_OUTPUT_INFO" type="a6xx_sp_a2d_output_info" variants="A7XX-" usage="rp_blit"/> 4264 3236 4265 4265 - <reg32 offset="0xae00" name="SP_DBG_ECO_CNTL" usage="cmd"/> 4266 4266 - <reg32 offset="0xae01" name="SP_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/> 3237 3237 + <reg32 offset="0xae00" name="SP_DBG_ECO_CNTL" usage="init"/> 3238 3238 + <reg32 offset="0xae01" name="SP_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode" variants="A6XX"/> 3239 3239 + <reg32 offset="0xae01" name="SP_SHADER_PROFILING" variants="A8XX-"/> 4267 3240 <reg32 offset="0xae02" name="SP_NC_MODE_CNTL"> 4268 3241 <!-- TODO: valid bits 0x3c3f, see kernel --> 4269 3242 </reg32> 4270 4270 - <reg32 offset="0xae03" name="SP_CHICKEN_BITS" usage="cmd"/> 4271 4271 - <reg32 offset="0xae04" name="SP_NC_MODE_CNTL_2" usage="cmd"> 3243 3243 + <reg32 offset="0xae03" name="SP_CHICKEN_BITS" usage="init"/> 3244 3244 + <reg32 offset="0xae04" name="SP_NC_MODE_CNTL_2" usage="init"> 4272 3245 <bitfield name="F16_NO_INF" pos="3" type="boolean"/> 4273 3246 </reg32> 4274 3247 4275 4275 - <reg32 offset="0xae06" name="SP_UNKNOWN_AE06" variants="A7XX-" usage="cmd"/> 4276 4276 - <reg32 offset="0xae08" name="SP_CHICKEN_BITS_1" variants="A7XX-" usage="cmd"/> 4277 4277 - <reg32 offset="0xae09" name="SP_CHICKEN_BITS_2" variants="A7XX-" usage="cmd"/> 4278 4278 - <reg32 offset="0xae0a" name="SP_CHICKEN_BITS_3" variants="A7XX-" usage="cmd"/> 3248 3248 + <reg32 offset="0xae05" name="SP_SS_CHICKEN_BITS_0" variants="A8XX-"/> 3249 3249 + <reg32 offset="0xae06" name="SP_ISDB_CNTL" variants="A7XX-" usage="init"/> 3250 3250 + <reg32 offset="0xae07" name="SP_PERFCTR_CNTL"/> 3251 3251 + <reg32 offset="0xae08" name="SP_CHICKEN_BITS_1" variants="A7XX-" usage="init"/> 3252 3252 + <reg32 offset="0xae09" name="SP_CHICKEN_BITS_2" variants="A7XX-" usage="init"/> 3253 3253 + <reg32 offset="0xae0a" name="SP_CHICKEN_BITS_3" variants="A7XX-" usage="init"/> 3254 3254 + <reg32 offset="0xae0b" name="SP_CHICKEN_BITS_4" variants="A8XX-"/> 3255 3255 + <reg32 offset="0xae0c" name="SP_STATUS"/> 4279 3256 4280 4280 - <reg32 offset="0xae0f" name="SP_PERFCTR_SHADER_MASK" usage="cmd"> 3257 3257 + <reg32 offset="0xae0f" name="SP_PERFCTR_SHADER_MASK" usage="init"> 4281 3258 <!-- some perfcntrs are affected by a per-stage enable bit 4282 3259 (PERF_SP_ALU_WORKING_CYCLES for example) 4283 3260 TODO: verify position of HS/DS/GS bits --> ··· 4293 3260 <bitfield name="FS" pos="4" type="boolean"/> 4294 3261 <bitfield name="CS" pos="5" type="boolean"/> 4295 3262 </reg32> 4296 4296 - <array offset="0xae10" name="SP_PERFCTR_SP_SEL" stride="1" length="24"/> 3263 3263 + <array offset="0xae10" name="SP_PERFCTR_SP_SEL" stride="1" length="24" variants="A6XX"/> 4297 3264 <array offset="0xae60" name="SP_PERFCTR_HLSQ_SEL" stride="1" length="6" variants="A7XX-"/> 4298 4298 - <reg32 offset="0xae6a" name="SP_UNKNOWN_AE6A" variants="A7XX-" usage="cmd"/> 4299 4299 - <reg32 offset="0xae6b" name="SP_UNKNOWN_AE6B" variants="A7XX-" usage="cmd"/> 4300 4300 - <reg32 offset="0xae6c" name="SP_HLSQ_DBG_ECO_CNTL" variants="A7XX-" usage="cmd"/> 3265 3265 + <reg32 offset="0xae6a" name="SP_UNKNOWN_AE6A" variants="A7XX-" usage="init"/> 3266 3266 + <reg32 offset="0xae6b" name="SP_HLSQ_TIMEOUT_THRESHOLD_DP" variants="A7XX-" usage="init"/> 3267 3267 + <reg32 offset="0xae6c" name="SP_HLSQ_DBG_ECO_CNTL" variants="A7XX-" usage="init"/> 4301 3268 <reg32 offset="0xae6d" name="SP_READ_SEL" variants="A7XX-"> 3269 3269 + <bitfield name="CONTEXT" low="26" high="30"/> 3270 3270 + <bitfield name="SLICE" low="21" high="25"/> 4302 3271 <bitfield name="LOCATION" low="18" high="20" type="a7xx_state_location"/> 4303 3272 <bitfield name="PIPE" low="16" high="17" type="adreno_pipe"/> 4304 3273 <bitfield name="STATETYPE" low="8" high="15" type="a7xx_statetype_id"/> ··· 4308 3273 <bitfield name="SPTP" low="0" high="3"/> 4309 3274 </reg32> 4310 3275 <reg32 offset="0xae71" name="SP_DBG_CNTL" variants="A7XX-"/> 4311 4311 - <reg32 offset="0xae73" name="SP_UNKNOWN_AE73" variants="A7XX-" usage="cmd"/> 3276 3276 + <reg32 offset="0xae73" name="SP_HLSQ_DBG_ECO_CNTL_1" variants="A7XX-"/> 3277 3277 + <reg32 offset="0xae74" name="SP_HLSQ_DBG_ECO_CNTL_2" variants="A7XX-"/> 3278 3278 + <reg32 offset="0xae76" name="SP_HLSQ_DBG_ECO_CNTL_3" variants="A8XX-"/> 4312 3279 <array offset="0xae80" name="SP_PERFCTR_SP_SEL" stride="1" length="36" variants="A7XX-"/> 4313 3280 <!-- TODO: there are 4 more percntr select registers (0xae28-0xae2b) --> 4314 3281 <!-- TODO: there are a few unknown registers in the 0xae30-0xae52 range --> 4315 4315 - <reg32 offset="0xbe22" name="SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE"/> 3282 3282 + <reg32 offset="0xae52" name="SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE"/> 3283 3283 + 3284 3284 + <reg64 offset="0xae10" name="SP_HLSQ_GC_GMEM_RANGE_MIN" variants="A8XX-"/> 3285 3285 + <reg64 offset="0xae12" name="SP_HLSQ_LPAC_GMEM_RANGE_MIN" variants="A8XX-"/> 3286 3286 + <reg32 offset="0xae15" name="SP_LPAC_CPI_STATUS" variants="A8XX-"/> 3287 3287 + <reg32 offset="0xae16" name="SP_LPAC_DBG_STATUS" variants="A8XX-"/> 3288 3288 + <reg32 offset="0xae17" name="SP_LPAC_ISDB_BATCH_COUNT" variants="A8XX-"/> 3289 3289 + <reg32 offset="0xae18" name="SP_LPAC_ISDB_BATCH_COUNT_INCR_EN" variants="A8XX-"/> 3290 3290 + <reg32 offset="0xae19" name="SP_LPAC_ISDB_BATCH_COUNT_SHADERS" variants="A8XX-"/> 3291 3291 + <reg32 offset="0xae30" name="SP_ISDB_BATCH_COUNT" variants="A7XX-"/> 3292 3292 + <reg32 offset="0xae31" name="SP_ISDB_BATCH_COUNT_INCR_EN" variants="A7XX-"/> 3293 3293 + <reg32 offset="0xae32" name="SP_ISDB_BATCH_COUNT_SHADERS" variants="A7XX-"/> 3294 3294 + <reg32 offset="0xae35" name="SP_ISDB_DEBUG_CONFIG" variants="A7XX-"/> 3295 3295 + 3296 3296 + <reg32 offset="0xae3a" name="SP_SELF_THROTTLE_CONTROL" variants="A7XX-"/> 3297 3297 + <reg32 offset="0xae3b" name="SP_DISPATCH_CNTL" variants="A7XX-"/> 3298 3298 + <reg64 offset="0xae3c" name="SP_SW_DEBUG_ADDR" variants="A7XX-"/> 3299 3299 + <reg64 offset="0xae3e" name="SP_ISDB_DEBUG_ADDR" variants="A7XX-"/> 3300 3300 + 3301 3301 + <array offset="0xaec0" name="SP_PERFCTR_HLSQ_SEL_2_0" stride="1" length="6" variants="A7XX-"/> 4316 3302 4317 3303 <!-- 4318 3304 The downstream kernel calls the debug cluster of registers ··· 4341 3285 color base for compute shaders. 4342 3286 --> 4343 3287 <reg64 offset="0xb180" name="TPL1_CS_BORDER_COLOR_BASE" type="address" align="128" usage="cmd"/> 4344 4344 - <reg32 offset="0xb182" name="SP_UNKNOWN_B182" low="0" high="2" usage="cmd"/> 4345 4345 - <reg32 offset="0xb183" name="SP_UNKNOWN_B183" low="0" high="23" usage="cmd"/> 3288 3288 + <reg32 offset="0xb182" name="TPL1_PS_ROTATION_CNTL" low="0" high="2" usage="cmd"/> 3289 3289 + <reg32 offset="0xb183" name="TPL1_PS_SWIZZLE_CNTL" low="0" high="23" usage="cmd"/> 4346 3290 4347 3291 <reg32 offset="0xb190" name="SP_UNKNOWN_B190"/> 4348 3292 <reg32 offset="0xb191" name="SP_UNKNOWN_B191"/> 3293 3293 + 3294 3294 + <reg32 offset="0xb2d6" name="TPL1_A2D_BIN_SIZE" type="a8xx_bin_size" variants="A8XX-" usage="rp_blit"/> 3295 3295 + <reg32 offset="0xb2d7" name="TPL1_A2D_FILTER_CNTL" variants="A8XX-" usage="rp_blit"/> 4349 3296 4350 3297 <reg32 offset="0xb300" name="TPL1_RAS_MSAA_CNTL" usage="rp_blit"> 4351 3298 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> ··· 4362 3303 <!-- looks to work in the same way as a5xx: --> 4363 3304 <reg64 offset="0xb302" name="TPL1_GFX_BORDER_COLOR_BASE" type="address" align="128" usage="cmd"/> 4364 3305 <reg32 offset="0xb304" name="TPL1_MSAA_SAMPLE_POS_CNTL" type="a6xx_msaa_sample_pos_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 4365 4365 - <reg32 offset="0xb305" name="TPL1_PROGRAMMABLE_MSAA_POS_0" type="a6xx_programmable_msaa_pos" usage="rp_blit"/> 4366 4366 - <reg32 offset="0xb306" name="TPL1_PROGRAMMABLE_MSAA_POS_1" type="a6xx_programmable_msaa_pos" usage="rp_blit"/> 3306 3306 + <reg32 offset="0xb305" name="TPL1_PROGRAMMABLE_MSAA_POS_0" type="a6xx_programmable_msaa_pos" usage="rp_blit" variants="A6XX-A7XX" /> 3307 3307 + <reg32 offset="0xb306" name="TPL1_PROGRAMMABLE_MSAA_POS_1" type="a6xx_programmable_msaa_pos" usage="rp_blit" variants="A6XX-A7XX" /> 4367 3308 <reg32 offset="0xb307" name="TPL1_WINDOW_OFFSET" type="a6xx_reg_xy" usage="rp_blit"/> 3309 3309 + 3310 3310 + <reg32 offset="0xb304" name="TPL1_BIN_SIZE" type="a8xx_bin_size" variants="A8XX-" usage="rp_blit"/> 4368 3311 4369 3312 <enum name="a6xx_coord_round"> 4370 3313 <value value="0" name="COORD_TRUNCATE"/> ··· 4376 3315 <enum name="a6xx_nearest_mode"> 4377 3316 <value value="0" name="ROUND_CLAMP_TRUNCATE"/> 4378 3317 <value value="1" name="CLAMP_ROUND_TRUNCATE"/> 3318 3318 + <value value="2" name="ROUND_FLOAT_TO_INT"/> <!-- only ARRAYCOORDROUNDMODE --> 4379 3319 </enum> 4380 3320 4381 3321 <reg32 offset="0xb309" name="TPL1_MODE_CNTL" usage="cmd"> 4382 3322 <bitfield name="ISAMMODE" low="0" high="1" type="a6xx_isam_mode"/> 4383 3323 <bitfield name="TEXCOORDROUNDMODE" pos="2" type="a6xx_coord_round"/> 3324 3324 + <bitfield name="ARRAYCOORDROUNDMODE" low="3" high="4" type="a6xx_coord_round"/> 4384 3325 <bitfield name="NEARESTMIPSNAP" pos="5" type="a6xx_nearest_mode"/> 3326 3326 + <bitfield name="SAMPLEREPLICATE" pos="6" type="boolean"/> 4385 3327 <bitfield name="DESTDATATYPEOVERRIDE" pos="7" type="boolean"/> 3328 3328 + <bitfield name="PACK_SAMP_REDUCED_PRECISION" pos="8" type="boolean"/> 4386 3329 </reg32> 4387 3330 <reg32 offset="0xb310" name="SP_UNKNOWN_B310" variants="A7XX-" usage="cmd"/> 4388 3331 ··· 4452 3387 <bitfield name="TYPE" low="29" high="31" type="a6xx_tex_type"/> 4453 3388 </reg32> 4454 3389 <reg32 offset="0xab21" name="SP_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A7XX" usage="rp_blit"/> 3390 3390 + <reg32 offset="0xab07" name="SP_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A8XX-" usage="rp_blit"/> 4455 3391 4456 3392 <!-- always 0x100000 or 0x1000000? --> 4457 4457 - <reg32 offset="0xb600" name="TPL1_DBG_ECO_CNTL" low="0" high="25" usage="cmd"/> 4458 4458 - <reg32 offset="0xb601" name="TPL1_ADDR_MODE_CNTL" type="a5xx_address_mode"/> 4459 4459 - <reg32 offset="0xb602" name="TPL1_DBG_ECO_CNTL1" usage="cmd"> 3393 3393 + <reg32 offset="0xb600" name="TPL1_DBG_ECO_CNTL" low="0" high="25" usage="init"/> 3394 3394 + <reg32 offset="0xb601" name="TPL1_ADDR_MODE_CNTL" type="a5xx_address_mode" variants="A6XX"/> 3395 3395 + <reg32 offset="0xb602" name="TPL1_DBG_ECO_CNTL1" usage="init"> 4460 3396 <!-- Affects UBWC in some way, if BLIT_OP_SCALE is done with this bit set 4461 3397 and if other blit is done without it - UBWC image may be copied incorrectly. 4462 3398 --> ··· 4470 3404 <bitfield name="UPPER_BIT" pos="4" type="uint"/> 4471 3405 <bitfield name="UNK6" low="6" high="7"/> 4472 3406 </reg32> 4473 4473 - <reg32 offset="0xb605" name="TPL1_UNKNOWN_B605" low="0" high="7" type="uint" variants="A6XX" usage="cmd"/> <!-- always 0x0 or 0x44 ? --> 3407 3407 + <reg32 offset="0xb605" name="TPL1_UNKNOWN_B605" low="0" high="7" type="uint" variants="A6XX" usage="init"/> <!-- always 0x0 or 0x44 ? --> 4474 3408 4475 3409 <array offset="0xb608" name="TPL1_BICUBIC_WEIGHTS_TABLE" stride="1" length="5" variants="A6XX"> 4476 3410 <reg32 offset="0" name="REG" low="0" high="29"/> ··· 4480 3414 <reg32 offset="0" name="REG" low="0" high="29" usage="cmd"/> 4481 3415 </array> 4482 3416 3417 3417 + <array offset="0xb606" name="TPL1_BICUBIC_WEIGHTS_TABLE" stride="1" length="25" variants="A8XX"> 3418 3418 + <reg32 offset="0" name="REG" low="0" high="29"/> 3419 3419 + </array> 3420 3420 + 4483 3421 <array offset="0xb610" name="TPL1_PERFCTR_TP_SEL" stride="1" length="12" variants="A6XX"/> 4484 3422 <array offset="0xb610" name="TPL1_PERFCTR_TP_SEL" stride="1" length="18" variants="A7XX"/> 3423 3423 + <array offset="0xb620" name="TPL1_PERFCTR_TP_SEL" stride="1" length="20" variants="A8XX"/> 4485 3424 4486 3425 <!-- TODO: 4 more perfcntr sel at 0xb620 ? --> 4487 3426 ··· 4529 3458 4530 3459 <reg32 offset="0xa9ae" name="SP_PS_CNTL_1" variants="A7XX-" usage="rp_blit"> 4531 3460 <bitfield name="SYSVAL_REGS_COUNT" low="0" high="7" type="uint"/> 4532 4532 - <!-- UNK8 is set on a730/a740 --> 4533 4533 - <bitfield name="UNK8" pos="8" type="boolean"/> 4534 4534 - <!-- UNK9 is set on a750 --> 4535 4535 - <bitfield name="UNK9" pos="9" type="boolean"/> 3461 3461 + <bitfield name="DEFER_WAVE_ALLOC_DIS" pos="8" type="boolean"/> 3462 3462 + <bitfield name="EVICT_BUF_MODE" low="9" high="10"/> 4536 3463 </reg32> 4537 3464 4538 3465 <reg32 offset="0xb820" name="HLSQ_LOAD_STATE_GEOM_CMD"/> ··· 4581 3512 <reg32 offset="0xb985" type="a6xx_sp_reg_prog_id_2" name="SP_REG_PROG_ID_2" variants="A6XX" usage="rp_blit"/> 4582 3513 <reg32 offset="0xb986" type="a6xx_sp_reg_prog_id_3" name="SP_REG_PROG_ID_3" variants="A6XX" usage="rp_blit"/> 4583 3514 <reg32 offset="0xb987" name="SP_CS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A6XX" usage="cmd"/> 4584 4584 - <reg32 offset="0xa9c6" type="a6xx_sp_ps_wave_cntl" name="SP_PS_WAVE_CNTL" variants="A7XX-" usage="rp_blit"/> 3515 3515 + <reg32 offset="0xa9c6" type="a6xx_sp_ps_wave_cntl" name="SP_PS_WAVE_CNTL" variants="A7XX" usage="rp_blit"/> 3516 3516 + <reg32 offset="0xa9c6" name="SP_PS_WAVE_CNTL" variants="A8XX-" usage="rp_blit"> 3517 3517 + <bitfield name="VARYINGS" pos="1" type="boolean"/> 3518 3518 + </reg32> 4585 3519 <reg32 offset="0xa9c7" name="SP_LB_PARAM_LIMIT" low="0" high="2" variants="A7XX-" usage="rp_blit"> 4586 4586 - <bitfield name="PRIMALLOCTHRESHOLD" low="0" high="2" type="uint"/> 3520 3520 + <bitfield name="PRIMALLOCTHRESHOLD" low="0" high="2" type="uint"/> 4587 3521 </reg32> 4588 3522 <reg32 offset="0xa9c8" name="SP_REG_PROG_ID_0" variants="A7XX-" usage="rp_blit"> 4589 3523 <bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/> ··· 4790 3718 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/> 4791 3719 </reg32> 4792 3720 4793 4793 - <reg32 offset="0xab1f" name="SP_UPDATE_CNTL" variants="A7XX-" usage="cmd"> 3721 3721 + <reg32 offset="0xab1f" name="SP_UPDATE_CNTL" variants="A7XX" usage="cmd"> 4794 3722 <doc> 4795 3723 This register clears pending loads queued up by 4796 3724 CP_LOAD_STATE6. Each bit resets a particular kind(s) of ··· 4813 3741 <bitfield name="GFX_BINDLESS" low="17" high="24" type="hex"/> 4814 3742 </reg32> 4815 3743 3744 3744 + <reg32 offset="0xab1f" name="SP_UPDATE_CNTL" variants="A8XX" usage="cmd"> 3745 3745 + <doc> 3746 3746 + This register clears pending loads queued up by 3747 3747 + CP_LOAD_STATE6. Each bit resets a particular kind(s) of 3748 3748 + CP_LOAD_STATE6. 3749 3749 + </doc> 3750 3750 + 3751 3751 + <!-- per-stage state: shader, non-bindless UBO, textures, and samplers --> 3752 3752 + <bitfield name="VS_STATE" pos="0" type="boolean"/> 3753 3753 + <bitfield name="HS_STATE" pos="1" type="boolean"/> 3754 3754 + <bitfield name="DS_STATE" pos="2" type="boolean"/> 3755 3755 + <bitfield name="GS_STATE" pos="3" type="boolean"/> 3756 3756 + <bitfield name="FS_STATE" pos="4" type="boolean"/> 3757 3757 + <bitfield name="CS_STATE" pos="5" type="boolean"/> 3758 3758 + </reg32> 3759 3759 + 3760 3760 + <reg32 offset="0xa9c0" name="SP_CS_BINDLESS_INVALIDATE"/> 3761 3761 + <reg32 offset="0xab08" name="SP_GFX_BINDLESS_INVALIDATE"/> 3762 3762 + 4816 3763 <reg32 offset="0xbb10" name="SP_PS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A6XX" usage="rp_blit"/> 4817 3764 <reg32 offset="0xab03" name="SP_PS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A7XX-" usage="rp_blit"/> 4818 3765 4819 3766 <array offset="0xab40" name="SP_SHARED_CONSTANT_GFX" stride="1" length="64" variants="A7XX"/> 3767 3767 + <array offset="0xab30" name="SP_SHARED_CONSTANT_GFX" stride="1" length="128" variants="A8XX-"/> 4820 3768 4821 3769 <reg32 offset="0xbb11" name="HLSQ_SHARED_CONSTS" variants="A6XX" usage="cmd"> 4822 3770 <doc> ··· 4873 3781 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/> 4874 3782 </reg32> 4875 3783 4876 4876 - <reg32 offset="0xbe00" name="HLSQ_UNKNOWN_BE00" variants="A6XX" usage="cmd"/> <!-- all bits valid except bit 29 --> 4877 4877 - <reg32 offset="0xbe01" name="HLSQ_UNKNOWN_BE01" low="4" high="6" variants="A6XX" usage="cmd"/> 4878 4878 - <reg32 offset="0xbe04" name="HLSQ_DBG_ECO_CNTL" variants="A6XX" usage="cmd"/> 4879 4879 - <reg32 offset="0xbe05" name="HLSQ_ADDR_MODE_CNTL" type="a5xx_address_mode"/> 3784 3784 + <reg32 offset="0xbe00" name="HLSQ_UNKNOWN_BE00" variants="A6XX" usage="init"/> <!-- all bits valid except bit 29 --> 3785 3785 + <reg32 offset="0xbe01" name="HLSQ_UNKNOWN_BE01" low="4" high="6" variants="A6XX" usage="init"/> 3786 3786 + <reg32 offset="0xbe04" name="HLSQ_DBG_ECO_CNTL" variants="A6XX" usage="init"/> 3787 3787 + <reg32 offset="0xbe05" name="HLSQ_ADDR_MODE_CNTL" type="a5xx_address_mode" variants="A6XX"/> 4880 3788 <reg32 offset="0xbe08" name="HLSQ_UNKNOWN_BE08" low="0" high="15"/> 4881 3789 <array offset="0xbe10" name="HLSQ_PERFCTR_HLSQ_SEL" stride="1" length="6"/> 4882 3790 4883 3791 <!-- TODO: some valid registers between 0xbe20 and 0xbe33 --> 4884 4884 - <reg32 offset="0xbe22" name="HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE"/> 3792 3792 + <reg32 offset="0xbe22" name="HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE" variants="A6XX"/> 4885 3793 4886 3794 <reg32 offset="0xc000" name="SP_AHB_READ_APERTURE" variants="A7XX-"/> 4887 3795 ··· 5010 3918 <reg32 offset="0x0001" name="SYSTEM_CACHE_CNTL_0"/> 5011 3919 <reg32 offset="0x0002" name="SYSTEM_CACHE_CNTL_1"/> 5012 3920 <reg32 offset="0x0039" name="CX_MISC_TCM_RET_CNTL" variants="A7XX-"/> 3921 3921 + <reg32 offset="0x0087" name="CX_MISC_SLICE_ENABLE_FINAL" variants="A8XX"/> 5013 3922 <reg32 offset="0x0400" name="CX_MISC_SW_FUSE_VALUE" variants="A7XX-"> 5014 3923 <bitfield pos="0" name="FASTBLEND" type="boolean"/> 5015 3924 <bitfield pos="1" name="LPAC" type="boolean"/>

+1 -1

drivers/gpu/drm/msm/registers/adreno/a6xx_enums.xml

reviewed

··· 303 303 </enum> 304 304 305 305 <!-- 306 306 - Used in a6xx_a2d_bit_cntl.. the value mostly seems to correlate to the 306 306 + Used in a6xx_a2d_blt_cntl.. the value mostly seems to correlate to the 307 307 component type/size, so I think it relates to internal format used for 308 308 blending? The one exception is that 16b unorm and 32b float use the 309 309 same value... maybe 16b unorm is uncommon enough that it was just easier

+121

drivers/gpu/drm/msm/registers/adreno/a8xx_descriptors.xml

reviewed

··· 1 1 + <?xml version="1.0" encoding="UTF-8"?> 2 2 + <database xmlns="http://nouveau.freedesktop.org/" 3 3 + xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" 4 4 + xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> 5 5 + <import file="freedreno_copyright.xml"/> 6 6 + <import file="adreno/adreno_common.xml"/> 7 7 + <import file="adreno/adreno_pm4.xml"/> 8 8 + <import file="adreno/a6xx_enums.xml"/> 9 9 + <import file="adreno/a8xx_enums.xml"/> 10 10 + 11 11 + <domain name="A8XX_TEX_SAMP" width="32"> 12 12 + <doc>Texture sampler dwords</doc> 13 13 + <reg32 offset="0" name="0"> 14 14 + <bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/> 15 15 + <bitfield name="MIPMAPING_DIS" pos="1" type="boolean"/> 16 16 + <bitfield name="XY_MAG" low="2" high="3" type="a6xx_tex_filter"/> 17 17 + <bitfield name="XY_MIN" low="4" high="5" type="a6xx_tex_filter"/> 18 18 + <bitfield name="WRAP_S" low="6" high="8" type="a6xx_tex_clamp"/> 19 19 + <bitfield name="WRAP_T" low="9" high="11" type="a6xx_tex_clamp"/> 20 20 + <bitfield name="WRAP_R" low="12" high="14" type="a6xx_tex_clamp"/> 21 21 + <bitfield name="MSAA_BOX_FILTERING" pos="15" type="boolean"/> 22 22 + <bitfield name="LOD_BIAS" low="16" high="28" type="fixed" radix="8"/> 23 23 + <bitfield name="ANISO" low="29" high="31" type="a6xx_tex_aniso"/> 24 24 + </reg32> 25 25 + <reg32 offset="1" name="1"> 26 26 + <bitfield name="MAX_LOD" low="0" high="11" type="ufixed" radix="8"/> 27 27 + <bitfield name="MIN_LOD" low="12" high="23" type="ufixed" radix="8"/> 28 28 + <bitfield name="REDUCTION_MODE" low="24" high="25" type="a6xx_reduction_mode"/> 29 29 + <bitfield name="COMPARE_FUNC" low="26" high="28" type="adreno_compare_func"/> 30 30 + <bitfield name="CHROMA_LINEAR" pos="29" type="boolean"/> 31 31 + <bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="30" type="boolean"/> 32 32 + <bitfield name="UNNORM_COORDS" pos="31" type="boolean"/> 33 33 + </reg32> 34 34 + <reg32 offset="2" name="2"> 35 35 + <bitfield name="FASTBORDERCOLOREN" pos="0" type="boolean"/> 36 36 + <bitfield name="FASTBORDERCOLOR" low="1" high="2" type="a6xx_fast_border_color"/> 37 37 + <bitfield name="BCOLOR" low="7" high="31"/> 38 38 + </reg32> 39 39 + <reg32 offset="3" name="3"/> 40 40 + </domain> 41 41 + 42 42 + <domain name="A8XX_TEX_MEMOBJ" width="32" varset="chip"> 43 43 + <doc>Texture memobj dwords</doc> 44 44 + <reg32 offset="0" name="0"> 45 45 + <bitfield name="BASE_LO" low="6" high="31" shr="6"/> 46 46 + </reg32> 47 47 + <reg32 offset="1" name="1"> 48 48 + <bitfield name="BASE_HI" low="0" high="16"/> 49 49 + <bitfield name="TYPE" low="17" high="19" type="a6xx_tex_type"/> 50 50 + <bitfield name="DEPTH" low="20" high="31" type="uint"/> 51 51 + </reg32> 52 52 + <reg32 offset="2" name="2"> 53 53 + <bitfield name="WIDTH" low="0" high="14" type="uint"/> 54 54 + <bitfield name="HEIGHT" low="15" high="29" type="uint"/> 55 55 + <bitfield name="SAMPLES" low="30" high="31" type="a3xx_msaa_samples"/> 56 56 + </reg32> 57 57 + <reg32 offset="3" name="3"> 58 58 + <bitfield name="FMT" low="0" high="7" type="a6xx_format"/> 59 59 + <bitfield name="SWAP" low="8" high="9" type="a3xx_color_swap"/> 60 60 + <bitfield name="SWIZ_X" low="10" high="12" type="a8xx_tex_swiz"/> 61 61 + <bitfield name="SWIZ_Y" low="13" high="15" type="a8xx_tex_swiz"/> 62 62 + <bitfield name="SWIZ_Z" low="16" high="18" type="a8xx_tex_swiz"/> 63 63 + <bitfield name="SWIZ_W" low="19" high="21" type="a8xx_tex_swiz"/> 64 64 + </reg32> 65 65 + <reg32 offset="4" name="4"> 66 66 + <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/> 67 67 + <bitfield name="FLAG" pos="2" type="boolean"/> 68 68 + <bitfield name="PRT_EN" pos="3" type="boolean"/> 69 69 + <bitfield name="TILE_ALL" pos="4" type="boolean"/> 70 70 + <bitfield name="SRGB" pos="5" type="boolean"/> 71 71 + <bitfield name="FLAG_LO" low="6" high="31" shr="6"/> 72 72 + <!-- For multiplanar: --> 73 73 + <bitfield name="BASE_U_LO" low="6" high="31" shr="6"/> 74 74 + </reg32> 75 75 + <reg32 offset="5" name="5"> 76 76 + <bitfield name="FLAG_HI" low="0" high="16"/> 77 77 + <!-- For multiplanar: --> 78 78 + <bitfield name="BASE_U_HI" low="0" high="16"/> 79 79 + <bitfield name="FLAG_BUFFER_PITCH" low="17" high="24" shr="6" type="uint"/> 80 80 + <bitfield name="ALL_SAMPLES_CENTER" pos="29" type="boolean"/> 81 81 + <bitfield name="MUTABLEEN" pos="31" type="boolean"/> 82 82 + </reg32> 83 83 + <reg32 offset="6" name="6"> 84 84 + <bitfield name="TEX_LINE_OFFSET" low="0" high="23" type="uint"/> <!-- PITCH --> 85 85 + <bitfield name="MIN_LINE_OFFSET" low="24" high="27" type="uint"/> <!-- PITCHALIGN --> 86 86 + <bitfield name="MIPLVLS" low="28" high="31" type="uint"/> 87 87 + </reg32> 88 88 + <reg32 offset="7" name="7"> 89 89 + <bitfield name="ARRAY_SLICE_OFFSET" low="0" high="22" shr="12" type="uint"/> <!-- ARRAY_PITCH --> 90 90 + <bitfield name="ASO_UNIT" pos="23"/> <!-- 4KB or 32B ? --> 91 91 + <bitfield name="MIN_ARRAY_SLIZE_OFFSET" low="24" high="27" shr="12"/> <!-- MIN_LAYERSZ --> 92 92 + <bitfield name="GMEM_TILING_FALLBACK_EN" pos="28" type="boolean"/> 93 93 + <bitfield name="CORNER_BASED_EN" pos="30" type="boolean"/> 94 94 + <bitfield name="GMEM_FULL_SURF" pos="31" type="boolean"/> 95 95 + <!-- For multiplanar. This overlaps other single-planar fields: --> 96 96 + <bitfield name="UV_OFFSET_H" low="24" high="25" type="ufixed" radix="2"/> <!-- CHROMA_MIDPOINT_X --> 97 97 + <bitfield name="UV_OFFSET_V" low="26" high="27" type="ufixed" radix="2"/> <!-- CHROMA_MIDPOINT_Y --> 98 98 + </reg32> 99 99 + <reg32 offset="8" name="8"> 100 100 + <bitfield name="FLAG_ARRAY_PITCH" low="0" high="14" shr="12" type="uint"/> <!-- FLAG_BUFFER_ARRAY_PITCH --> 101 101 + <!-- log2 size of the first level, required for mipmapping --> 102 102 + <bitfield name="FLAG_BUFFER_LOGW" low="24" high="27" type="uint"/> 103 103 + <bitfield name="FLAG_BUFFER_LOGH" low="28" high="31" type="uint"/> 104 104 + <!-- For multiplanar. This overlaps other single-planar fields: --> 105 105 + <bitfield name="BASE_V_LO" low="6" high="31" shr="6"/> 106 106 + </reg32> 107 107 + <reg32 offset="9" name="9"> 108 108 + <bitfield name="MIN_LOD_CLAMP" low="19" high="30" type="ufixed" radix="8"/> 109 109 + <!-- For multiplanar, this overlaps other fields: --> 110 110 + <bitfield name="BASE_V_HI" low="0" high="16"/> 111 111 + <bitfield name="UV_PITCH" low="17" high="26"/> <!-- PLANE_PITCH --> 112 112 + </reg32> 113 113 + <reg32 offset="10" name="10"/> 114 114 + <reg32 offset="11" name="11"/> 115 115 + <reg32 offset="12" name="12"/> 116 116 + <reg32 offset="13" name="13"/> 117 117 + <reg32 offset="14" name="14"/> 118 118 + <reg32 offset="15" name="15"/> 119 119 + </domain> 120 120 + 121 121 + </database>

+299

drivers/gpu/drm/msm/registers/adreno/a8xx_enums.xml

reviewed

··· 1 1 + <?xml version="1.0" encoding="UTF-8"?> 2 2 + <database xmlns="http://nouveau.freedesktop.org/" 3 3 + xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" 4 4 + xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> 5 5 + <import file="freedreno_copyright.xml"/> 6 6 + <import file="adreno/adreno_common.xml"/> 7 7 + <import file="adreno/adreno_pm4.xml"/> 8 8 + 9 9 + <enum name="a8xx_statetype_id"> 10 10 + <value value="0" name="A8XX_TP0_NCTX_REG"/> 11 11 + <value value="1" name="A8XX_TP0_CTX0_3D_CVS_REG"/> 12 12 + <value value="2" name="A8XX_TP0_CTX0_3D_CPS_REG"/> 13 13 + <value value="3" name="A8XX_TP0_CTX1_3D_CVS_REG"/> 14 14 + <value value="4" name="A8XX_TP0_CTX1_3D_CPS_REG"/> 15 15 + <value value="5" name="A8XX_TP0_CTX2_3D_CPS_REG"/> 16 16 + <value value="6" name="A8XX_TP0_CTX3_3D_CPS_REG"/> 17 17 + <value value="9" name="A8XX_TP0_TMO_DATA"/> 18 18 + <value value="10" name="A8XX_TP0_SMO_DATA"/> 19 19 + <value value="11" name="A8XX_TP0_MIPMAP_BASE_DATA"/> 20 20 + <value value="12" name="A8XX_TP_3D_CVS_REG"/> 21 21 + <value value="13" name="A8XX_TP_3D_CPS_REG"/> 22 22 + <value value="16" name="A8XX_SP_3D_CVS_REG"/> 23 23 + <value value="17" name="A8XX_SP_3D_CPS_REG"/> 24 24 + <value value="22" name="A8XX_SP_LB_DATA_RAM"/> 25 25 + <value value="23" name="A8XX_SP_INST_DATA_RAM"/> 26 26 + <value value="24" name="A8XX_SP_STH"/> 27 27 + <value value="25" name="A8XX_SP_EVQ"/> 28 28 + <value value="26" name="A8XX_SP_CONSMNG"/> 29 29 + <value value="30" name="A8XX_HLSQ_INST_DATA_RAM"/> 30 30 + <value value="31" name="A8XX_SP_INST_DATA_3"/> 31 31 + <value value="32" name="A8XX_SP_NCTX_REG"/> 32 32 + <value value="33" name="A8XX_SP_CTX0_3D_CVS_REG"/> 33 33 + <value value="34" name="A8XX_SP_CTX0_3D_CPS_REG"/> 34 34 + <value value="35" name="A8XX_SP_CTX1_3D_CVS_REG"/> 35 35 + <value value="36" name="A8XX_SP_CTX1_3D_CPS_REG"/> 36 36 + <value value="37" name="A8XX_SP_CTX2_3D_CPS_REG"/> 37 37 + <value value="38" name="A8XX_SP_CTX3_3D_CPS_REG"/> 38 38 + <value value="39" name="A8XX_SP_INST_DATA"/> 39 39 + <value value="40" name="A8XX_SP_INST_DATA_1"/> 40 40 + <value value="41" name="A8XX_SP_LB_0_DATA"/> 41 41 + <value value="42" name="A8XX_SP_LB_1_DATA"/> 42 42 + <value value="43" name="A8XX_SP_LB_2_DATA"/> 43 43 + <value value="44" name="A8XX_SP_LB_3_DATA"/> 44 44 + <value value="45" name="A8XX_SP_LB_4_DATA"/> 45 45 + <value value="46" name="A8XX_SP_LB_5_DATA"/> 46 46 + <value value="47" name="A8XX_SP_LB_6_DATA"/> 47 47 + <value value="48" name="A8XX_SP_LB_7_DATA"/> 48 48 + <value value="49" name="A8XX_SP_CB_RAM"/> 49 49 + <value value="50" name="A8XX_SP_LB_13_DATA"/> 50 50 + <value value="51" name="A8XX_SP_LB_14_DATA"/> 51 51 + <value value="52" name="A8XX_SP_INST_TAG"/> 52 52 + <value value="53" name="A8XX_SP_INST_DATA_2"/> 53 53 + <value value="54" name="A8XX_SP_TMO_TAG"/> 54 54 + <value value="55" name="A8XX_SP_SMO_TAG"/> 55 55 + <value value="56" name="A8XX_SP_STATE_DATA"/> 56 56 + <value value="57" name="A8XX_SP_HWAVE_RAM"/> 57 57 + <value value="58" name="A8XX_SP_L0_INST_BUF"/> 58 58 + <value value="59" name="A8XX_SP_LB_8_DATA"/> 59 59 + <value value="60" name="A8XX_SP_LB_9_DATA"/> 60 60 + <value value="61" name="A8XX_SP_LB_10_DATA"/> 61 61 + <value value="62" name="A8XX_SP_LB_11_DATA"/> 62 62 + <value value="63" name="A8XX_SP_LB_12_DATA"/> 63 63 + <value value="64" name="A8XX_HLSQ_DATAPATH_DSTR_META"/> 64 64 + <value value="65" name="A8XX_HLSQ_DESC_REMAP_META"/> 65 65 + <value value="66" name="A8XX_HLSQ_SLICE_TOP_META"/> 66 66 + <value value="67" name="A8XX_HLSQ_L2STC_TAG_RAM"/> 67 67 + <value value="68" name="A8XX_HLSQ_L2STC_INFO_CMD"/> 68 68 + <value value="69" name="A8XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG"/> 69 69 + <value value="70" name="A8XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG"/> 70 70 + <value value="71" name="A8XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM"/> 71 71 + <value value="72" name="A8XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM"/> 72 72 + <value value="73" name="A8XX_HLSQ_CHUNK_CVS_RAM"/> 73 73 + <value value="74" name="A8XX_HLSQ_CHUNK_CPS_RAM"/> 74 74 + <value value="75" name="A8XX_HLSQ_CHUNK_CVS_RAM_TAG"/> 75 75 + <value value="76" name="A8XX_HLSQ_CHUNK_CPS_RAM_TAG"/> 76 76 + <value value="77" name="A8XX_HLSQ_ICB_CVS_CB_BASE_TAG"/> 77 77 + <value value="78" name="A8XX_HLSQ_ICB_CPS_CB_BASE_TAG"/> 78 78 + <value value="79" name="A8XX_HLSQ_CVS_MISC_RAM"/> 79 79 + <value value="80" name="A8XX_HLSQ_CPS_MISC_RAM"/> 80 80 + <value value="81" name="A8XX_HLSQ_CPS_MISC_RAM_1"/> 81 81 + <value value="82" name="A8XX_HLSQ_INST_RAM"/> 82 82 + <value value="83" name="A8XX_HLSQ_GFX_CVS_CONST_RAM"/> 83 83 + <value value="84" name="A8XX_HLSQ_GFX_CPS_CONST_RAM"/> 84 84 + <value value="85" name="A8XX_HLSQ_CVS_MISC_RAM_TAG"/> 85 85 + <value value="86" name="A8XX_HLSQ_CPS_MISC_RAM_TAG"/> 86 86 + <value value="87" name="A8XX_HLSQ_INST_RAM_TAG"/> 87 87 + <value value="88" name="A8XX_HLSQ_GFX_CVS_CONST_RAM_TAG"/> 88 88 + <value value="89" name="A8XX_HLSQ_GFX_CPS_CONST_RAM_TAG"/> 89 89 + <value value="90" name="A8XX_HLSQ_GFX_LOCAL_MISC_RAM"/> 90 90 + <value value="91" name="A8XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG"/> 91 91 + <value value="92" name="A8XX_HLSQ_INST_RAM_1"/> 92 92 + <value value="93" name="A8XX_HLSQ_STPROC_META"/> 93 93 + <value value="94" name="A8XX_HLSQ_SLICE_BACKEND_META"/> 94 94 + <value value="95" name="A8XX_HLSQ_INST_RAM_2"/> 95 95 + <value value="96" name="A8XX_HLSQ_DATAPATH_META"/> 96 96 + <value value="97" name="A8XX_HLSQ_FRONTEND_META"/> 97 97 + <value value="98" name="A8XX_HLSQ_INDIRECT_META"/> 98 98 + <value value="99" name="A8XX_HLSQ_BACKEND_META"/> 99 99 + </enum> 100 100 + 101 101 + <enum name="a8xx_state_location"> 102 102 + <value value="0" name="A8XX_HLSQ_STATE"/> 103 103 + <value value="1" name="A8XX_HLSQ_DP"/> 104 104 + <value value="2" name="A8XX_SP_TOP"/> 105 105 + <value value="3" name="A8XX_USPTP"/> 106 106 + <value value="4" name="A8XX_HLSQ_DP_STR"/> 107 107 + </enum> 108 108 + 109 109 + <enum name="a8xx_cluster"> 110 110 + <value value="0" name="A8XX_CLUSTER_NONE"/> 111 111 + <value value="1" name="A8XX_CLUSTER_FE_US"/> 112 112 + <value value="2" name="A8XX_CLUSTER_FE_S"/> 113 113 + <value value="3" name="A8XX_CLUSTER_SP_VS"/> 114 114 + <value value="4" name="A8XX_CLUSTER_VPC_VS"/> 115 115 + <value value="5" name="A8XX_CLUSTER_VPC_US"/> 116 116 + <value value="6" name="A8XX_CLUSTER_GRAS"/> 117 117 + <value value="7" name="A8XX_CLUSTER_SP_PS"/> 118 118 + <value value="8" name="A8XX_CLUSTER_VPC_PS"/> 119 119 + <value value="9" name="A8XX_CLUSTER_PS"/> 120 120 + </enum> 121 121 + 122 122 + <enum name="a8xx_debugbus_id"> 123 123 + <value value="1" name="A8XX_DEBUGBUS_GBIF_CX_GC_US_I_0"/> 124 124 + <value value="2" name="A8XX_DEBUGBUS_GMU_CX_GC_US_I_0"/> 125 125 + <value value="3" name="A8XX_DEBUGBUS_CX_GC_US_I_0"/> 126 126 + <value value="8" name="A8XX_DEBUGBUS_GBIF_GX_GC_US_I_0"/> 127 127 + <value value="9" name="A8XX_DEBUGBUS_GMU_GX_GC_US_I_0"/> 128 128 + <value value="10" name="A8XX_DEBUGBUS_DBGC_GC_US_I_0"/> 129 129 + <value value="11" name="A8XX_DEBUGBUS_RBBM_GC_US_I_0"/> 130 130 + <value value="12" name="A8XX_DEBUGBUS_LARC_GC_US_I_0"/> 131 131 + <value value="13" name="A8XX_DEBUGBUS_COM_GC_US_I_0"/> 132 132 + <value value="14" name="A8XX_DEBUGBUS_HLSQ_GC_US_I_0"/> 133 133 + <value value="15" name="A8XX_DEBUGBUS_CGC_GC_US_I_0"/> 134 134 + <value value="20" name="A8XX_DEBUGBUS_VSC_GC_US_I_0_0"/> 135 135 + <value value="21" name="A8XX_DEBUGBUS_VSC_GC_US_I_0_1"/> 136 136 + <value value="24" name="A8XX_DEBUGBUS_UFC_GC_US_I_0"/> 137 137 + <value value="25" name="A8XX_DEBUGBUS_UFC_GC_US_I_1"/> 138 138 + <value value="40" name="A8XX_DEBUGBUS_CP_GC_US_I_0_0"/> 139 139 + <value value="41" name="A8XX_DEBUGBUS_CP_GC_US_I_0_1"/> 140 140 + <value value="42" name="A8XX_DEBUGBUS_CP_GC_US_I_0_2"/> 141 141 + <value value="56" name="A8XX_DEBUGBUS_PC_BR_US_I_0"/> 142 142 + <value value="57" name="A8XX_DEBUGBUS_PC_BV_US_I_0"/> 143 143 + <value value="58" name="A8XX_DEBUGBUS_GPC_BR_US_I_0"/> 144 144 + <value value="59" name="A8XX_DEBUGBUS_GPC_BV_US_I_0"/> 145 145 + <value value="60" name="A8XX_DEBUGBUS_VPC_BR_US_I_0"/> 146 146 + <value value="61" name="A8XX_DEBUGBUS_VPC_BV_US_I_0"/> 147 147 + <value value="80" name="A8XX_DEBUGBUS_UCHE_WRAPPER_GC_US_I_0"/> 148 148 + <value value="81" name="A8XX_DEBUGBUS_UCHE_GC_US_I_0"/> 149 149 + <value value="82" name="A8XX_DEBUGBUS_UCHE_GC_US_I_1"/> 150 150 + <value value="83" name="A8XX_DEBUGBUS_UCHE_GC_US_I_0_1"/> 151 151 + <value value="84" name="A8XX_DEBUGBUS_UCHE_GC_US_I_1_1"/> 152 152 + <value value="128" name="A8XX_DEBUGBUS_CP_GC_S_0_I_0"/> 153 153 + <value value="129" name="A8XX_DEBUGBUS_PC_BR_S_0_I_0"/> 154 154 + <value value="130" name="A8XX_DEBUGBUS_PC_BV_S_0_I_0"/> 155 155 + <value value="131" name="A8XX_DEBUGBUS_TESS_GC_S_0_I_0"/> 156 156 + <value value="132" name="A8XX_DEBUGBUS_TSEFE_GC_S_0_I_0"/> 157 157 + <value value="133" name="A8XX_DEBUGBUS_TSEBE_GC_S_0_I_0"/> 158 158 + <value value="134" name="A8XX_DEBUGBUS_RAS_GC_S_0_I_0"/> 159 159 + <value value="135" name="A8XX_DEBUGBUS_LRZ_BR_S_0_I_0"/> 160 160 + <value value="136" name="A8XX_DEBUGBUS_LRZ_BV_S_0_I_0"/> 161 161 + <value value="137" name="A8XX_DEBUGBUS_VFDP_GC_S_0_I_0"/> 162 162 + <value value="138" name="A8XX_DEBUGBUS_GPC_BR_S_0_I_0"/> 163 163 + <value value="139" name="A8XX_DEBUGBUS_GPC_BV_S_0_I_0"/> 164 164 + <value value="140" name="A8XX_DEBUGBUS_VPCFE_BR_S_0_I_0"/> 165 165 + <value value="141" name="A8XX_DEBUGBUS_VPCFE_BV_S_0_I_0"/> 166 166 + <value value="142" name="A8XX_DEBUGBUS_VPCBE_BR_S_0_I_0"/> 167 167 + <value value="143" name="A8XX_DEBUGBUS_VPCBE_BV_S_0_I_0"/> 168 168 + <value value="144" name="A8XX_DEBUGBUS_CCHE_GC_S_0_I_0"/> 169 169 + <value value="145" name="A8XX_DEBUGBUS_DBGC_GC_S_0_I_0"/> 170 170 + <value value="146" name="A8XX_DEBUGBUS_LARC_GC_S_0_I_0"/> 171 171 + <value value="147" name="A8XX_DEBUGBUS_RBBM_GC_S_0_I_0"/> 172 172 + <value value="148" name="A8XX_DEBUGBUS_CCRE_GC_S_0_I_0"/> 173 173 + <value value="149" name="A8XX_DEBUGBUS_CGC_GC_S_0_I_0"/> 174 174 + <value value="150" name="A8XX_DEBUGBUS_GMU_GC_S_0_I_0"/> 175 175 + <value value="151" name="A8XX_DEBUGBUS_SLICE_GC_S_0_I_0"/> 176 176 + <value value="152" name="A8XX_DEBUGBUS_HLSQ_SPTP_STAR_GC_S_0_I_0"/> 177 177 + <value value="160" name="A8XX_DEBUGBUS_USP_GC_S_0_I_0"/> 178 178 + <value value="161" name="A8XX_DEBUGBUS_USP_GC_S_0_I_1"/> 179 179 + <value value="166" name="A8XX_DEBUGBUS_USPTP_GC_S_0_I_0"/> 180 180 + <value value="167" name="A8XX_DEBUGBUS_USPTP_GC_S_0_I_1"/> 181 181 + <value value="168" name="A8XX_DEBUGBUS_USPTP_GC_S_0_I_2"/> 182 182 + <value value="169" name="A8XX_DEBUGBUS_USPTP_GC_S_0_I_3"/> 183 183 + <value value="178" name="A8XX_DEBUGBUS_TP_GC_S_0_I_0"/> 184 184 + <value value="179" name="A8XX_DEBUGBUS_TP_GC_S_0_I_1"/> 185 185 + <value value="180" name="A8XX_DEBUGBUS_TP_GC_S_0_I_2"/> 186 186 + <value value="181" name="A8XX_DEBUGBUS_TP_GC_S_0_I_3"/> 187 187 + <value value="190" name="A8XX_DEBUGBUS_RB_GC_S_0_I_0"/> 188 188 + <value value="191" name="A8XX_DEBUGBUS_RB_GC_S_0_I_1"/> 189 189 + <value value="196" name="A8XX_DEBUGBUS_CCU_GC_S_0_I_0"/> 190 190 + <value value="197" name="A8XX_DEBUGBUS_CCU_GC_S_0_I_1"/> 191 191 + <value value="202" name="A8XX_DEBUGBUS_HLSQ_GC_S_0_I_0"/> 192 192 + <value value="203" name="A8XX_DEBUGBUS_HLSQ_GC_S_0_I_1"/> 193 193 + <value value="208" name="A8XX_DEBUGBUS_VFD_GC_S_0_I_0"/> 194 194 + <value value="209" name="A8XX_DEBUGBUS_VFD_GC_S_0_I_1"/> 195 195 + <value value="256" name="A8XX_DEBUGBUS_CP_GC_S_1_I_0"/> 196 196 + <value value="257" name="A8XX_DEBUGBUS_PC_BR_S_1_I_0"/> 197 197 + <value value="258" name="A8XX_DEBUGBUS_PC_BV_S_1_I_0"/> 198 198 + <value value="259" name="A8XX_DEBUGBUS_TESS_GC_S_1_I_0"/> 199 199 + <value value="260" name="A8XX_DEBUGBUS_TSEFE_GC_S_1_I_0"/> 200 200 + <value value="261" name="A8XX_DEBUGBUS_TSEBE_GC_S_1_I_0"/> 201 201 + <value value="262" name="A8XX_DEBUGBUS_RAS_GC_S_1_I_0"/> 202 202 + <value value="263" name="A8XX_DEBUGBUS_LRZ_BR_S_1_I_0"/> 203 203 + <value value="264" name="A8XX_DEBUGBUS_LRZ_BV_S_1_I_0"/> 204 204 + <value value="265" name="A8XX_DEBUGBUS_VFDP_GC_S_1_I_0"/> 205 205 + <value value="266" name="A8XX_DEBUGBUS_GPC_BR_S_1_I_0"/> 206 206 + <value value="267" name="A8XX_DEBUGBUS_GPC_BV_S_1_I_0"/> 207 207 + <value value="268" name="A8XX_DEBUGBUS_VPCFE_BR_S_1_I_0"/> 208 208 + <value value="269" name="A8XX_DEBUGBUS_VPCFE_BV_S_1_I_0"/> 209 209 + <value value="270" name="A8XX_DEBUGBUS_VPCBE_BR_S_1_I_0"/> 210 210 + <value value="271" name="A8XX_DEBUGBUS_VPCBE_BV_S_1_I_0"/> 211 211 + <value value="272" name="A8XX_DEBUGBUS_CCHE_GC_S_1_I_0"/> 212 212 + <value value="273" name="A8XX_DEBUGBUS_DBGC_GC_S_1_I_0"/> 213 213 + <value value="274" name="A8XX_DEBUGBUS_LARC_GC_S_1_I_0"/> 214 214 + <value value="275" name="A8XX_DEBUGBUS_RBBM_GC_S_1_I_0"/> 215 215 + <value value="276" name="A8XX_DEBUGBUS_CCRE_GC_S_1_I_0"/> 216 216 + <value value="277" name="A8XX_DEBUGBUS_CGC_GC_S_1_I_0"/> 217 217 + <value value="278" name="A8XX_DEBUGBUS_GMU_GC_S_1_I_0"/> 218 218 + <value value="279" name="A8XX_DEBUGBUS_SLICE_GC_S_1_I_0"/> 219 219 + <value value="280" name="A8XX_DEBUGBUS_HLSQ_SPTP_STAR_GC_S_1_I_0"/> 220 220 + <value value="288" name="A8XX_DEBUGBUS_USP_GC_S_1_I_0"/> 221 221 + <value value="289" name="A8XX_DEBUGBUS_USP_GC_S_1_I_1"/> 222 222 + <value value="294" name="A8XX_DEBUGBUS_USPTP_GC_S_1_I_0"/> 223 223 + <value value="295" name="A8XX_DEBUGBUS_USPTP_GC_S_1_I_1"/> 224 224 + <value value="296" name="A8XX_DEBUGBUS_USPTP_GC_S_1_I_2"/> 225 225 + <value value="297" name="A8XX_DEBUGBUS_USPTP_GC_S_1_I_3"/> 226 226 + <value value="306" name="A8XX_DEBUGBUS_TP_GC_S_1_I_0"/> 227 227 + <value value="307" name="A8XX_DEBUGBUS_TP_GC_S_1_I_1"/> 228 228 + <value value="308" name="A8XX_DEBUGBUS_TP_GC_S_1_I_2"/> 229 229 + <value value="309" name="A8XX_DEBUGBUS_TP_GC_S_1_I_3"/> 230 230 + <value value="318" name="A8XX_DEBUGBUS_RB_GC_S_1_I_0"/> 231 231 + <value value="319" name="A8XX_DEBUGBUS_RB_GC_S_1_I_1"/> 232 232 + <value value="324" name="A8XX_DEBUGBUS_CCU_GC_S_1_I_0"/> 233 233 + <value value="325" name="A8XX_DEBUGBUS_CCU_GC_S_1_I_1"/> 234 234 + <value value="330" name="A8XX_DEBUGBUS_HLSQ_GC_S_1_I_0"/> 235 235 + <value value="331" name="A8XX_DEBUGBUS_HLSQ_GC_S_1_I_1"/> 236 236 + <value value="336" name="A8XX_DEBUGBUS_VFD_GC_S_1_I_0"/> 237 237 + <value value="337" name="A8XX_DEBUGBUS_VFD_GC_S_1_I_1"/> 238 238 + <value value="384" name="A8XX_DEBUGBUS_CP_GC_S_2_I_0"/> 239 239 + <value value="385" name="A8XX_DEBUGBUS_PC_BR_S_2_I_0"/> 240 240 + <value value="386" name="A8XX_DEBUGBUS_PC_BV_S_2_I_0"/> 241 241 + <value value="387" name="A8XX_DEBUGBUS_TESS_GC_S_2_I_0"/> 242 242 + <value value="388" name="A8XX_DEBUGBUS_TSEFE_GC_S_2_I_0"/> 243 243 + <value value="389" name="A8XX_DEBUGBUS_TSEBE_GC_S_2_I_0"/> 244 244 + <value value="390" name="A8XX_DEBUGBUS_RAS_GC_S_2_I_0"/> 245 245 + <value value="391" name="A8XX_DEBUGBUS_LRZ_BR_S_2_I_0"/> 246 246 + <value value="392" name="A8XX_DEBUGBUS_LRZ_BV_S_2_I_0"/> 247 247 + <value value="393" name="A8XX_DEBUGBUS_VFDP_GC_S_2_I_0"/> 248 248 + <value value="394" name="A8XX_DEBUGBUS_GPC_BR_S_2_I_0"/> 249 249 + <value value="395" name="A8XX_DEBUGBUS_GPC_BV_S_2_I_0"/> 250 250 + <value value="396" name="A8XX_DEBUGBUS_VPCFE_BR_S_2_I_0"/> 251 251 + <value value="397" name="A8XX_DEBUGBUS_VPCFE_BV_S_2_I_0"/> 252 252 + <value value="398" name="A8XX_DEBUGBUS_VPCBE_BR_S_2_I_0"/> 253 253 + <value value="399" name="A8XX_DEBUGBUS_VPCBE_BV_S_2_I_0"/> 254 254 + <value value="400" name="A8XX_DEBUGBUS_CCHE_GC_S_2_I_0"/> 255 255 + <value value="401" name="A8XX_DEBUGBUS_DBGC_GC_S_2_I_0"/> 256 256 + <value value="402" name="A8XX_DEBUGBUS_LARC_GC_S_2_I_0"/> 257 257 + <value value="403" name="A8XX_DEBUGBUS_RBBM_GC_S_2_I_0"/> 258 258 + <value value="404" name="A8XX_DEBUGBUS_CCRE_GC_S_2_I_0"/> 259 259 + <value value="405" name="A8XX_DEBUGBUS_CGC_GC_S_2_I_0"/> 260 260 + <value value="406" name="A8XX_DEBUGBUS_GMU_GC_S_2_I_0"/> 261 261 + <value value="407" name="A8XX_DEBUGBUS_SLICE_GC_S_2_I_0"/> 262 262 + <value value="408" name="A8XX_DEBUGBUS_HLSQ_SPTP_STAR_GC_S_2_I_0"/> 263 263 + <value value="416" name="A8XX_DEBUGBUS_USP_GC_S_2_I_0"/> 264 264 + <value value="417" name="A8XX_DEBUGBUS_USP_GC_S_2_I_1"/> 265 265 + <value value="422" name="A8XX_DEBUGBUS_USPTP_GC_S_2_I_0"/> 266 266 + <value value="423" name="A8XX_DEBUGBUS_USPTP_GC_S_2_I_1"/> 267 267 + <value value="424" name="A8XX_DEBUGBUS_USPTP_GC_S_2_I_2"/> 268 268 + <value value="425" name="A8XX_DEBUGBUS_USPTP_GC_S_2_I_3"/> 269 269 + <value value="434" name="A8XX_DEBUGBUS_TP_GC_S_2_I_0"/> 270 270 + <value value="435" name="A8XX_DEBUGBUS_TP_GC_S_2_I_1"/> 271 271 + <value value="436" name="A8XX_DEBUGBUS_TP_GC_S_2_I_2"/> 272 272 + <value value="437" name="A8XX_DEBUGBUS_TP_GC_S_2_I_3"/> 273 273 + <value value="446" name="A8XX_DEBUGBUS_RB_GC_S_2_I_0"/> 274 274 + <value value="447" name="A8XX_DEBUGBUS_RB_GC_S_2_I_1"/> 275 275 + <value value="452" name="A8XX_DEBUGBUS_CCU_GC_S_2_I_0"/> 276 276 + <value value="453" name="A8XX_DEBUGBUS_CCU_GC_S_2_I_1"/> 277 277 + <value value="458" name="A8XX_DEBUGBUS_HLSQ_GC_S_2_I_0"/> 278 278 + <value value="459" name="A8XX_DEBUGBUS_HLSQ_GC_S_2_I_1"/> 279 279 + <value value="464" name="A8XX_DEBUGBUS_VFD_GC_S_2_I_0"/> 280 280 + <value value="465" name="A8XX_DEBUGBUS_VFD_GC_S_2_I_1"/> 281 281 + </enum> 282 282 + 283 283 + <enum name="a8xx_usptp_id"> 284 284 + <value value="0" name="A8XX_uSPTP0"/> 285 285 + <value value="1" name="A8XX_uSPTP1"/> 286 286 + <value value="15" name="A8XX_SPTOP"/> 287 287 + </enum> 288 288 + 289 289 + <enum name="a8xx_tex_swiz"> 290 290 + <value name="A8XX_SWIZ_IDENTITY" value="0"/> 291 291 + <value name="A8XX_SWIZ_ZERO" value="1"/> 292 292 + <value name="A8XX_SWIZ_ONE" value="2"/> 293 293 + <value name="A8XX_SWIZ_X" value="3"/> 294 294 + <value name="A8XX_SWIZ_Y" value="4"/> 295 295 + <value name="A8XX_SWIZ_Z" value="5"/> 296 296 + <value name="A8XX_SWIZ_W" value="6"/> 297 297 + </enum> 298 298 + 299 299 + </database>

+1

drivers/gpu/drm/msm/registers/adreno/adreno_common.xml

reviewed

··· 11 11 <value name="A5XX" value="5"/> 12 12 <value name="A6XX" value="6"/> 13 13 <value name="A7XX" value="7"/> 14 14 + <value name="A8XX" value="8"/> 14 15 </enum> 15 16 16 17 <enum name="adreno_pa_su_sc_draw">

+242 -109

drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml

reviewed

··· 6 6 <import file="adreno/adreno_common.xml"/> 7 7 8 8 <enum name="vgt_event_type" varset="chip"> 9 9 - <value name="VS_DEALLOC" value="0"/> 10 10 - <value name="PS_DEALLOC" value="1" variants="A2XX-A6XX"/> 11 11 - <value name="VS_DONE_TS" value="2"/> 12 12 - <value name="PS_DONE_TS" value="3"/> 9 9 + <value name="VS_DEALLOC" value="0x00" variants="A2XX-A5XX"/> 10 10 + <value name="PS_DEALLOC" value="0x01" variants="A2XX-A5XX"/> 11 11 + <value name="VS_DONE_TS" value="0x02" variants="A2XX-A5XX"/> 12 12 + <value name="PS_DONE_TS" value="0x03" variants="A2XX-A5XX"/> 13 13 <doc> 14 14 Flushes dirty data from UCHE, and also writes a GPU timestamp to 15 15 the address if one is provided. 16 16 </doc> 17 17 - <value name="CACHE_FLUSH_TS" value="4"/> 18 18 - <value name="CONTEXT_DONE" value="5"/> 19 19 - <value name="CACHE_FLUSH" value="6" variants="A2XX-A4XX"/> 20 20 - <value name="VIZQUERY_START" value="7" variants="A2XX"/> 21 21 - <value name="HLSQ_FLUSH" value="7" variants="A3XX-A4XX"/> 22 22 - <value name="VIZQUERY_END" value="8" variants="A2XX"/> 23 23 - <value name="SC_WAIT_WC" value="9" variants="A2XX"/> 24 24 - <value name="WRITE_PRIMITIVE_COUNTS" value="9" variants="A6XX-"/> 25 25 - <value name="START_PRIMITIVE_CTRS" value="11" variants="A6XX-"/> 26 26 - <value name="STOP_PRIMITIVE_CTRS" value="12" variants="A6XX-"/> 17 17 + <value name="CACHE_FLUSH_TS" value="0x04"/> 18 18 + <value name="CONTEXT_DONE" value="0x05"/> 19 19 + <value name="CACHE_FLUSH" value="0x06" variants="A2XX-A4XX"/> 20 20 + <value name="VIZQUERY_START" value="0x07" variants="A2XX"/> 21 21 + <value name="HLSQ_FLUSH" value="0x07" variants="A3XX-A4XX"/> 22 22 + <value name="VIZQUERY_END" value="0x08" variants="A2XX"/> 23 23 + <value name="SC_WAIT_WC" value="0x09" variants="A2XX"/> 24 24 + <value name="WRITE_PRIMITIVE_COUNTS" value="0x09" variants="A6XX-"/> 25 25 + <value name="START_PRIMITIVE_CTRS" value="0x0b" variants="A6XX-"/> 26 26 + <value name="STOP_PRIMITIVE_CTRS" value="0x0c" variants="A6XX-"/> 27 27 <!-- Not sure that these 4 events don't have the same meaning as on A5XX+ --> 28 28 - <value name="RST_PIX_CNT" value="13" variants="A2XX-A4XX"/> 29 29 - <value name="RST_VTX_CNT" value="14" variants="A2XX-A4XX"/> 30 30 - <value name="TILE_FLUSH" value="15" variants="A2XX-A4XX"/> 31 31 - <value name="STAT_EVENT" value="16" variants="A2XX-A4XX"/> 32 32 - <value name="CACHE_FLUSH_AND_INV_TS_EVENT" value="20" variants="A2XX-A4XX"/> 28 28 + <value name="RST_PIX_CNT" value="0x0d" variants="A2XX-A4XX"/> 29 29 + <value name="RST_VTX_CNT" value="0x0e" variants="A2XX-A4XX"/> 30 30 + <value name="TILE_FLUSH" value="0x0f" variants="A2XX-A4XX"/> 31 31 + <value name="STAT_EVENT" value="0x10" variants="A2XX-A4XX"/> 32 32 + <value name="CACHE_FLUSH_AND_INV_TS_EVENT" value="0x14" variants="A2XX-A4XX"/> 33 33 <doc> 34 34 If A6XX_RB_SAMPLE_COUNTER_CNTL.copy is true, writes OQ Z passed 35 35 sample counts to RB_SAMPLE_COUNTER_BASE. This writes to main 36 36 memory, skipping UCHE. 37 37 </doc> 38 38 - <value name="ZPASS_DONE" value="21"/> 39 39 - <value name="CACHE_FLUSH_AND_INV_EVENT" value="22" variants="A2XX"/> 38 38 + <value name="ZPASS_DONE" value="0x15"/> 39 39 + <value name="CACHE_FLUSH_AND_INV_EVENT" value="0x16" variants="A2XX"/> 40 40 41 41 <doc> 42 42 Writes the GPU timestamp to the address that follows, once RB 43 43 access and flushes are complete. 44 44 </doc> 45 45 - <value name="RB_DONE_TS" value="22" variants="A3XX-"/> 45 45 + <value name="RB_DONE_TS" value="0x16" variants="A3XX-"/> 46 46 47 47 - <value name="PERFCOUNTER_START" value="23" variants="A2XX-A4XX"/> 48 48 - <value name="PERFCOUNTER_STOP" value="24" variants="A2XX-A4XX"/> 49 49 - <value name="VS_FETCH_DONE" value="27"/> 50 50 - <value name="FACENESS_FLUSH" value="28" variants="A2XX-A4XX"/> 47 47 + <value name="PERFCOUNTER_START" value="0x17" variants="A2XX-A4XX"/> 48 48 + <value name="PERFCOUNTER_STOP" value="0x18" variants="A2XX-A4XX"/> 49 49 + <value name="VS_FETCH_DONE" value="0x1b" variants="A2XX-A5XX"/> 50 50 + <value name="FACENESS_FLUSH" value="0x1c" variants="A2XX-A4XX"/> 51 51 52 52 <!-- a5xx events --> 53 53 - <value name="WT_DONE_TS" value="8" variants="A5XX-"/> 54 54 - <value name="START_FRAGMENT_CTRS" value="13" variants="A5XX-"/> 55 55 - <value name="STOP_FRAGMENT_CTRS" value="14" variants="A5XX-"/> 56 56 - <value name="START_COMPUTE_CTRS" value="15" variants="A5XX-"/> 57 57 - <value name="STOP_COMPUTE_CTRS" value="16" variants="A5XX-"/> 58 58 - <value name="FLUSH_SO_0" value="17" variants="A5XX-"/> 59 59 - <value name="FLUSH_SO_1" value="18" variants="A5XX-"/> 60 60 - <value name="FLUSH_SO_2" value="19" variants="A5XX-"/> 61 61 - <value name="FLUSH_SO_3" value="20" variants="A5XX-"/> 53 53 + <value name="WT_DONE_TS" value="0x08" variants="A5XX-A6XX"/> 54 54 + <value name="START_FRAGMENT_CTRS" value="0x0d" variants="A5XX-"/> 55 55 + <value name="STOP_FRAGMENT_CTRS" value="0x0e" variants="A5XX-"/> 56 56 + <value name="START_COMPUTE_CTRS" value="0x0f" variants="A5XX-"/> 57 57 + <value name="STOP_COMPUTE_CTRS" value="0x10" variants="A5XX-"/> 58 58 + <value name="FLUSH_SO_0" value="0x11" variants="A5XX-"/> 59 59 + <value name="FLUSH_SO_1" value="0x12" variants="A5XX-"/> 60 60 + <value name="FLUSH_SO_2" value="0x13" variants="A5XX-"/> 61 61 + <value name="FLUSH_SO_3" value="0x14" variants="A5XX-"/> 62 62 63 63 <doc> 64 64 Invalidates depth attachment data from the CCU. We assume this 65 65 happens in the last stage. 66 66 </doc> 67 67 - <value name="PC_CCU_INVALIDATE_DEPTH" value="24" variants="A5XX-"/> 67 67 + <value name="PC_CCU_INVALIDATE_DEPTH" value="0x18" variants="A5XX-A6XX"/> 68 68 69 69 <doc> 70 70 Invalidates color attachment data from the CCU. We assume this 71 71 happens in the last stage. 72 72 </doc> 73 73 - <value name="PC_CCU_INVALIDATE_COLOR" value="25" variants="A5XX-"/> 73 73 + <value name="PC_CCU_INVALIDATE_COLOR" value="0x19" variants="A5XX-A6XX"/> 74 74 75 75 <doc> 76 76 Flushes the small cache used by CP_EVENT_WRITE::BLIT (which, 77 77 along with its registers, would be better named RESOLVE). 78 78 </doc> 79 79 - <value name="PC_CCU_RESOLVE_TS" value="26" variants="A6XX"/> 79 79 + <value name="PC_CCU_RESOLVE_TS" value="0x1a" variants="A6XX"/> 80 80 81 81 <doc> 82 82 Flushes depth attachment data from the CCU. We assume this 83 83 happens in the last stage. 84 84 </doc> 85 85 - <value name="PC_CCU_FLUSH_DEPTH_TS" value="28" variants="A5XX-"/> 85 85 + <value name="PC_CCU_FLUSH_DEPTH_TS" value="0x1c" variants="A5XX-A6XX"/> 86 86 87 87 <doc> 88 88 Flushes color attachment data from the CCU. We assume this 89 89 happens in the last stage. 90 90 </doc> 91 91 - <value name="PC_CCU_FLUSH_COLOR_TS" value="29" variants="A5XX-"/> 91 91 + <value name="PC_CCU_FLUSH_COLOR_TS" value="0x1d" variants="A5XX-A6XX"/> 92 92 93 93 <doc> 94 94 - 2D blit to resolve GMEM to system memory (skipping CCU) at the 95 95 - end of a render pass. Compare to CP_BLIT's BLIT_OP_SCALE for 96 96 - more general blitting. 94 94 + Triggers a resolve (GMEM to sysmem) or unresolve (sysmem to 95 95 + GMEM) or clear blit, depending on CCU programming. 97 96 </doc> 98 98 - <value name="BLIT" value="30" variants="A5XX-"/> 97 97 + <value name="CCU_RESOLVE" value="0x1e" variants="A5XX-"/> 99 98 100 99 <doc> 101 100 Flip between the primary and secondary LRZ buffers. This is used 102 101 for concurrent binning, so that BV can write to one buffer while 103 102 BR reads from the other. 104 103 </doc> 105 105 - <value name="LRZ_FLIP_BUFFER" value="36" variants="A7XX"/> 104 104 + <value name="LRZ_FLIP_BUFFER" value="0x24" variants="A7XX-"/> 106 105 107 106 <doc> 108 107 Clears based on GRAS_LRZ_CNTL configuration, could clear ··· 114 115 CUR_DIR_UNSET = 0x3 115 116 Clear of direction means setting the direction to CUR_DIR_UNSET. 116 117 </doc> 117 117 - <value name="LRZ_CLEAR" value="37" variants="A5XX-"/> 118 118 + <value name="LRZ_CLEAR" value="0x25" variants="A5XX-"/> 118 119 119 119 - <value name="LRZ_FLUSH" value="38" variants="A5XX-"/> 120 120 - <value name="BLIT_OP_FILL_2D" value="39" variants="A5XX-"/> 121 121 - <value name="BLIT_OP_COPY_2D" value="40" variants="A5XX-A6XX"/> 122 122 - <value name="LRZ_CACHE_INVALIDATE" value="40" variants="A7XX"/> 123 123 - <value name="LRZ_Q_CACHE_INVALIDATE" value="41" variants="A7XX"/> 124 124 - <value name="BLIT_OP_SCALE_2D" value="42" variants="A5XX-"/> 125 125 - <value name="CONTEXT_DONE_2D" value="43" variants="A5XX-"/> 126 126 - <value name="VSC_BINNING_START" value="44" variants="A5XX-"/> 127 127 - <value name="VSC_BINNING_END" value="45" variants="A5XX-"/> 120 120 + <value name="LRZ_FLUSH_INVALIDATE" value="0x26" variants="A5XX-A6XX"/> 121 121 + <value name="LRZ_CACHE_FLUSH" value="0x26" variants="A7XX-"/> 122 122 + <value name="BLIT_OP_FILL_2D" value="0x27" variants="A5XX-A6XX"/> 123 123 + <value name="BLIT_OP_COPY_2D" value="0x28" variants="A5XX-A6XX"/> 124 124 + <value name="LRZ_CACHE_INVALIDATE" value="0x28" variants="A7XX-"/> 125 125 + <value name="LRZ_Q_CACHE_INVALIDATE" value="0x29" variants="A7XX-"/> 126 126 + <value name="BLIT_OP_SCALE_2D" value="0x2a" variants="A5XX-"/> 127 127 + <value name="CONTEXT_DONE_2D" value="0x2b" variants="A5XX-"/> 128 128 + <value name="VSC_BINNING_START" value="0x2c" variants="A5XX-"/> 129 129 + <value name="VSC_BINNING_END" value="0x2d" variants="A5XX-"/> 128 130 129 131 <!-- a6xx events --> 130 132 <doc> 131 133 Invalidates UCHE. 132 134 </doc> 133 133 - <value name="CACHE_INVALIDATE" value="49" variants="A6XX"/> 135 135 + <value name="CACHE_INVALIDATE" value="0x31" variants="A6XX"/> 134 136 135 135 - <value name="LABEL" value="63" variants="A6XX-"/> 137 137 + <value name="DEBUG_LABEL" value="0x3f" variants="A6XX-"/> 136 138 137 139 <!-- note, some of these are the same as a6xx, just named differently --> 138 140 139 141 <doc> Doesn't seem to do anything </doc> 140 140 - <value name="DUMMY_EVENT" value="1" variants="A7XX"/> 141 141 - <value name="CCU_INVALIDATE_DEPTH" value="24" variants="A7XX"/> 142 142 - <value name="CCU_INVALIDATE_COLOR" value="25" variants="A7XX"/> 143 143 - <value name="CCU_RESOLVE_CLEAN" value="26" variants="A7XX"/> 144 144 - <value name="CCU_FLUSH_DEPTH" value="28" variants="A7XX"/> 145 145 - <value name="CCU_FLUSH_COLOR" value="29" variants="A7XX"/> 146 146 - <value name="CCU_RESOLVE" value="30" variants="A7XX"/> 147 147 - <value name="CCU_END_RESOLVE_GROUP" value="31" variants="A7XX"/> 148 148 - <value name="CCU_CLEAN_DEPTH" value="32" variants="A7XX"/> 149 149 - <value name="CCU_CLEAN_COLOR" value="33" variants="A7XX"/> 150 150 - <value name="CACHE_RESET" value="48" variants="A7XX"/> 151 151 - <value name="CACHE_CLEAN" value="49" variants="A7XX"/> 142 142 + <value name="DUMMY_EVENT" value="0x01" variants="A7XX-"/> 143 143 + <value name="CCU_INVALIDATE_DEPTH" value="0x18" variants="A7XX-"/> 144 144 + <value name="CCU_INVALIDATE_COLOR" value="0x19" variants="A7XX-"/> 145 145 + <value name="CCU_RESOLVE_CLEAN" value="0x1a" variants="A7XX-"/> 146 146 + <value name="CCU_FLUSH_DEPTH" value="0x1c" variants="A7XX-"/> 147 147 + <value name="CCU_FLUSH_COLOR" value="0x1d" variants="A7XX-"/> 148 148 + <value name="CCU_END_RESOLVE_GROUP" value="0x1f" variants="A7XX-"/> 149 149 + <value name="CCU_CLEAN_DEPTH" value="0x20" variants="A7XX-"/> 150 150 + <value name="CCU_CLEAN_COLOR" value="0x21" variants="A7XX-"/> 151 151 + <value name="CACHE_RESET" value="0x30" variants="A7XX-"/> 152 152 + <value name="CACHE_CLEAN" value="0x31" variants="A7XX-"/> 152 153 <!-- TODO: deal with name conflicts with other gens --> 153 153 - <value name="CACHE_FLUSH7" value="50" variants="A7XX"/> 154 154 - <value name="CACHE_INVALIDATE7" value="51" variants="A7XX"/> 154 154 + <value name="CACHE_FLUSH7" value="0x32" variants="A7XX-"/> 155 155 + <value name="CACHE_INVALIDATE7" value="0x33" variants="A7XX-"/> 156 156 + <value name="DEPTH_BUFFER_FLIP" value="0x3d" variants="A8XX-"/> 157 157 + <value name="CCH_FAST_CLEAR_CLEAN" value="0x1b" variants="A8XX-"/> 155 158 </enum> 156 159 157 160 <enum name="pc_di_primtype"> ··· 311 310 <value name="CP_EVENT_WRITE" value="0x46" variants="A2XX-A6XX"/> 312 311 <value name="CP_EVENT_WRITE7" value="0x46" variants="A7XX-"/> 313 312 <doc>generate a VS|PS_done event</doc> 314 314 - <value name="CP_EVENT_WRITE_SHD" value="0x58"/> 313 313 + <value name="CP_EVENT_WRITE_SHD" value="0x58" variants="A2XX"/> 315 314 <doc>generate a cache flush done event</doc> 316 316 - <value name="CP_EVENT_WRITE_CFL" value="0x59"/> 315 315 + <value name="CP_EVENT_WRITE_CFL" value="0x59" variants="A2XX"/> 317 316 <doc>generate a z_pass done event</doc> 318 318 - <value name="CP_EVENT_WRITE_ZPD" value="0x5b"/> 317 317 + <value name="CP_EVENT_WRITE_ZPD" value="0x5b" variants="A2XX"/> 319 318 <doc> 320 319 not sure the real name, but this seems to be what is used for 321 320 opencl, instead of CP_DRAW_INDX.. ··· 336 335 <doc>load constant into chip and to memory</doc> 337 336 <value name="CP_SET_CONSTANT" value="0x2d" variants="A2XX"/> 338 337 <doc>load sequencer instruction memory (pointer-based)</doc> 339 339 - <value name="CP_IM_LOAD" value="0x27"/> 338 338 + <value name="CP_IM_LOAD" value="0x27" variants="A2XX"/> 340 339 <doc>load sequencer instruction memory (code embedded in packet)</doc> 341 341 - <value name="CP_IM_LOAD_IMMEDIATE" value="0x2b"/> 340 340 + <value name="CP_IM_LOAD_IMMEDIATE" value="0x2b" variants="A2XX"/> 342 341 <doc>load constants from a location in memory</doc> 343 342 <value name="CP_LOAD_CONSTANT_CONTEXT" value="0x2e" variants="A2XX"/> 344 343 <doc>selective invalidation of state pointers</doc> ··· 663 662 <value name="CP_CCHE_INVALIDATE" value="0x3a" variants="A7XX-"/> 664 663 665 664 <value name="CP_SCOPE_CNTL" value="0x6c" variants="A7XX-"/> 665 665 + 666 666 + <value name="CP_SKIP_IB_MODE" value="0x27" variants="A7XX-"/> 667 667 + 668 668 + <value name="CP_MEMORY_MAP_UPDATE" value="0x58" variants="A8XX-"/> 669 669 + 670 670 + <value name="CP_BARRIER" value="0x59" variants="A8XX-"/> 666 671 </enum> 667 672 668 673 ··· 1807 1800 <value value="6" name="RM6_BIN_RESOLVE"/> 1808 1801 <value value="7" name="RM6_BIN_RENDER_END"/> 1809 1802 <value value="8" name="RM6_COMPUTE"/> 1810 1810 - <value value="0xc" name="RM6_BLIT2DSCALE"/> <!-- no-op (at least on current sqe fw) --> 1803 1803 + <value value="12" name="RM6_BLIT2DSCALE"/> <!-- no-op (at least on current sqe fw) --> 1811 1804 1812 1805 <!-- 1813 1806 These values come from a6xx_set_marker() in the 1814 1807 downstream kernel, and they can only be set by the kernel 1815 1808 --> 1816 1816 - <value value="0xd" name="RM6_IB1LIST_START"/> 1817 1817 - <value value="0xe" name="RM6_IB1LIST_END"/> 1809 1809 + <value value="13" name="RM6_IB1LIST_START"/> 1810 1810 + <value value="14" name="RM6_IB1LIST_END"/> 1811 1811 + <value value="15" name="RM7_BIN_VISIBILITY_END"/> 1812 1812 + 1813 1813 + <!-- new in a8xx: --> 1814 1814 + <value value="32" name="RM8_DEPTH_PASS_START"/> 1815 1815 + <value value="33" name="RM8_DEPTH_PASS_END"/> 1816 1816 + <value value="34" name="RM8_SET_RENDER_TARGET"/> 1817 1817 + <value value="35" name="RM8_PGMEM_ON"/> 1818 1818 + <value value="36" name="RM8_PGMEM_OFF"/> 1818 1819 </enum> 1819 1819 - <reg32 offset="0" name="0"> 1820 1820 - <!-- if b8 is set, the low bits are interpreted differently (and b4 ignored) --> 1821 1821 - <bitfield name="MARKER_MODE" pos="8" type="set_marker_mode" addvariant="yes"/> 1820 1820 + <stripe varset="chip" variants="A6XX-A7XX"> 1821 1821 + <reg32 offset="0" name="0"> 1822 1822 + <!-- if b8 is set, the low bits are interpreted differently (and b4 ignored) --> 1823 1823 + <bitfield name="MARKER_MODE" pos="8" type="set_marker_mode" addvariant="yes"/> 1822 1824 1823 1823 - <bitfield name="MODE" low="0" high="3" type="a6xx_marker" varset="set_marker_mode" variants="SET_RENDER_MODE"/> 1824 1824 - <!-- used by preemption to determine if GMEM needs to be saved or not --> 1825 1825 - <bitfield name="USES_GMEM" pos="4" type="boolean" varset="set_marker_mode" variants="SET_RENDER_MODE"/> 1826 1825 1827 1827 - <bitfield name="IFPC_MODE" pos="0" type="a6xx_ifpc_mode" varset="set_marker_mode" variants="SET_IFPC_MODE"/> 1826 1826 + <bitfield name="MODE" low="0" high="3" type="a6xx_marker" varset="set_marker_mode" variants="SET_RENDER_MODE"/> 1827 1827 + <!-- used by preemption to determine if GMEM needs to be saved or not --> 1828 1828 + <bitfield name="USES_GMEM" pos="4" type="boolean" varset="set_marker_mode" variants="SET_RENDER_MODE"/> 1828 1829 1829 1829 - <!-- 1830 1830 - CP_SET_MARKER is used with these bits to create a 1831 1831 - critical section around a workaround for ray tracing. 1832 1832 - The workaround happens after BVH building, and appears 1833 1833 - to invalidate the RTU's BVH node cache. It makes sure 1834 1834 - that only one of BR/BV/LPAC is executing the 1835 1835 - workaround at a time, and no draws using RT on BV/LPAC 1836 1836 - are executing while the workaround is executed on BR (or 1837 1837 - vice versa, that no draws on BV/BR using RT are executed 1838 1838 - while the workaround executes on LPAC), by 1839 1839 - hooking subsequent CP_EVENT_WRITE/CP_DRAW_*/CP_EXEC_CS. 1840 1840 - The blob usage is: 1841 1830 1842 1842 - CP_SET_MARKER(RT_WA_START) 1843 1843 - ... workaround here ... 1844 1844 - CP_SET_MARKER(RT_WA_END) 1845 1845 - ... 1846 1846 - CP_SET_MARKER(SHADER_USES_RT) 1847 1847 - CP_DRAW_INDX(...) or CP_EXEC_CS(...) 1848 1848 - --> 1849 1849 - <bitfield name="SHADER_USES_RT" pos="9" type="boolean" variants="A7XX-"/> 1850 1850 - <bitfield name="RT_WA_START" pos="10" type="boolean" variants="A7XX-"/> 1851 1851 - <bitfield name="RT_WA_END" pos="11" type="boolean" variants="A7XX-"/> 1852 1852 - </reg32> 1831 1831 + <bitfield name="IFPC_MODE" pos="0" type="a6xx_ifpc_mode" varset="set_marker_mode" variants="SET_IFPC_MODE"/> 1832 1832 + 1833 1833 + 1834 1834 + <!-- 1835 1835 + CP_SET_MARKER is used with these bits to create a 1836 1836 + critical section around a workaround for ray tracing. 1837 1837 + The workaround happens after BVH building, and appears 1838 1838 + to invalidate the RTU's BVH node cache. It makes sure 1839 1839 + that only one of BR/BV/LPAC is executing the 1840 1840 + workaround at a time, and no draws using RT on BV/LPAC 1841 1841 + are executing while the workaround is executed on BR (or 1842 1842 + vice versa, that no draws on BV/BR using RT are executed 1843 1843 + while the workaround executes on LPAC), by 1844 1844 + hooking subsequent CP_EVENT_WRITE/CP_DRAW_*/CP_EXEC_CS. 1845 1845 + The blob usage is: 1846 1846 + 1847 1847 + 1848 1848 + CP_SET_MARKER(RT_WA_START) 1849 1849 + ... workaround here ... 1850 1850 + CP_SET_MARKER(RT_WA_END) 1851 1851 + ... 1852 1852 + CP_SET_MARKER(SHADER_USES_RT) 1853 1853 + CP_DRAW_INDX(...) or CP_EXEC_CS(...) 1854 1854 + --> 1855 1855 + <bitfield name="SHADER_USES_RT" pos="9" type="boolean" variants="A7XX-"/> 1856 1856 + <bitfield name="RT_WA_START" pos="10" type="boolean" variants="A7XX-"/> 1857 1857 + <bitfield name="RT_WA_END" pos="11" type="boolean" variants="A7XX-"/> 1858 1858 + </reg32> 1859 1859 + </stripe> 1860 1860 + <stripe varset="chip" variants="A8XX-"> 1861 1861 + <reg32 offset="0" name="0"> 1862 1862 + <!-- if b8 is set, the low bits are interpreted differently (and b4 ignored) --> 1863 1863 + <bitfield name="MARKER_MODE" pos="8" type="set_marker_mode" addvariant="yes"/> 1864 1864 + <bitfield name="MODE" low="0" high="6" type="a6xx_marker" varset="set_marker_mode" variants="SET_RENDER_MODE"/> 1865 1865 + <bitfield name="USES_GMEM" pos="7" type="boolean" varset="set_marker_mode" variants="SET_RENDER_MODE"/> 1866 1866 + <bitfield name="IFPC_MODE" pos="0" type="a6xx_ifpc_mode" varset="set_marker_mode" variants="SET_IFPC_MODE"/> 1867 1867 + <!-- idk if the RT w/a fields apply to a8xx as well --> 1868 1868 + </reg32> 1869 1869 + </stripe> 1853 1870 </domain> 1854 1871 1855 1872 <domain name="CP_SET_PSEUDO_REG" width="32" varset="chip" prefix="chip" variants="A6XX-"> ··· 2097 2066 payload *and* skipsaverestore is set. This is 2098 2067 expected to restore static register values not 2099 2068 saved when skipsaverestore is set. 2069 2069 + 2070 2070 + On BV, a skipsaverestore preemption is triggered 2071 2071 + and this preamble type is executed whenever a 2072 2072 + CP_THREAD_CONTROL that synchronizes threads 2073 2073 + happens. This can be explicitly via 2074 2074 + SYNC_THREADS, or implicitly when the value of 2075 2075 + CONCURRENT_BIN_DISABLE changes from the previous 2076 2076 + thread control. 2100 2077 </doc> 2101 2078 </value> 2102 2079 <value name="POSTAMBLE_AMBLE_TYPE" value="2"> ··· 2345 2306 <reg32 offset="2" name="2"> 2346 2307 <bitfield name="IB_SIZE" low="0" high="19"/> 2347 2308 </reg32> 2309 2309 + </domain> 2310 2310 + 2311 2311 + <domain name="CP_RESOURCE_LIST" width="32"> 2312 2312 + <doc> 2313 2313 + A7xx introduces the "resource table" which is managed by 2314 2314 + CP_RESOURCE_LIST. It is used to synchronize BR and BV access 2315 2315 + to resources such as LRZ buffers. 2316 2316 + 2317 2317 + The resource table consists of resources that are in-use by BR. 2318 2318 + Each "resource" has a base address, which is 2319 2319 + usually a pointer but is treated by the HW as an opaque handle, 2320 2320 + a read/write bit, and a timestamp when it was last used. 2321 2321 + Resources are removed from the table upon event completion when 2322 2322 + a special CP_EVENT_WRITE::CLEAR_RENDER_RESOURCE bit is set, which 2323 2323 + will remove all resources with a timestamp up to the current 2324 2324 + timestamp. 2325 2325 + 2326 2326 + CP_RESOURCE_LIST first specifies a list of BV resources. For 2327 2327 + each BV resource, the HW will check if there is a corresponding 2328 2328 + BR resource in the table, and if at least one of the BV and BR 2329 2329 + resources is marked WRITE then it will stall until the BR 2330 2330 + resource is removed. 2331 2331 + 2332 2332 + It then specifies a list of BR resources. These will be added to 2333 2333 + the resource table, unless there is an overflow in which case 2334 2334 + the designated overflow register will have bit 0 set. Overflow 2335 2335 + should cause the next binning pass to stall until BR is done, 2336 2336 + effectively disabling concurrent binning. 2337 2337 + 2338 2338 + CP_RESOURCE_LIST must be executed by BV. BR resources are added 2339 2339 + by BV and removed by BR. 2340 2340 + 2341 2341 + There is a separate table for "LRZ resources." These behave a 2342 2342 + bit differently: specifying an LRZ resource via BV_RES_LRZ 2343 2343 + stalls on any matching resource existing and then adds it to the 2344 2344 + table, making it both a BV and BR resource in one. There is a 2345 2345 + separate CLEAR_LRZ_RESOURCE bit for removing resources from the 2346 2346 + LRZ table, and it only removes one resource given by a base 2347 2347 + address passed to CP_EVENT_WRITE. Therefore timestamps are 2348 2348 + unnecessary. 2349 2349 + </doc> 2350 2350 + <reg32 offset="0" name="BV_COUNT" type="uint"/> 2351 2351 + <doc> 2352 2352 + What follows is a list of CP_BV_RESOURCE and then CP_RESOURCE_LIST_BR. 2353 2353 + </doc> 2354 2354 + </domain> 2355 2355 + 2356 2356 + <domain name="CP_BV_RESOURCE" width="32"> 2357 2357 + <doc> 2358 2358 + BV resources don't go in the table. Instead CP waits until any 2359 2359 + corresponding BR resources with the same base pointer are 2360 2360 + finished before the packet completes. 2361 2361 + </doc> 2362 2362 + <enum name="cp_bv_resource_encoding"> 2363 2363 + <value value="0" name="BV_RES_DIRECT"/> 2364 2364 + <doc> 2365 2365 + INDIRECT resources are encoded as a 32b offset + 3b 2366 2366 + bindless base selector. The offset is added to the given 2367 2367 + BINDLESS_BASE pseudoregister and then the 64b value 2368 2368 + fetched there is used as the pointer. 2369 2369 + </doc> 2370 2370 + <value value="1" name="BV_RES_INDIRECT_READ"/> 2371 2371 + <value value="2" name="BV_RES_LRZ"/> 2372 2372 + <value value="3" name="BV_RES_INDIRECT_WRITE"/> 2373 2373 + </enum> 2374 2374 + <reg64 offset="0" name="0"> 2375 2375 + <bitfield name="BASE_ADDR" low="1" high="61" shr="1" type="address"/> 2376 2376 + <bitfield name="WRITE" pos="0" type="boolean"/> 2377 2377 + <bitfield name="ENCODING" low="62" high="63" type="cp_bv_resource_encoding"/> 2378 2378 + </reg64> 2379 2379 + </domain> 2380 2380 + 2381 2381 + <domain name="CP_RESOURCE_LIST_BR" width="32"> 2382 2382 + <reg32 offset="0" name="0"> 2383 2383 + <bitfield name="BR_COUNT" low="0" high="23" type="uint"/> 2384 2384 + <bitfield name="OVERFLOW_ONCHIP_ADDR" low="24" high="26"/> 2385 2385 + <bitfield name="OVERFLOW" pos="31" type="boolean"/> 2386 2386 + </reg32> 2387 2387 + <doc> 2388 2388 + What follows is a list of CP_BR_RESOURCE. 2389 2389 + </doc> 2390 2390 + </domain> 2391 2391 + 2392 2392 + <domain name="CP_BR_RESOURCE" width="32"> 2393 2393 + <enum name="cp_br_resource_encoding"> 2394 2394 + <value value="0" name="BR_RES_DIRECT"/> 2395 2395 + <value value="2" name="BR_RES_INDIRECT_READ"/> 2396 2396 + <value value="3" name="BR_RES_INDIRECT_WRITE"/> <!-- set WRITE bit --> 2397 2397 + </enum> 2398 2398 + <reg64 offset="0" name="0"> 2399 2399 + <bitfield name="BASE_ADDR" low="1" high="61" shr="1" type="address"/> 2400 2400 + <bitfield name="WRITE" pos="0" type="boolean"/> 2401 2401 + <bitfield name="ENCODING" low="62" high="63" type="cp_br_resource_encoding"/> 2402 2402 + </reg64> 2348 2403 </domain> 2349 2404 2350 2405 </database>