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usb: dwc3: xilinx: set coherency mode for AMD versal adaptive platform

If device is coherent or if DMA (direct memory access) is translated by
an IOMMU then program USB2.0 IP to route transactions through the CCI for
coherency even if the target of transaction is in low power domain (LPD).

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Link: https://lore.kernel.org/r/1748976818-710088-1-git-send-email-radhey.shyam.pandey@amd.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Radhey Shyam Pandey and committed by
Greg Kroah-Hartman 1f25307c 70627bf8

+22 -12
+22 -12
drivers/usb/dwc3/dwc3-xilinx.c
··· 32 32 #define XLNX_USB_TRAFFIC_ROUTE_CONFIG 0x005C 33 33 #define XLNX_USB_TRAFFIC_ROUTE_FPD 0x1 34 34 35 + /* USB 2.0 IP Register */ 36 + #define XLNX_USB2_TRAFFIC_ROUTE_CONFIG 0x0044 37 + 35 38 #define XLNX_USB_FPD_PIPE_CLK 0x7c 36 39 #define PIPE_CLK_DESELECT 1 37 40 #define PIPE_CLK_SELECT 0 ··· 69 66 writel(reg, priv_data->regs + XLNX_USB_PHY_RST_EN); 70 67 } 71 68 69 + static void dwc3_xlnx_set_coherency(struct dwc3_xlnx *priv_data, u32 coherency_offset) 70 + { 71 + struct device *dev = priv_data->dev; 72 + u32 reg; 73 + 74 + /* 75 + * This routes the USB DMA traffic to go through FPD path instead 76 + * of reaching DDR directly. This traffic routing is needed to 77 + * make SMMU and CCI work with USB DMA. 78 + */ 79 + if (of_dma_is_coherent(dev->of_node) || device_iommu_mapped(dev)) { 80 + reg = readl(priv_data->regs + coherency_offset); 81 + reg |= XLNX_USB_TRAFFIC_ROUTE_FPD; 82 + writel(reg, priv_data->regs + coherency_offset); 83 + } 84 + } 85 + 72 86 static int dwc3_xlnx_init_versal(struct dwc3_xlnx *priv_data) 73 87 { 74 88 struct device *dev = priv_data->dev; ··· 112 92 } 113 93 114 94 dwc3_xlnx_mask_phy_rst(priv_data, true); 95 + dwc3_xlnx_set_coherency(priv_data, XLNX_USB2_TRAFFIC_ROUTE_CONFIG); 115 96 116 97 return 0; 117 98 } ··· 123 102 struct reset_control *crst, *hibrst, *apbrst; 124 103 struct gpio_desc *reset_gpio; 125 104 int ret = 0; 126 - u32 reg; 127 105 128 106 priv_data->usb3_phy = devm_phy_optional_get(dev, "usb3-phy"); 129 107 if (IS_ERR(priv_data->usb3_phy)) { ··· 239 219 usleep_range(5000, 10000); 240 220 } 241 221 242 - /* 243 - * This routes the USB DMA traffic to go through FPD path instead 244 - * of reaching DDR directly. This traffic routing is needed to 245 - * make SMMU and CCI work with USB DMA. 246 - */ 247 - if (of_dma_is_coherent(dev->of_node) || device_iommu_mapped(dev)) { 248 - reg = readl(priv_data->regs + XLNX_USB_TRAFFIC_ROUTE_CONFIG); 249 - reg |= XLNX_USB_TRAFFIC_ROUTE_FPD; 250 - writel(reg, priv_data->regs + XLNX_USB_TRAFFIC_ROUTE_CONFIG); 251 - } 252 - 222 + dwc3_xlnx_set_coherency(priv_data, XLNX_USB_TRAFFIC_ROUTE_CONFIG); 253 223 err: 254 224 return ret; 255 225 }