tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

drm/i915/dp: Return a fixed point BPP value from intel_dp_output_bpp()

Convert intel_dp_output_bpp() and intel_dp_mode_min_output_bpp() to
return an x16 fixed point bpp value, as this value will be always the
link BPP (either compressed or uncompressed) tracked in the same x16
fixed point format.

While at it rename
intel_dp_output_bpp() to intel_dp_output_format_link_bpp_x16() and
intel_dp_mode_min_output_bpp() to intel_dp_mode_min_link_bpp_x16() to
better reflect that these functions return an x16 link BPP value
specific to a particular output format or mode.

Also rename intel_dp_output_bpp()'s bpp parameter to pipe_bpp, to
clarify which kind of (pipe vs. link) BPP the parameter is.

Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patch.msgid.link/20251215192357.172201-5-imre.deak@intel.com

Imre Deak 1f28404a 0b149905

+26 -22
+22 -19
drivers/gpu/drm/i915/display/intel_dp.c
··· 1235 1235 return 8 * 3; 1236 1236 } 1237 1237 1238 - int intel_dp_output_bpp(enum intel_output_format output_format, int bpp) 1238 + int intel_dp_output_format_link_bpp_x16(enum intel_output_format output_format, int pipe_bpp) 1239 1239 { 1240 1240 /* 1241 1241 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output ··· 1243 1243 * of bytes of RGB pixel. 1244 1244 */ 1245 1245 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1246 - bpp /= 2; 1246 + pipe_bpp /= 2; 1247 1247 1248 - return bpp; 1248 + return fxp_q4_from_int(pipe_bpp); 1249 1249 } 1250 1250 1251 1251 static enum intel_output_format ··· 1261 1261 } 1262 1262 1263 1263 static int 1264 - intel_dp_mode_min_output_bpp(struct intel_connector *connector, 1265 - const struct drm_display_mode *mode) 1264 + intel_dp_mode_min_link_bpp_x16(struct intel_connector *connector, 1265 + const struct drm_display_mode *mode) 1266 1266 { 1267 1267 enum intel_output_format output_format, sink_format; 1268 1268 ··· 1270 1270 1271 1271 output_format = intel_dp_output_format(connector, sink_format); 1272 1272 1273 - return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format)); 1273 + return intel_dp_output_format_link_bpp_x16(output_format, 1274 + intel_dp_min_bpp(output_format)); 1274 1275 } 1275 1276 1276 1277 static bool intel_dp_hdisplay_bad(struct intel_display *display, ··· 1343 1342 1344 1343 /* If PCON supports FRL MODE, check FRL bandwidth constraints */ 1345 1344 if (intel_dp->dfp.pcon_max_frl_bw) { 1345 + int link_bpp_x16 = intel_dp_mode_min_link_bpp_x16(connector, mode); 1346 1346 int target_bw; 1347 1347 int max_frl_bw; 1348 - int bpp = intel_dp_mode_min_output_bpp(connector, mode); 1349 1348 1350 - target_bw = bpp * target_clock; 1349 + target_bw = fxp_q4_to_int_roundup(link_bpp_x16) * target_clock; 1351 1350 1352 1351 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw; 1353 1352 ··· 1462 1461 enum drm_mode_status status; 1463 1462 bool dsc = false; 1464 1463 int num_joined_pipes; 1464 + int link_bpp_x16; 1465 1465 1466 1466 status = intel_cpu_transcoder_mode_valid(display, mode); 1467 1467 if (status != MODE_OK) ··· 1505 1503 1506 1504 max_rate = intel_dp_max_link_data_rate(intel_dp, max_link_clock, max_lanes); 1507 1505 1508 - mode_rate = intel_dp_link_required(target_clock, 1509 - intel_dp_mode_min_output_bpp(connector, mode)); 1506 + link_bpp_x16 = intel_dp_mode_min_link_bpp_x16(connector, mode); 1507 + mode_rate = intel_dp_link_required(target_clock, fxp_q4_to_int_roundup(link_bpp_x16)); 1510 1508 1511 1509 if (intel_dp_has_dsc(connector)) { 1512 1510 int pipe_bpp; ··· 1818 1816 for (bpp = fxp_q4_to_int(limits->link.max_bpp_x16); 1819 1817 bpp >= fxp_q4_to_int(limits->link.min_bpp_x16); 1820 1818 bpp -= 2 * 3) { 1821 - int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp); 1819 + int link_bpp_x16 = 1820 + intel_dp_output_format_link_bpp_x16(pipe_config->output_format, bpp); 1822 1821 1823 - mode_rate = intel_dp_link_required(clock, link_bpp); 1822 + mode_rate = intel_dp_link_required(clock, fxp_q4_to_int_roundup(link_bpp_x16)); 1824 1823 1825 1824 for (i = 0; i < intel_dp->num_common_rates; i++) { 1826 1825 link_rate = intel_dp_common_rate(intel_dp, i); ··· 2205 2202 struct intel_display *display = to_intel_display(intel_dp); 2206 2203 const struct intel_connector *connector = to_intel_connector(conn_state->connector); 2207 2204 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2208 - int output_bpp; 2209 2205 int min_bpp_x16, max_bpp_x16, bpp_step_x16; 2210 2206 int dsc_joiner_max_bpp; 2211 2207 int num_joined_pipes = intel_crtc_num_joined_pipes(pipe_config); 2208 + int link_bpp_x16; 2212 2209 int bpp_x16; 2213 2210 int ret; 2214 2211 ··· 2220 2217 bpp_step_x16 = intel_dp_dsc_bpp_step_x16(connector); 2221 2218 2222 2219 /* Compressed BPP should be less than the Input DSC bpp */ 2223 - output_bpp = intel_dp_output_bpp(pipe_config->output_format, pipe_bpp); 2224 - max_bpp_x16 = min(max_bpp_x16, fxp_q4_from_int(output_bpp) - bpp_step_x16); 2220 + link_bpp_x16 = intel_dp_output_format_link_bpp_x16(pipe_config->output_format, pipe_bpp); 2221 + max_bpp_x16 = min(max_bpp_x16, link_bpp_x16 - bpp_step_x16); 2225 2222 2226 2223 drm_WARN_ON(display->drm, !is_power_of_2(bpp_step_x16)); 2227 2224 min_bpp_x16 = round_up(limits->link.min_bpp_x16, bpp_step_x16); ··· 3271 3268 if (crtc_state->dsc.compression_enable) 3272 3269 link_bpp_x16 = crtc_state->dsc.compressed_bpp_x16; 3273 3270 else 3274 - link_bpp_x16 = fxp_q4_from_int(intel_dp_output_bpp(crtc_state->output_format, 3275 - crtc_state->pipe_bpp)); 3271 + link_bpp_x16 = intel_dp_output_format_link_bpp_x16(crtc_state->output_format, 3272 + crtc_state->pipe_bpp); 3276 3273 3277 3274 /* Calculate min Hblank Link Layer Symbol Cycle Count for 8b/10b MST & 128b/132b */ 3278 3275 hactive_sym_cycles = drm_dp_link_symbol_cycles(max_lane_count, ··· 3382 3379 if (pipe_config->dsc.compression_enable) 3383 3380 link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16; 3384 3381 else 3385 - link_bpp_x16 = fxp_q4_from_int(intel_dp_output_bpp(pipe_config->output_format, 3386 - pipe_config->pipe_bpp)); 3382 + link_bpp_x16 = intel_dp_output_format_link_bpp_x16(pipe_config->output_format, 3383 + pipe_config->pipe_bpp); 3387 3384 3388 3385 if (intel_dp->mso_link_count) { 3389 3386 int n = intel_dp->mso_link_count;
+2 -1
drivers/gpu/drm/i915/display/intel_dp.h
··· 193 193 194 194 void intel_dp_invalidate_source_oui(struct intel_dp *intel_dp); 195 195 void intel_dp_wait_source_oui(struct intel_dp *intel_dp); 196 - int intel_dp_output_bpp(enum intel_output_format output_format, int bpp); 196 + int intel_dp_output_format_link_bpp_x16(enum intel_output_format output_format, 197 + int pipe_bpp); 197 198 198 199 bool intel_dp_compute_config_limits(struct intel_dp *intel_dp, 199 200 struct drm_connector_state *conn_state,
+2 -2
drivers/gpu/drm/i915/display/intel_dp_mst.c
··· 344 344 } 345 345 346 346 link_bpp_x16 = dsc ? bpp_x16 : 347 - fxp_q4_from_int(intel_dp_output_bpp(crtc_state->output_format, 348 - fxp_q4_to_int(bpp_x16))); 347 + intel_dp_output_format_link_bpp_x16(crtc_state->output_format, 348 + fxp_q4_to_int(bpp_x16)); 349 349 350 350 local_bw_overhead = intel_dp_mst_bw_overhead(crtc_state, 351 351 false, dsc_slice_count, link_bpp_x16);