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drm/i915/dp_mst: Simplify computing the min/max compressed bpp limits

Adjusting the compressed bpp range min/max limits in
intel_dp_dsc_nearest_valid_bpp() is unnecessary:

- The source/sink min/max values are enforced already by the
link_config_limits::min_bpp_x16/max_bpp_x16 values computed early in
intel_dp_compute_config_link_bpp_limits().
- The fixed set of valid bpps are enforced already - for all bpps in the
min .. max range by intel_dp_dsc_valid_compressed_bpp() called from
intel_dp_mtp_tu_compute_config().

The only thing needed is limiting max compressed bpp below the
uncompressed pipe bpp, do that one thing only instead of calling
intel_dp_dsc_nearest_valid_bpp().

Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://lore.kernel.org/r/20250509180340.554867-7-imre.deak@intel.com

Imre Deak 1f581f38 c2a38dc3

+2 -8
+1 -1
drivers/gpu/drm/i915/display/intel_dp.c
··· 847 847 return 6144 * 8; 848 848 } 849 849 850 - u32 intel_dp_dsc_nearest_valid_bpp(struct intel_display *display, u32 bpp, u32 pipe_bpp) 850 + static u32 intel_dp_dsc_nearest_valid_bpp(struct intel_display *display, u32 bpp, u32 pipe_bpp) 851 851 { 852 852 u32 bits_per_pixel = bpp; 853 853 int i;
-2
drivers/gpu/drm/i915/display/intel_dp.h
··· 174 174 const struct intel_connector *connector, 175 175 const struct intel_crtc_state *crtc_state); 176 176 177 - u32 intel_dp_dsc_nearest_valid_bpp(struct intel_display *display, u32 bpp, u32 pipe_bpp); 178 - 179 177 void intel_ddi_update_pipe(struct intel_atomic_state *state, 180 178 struct intel_encoder *encoder, 181 179 const struct intel_crtc_state *crtc_state,
+1 -5
drivers/gpu/drm/i915/display/intel_dp_mst.c
··· 491 491 drm_dbg_kms(display->drm, "DSC Sink supported compressed min bpp %d compressed max bpp %d\n", 492 492 min_compressed_bpp, max_compressed_bpp); 493 493 494 - /* Align compressed bpps according to our own constraints */ 495 - max_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(display, max_compressed_bpp, 496 - crtc_state->pipe_bpp); 497 - min_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(display, min_compressed_bpp, 498 - crtc_state->pipe_bpp); 494 + max_compressed_bpp = min(max_compressed_bpp, crtc_state->pipe_bpp - 1); 499 495 500 496 crtc_state->lane_count = limits->max_lane_count; 501 497 crtc_state->port_clock = limits->max_rate;