tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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net/mlx5: Add IFC bits for PCIe Congestion Event object

Add definitions for the PCIe Congestion Event object
and the relevant FW command structures.

Signed-off-by: Dragos Tatulea <dtatulea@nvidia.com>
Reviewed-by: Tariq Toukan <tariqt@nvidia.com>
Signed-off-by: Mark Bloch <mbloch@nvidia.com>
Link: https://patch.msgid.link/20250619113721.60201-3-mbloch@nvidia.com
Signed-off-by: Leon Romanovsky <leon@kernel.org>

authored by

Dragos Tatulea and committed by
Leon Romanovsky 1f6da566 ebf8d471

+40
+40
include/linux/mlx5/mlx5_ifc.h
··· 12509 12509 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 12510 12510 MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47, 12511 12511 MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL = 0x53, 12512 + MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT = 0x58, 12512 12513 MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15, 12513 12514 }; 12514 12515 ··· 12527 12526 enum { 12528 12527 MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL = 12529 12528 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL - 0x40), 12529 + MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT = 12530 + BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT - 0x40), 12530 12531 }; 12531 12532 12532 12533 enum { ··· 13285 13282 u8 rt_clock_identity[0x40]; 13286 13283 13287 13284 u8 reserved_at_80[0x180]; 13285 + }; 13286 + 13287 + struct mlx5_ifc_pcie_cong_event_obj_bits { 13288 + u8 modify_select_field[0x40]; 13289 + 13290 + u8 inbound_event_en[0x1]; 13291 + u8 outbound_event_en[0x1]; 13292 + u8 reserved_at_42[0x1e]; 13293 + 13294 + u8 reserved_at_60[0x1]; 13295 + u8 inbound_cong_state[0x3]; 13296 + u8 reserved_at_64[0x1]; 13297 + u8 outbound_cong_state[0x3]; 13298 + u8 reserved_at_68[0x18]; 13299 + 13300 + u8 inbound_cong_low_threshold[0x10]; 13301 + u8 inbound_cong_high_threshold[0x10]; 13302 + 13303 + u8 outbound_cong_low_threshold[0x10]; 13304 + u8 outbound_cong_high_threshold[0x10]; 13305 + 13306 + u8 reserved_at_e0[0x340]; 13307 + }; 13308 + 13309 + struct mlx5_ifc_pcie_cong_event_cmd_in_bits { 13310 + struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 13311 + struct mlx5_ifc_pcie_cong_event_obj_bits cong_obj; 13312 + }; 13313 + 13314 + struct mlx5_ifc_pcie_cong_event_cmd_out_bits { 13315 + struct mlx5_ifc_general_obj_out_cmd_hdr_bits hdr; 13316 + struct mlx5_ifc_pcie_cong_event_obj_bits cong_obj; 13317 + }; 13318 + 13319 + enum mlx5e_pcie_cong_event_mod_field { 13320 + MLX5_PCIE_CONG_EVENT_MOD_EVENT_EN = BIT(0), 13321 + MLX5_PCIE_CONG_EVENT_MOD_THRESH = BIT(2), 13288 13322 }; 13289 13323 13290 13324 #endif /* MLX5_IFC_H */