+2 -2

arch/x86/boot/startup/sme.c

reviewed

··· 523 523 me_mask = 1UL << (ebx & 0x3f); 524 524 525 525 /* Check the SEV MSR whether SEV or SME is enabled */ 526 526 - sev_status = msr = __rdmsr(MSR_AMD64_SEV); 526 526 + sev_status = msr = native_rdmsrq(MSR_AMD64_SEV); 527 527 feature_mask = (msr & MSR_AMD64_SEV_ENABLED) ? AMD_SEV_BIT : AMD_SME_BIT; 528 528 529 529 /* ··· 554 554 return; 555 555 556 556 /* For SME, check the SYSCFG MSR */ 557 557 - msr = __rdmsr(MSR_AMD64_SYSCFG); 557 557 + msr = native_rdmsrq(MSR_AMD64_SYSCFG); 558 558 if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT)) 559 559 return; 560 560 }

+2 -1

arch/x86/coco/sev/core.c

reviewed

··· 44 44 #include <asm/apic.h> 45 45 #include <asm/cpuid.h> 46 46 #include <asm/cmdline.h> 47 47 + #include <asm/msr.h> 47 48 48 49 /* AP INIT values as documented in the APM2 section "Processor Initialization State" */ 49 50 #define AP_INIT_CS_LIMIT 0xffff ··· 2040 2039 return; 2041 2040 2042 2041 setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ); 2043 2043 - rdmsrl(MSR_AMD64_GUEST_TSC_FREQ, tsc_freq_mhz); 2042 2042 + rdmsrq(MSR_AMD64_GUEST_TSC_FREQ, tsc_freq_mhz); 2044 2043 snp_tsc_freq_khz = (unsigned long)(tsc_freq_mhz * 1000); 2045 2044 2046 2045 x86_platform.calibrate_cpu = securetsc_get_tsc_khz;

+6 -6

arch/x86/events/amd/brs.c

reviewed

··· 44 44 static __always_inline void set_debug_extn_cfg(u64 val) 45 45 { 46 46 /* bits[4:3] must always be set to 11b */ 47 47 - __wrmsr(MSR_AMD_DBG_EXTN_CFG, val | 3ULL << 3, val >> 32); 47 47 + native_wrmsrq(MSR_AMD_DBG_EXTN_CFG, val | 3ULL << 3); 48 48 } 49 49 50 50 static __always_inline u64 get_debug_extn_cfg(void) 51 51 { 52 52 - return __rdmsr(MSR_AMD_DBG_EXTN_CFG); 52 52 + return native_rdmsrq(MSR_AMD_DBG_EXTN_CFG); 53 53 } 54 54 55 55 static bool __init amd_brs_detect(void) ··· 187 187 /* 188 188 * Mark first entry as poisoned 189 189 */ 190 190 - wrmsrl(brs_to(0), BRS_POISON); 190 190 + wrmsrq(brs_to(0), BRS_POISON); 191 191 } 192 192 193 193 int __init amd_brs_init(void) ··· 325 325 u32 brs_idx = tos - i; 326 326 u64 from, to; 327 327 328 328 - rdmsrl(brs_to(brs_idx), to); 328 328 + rdmsrq(brs_to(brs_idx), to); 329 329 330 330 /* Entry does not belong to us (as marked by kernel) */ 331 331 if (to == BRS_POISON) ··· 341 341 if (!amd_brs_match_plm(event, to)) 342 342 continue; 343 343 344 344 - rdmsrl(brs_from(brs_idx), from); 344 344 + rdmsrq(brs_from(brs_idx), from); 345 345 346 346 perf_clear_branch_entry_bitfields(br+nr); 347 347 ··· 371 371 idx = amd_brs_get_tos(&cfg); 372 372 373 373 /* Poison target of entry */ 374 374 - wrmsrl(brs_to(idx), BRS_POISON); 374 374 + wrmsrq(brs_to(idx), BRS_POISON); 375 375 } 376 376 377 377 /*

+7 -6

arch/x86/events/amd/core.c

reviewed

··· 9 9 #include <linux/jiffies.h> 10 10 #include <asm/apicdef.h> 11 11 #include <asm/apic.h> 12 12 + #include <asm/msr.h> 12 13 #include <asm/nmi.h> 13 14 14 15 #include "../perf_event.h" ··· 564 563 return; 565 564 566 565 /* Clear enable bits i.e. PerfCntrGlobalCtl.PerfCntrEn */ 567 567 - wrmsrl(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, 0); 566 566 + wrmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, 0); 568 567 569 568 /* 570 569 * Clear freeze and overflow bits i.e. PerfCntrGLobalStatus.LbrFreeze 571 570 * and PerfCntrGLobalStatus.PerfCntrOvfl 572 571 */ 573 573 - wrmsrl(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, 572 572 + wrmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, 574 573 GLOBAL_STATUS_LBRS_FROZEN | amd_pmu_global_cntr_mask); 575 574 } 576 575 ··· 652 651 653 652 static __always_inline void amd_pmu_set_global_ctl(u64 ctl) 654 653 { 655 655 - wrmsrl(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, ctl); 654 654 + wrmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, ctl); 656 655 } 657 656 658 657 static inline u64 amd_pmu_get_global_status(void) ··· 660 659 u64 status; 661 660 662 661 /* PerfCntrGlobalStatus is read-only */ 663 663 - rdmsrl(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS, status); 662 662 + rdmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS, status); 664 663 665 664 return status; 666 665 } ··· 673 672 * clears the same bit in PerfCntrGlobalStatus 674 673 */ 675 674 676 676 - wrmsrl(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, status); 675 675 + wrmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, status); 677 676 } 678 677 679 678 static bool amd_pmu_test_overflow_topbit(int idx) 680 679 { 681 680 u64 counter; 682 681 683 683 - rdmsrl(x86_pmu_event_addr(idx), counter); 682 682 + rdmsrq(x86_pmu_event_addr(idx), counter); 684 683 685 684 return !(counter & BIT_ULL(x86_pmu.cntval_bits - 1)); 686 685 }

+14 -13

arch/x86/events/amd/ibs.c

reviewed

··· 15 15 #include <linux/sched/clock.h> 16 16 17 17 #include <asm/apic.h> 18 18 + #include <asm/msr.h> 18 19 19 20 #include "../perf_event.h" 20 21 ··· 425 424 * prev count manually on overflow. 426 425 */ 427 426 while (!perf_event_try_update(event, count, 64)) { 428 428 - rdmsrl(event->hw.config_base, *config); 427 427 + rdmsrq(event->hw.config_base, *config); 429 428 count = perf_ibs->get_count(*config); 430 429 } 431 430 } ··· 436 435 u64 tmp = hwc->config | config; 437 436 438 437 if (perf_ibs->fetch_count_reset_broken) 439 439 - wrmsrl(hwc->config_base, tmp & ~perf_ibs->enable_mask); 438 438 + wrmsrq(hwc->config_base, tmp & ~perf_ibs->enable_mask); 440 439 441 441 - wrmsrl(hwc->config_base, tmp | perf_ibs->enable_mask); 440 440 + wrmsrq(hwc->config_base, tmp | perf_ibs->enable_mask); 442 441 } 443 442 444 443 /* ··· 453 452 { 454 453 config &= ~perf_ibs->cnt_mask; 455 454 if (boot_cpu_data.x86 == 0x10) 456 456 - wrmsrl(hwc->config_base, config); 455 455 + wrmsrq(hwc->config_base, config); 457 456 config &= ~perf_ibs->enable_mask; 458 458 - wrmsrl(hwc->config_base, config); 457 457 + wrmsrq(hwc->config_base, config); 459 458 } 460 459 461 460 /* ··· 514 513 if (!stopping && (hwc->state & PERF_HES_UPTODATE)) 515 514 return; 516 515 517 517 - rdmsrl(hwc->config_base, config); 516 516 + rdmsrq(hwc->config_base, config); 518 517 519 518 if (stopping) { 520 519 /* ··· 1257 1256 hwc = &event->hw; 1258 1257 msr = hwc->config_base; 1259 1258 buf = ibs_data.regs; 1260 1260 - rdmsrl(msr, *buf); 1259 1259 + rdmsrq(msr, *buf); 1261 1260 if (!(*buf++ & perf_ibs->valid_mask)) 1262 1261 goto fail; 1263 1262 ··· 1275 1274 offset_max = perf_ibs_get_offset_max(perf_ibs, event, check_rip); 1276 1275 1277 1276 do { 1278 1278 - rdmsrl(msr + offset, *buf++); 1277 1277 + rdmsrq(msr + offset, *buf++); 1279 1278 size++; 1280 1279 offset = find_next_bit(perf_ibs->offset_mask, 1281 1280 perf_ibs->offset_max, ··· 1305 1304 if (event->attr.sample_type & PERF_SAMPLE_RAW) { 1306 1305 if (perf_ibs == &perf_ibs_op) { 1307 1306 if (ibs_caps & IBS_CAPS_BRNTRGT) { 1308 1308 - rdmsrl(MSR_AMD64_IBSBRTARGET, *buf++); 1307 1307 + rdmsrq(MSR_AMD64_IBSBRTARGET, *buf++); 1309 1308 br_target_idx = size; 1310 1309 size++; 1311 1310 } 1312 1311 if (ibs_caps & IBS_CAPS_OPDATA4) { 1313 1313 - rdmsrl(MSR_AMD64_IBSOPDATA4, *buf++); 1312 1312 + rdmsrq(MSR_AMD64_IBSOPDATA4, *buf++); 1314 1313 size++; 1315 1314 } 1316 1315 } 1317 1316 if (perf_ibs == &perf_ibs_fetch && (ibs_caps & IBS_CAPS_FETCHCTLEXTD)) { 1318 1318 - rdmsrl(MSR_AMD64_ICIBSEXTDCTL, *buf++); 1317 1317 + rdmsrq(MSR_AMD64_ICIBSEXTDCTL, *buf++); 1319 1318 size++; 1320 1319 } 1321 1320 } ··· 1566 1565 1567 1566 preempt_disable(); 1568 1567 1569 1569 - rdmsrl(MSR_AMD64_IBSCTL, val); 1568 1568 + rdmsrq(MSR_AMD64_IBSCTL, val); 1570 1569 offset = val & IBSCTL_LVT_OFFSET_MASK; 1571 1570 1572 1571 if (!(val & IBSCTL_LVT_OFFSET_VALID)) { ··· 1681 1680 { 1682 1681 u64 val; 1683 1682 1684 1684 - rdmsrl(MSR_AMD64_IBSCTL, val); 1683 1683 + rdmsrq(MSR_AMD64_IBSCTL, val); 1685 1684 if (!(val & IBSCTL_LVT_OFFSET_VALID)) 1686 1685 return -EINVAL; 1687 1686

+2

arch/x86/events/amd/iommu.c

reviewed

··· 16 16 #include <linux/slab.h> 17 17 #include <linux/amd-iommu.h> 18 18 19 19 + #include <asm/msr.h> 20 20 + 19 21 #include "../perf_event.h" 20 22 #include "iommu.h" 21 23

+11 -10

arch/x86/events/amd/lbr.c

reviewed

··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 2 #include <linux/perf_event.h> 3 3 + #include <asm/msr.h> 3 4 #include <asm/perf_event.h> 4 5 5 6 #include "../perf_event.h" ··· 62 61 63 62 static __always_inline void amd_pmu_lbr_set_from(unsigned int idx, u64 val) 64 63 { 65 65 - wrmsrl(MSR_AMD_SAMP_BR_FROM + idx * 2, val); 64 64 + wrmsrq(MSR_AMD_SAMP_BR_FROM + idx * 2, val); 66 65 } 67 66 68 67 static __always_inline void amd_pmu_lbr_set_to(unsigned int idx, u64 val) 69 68 { 70 70 - wrmsrl(MSR_AMD_SAMP_BR_FROM + idx * 2 + 1, val); 69 69 + wrmsrq(MSR_AMD_SAMP_BR_FROM + idx * 2 + 1, val); 71 70 } 72 71 73 72 static __always_inline u64 amd_pmu_lbr_get_from(unsigned int idx) 74 73 { 75 74 u64 val; 76 75 77 77 - rdmsrl(MSR_AMD_SAMP_BR_FROM + idx * 2, val); 76 76 + rdmsrq(MSR_AMD_SAMP_BR_FROM + idx * 2, val); 78 77 79 78 return val; 80 79 } ··· 83 82 { 84 83 u64 val; 85 84 86 86 - rdmsrl(MSR_AMD_SAMP_BR_FROM + idx * 2 + 1, val); 85 85 + rdmsrq(MSR_AMD_SAMP_BR_FROM + idx * 2 + 1, val); 87 86 88 87 return val; 89 88 } ··· 334 333 335 334 cpuc->last_task_ctx = NULL; 336 335 cpuc->last_log_id = 0; 337 337 - wrmsrl(MSR_AMD64_LBR_SELECT, 0); 336 336 + wrmsrq(MSR_AMD64_LBR_SELECT, 0); 338 337 } 339 338 340 339 void amd_pmu_lbr_add(struct perf_event *event) ··· 397 396 /* Set hardware branch filter */ 398 397 if (cpuc->lbr_select) { 399 398 lbr_select = cpuc->lbr_sel->config & LBR_SELECT_MASK; 400 400 - wrmsrl(MSR_AMD64_LBR_SELECT, lbr_select); 399 399 + wrmsrq(MSR_AMD64_LBR_SELECT, lbr_select); 401 400 } 402 401 403 402 if (cpu_feature_enabled(X86_FEATURE_AMD_LBR_PMC_FREEZE)) { 404 404 - rdmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl); 405 405 - wrmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI); 403 403 + rdmsrq(MSR_IA32_DEBUGCTLMSR, dbg_ctl); 404 404 + wrmsrq(MSR_IA32_DEBUGCTLMSR, dbg_ctl | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI); 406 405 } 407 406 408 408 - rdmsrl(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg); 409 409 - wrmsrl(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg | DBG_EXTN_CFG_LBRV2EN); 407 407 + rdmsrq(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg); 408 408 + wrmsrq(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg | DBG_EXTN_CFG_LBRV2EN); 410 409 } 411 410 412 411 void amd_pmu_lbr_disable_all(void)

+6 -5

arch/x86/events/amd/power.c

reviewed

··· 11 11 #include <linux/slab.h> 12 12 #include <linux/perf_event.h> 13 13 #include <asm/cpu_device_id.h> 14 14 + #include <asm/msr.h> 14 15 #include "../perf_event.h" 15 16 16 17 /* Event code: LSB 8 bits, passed in attr->config any other bit is reserved. */ ··· 49 48 50 49 prev_pwr_acc = hwc->pwr_acc; 51 50 prev_ptsc = hwc->ptsc; 52 52 - rdmsrl(MSR_F15H_CU_PWR_ACCUMULATOR, new_pwr_acc); 53 53 - rdmsrl(MSR_F15H_PTSC, new_ptsc); 51 51 + rdmsrq(MSR_F15H_CU_PWR_ACCUMULATOR, new_pwr_acc); 52 52 + rdmsrq(MSR_F15H_PTSC, new_ptsc); 54 53 55 54 /* 56 55 * Calculate the CU power consumption over a time period, the unit of ··· 76 75 77 76 event->hw.state = 0; 78 77 79 79 - rdmsrl(MSR_F15H_PTSC, event->hw.ptsc); 80 80 - rdmsrl(MSR_F15H_CU_PWR_ACCUMULATOR, event->hw.pwr_acc); 78 78 + rdmsrq(MSR_F15H_PTSC, event->hw.ptsc); 79 79 + rdmsrq(MSR_F15H_CU_PWR_ACCUMULATOR, event->hw.pwr_acc); 81 80 } 82 81 83 82 static void pmu_event_start(struct perf_event *event, int mode) ··· 273 272 274 273 cpu_pwr_sample_ratio = cpuid_ecx(0x80000007); 275 274 276 276 - if (rdmsrl_safe(MSR_F15H_CU_MAX_PWR_ACCUMULATOR, &max_cu_acc_power)) { 275 275 + if (rdmsrq_safe(MSR_F15H_CU_MAX_PWR_ACCUMULATOR, &max_cu_acc_power)) { 277 276 pr_err("Failed to read max compute unit power accumulator MSR\n"); 278 277 return -ENODEV; 279 278 }

+7 -7

arch/x86/events/amd/uncore.c

reviewed

··· 106 106 * read counts directly from the corresponding PERF_CTR. 107 107 */ 108 108 if (hwc->event_base_rdpmc < 0) 109 109 - rdmsrl(hwc->event_base, new); 109 109 + rdmsrq(hwc->event_base, new); 110 110 else 111 111 - rdpmcl(hwc->event_base_rdpmc, new); 111 111 + new = rdpmc(hwc->event_base_rdpmc); 112 112 113 113 local64_set(&hwc->prev_count, new); 114 114 delta = (new << COUNTER_SHIFT) - (prev << COUNTER_SHIFT); ··· 121 121 struct hw_perf_event *hwc = &event->hw; 122 122 123 123 if (flags & PERF_EF_RELOAD) 124 124 - wrmsrl(hwc->event_base, (u64)local64_read(&hwc->prev_count)); 124 124 + wrmsrq(hwc->event_base, (u64)local64_read(&hwc->prev_count)); 125 125 126 126 hwc->state = 0; 127 127 - wrmsrl(hwc->config_base, (hwc->config | ARCH_PERFMON_EVENTSEL_ENABLE)); 127 127 + wrmsrq(hwc->config_base, (hwc->config | ARCH_PERFMON_EVENTSEL_ENABLE)); 128 128 perf_event_update_userpage(event); 129 129 } 130 130 ··· 132 132 { 133 133 struct hw_perf_event *hwc = &event->hw; 134 134 135 135 - wrmsrl(hwc->config_base, hwc->config); 135 135 + wrmsrq(hwc->config_base, hwc->config); 136 136 hwc->state |= PERF_HES_STOPPED; 137 137 138 138 if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { ··· 883 883 struct hw_perf_event *hwc = &event->hw; 884 884 885 885 if (flags & PERF_EF_RELOAD) 886 886 - wrmsrl(hwc->event_base, (u64)local64_read(&hwc->prev_count)); 886 886 + wrmsrq(hwc->event_base, (u64)local64_read(&hwc->prev_count)); 887 887 888 888 hwc->state = 0; 889 889 - wrmsrl(hwc->config_base, (hwc->config | AMD64_PERFMON_V2_ENABLE_UMC)); 889 889 + wrmsrq(hwc->config_base, (hwc->config | AMD64_PERFMON_V2_ENABLE_UMC)); 890 890 perf_event_update_userpage(event); 891 891 } 892 892

+23 -22

arch/x86/events/core.c

reviewed

··· 32 32 33 33 #include <asm/apic.h> 34 34 #include <asm/stacktrace.h> 35 35 + #include <asm/msr.h> 35 36 #include <asm/nmi.h> 36 37 #include <asm/smp.h> 37 38 #include <asm/alternative.h> ··· 135 134 */ 136 135 prev_raw_count = local64_read(&hwc->prev_count); 137 136 do { 138 138 - rdpmcl(hwc->event_base_rdpmc, new_raw_count); 137 137 + new_raw_count = rdpmc(hwc->event_base_rdpmc); 139 138 } while (!local64_try_cmpxchg(&hwc->prev_count, 140 139 &prev_raw_count, new_raw_count)); 141 140 ··· 270 269 */ 271 270 for_each_set_bit(i, cntr_mask, X86_PMC_IDX_MAX) { 272 271 reg = x86_pmu_config_addr(i); 273 273 - ret = rdmsrl_safe(reg, &val); 272 272 + ret = rdmsrq_safe(reg, &val); 274 273 if (ret) 275 274 goto msr_fail; 276 275 if (val & ARCH_PERFMON_EVENTSEL_ENABLE) { ··· 284 283 285 284 if (*(u64 *)fixed_cntr_mask) { 286 285 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; 287 287 - ret = rdmsrl_safe(reg, &val); 286 286 + ret = rdmsrq_safe(reg, &val); 288 287 if (ret) 289 288 goto msr_fail; 290 289 for_each_set_bit(i, fixed_cntr_mask, X86_PMC_IDX_MAX) { ··· 315 314 * (qemu/kvm) that don't trap on the MSR access and always return 0s. 316 315 */ 317 316 reg = x86_pmu_event_addr(reg_safe); 318 318 - if (rdmsrl_safe(reg, &val)) 317 317 + if (rdmsrq_safe(reg, &val)) 319 318 goto msr_fail; 320 319 val ^= 0xffffUL; 321 321 - ret = wrmsrl_safe(reg, val); 322 322 - ret |= rdmsrl_safe(reg, &val_new); 320 320 + ret = wrmsrq_safe(reg, val); 321 321 + ret |= rdmsrq_safe(reg, &val_new); 323 322 if (ret || val != val_new) 324 323 goto msr_fail; 325 324 ··· 694 693 695 694 if (!test_bit(idx, cpuc->active_mask)) 696 695 continue; 697 697 - rdmsrl(x86_pmu_config_addr(idx), val); 696 696 + rdmsrq(x86_pmu_config_addr(idx), val); 698 697 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) 699 698 continue; 700 699 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 701 701 - wrmsrl(x86_pmu_config_addr(idx), val); 700 700 + wrmsrq(x86_pmu_config_addr(idx), val); 702 701 if (is_counter_pair(hwc)) 703 703 - wrmsrl(x86_pmu_config_addr(idx + 1), 0); 702 702 + wrmsrq(x86_pmu_config_addr(idx + 1), 0); 704 703 } 705 704 } 706 705 ··· 1421 1420 */ 1422 1421 local64_set(&hwc->prev_count, (u64)-left); 1423 1422 1424 1424 - wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); 1423 1423 + wrmsrq(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); 1425 1424 1426 1425 /* 1427 1426 * Sign extend the Merge event counter's upper 16 bits since 1428 1427 * we currently declare a 48-bit counter width 1429 1428 */ 1430 1429 if (is_counter_pair(hwc)) 1431 1431 - wrmsrl(x86_pmu_event_addr(idx + 1), 0xffff); 1430 1430 + wrmsrq(x86_pmu_event_addr(idx + 1), 0xffff); 1432 1431 1433 1432 perf_event_update_userpage(event); 1434 1433 ··· 1551 1550 return; 1552 1551 1553 1552 if (x86_pmu.version >= 2) { 1554 1554 - rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); 1555 1555 - rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); 1556 1556 - rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); 1557 1557 - rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); 1553 1553 + rdmsrq(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); 1554 1554 + rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS, status); 1555 1555 + rdmsrq(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); 1556 1556 + rdmsrq(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); 1558 1557 1559 1558 pr_info("\n"); 1560 1559 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); ··· 1562 1561 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); 1563 1562 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); 1564 1563 if (pebs_constraints) { 1565 1565 - rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); 1564 1564 + rdmsrq(MSR_IA32_PEBS_ENABLE, pebs); 1566 1565 pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs); 1567 1566 } 1568 1567 if (x86_pmu.lbr_nr) { 1569 1569 - rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 1568 1568 + rdmsrq(MSR_IA32_DEBUGCTLMSR, debugctl); 1570 1569 pr_info("CPU#%d: debugctl: %016llx\n", cpu, debugctl); 1571 1570 } 1572 1571 } 1573 1572 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); 1574 1573 1575 1574 for_each_set_bit(idx, cntr_mask, X86_PMC_IDX_MAX) { 1576 1576 - rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl); 1577 1577 - rdmsrl(x86_pmu_event_addr(idx), pmc_count); 1575 1575 + rdmsrq(x86_pmu_config_addr(idx), pmc_ctrl); 1576 1576 + rdmsrq(x86_pmu_event_addr(idx), pmc_count); 1578 1577 1579 1578 prev_left = per_cpu(pmc_prev_left[idx], cpu); 1580 1579 ··· 1588 1587 for_each_set_bit(idx, fixed_cntr_mask, X86_PMC_IDX_MAX) { 1589 1588 if (fixed_counter_disabled(idx, cpuc->pmu)) 1590 1589 continue; 1591 1591 - rdmsrl(x86_pmu_fixed_ctr_addr(idx), pmc_count); 1590 1590 + rdmsrq(x86_pmu_fixed_ctr_addr(idx), pmc_count); 1592 1591 1593 1592 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", 1594 1593 cpu, idx, pmc_count); ··· 2497 2496 if (!test_bit(i - INTEL_PMC_IDX_FIXED, hybrid(cpuc->pmu, fixed_cntr_mask))) 2498 2497 continue; 2499 2498 2500 2500 - wrmsrl(x86_pmu_fixed_ctr_addr(i - INTEL_PMC_IDX_FIXED), 0); 2499 2499 + wrmsrq(x86_pmu_fixed_ctr_addr(i - INTEL_PMC_IDX_FIXED), 0); 2501 2500 } else { 2502 2502 - wrmsrl(x86_pmu_event_addr(i), 0); 2501 2501 + wrmsrq(x86_pmu_event_addr(i), 0); 2503 2502 } 2504 2503 } 2505 2504

+1

arch/x86/events/intel/bts.c

reviewed

··· 17 17 18 18 #include <linux/sizes.h> 19 19 #include <asm/perf_event.h> 20 20 + #include <asm/msr.h> 20 21 21 22 #include "../perf_event.h" 22 23

+36 -35

arch/x86/events/intel/core.c

reviewed

··· 23 23 #include <asm/intel_pt.h> 24 24 #include <asm/apic.h> 25 25 #include <asm/cpu_device_id.h> 26 26 + #include <asm/msr.h> 26 27 27 28 #include "../perf_event.h" 28 29 ··· 2286 2285 { 2287 2286 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2288 2287 2289 2289 - wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 2288 2288 + wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0); 2290 2289 2291 2290 if (bts && test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) 2292 2291 intel_pmu_disable_bts(); ··· 2307 2306 intel_pmu_lbr_enable_all(pmi); 2308 2307 2309 2308 if (cpuc->fixed_ctrl_val != cpuc->active_fixed_ctrl_val) { 2310 2310 - wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, cpuc->fixed_ctrl_val); 2309 2309 + wrmsrq(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, cpuc->fixed_ctrl_val); 2311 2310 cpuc->active_fixed_ctrl_val = cpuc->fixed_ctrl_val; 2312 2311 } 2313 2312 2314 2314 - wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 2313 2313 + wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 2315 2314 intel_ctrl & ~cpuc->intel_ctrl_guest_mask); 2316 2315 2317 2316 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { ··· 2427 2426 } 2428 2427 2429 2428 for (i = 0; i < 4; i++) { 2430 2430 - wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]); 2431 2431 - wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0); 2429 2429 + wrmsrq(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]); 2430 2430 + wrmsrq(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0); 2432 2431 } 2433 2432 2434 2434 - wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf); 2435 2435 - wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0); 2433 2433 + wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0xf); 2434 2434 + wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0x0); 2436 2435 2437 2436 for (i = 0; i < 4; i++) { 2438 2437 event = cpuc->events[i]; ··· 2442 2441 __x86_pmu_enable_event(&event->hw, 2443 2442 ARCH_PERFMON_EVENTSEL_ENABLE); 2444 2443 } else 2445 2445 - wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0); 2444 2444 + wrmsrq(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0); 2446 2445 } 2447 2446 } 2448 2447 ··· 2459 2458 2460 2459 if (cpuc->tfa_shadow != val) { 2461 2460 cpuc->tfa_shadow = val; 2462 2462 - wrmsrl(MSR_TSX_FORCE_ABORT, val); 2461 2461 + wrmsrq(MSR_TSX_FORCE_ABORT, val); 2463 2462 } 2464 2463 } 2465 2464 ··· 2490 2489 { 2491 2490 u64 status; 2492 2491 2493 2493 - rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); 2492 2492 + rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS, status); 2494 2493 2495 2494 return status; 2496 2495 } 2497 2496 2498 2497 static inline void intel_pmu_ack_status(u64 ack) 2499 2498 { 2500 2500 - wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); 2499 2499 + wrmsrq(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); 2501 2500 } 2502 2501 2503 2502 static inline bool event_is_checkpointed(struct perf_event *event) ··· 2620 2619 * Don't need to clear them again. 2621 2620 */ 2622 2621 if (left == x86_pmu.max_period) { 2623 2623 - wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0); 2624 2624 - wrmsrl(MSR_PERF_METRICS, 0); 2622 2622 + wrmsrq(MSR_CORE_PERF_FIXED_CTR3, 0); 2623 2623 + wrmsrq(MSR_PERF_METRICS, 0); 2625 2624 hwc->saved_slots = 0; 2626 2625 hwc->saved_metric = 0; 2627 2626 } 2628 2627 2629 2628 if ((hwc->saved_slots) && is_slots_event(event)) { 2630 2630 - wrmsrl(MSR_CORE_PERF_FIXED_CTR3, hwc->saved_slots); 2631 2631 - wrmsrl(MSR_PERF_METRICS, hwc->saved_metric); 2629 2629 + wrmsrq(MSR_CORE_PERF_FIXED_CTR3, hwc->saved_slots); 2630 2630 + wrmsrq(MSR_PERF_METRICS, hwc->saved_metric); 2632 2631 } 2633 2632 2634 2633 perf_event_update_userpage(event); ··· 2725 2724 2726 2725 if (!val) { 2727 2726 /* read Fixed counter 3 */ 2728 2728 - rdpmcl((3 | INTEL_PMC_FIXED_RDPMC_BASE), slots); 2727 2727 + slots = rdpmc(3 | INTEL_PMC_FIXED_RDPMC_BASE); 2729 2728 if (!slots) 2730 2729 return 0; 2731 2730 2732 2731 /* read PERF_METRICS */ 2733 2733 - rdpmcl(INTEL_PMC_FIXED_RDPMC_METRICS, metrics); 2732 2732 + metrics = rdpmc(INTEL_PMC_FIXED_RDPMC_METRICS); 2734 2733 } else { 2735 2734 slots = val[0]; 2736 2735 metrics = val[1]; ··· 2774 2773 2775 2774 if (reset) { 2776 2775 /* The fixed counter 3 has to be written before the PERF_METRICS. */ 2777 2777 - wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0); 2778 2778 - wrmsrl(MSR_PERF_METRICS, 0); 2776 2776 + wrmsrq(MSR_CORE_PERF_FIXED_CTR3, 0); 2777 2777 + wrmsrq(MSR_PERF_METRICS, 0); 2779 2778 if (event) 2780 2779 update_saved_topdown_regs(event, 0, 0, metric_end); 2781 2780 } ··· 2938 2937 */ 2939 2938 if (unlikely(event_is_checkpointed(event))) { 2940 2939 /* No race with NMIs because the counter should not be armed */ 2941 2941 - wrmsrl(event->hw.event_base, 0); 2940 2940 + wrmsrq(event->hw.event_base, 0); 2942 2941 local64_set(&event->hw.prev_count, 0); 2943 2942 } 2944 2943 return static_call(x86_pmu_set_period)(event); ··· 2977 2976 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id()); 2978 2977 2979 2978 for_each_set_bit(idx, cntr_mask, INTEL_PMC_MAX_GENERIC) { 2980 2980 - wrmsrl_safe(x86_pmu_config_addr(idx), 0ull); 2981 2981 - wrmsrl_safe(x86_pmu_event_addr(idx), 0ull); 2979 2979 + wrmsrq_safe(x86_pmu_config_addr(idx), 0ull); 2980 2980 + wrmsrq_safe(x86_pmu_event_addr(idx), 0ull); 2982 2981 } 2983 2982 for_each_set_bit(idx, fixed_cntr_mask, INTEL_PMC_MAX_FIXED) { 2984 2983 if (fixed_counter_disabled(idx, cpuc->pmu)) 2985 2984 continue; 2986 2986 - wrmsrl_safe(x86_pmu_fixed_ctr_addr(idx), 0ull); 2985 2985 + wrmsrq_safe(x86_pmu_fixed_ctr_addr(idx), 0ull); 2987 2986 } 2988 2987 2989 2988 if (ds) ··· 2992 2991 /* Ack all overflows and disable fixed counters */ 2993 2992 if (x86_pmu.version >= 2) { 2994 2993 intel_pmu_ack_status(intel_pmu_get_status()); 2995 2995 - wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 2994 2994 + wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0); 2996 2995 } 2997 2996 2998 2997 /* Reset LBRs and LBR freezing */ ··· 3102 3101 * Update the MSR if pebs_enabled is changed. 3103 3102 */ 3104 3103 if (pebs_enabled != cpuc->pebs_enabled) 3105 3105 - wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); 3104 3104 + wrmsrq(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); 3106 3105 3107 3106 /* 3108 3107 * Above PEBS handler (PEBS counters snapshotting) has updated fixed ··· 5064 5063 5065 5064 if (!intel_pmu_broken_perf_cap()) { 5066 5065 /* Perf Metric (Bit 15) and PEBS via PT (Bit 16) are hybrid enumeration */ 5067 5067 - rdmsrl(MSR_IA32_PERF_CAPABILITIES, pmu->intel_cap.capabilities); 5066 5066 + rdmsrq(MSR_IA32_PERF_CAPABILITIES, pmu->intel_cap.capabilities); 5068 5067 } 5069 5068 } 5070 5069 ··· 5212 5211 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) { 5213 5212 union perf_capabilities perf_cap; 5214 5213 5215 5215 - rdmsrl(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities); 5214 5214 + rdmsrq(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities); 5216 5215 if (!perf_cap.perf_metrics) { 5217 5216 x86_pmu.intel_cap.perf_metrics = 0; 5218 5217 x86_pmu.intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS); ··· 5620 5619 * matches, this is needed to detect certain hardware emulators 5621 5620 * (qemu/kvm) that don't trap on the MSR access and always return 0s. 5622 5621 */ 5623 5623 - if (rdmsrl_safe(msr, &val_old)) 5622 5622 + if (rdmsrq_safe(msr, &val_old)) 5624 5623 return false; 5625 5624 5626 5625 /* 5627 5627 - * Only change the bits which can be updated by wrmsrl. 5626 5626 + * Only change the bits which can be updated by wrmsrq. 5628 5627 */ 5629 5628 val_tmp = val_old ^ mask; 5630 5629 5631 5630 if (is_lbr_from(msr)) 5632 5631 val_tmp = lbr_from_signext_quirk_wr(val_tmp); 5633 5632 5634 5634 - if (wrmsrl_safe(msr, val_tmp) || 5635 5635 - rdmsrl_safe(msr, &val_new)) 5633 5633 + if (wrmsrq_safe(msr, val_tmp) || 5634 5634 + rdmsrq_safe(msr, &val_new)) 5636 5635 return false; 5637 5636 5638 5637 /* 5639 5639 - * Quirk only affects validation in wrmsr(), so wrmsrl()'s value 5640 5640 - * should equal rdmsrl()'s even with the quirk. 5638 5638 + * Quirk only affects validation in wrmsr(), so wrmsrq()'s value 5639 5639 + * should equal rdmsrq()'s even with the quirk. 5641 5640 */ 5642 5641 if (val_new != val_tmp) 5643 5642 return false; ··· 5648 5647 /* Here it's sure that the MSR can be safely accessed. 5649 5648 * Restore the old value and return. 5650 5649 */ 5651 5651 - wrmsrl(msr, val_old); 5650 5650 + wrmsrq(msr, val_old); 5652 5651 5653 5652 return true; 5654 5653 } ··· 6652 6651 if (boot_cpu_has(X86_FEATURE_PDCM)) { 6653 6652 u64 capabilities; 6654 6653 6655 6655 - rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities); 6654 6654 + rdmsrq(MSR_IA32_PERF_CAPABILITIES, capabilities); 6656 6655 x86_pmu.intel_cap.capabilities = capabilities; 6657 6656 } 6658 6657

+2 -1

arch/x86/events/intel/cstate.c

reviewed

··· 111 111 #include <linux/nospec.h> 112 112 #include <asm/cpu_device_id.h> 113 113 #include <asm/intel-family.h> 114 114 + #include <asm/msr.h> 114 115 #include "../perf_event.h" 115 116 #include "../probe.h" 116 117 ··· 321 320 { 322 321 u64 val; 323 322 324 324 - rdmsrl(event->hw.event_base, val); 323 323 + rdmsrq(event->hw.event_base, val); 325 324 return val; 326 325 } 327 326

+7 -6

arch/x86/events/intel/ds.c

reviewed

··· 10 10 #include <asm/tlbflush.h> 11 11 #include <asm/insn.h> 12 12 #include <asm/io.h> 13 13 + #include <asm/msr.h> 13 14 #include <asm/timer.h> 14 15 15 16 #include "../perf_event.h" ··· 1518 1517 else 1519 1518 value = ds->pebs_event_reset[MAX_PEBS_EVENTS + idx]; 1520 1519 } 1521 1521 - wrmsrl(base + idx, value); 1520 1520 + wrmsrq(base + idx, value); 1522 1521 } 1523 1522 1524 1523 static inline void intel_pmu_drain_large_pebs(struct cpu_hw_events *cpuc) ··· 1555 1554 */ 1556 1555 intel_pmu_drain_pebs_buffer(); 1557 1556 adaptive_pebs_record_size_update(); 1558 1558 - wrmsrl(MSR_PEBS_DATA_CFG, pebs_data_cfg); 1557 1557 + wrmsrq(MSR_PEBS_DATA_CFG, pebs_data_cfg); 1559 1558 cpuc->active_pebs_data_cfg = pebs_data_cfg; 1560 1559 } 1561 1560 } ··· 1618 1617 intel_pmu_pebs_via_pt_disable(event); 1619 1618 1620 1619 if (cpuc->enabled) 1621 1621 - wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); 1620 1620 + wrmsrq(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); 1622 1621 1623 1622 hwc->config |= ARCH_PERFMON_EVENTSEL_INT; 1624 1623 } ··· 1628 1627 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1629 1628 1630 1629 if (cpuc->pebs_enabled) 1631 1631 - wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); 1630 1630 + wrmsrq(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); 1632 1631 } 1633 1632 1634 1633 void intel_pmu_pebs_disable_all(void) ··· 2277 2276 WARN_ON(this_cpu_read(cpu_hw_events.enabled)); 2278 2277 2279 2278 prev_raw_count = local64_read(&hwc->prev_count); 2280 2280 - rdpmcl(hwc->event_base_rdpmc, new_raw_count); 2279 2279 + new_raw_count = rdpmc(hwc->event_base_rdpmc); 2281 2280 local64_set(&hwc->prev_count, new_raw_count); 2282 2281 2283 2282 /* ··· 2791 2790 if (!x86_pmu.bts && !x86_pmu.pebs) 2792 2791 return; 2793 2792 2794 2794 - wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds); 2793 2793 + wrmsrq(MSR_IA32_DS_AREA, (unsigned long)ds); 2795 2794 }

+9 -8

arch/x86/events/intel/knc.c

reviewed

··· 5 5 #include <linux/types.h> 6 6 7 7 #include <asm/hardirq.h> 8 8 + #include <asm/msr.h> 8 9 9 10 #include "../perf_event.h" 10 11 ··· 160 159 { 161 160 u64 val; 162 161 163 163 - rdmsrl(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val); 162 162 + rdmsrq(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val); 164 163 val &= ~(KNC_ENABLE_COUNTER0|KNC_ENABLE_COUNTER1); 165 165 - wrmsrl(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val); 164 164 + wrmsrq(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val); 166 165 } 167 166 168 167 static void knc_pmu_enable_all(int added) 169 168 { 170 169 u64 val; 171 170 172 172 - rdmsrl(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val); 171 171 + rdmsrq(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val); 173 172 val |= (KNC_ENABLE_COUNTER0|KNC_ENABLE_COUNTER1); 174 174 - wrmsrl(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val); 173 173 + wrmsrq(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val); 175 174 } 176 175 177 176 static inline void ··· 183 182 val = hwc->config; 184 183 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 185 184 186 186 - (void)wrmsrl_safe(hwc->config_base + hwc->idx, val); 185 185 + (void)wrmsrq_safe(hwc->config_base + hwc->idx, val); 187 186 } 188 187 189 188 static void knc_pmu_enable_event(struct perf_event *event) ··· 194 193 val = hwc->config; 195 194 val |= ARCH_PERFMON_EVENTSEL_ENABLE; 196 195 197 197 - (void)wrmsrl_safe(hwc->config_base + hwc->idx, val); 196 196 + (void)wrmsrq_safe(hwc->config_base + hwc->idx, val); 198 197 } 199 198 200 199 static inline u64 knc_pmu_get_status(void) 201 200 { 202 201 u64 status; 203 202 204 204 - rdmsrl(MSR_KNC_IA32_PERF_GLOBAL_STATUS, status); 203 203 + rdmsrq(MSR_KNC_IA32_PERF_GLOBAL_STATUS, status); 205 204 206 205 return status; 207 206 } 208 207 209 208 static inline void knc_pmu_ack_status(u64 ack) 210 209 { 211 211 - wrmsrl(MSR_KNC_IA32_PERF_GLOBAL_OVF_CONTROL, ack); 210 210 + wrmsrq(MSR_KNC_IA32_PERF_GLOBAL_OVF_CONTROL, ack); 212 211 } 213 212 214 213 static int knc_pmu_handle_irq(struct pt_regs *regs)

+22 -22

arch/x86/events/intel/lbr.c

reviewed

··· 137 137 if (cpuc->lbr_sel) 138 138 lbr_select = cpuc->lbr_sel->config & x86_pmu.lbr_sel_mask; 139 139 if (!static_cpu_has(X86_FEATURE_ARCH_LBR) && !pmi && cpuc->lbr_sel) 140 140 - wrmsrl(MSR_LBR_SELECT, lbr_select); 140 140 + wrmsrq(MSR_LBR_SELECT, lbr_select); 141 141 142 142 - rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 142 142 + rdmsrq(MSR_IA32_DEBUGCTLMSR, debugctl); 143 143 orig_debugctl = debugctl; 144 144 145 145 if (!static_cpu_has(X86_FEATURE_ARCH_LBR)) ··· 155 155 debugctl |= DEBUGCTLMSR_FREEZE_LBRS_ON_PMI; 156 156 157 157 if (orig_debugctl != debugctl) 158 158 - wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 158 158 + wrmsrq(MSR_IA32_DEBUGCTLMSR, debugctl); 159 159 160 160 if (static_cpu_has(X86_FEATURE_ARCH_LBR)) 161 161 - wrmsrl(MSR_ARCH_LBR_CTL, lbr_select | ARCH_LBR_CTL_LBREN); 161 161 + wrmsrq(MSR_ARCH_LBR_CTL, lbr_select | ARCH_LBR_CTL_LBREN); 162 162 } 163 163 164 164 void intel_pmu_lbr_reset_32(void) ··· 166 166 int i; 167 167 168 168 for (i = 0; i < x86_pmu.lbr_nr; i++) 169 169 - wrmsrl(x86_pmu.lbr_from + i, 0); 169 169 + wrmsrq(x86_pmu.lbr_from + i, 0); 170 170 } 171 171 172 172 void intel_pmu_lbr_reset_64(void) ··· 174 174 int i; 175 175 176 176 for (i = 0; i < x86_pmu.lbr_nr; i++) { 177 177 - wrmsrl(x86_pmu.lbr_from + i, 0); 178 178 - wrmsrl(x86_pmu.lbr_to + i, 0); 177 177 + wrmsrq(x86_pmu.lbr_from + i, 0); 178 178 + wrmsrq(x86_pmu.lbr_to + i, 0); 179 179 if (x86_pmu.lbr_has_info) 180 180 - wrmsrl(x86_pmu.lbr_info + i, 0); 180 180 + wrmsrq(x86_pmu.lbr_info + i, 0); 181 181 } 182 182 } 183 183 184 184 static void intel_pmu_arch_lbr_reset(void) 185 185 { 186 186 /* Write to ARCH_LBR_DEPTH MSR, all LBR entries are reset to 0 */ 187 187 - wrmsrl(MSR_ARCH_LBR_DEPTH, x86_pmu.lbr_nr); 187 187 + wrmsrq(MSR_ARCH_LBR_DEPTH, x86_pmu.lbr_nr); 188 188 } 189 189 190 190 void intel_pmu_lbr_reset(void) ··· 199 199 cpuc->last_task_ctx = NULL; 200 200 cpuc->last_log_id = 0; 201 201 if (!static_cpu_has(X86_FEATURE_ARCH_LBR) && cpuc->lbr_select) 202 202 - wrmsrl(MSR_LBR_SELECT, 0); 202 202 + wrmsrq(MSR_LBR_SELECT, 0); 203 203 } 204 204 205 205 /* ··· 209 209 { 210 210 u64 tos; 211 211 212 212 - rdmsrl(x86_pmu.lbr_tos, tos); 212 212 + rdmsrq(x86_pmu.lbr_tos, tos); 213 213 return tos; 214 214 } 215 215 ··· 282 282 static __always_inline void wrlbr_from(unsigned int idx, u64 val) 283 283 { 284 284 val = lbr_from_signext_quirk_wr(val); 285 285 - wrmsrl(x86_pmu.lbr_from + idx, val); 285 285 + wrmsrq(x86_pmu.lbr_from + idx, val); 286 286 } 287 287 288 288 static __always_inline void wrlbr_to(unsigned int idx, u64 val) 289 289 { 290 290 - wrmsrl(x86_pmu.lbr_to + idx, val); 290 290 + wrmsrq(x86_pmu.lbr_to + idx, val); 291 291 } 292 292 293 293 static __always_inline void wrlbr_info(unsigned int idx, u64 val) 294 294 { 295 295 - wrmsrl(x86_pmu.lbr_info + idx, val); 295 295 + wrmsrq(x86_pmu.lbr_info + idx, val); 296 296 } 297 297 298 298 static __always_inline u64 rdlbr_from(unsigned int idx, struct lbr_entry *lbr) ··· 302 302 if (lbr) 303 303 return lbr->from; 304 304 305 305 - rdmsrl(x86_pmu.lbr_from + idx, val); 305 305 + rdmsrq(x86_pmu.lbr_from + idx, val); 306 306 307 307 return lbr_from_signext_quirk_rd(val); 308 308 } ··· 314 314 if (lbr) 315 315 return lbr->to; 316 316 317 317 - rdmsrl(x86_pmu.lbr_to + idx, val); 317 317 + rdmsrq(x86_pmu.lbr_to + idx, val); 318 318 319 319 return val; 320 320 } ··· 326 326 if (lbr) 327 327 return lbr->info; 328 328 329 329 - rdmsrl(x86_pmu.lbr_info + idx, val); 329 329 + rdmsrq(x86_pmu.lbr_info + idx, val); 330 330 331 331 return val; 332 332 } ··· 380 380 wrlbr_info(lbr_idx, 0); 381 381 } 382 382 383 383 - wrmsrl(x86_pmu.lbr_tos, tos); 383 383 + wrmsrq(x86_pmu.lbr_tos, tos); 384 384 385 385 if (cpuc->lbr_select) 386 386 - wrmsrl(MSR_LBR_SELECT, task_ctx->lbr_sel); 386 386 + wrmsrq(MSR_LBR_SELECT, task_ctx->lbr_sel); 387 387 } 388 388 389 389 static void intel_pmu_arch_lbr_restore(void *ctx) ··· 475 475 task_ctx->tos = tos; 476 476 477 477 if (cpuc->lbr_select) 478 478 - rdmsrl(MSR_LBR_SELECT, task_ctx->lbr_sel); 478 478 + rdmsrq(MSR_LBR_SELECT, task_ctx->lbr_sel); 479 479 } 480 480 481 481 static void intel_pmu_arch_lbr_save(void *ctx) ··· 752 752 u64 lbr; 753 753 } msr_lastbranch; 754 754 755 755 - rdmsrl(x86_pmu.lbr_from + lbr_idx, msr_lastbranch.lbr); 755 755 + rdmsrq(x86_pmu.lbr_from + lbr_idx, msr_lastbranch.lbr); 756 756 757 757 perf_clear_branch_entry_bitfields(br); 758 758 ··· 1602 1602 goto clear_arch_lbr; 1603 1603 1604 1604 /* Apply the max depth of Arch LBR */ 1605 1605 - if (wrmsrl_safe(MSR_ARCH_LBR_DEPTH, lbr_nr)) 1605 1605 + if (wrmsrq_safe(MSR_ARCH_LBR_DEPTH, lbr_nr)) 1606 1606 goto clear_arch_lbr; 1607 1607 1608 1608 x86_pmu.lbr_depth_mask = eax.split.lbr_depth_mask;

+13 -12

arch/x86/events/intel/p4.c

reviewed

··· 13 13 #include <asm/cpu_device_id.h> 14 14 #include <asm/hardirq.h> 15 15 #include <asm/apic.h> 16 16 + #include <asm/msr.h> 16 17 17 18 #include "../perf_event.h" 18 19 ··· 860 859 u64 v; 861 860 862 861 /* an official way for overflow indication */ 863 863 - rdmsrl(hwc->config_base, v); 862 862 + rdmsrq(hwc->config_base, v); 864 863 if (v & P4_CCCR_OVF) { 865 865 - wrmsrl(hwc->config_base, v & ~P4_CCCR_OVF); 864 864 + wrmsrq(hwc->config_base, v & ~P4_CCCR_OVF); 866 865 return 1; 867 866 } 868 867 ··· 873 872 * the counter has reached zero value and continued counting before 874 873 * real NMI signal was received: 875 874 */ 876 876 - rdmsrl(hwc->event_base, v); 875 875 + rdmsrq(hwc->event_base, v); 877 876 if (!(v & ARCH_P4_UNFLAGGED_BIT)) 878 877 return 1; 879 878 ··· 898 897 * So at moment let leave metrics turned on forever -- it's 899 898 * ok for now but need to be revisited! 900 899 * 901 901 - * (void)wrmsrl_safe(MSR_IA32_PEBS_ENABLE, 0); 902 902 - * (void)wrmsrl_safe(MSR_P4_PEBS_MATRIX_VERT, 0); 900 900 + * (void)wrmsrq_safe(MSR_IA32_PEBS_ENABLE, 0); 901 901 + * (void)wrmsrq_safe(MSR_P4_PEBS_MATRIX_VERT, 0); 903 902 */ 904 903 } 905 904 ··· 912 911 * state we need to clear P4_CCCR_OVF, otherwise interrupt get 913 912 * asserted again and again 914 913 */ 915 915 - (void)wrmsrl_safe(hwc->config_base, 914 914 + (void)wrmsrq_safe(hwc->config_base, 916 915 p4_config_unpack_cccr(hwc->config) & ~P4_CCCR_ENABLE & ~P4_CCCR_OVF & ~P4_CCCR_RESERVED); 917 916 } 918 917 ··· 945 944 946 945 bind = &p4_pebs_bind_map[idx]; 947 946 948 948 - (void)wrmsrl_safe(MSR_IA32_PEBS_ENABLE, (u64)bind->metric_pebs); 949 949 - (void)wrmsrl_safe(MSR_P4_PEBS_MATRIX_VERT, (u64)bind->metric_vert); 947 947 + (void)wrmsrq_safe(MSR_IA32_PEBS_ENABLE, (u64)bind->metric_pebs); 948 948 + (void)wrmsrq_safe(MSR_P4_PEBS_MATRIX_VERT, (u64)bind->metric_vert); 950 949 } 951 950 952 951 static void __p4_pmu_enable_event(struct perf_event *event) ··· 980 979 */ 981 980 p4_pmu_enable_pebs(hwc->config); 982 981 983 983 - (void)wrmsrl_safe(escr_addr, escr_conf); 984 984 - (void)wrmsrl_safe(hwc->config_base, 982 982 + (void)wrmsrq_safe(escr_addr, escr_conf); 983 983 + (void)wrmsrq_safe(hwc->config_base, 985 984 (cccr & ~P4_CCCR_RESERVED) | P4_CCCR_ENABLE); 986 985 } 987 986 ··· 1025 1024 * 1026 1025 * the former idea is taken from OProfile code 1027 1026 */ 1028 1028 - wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); 1027 1027 + wrmsrq(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); 1029 1028 } 1030 1029 1031 1030 return ret; ··· 1399 1398 */ 1400 1399 for_each_set_bit(i, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { 1401 1400 reg = x86_pmu_config_addr(i); 1402 1402 - wrmsrl_safe(reg, 0ULL); 1401 1401 + wrmsrq_safe(reg, 0ULL); 1403 1402 } 1404 1403 1405 1404 return 0;

+7 -6

arch/x86/events/intel/p6.c

reviewed

··· 3 3 #include <linux/types.h> 4 4 5 5 #include <asm/cpu_device_id.h> 6 6 + #include <asm/msr.h> 6 7 7 8 #include "../perf_event.h" 8 9 ··· 143 142 u64 val; 144 143 145 144 /* p6 only has one enable register */ 146 146 - rdmsrl(MSR_P6_EVNTSEL0, val); 145 145 + rdmsrq(MSR_P6_EVNTSEL0, val); 147 146 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; 148 148 - wrmsrl(MSR_P6_EVNTSEL0, val); 147 147 + wrmsrq(MSR_P6_EVNTSEL0, val); 149 148 } 150 149 151 150 static void p6_pmu_enable_all(int added) ··· 153 152 unsigned long val; 154 153 155 154 /* p6 only has one enable register */ 156 156 - rdmsrl(MSR_P6_EVNTSEL0, val); 155 155 + rdmsrq(MSR_P6_EVNTSEL0, val); 157 156 val |= ARCH_PERFMON_EVENTSEL_ENABLE; 158 158 - wrmsrl(MSR_P6_EVNTSEL0, val); 157 157 + wrmsrq(MSR_P6_EVNTSEL0, val); 159 158 } 160 159 161 160 static inline void ··· 164 163 struct hw_perf_event *hwc = &event->hw; 165 164 u64 val = P6_NOP_EVENT; 166 165 167 167 - (void)wrmsrl_safe(hwc->config_base, val); 166 166 + (void)wrmsrq_safe(hwc->config_base, val); 168 167 } 169 168 170 169 static void p6_pmu_enable_event(struct perf_event *event) ··· 181 180 * to actually enable the events. 182 181 */ 183 182 184 184 - (void)wrmsrl_safe(hwc->config_base, val); 183 183 + (void)wrmsrq_safe(hwc->config_base, val); 185 184 } 186 185 187 186 PMU_FORMAT_ATTR(event, "config:0-7" );

+17 -16

arch/x86/events/intel/pt.c

reviewed

··· 24 24 #include <asm/io.h> 25 25 #include <asm/intel_pt.h> 26 26 #include <asm/cpu_device_id.h> 27 27 + #include <asm/msr.h> 27 28 28 29 #include "../perf_event.h" 29 30 #include "pt.h" ··· 195 194 int ret; 196 195 long i; 197 196 198 198 - rdmsrl(MSR_PLATFORM_INFO, reg); 197 197 + rdmsrq(MSR_PLATFORM_INFO, reg); 199 198 pt_pmu.max_nonturbo_ratio = (reg & 0xff00) >> 8; 200 199 201 200 /* ··· 231 230 * "IA32_VMX_MISC[bit 14]" being 1 means PT can trace 232 231 * post-VMXON. 233 232 */ 234 234 - rdmsrl(MSR_IA32_VMX_MISC, reg); 233 233 + rdmsrq(MSR_IA32_VMX_MISC, reg); 235 234 if (reg & BIT(14)) 236 235 pt_pmu.vmx = true; 237 236 } ··· 427 426 if (READ_ONCE(pt->vmx_on)) 428 427 perf_aux_output_flag(&pt->handle, PERF_AUX_FLAG_PARTIAL); 429 428 else 430 430 - wrmsrl(MSR_IA32_RTIT_CTL, ctl); 429 429 + wrmsrq(MSR_IA32_RTIT_CTL, ctl); 431 430 432 431 WRITE_ONCE(event->hw.aux_config, ctl); 433 432 } ··· 486 485 487 486 /* avoid redundant msr writes */ 488 487 if (pt->filters.filter[range].msr_a != filter->msr_a) { 489 489 - wrmsrl(pt_address_ranges[range].msr_a, filter->msr_a); 488 488 + wrmsrq(pt_address_ranges[range].msr_a, filter->msr_a); 490 489 pt->filters.filter[range].msr_a = filter->msr_a; 491 490 } 492 491 493 492 if (pt->filters.filter[range].msr_b != filter->msr_b) { 494 494 - wrmsrl(pt_address_ranges[range].msr_b, filter->msr_b); 493 493 + wrmsrq(pt_address_ranges[range].msr_b, filter->msr_b); 495 494 pt->filters.filter[range].msr_b = filter->msr_b; 496 495 } 497 496 ··· 510 509 /* First round: clear STATUS, in particular the PSB byte counter. */ 511 510 if (!event->hw.aux_config) { 512 511 perf_event_itrace_started(event); 513 513 - wrmsrl(MSR_IA32_RTIT_STATUS, 0); 512 512 + wrmsrq(MSR_IA32_RTIT_STATUS, 0); 514 513 } 515 514 516 515 reg = pt_config_filters(event); ··· 570 569 571 570 ctl &= ~RTIT_CTL_TRACEEN; 572 571 if (!READ_ONCE(pt->vmx_on)) 573 573 - wrmsrl(MSR_IA32_RTIT_CTL, ctl); 572 572 + wrmsrq(MSR_IA32_RTIT_CTL, ctl); 574 573 575 574 WRITE_ONCE(event->hw.aux_config, ctl); 576 575 ··· 659 658 reg = virt_to_phys(base); 660 659 if (pt->output_base != reg) { 661 660 pt->output_base = reg; 662 662 - wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, reg); 661 661 + wrmsrq(MSR_IA32_RTIT_OUTPUT_BASE, reg); 663 662 } 664 663 665 664 reg = 0x7f | (mask << 7) | ((u64)buf->output_off << 32); 666 665 if (pt->output_mask != reg) { 667 666 pt->output_mask = reg; 668 668 - wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, reg); 667 667 + wrmsrq(MSR_IA32_RTIT_OUTPUT_MASK, reg); 669 668 } 670 669 } 671 670 ··· 927 926 int advance = 0; 928 927 u64 status; 929 928 930 930 - rdmsrl(MSR_IA32_RTIT_STATUS, status); 929 929 + rdmsrq(MSR_IA32_RTIT_STATUS, status); 931 930 932 931 if (status & RTIT_STATUS_ERROR) { 933 932 pr_err_ratelimited("ToPA ERROR encountered, trying to recover\n"); ··· 971 970 if (advance) 972 971 pt_buffer_advance(buf); 973 972 974 974 - wrmsrl(MSR_IA32_RTIT_STATUS, status); 973 973 + wrmsrq(MSR_IA32_RTIT_STATUS, status); 975 974 } 976 975 977 976 /** ··· 986 985 struct topa_page *tp; 987 986 988 987 if (!buf->single) { 989 989 - rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, pt->output_base); 988 988 + rdmsrq(MSR_IA32_RTIT_OUTPUT_BASE, pt->output_base); 990 989 tp = phys_to_virt(pt->output_base); 991 990 buf->cur = &tp->topa; 992 991 } 993 992 994 994 - rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, pt->output_mask); 993 993 + rdmsrq(MSR_IA32_RTIT_OUTPUT_MASK, pt->output_mask); 995 994 /* offset within current output region */ 996 995 buf->output_off = pt->output_mask >> 32; 997 996 /* index of current output region within this table */ ··· 1586 1585 1587 1586 /* Turn PTs back on */ 1588 1587 if (!on && event) 1589 1589 - wrmsrl(MSR_IA32_RTIT_CTL, event->hw.aux_config); 1588 1588 + wrmsrq(MSR_IA32_RTIT_CTL, event->hw.aux_config); 1590 1589 1591 1590 local_irq_restore(flags); 1592 1591 } ··· 1612 1611 * PMI might have just cleared these, so resume_allowed 1613 1612 * must be checked again also. 1614 1613 */ 1615 1615 - rdmsrl(MSR_IA32_RTIT_STATUS, status); 1614 1614 + rdmsrq(MSR_IA32_RTIT_STATUS, status); 1616 1615 if (!(status & (RTIT_STATUS_TRIGGEREN | 1617 1616 RTIT_STATUS_ERROR | 1618 1617 RTIT_STATUS_STOPPED)) && ··· 1840 1839 for_each_online_cpu(cpu) { 1841 1840 u64 ctl; 1842 1841 1843 1843 - ret = rdmsrl_safe_on_cpu(cpu, MSR_IA32_RTIT_CTL, &ctl); 1842 1842 + ret = rdmsrq_safe_on_cpu(cpu, MSR_IA32_RTIT_CTL, &ctl); 1844 1843 if (!ret && (ctl & RTIT_CTL_TRACEEN)) 1845 1844 prior_warn++; 1846 1845 }

+2 -1

arch/x86/events/intel/uncore.c

reviewed

··· 3 3 4 4 #include <asm/cpu_device_id.h> 5 5 #include <asm/intel-family.h> 6 6 + #include <asm/msr.h> 6 7 #include "uncore.h" 7 8 #include "uncore_discovery.h" 8 9 ··· 151 150 { 152 151 u64 count; 153 152 154 154 - rdmsrl(event->hw.event_base, count); 153 153 + rdmsrq(event->hw.event_base, count); 155 154 156 155 return count; 157 156 }

+6 -5

arch/x86/events/intel/uncore_discovery.c

reviewed

··· 5 5 */ 6 6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 7 7 8 8 + #include <asm/msr.h> 8 9 #include "uncore.h" 9 10 #include "uncore_discovery.h" 10 11 ··· 442 441 443 442 void intel_generic_uncore_msr_init_box(struct intel_uncore_box *box) 444 443 { 445 445 - wrmsrl(intel_generic_uncore_box_ctl(box), GENERIC_PMON_BOX_CTL_INT); 444 444 + wrmsrq(intel_generic_uncore_box_ctl(box), GENERIC_PMON_BOX_CTL_INT); 446 445 } 447 446 448 447 void intel_generic_uncore_msr_disable_box(struct intel_uncore_box *box) 449 448 { 450 450 - wrmsrl(intel_generic_uncore_box_ctl(box), GENERIC_PMON_BOX_CTL_FRZ); 449 449 + wrmsrq(intel_generic_uncore_box_ctl(box), GENERIC_PMON_BOX_CTL_FRZ); 451 450 } 452 451 453 452 void intel_generic_uncore_msr_enable_box(struct intel_uncore_box *box) 454 453 { 455 455 - wrmsrl(intel_generic_uncore_box_ctl(box), 0); 454 454 + wrmsrq(intel_generic_uncore_box_ctl(box), 0); 456 455 } 457 456 458 457 static void intel_generic_uncore_msr_enable_event(struct intel_uncore_box *box, ··· 460 459 { 461 460 struct hw_perf_event *hwc = &event->hw; 462 461 463 463 - wrmsrl(hwc->config_base, hwc->config); 462 462 + wrmsrq(hwc->config_base, hwc->config); 464 463 } 465 464 466 465 static void intel_generic_uncore_msr_disable_event(struct intel_uncore_box *box, ··· 468 467 { 469 468 struct hw_perf_event *hwc = &event->hw; 470 469 471 471 - wrmsrl(hwc->config_base, 0); 470 470 + wrmsrq(hwc->config_base, 0); 472 471 } 473 472 474 473 static struct intel_uncore_ops generic_uncore_msr_ops = {

+36 -35

arch/x86/events/intel/uncore_nhmex.c

reviewed

··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 2 /* Nehalem-EX/Westmere-EX uncore support */ 3 3 #include <asm/cpu_device_id.h> 4 4 + #include <asm/msr.h> 4 5 #include "uncore.h" 5 6 6 7 /* NHM-EX event control */ ··· 201 200 202 201 static void nhmex_uncore_msr_init_box(struct intel_uncore_box *box) 203 202 { 204 204 - wrmsrl(NHMEX_U_MSR_PMON_GLOBAL_CTL, NHMEX_U_PMON_GLOBAL_EN_ALL); 203 203 + wrmsrq(NHMEX_U_MSR_PMON_GLOBAL_CTL, NHMEX_U_PMON_GLOBAL_EN_ALL); 205 204 } 206 205 207 206 static void nhmex_uncore_msr_exit_box(struct intel_uncore_box *box) 208 207 { 209 209 - wrmsrl(NHMEX_U_MSR_PMON_GLOBAL_CTL, 0); 208 208 + wrmsrq(NHMEX_U_MSR_PMON_GLOBAL_CTL, 0); 210 209 } 211 210 212 211 static void nhmex_uncore_msr_disable_box(struct intel_uncore_box *box) ··· 215 214 u64 config; 216 215 217 216 if (msr) { 218 218 - rdmsrl(msr, config); 217 217 + rdmsrq(msr, config); 219 218 config &= ~((1ULL << uncore_num_counters(box)) - 1); 220 219 /* WBox has a fixed counter */ 221 220 if (uncore_msr_fixed_ctl(box)) 222 221 config &= ~NHMEX_W_PMON_GLOBAL_FIXED_EN; 223 223 - wrmsrl(msr, config); 222 222 + wrmsrq(msr, config); 224 223 } 225 224 } 226 225 ··· 230 229 u64 config; 231 230 232 231 if (msr) { 233 233 - rdmsrl(msr, config); 232 232 + rdmsrq(msr, config); 234 233 config |= (1ULL << uncore_num_counters(box)) - 1; 235 234 /* WBox has a fixed counter */ 236 235 if (uncore_msr_fixed_ctl(box)) 237 236 config |= NHMEX_W_PMON_GLOBAL_FIXED_EN; 238 238 - wrmsrl(msr, config); 237 237 + wrmsrq(msr, config); 239 238 } 240 239 } 241 240 242 241 static void nhmex_uncore_msr_disable_event(struct intel_uncore_box *box, struct perf_event *event) 243 242 { 244 244 - wrmsrl(event->hw.config_base, 0); 243 243 + wrmsrq(event->hw.config_base, 0); 245 244 } 246 245 247 246 static void nhmex_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event) ··· 249 248 struct hw_perf_event *hwc = &event->hw; 250 249 251 250 if (hwc->idx == UNCORE_PMC_IDX_FIXED) 252 252 - wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0); 251 251 + wrmsrq(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0); 253 252 else if (box->pmu->type->event_mask & NHMEX_PMON_CTL_EN_BIT0) 254 254 - wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22); 253 253 + wrmsrq(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22); 255 254 else 256 256 - wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0); 255 255 + wrmsrq(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0); 257 256 } 258 257 259 258 #define NHMEX_UNCORE_OPS_COMMON_INIT() \ ··· 383 382 struct hw_perf_event_extra *reg2 = &hwc->branch_reg; 384 383 385 384 if (reg1->idx != EXTRA_REG_NONE) { 386 386 - wrmsrl(reg1->reg, reg1->config); 387 387 - wrmsrl(reg1->reg + 1, reg2->config); 385 385 + wrmsrq(reg1->reg, reg1->config); 386 386 + wrmsrq(reg1->reg + 1, reg2->config); 388 387 } 389 389 - wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0 | 388 388 + wrmsrq(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0 | 390 389 (hwc->config & NHMEX_B_PMON_CTL_EV_SEL_MASK)); 391 390 } 392 391 ··· 468 467 struct hw_perf_event_extra *reg2 = &hwc->branch_reg; 469 468 470 469 if (reg1->idx != EXTRA_REG_NONE) { 471 471 - wrmsrl(reg1->reg, 0); 472 472 - wrmsrl(reg1->reg + 1, reg1->config); 473 473 - wrmsrl(reg1->reg + 2, reg2->config); 474 474 - wrmsrl(reg1->reg, NHMEX_S_PMON_MM_CFG_EN); 470 470 + wrmsrq(reg1->reg, 0); 471 471 + wrmsrq(reg1->reg + 1, reg1->config); 472 472 + wrmsrq(reg1->reg + 2, reg2->config); 473 473 + wrmsrq(reg1->reg, NHMEX_S_PMON_MM_CFG_EN); 475 474 } 476 476 - wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22); 475 475 + wrmsrq(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22); 477 476 } 478 477 479 478 static struct attribute *nhmex_uncore_sbox_formats_attr[] = { ··· 843 842 844 843 idx = __BITS_VALUE(reg1->idx, 0, 8); 845 844 if (idx != 0xff) 846 846 - wrmsrl(__BITS_VALUE(reg1->reg, 0, 16), 845 845 + wrmsrq(__BITS_VALUE(reg1->reg, 0, 16), 847 846 nhmex_mbox_shared_reg_config(box, idx)); 848 847 idx = __BITS_VALUE(reg1->idx, 1, 8); 849 848 if (idx != 0xff) 850 850 - wrmsrl(__BITS_VALUE(reg1->reg, 1, 16), 849 849 + wrmsrq(__BITS_VALUE(reg1->reg, 1, 16), 851 850 nhmex_mbox_shared_reg_config(box, idx)); 852 851 853 852 if (reg2->idx != EXTRA_REG_NONE) { 854 854 - wrmsrl(reg2->reg, 0); 853 853 + wrmsrq(reg2->reg, 0); 855 854 if (reg2->config != ~0ULL) { 856 856 - wrmsrl(reg2->reg + 1, 855 855 + wrmsrq(reg2->reg + 1, 857 856 reg2->config & NHMEX_M_PMON_ADDR_MATCH_MASK); 858 858 - wrmsrl(reg2->reg + 2, NHMEX_M_PMON_ADDR_MASK_MASK & 857 857 + wrmsrq(reg2->reg + 2, NHMEX_M_PMON_ADDR_MASK_MASK & 859 858 (reg2->config >> NHMEX_M_PMON_ADDR_MASK_SHIFT)); 860 860 - wrmsrl(reg2->reg, NHMEX_M_PMON_MM_CFG_EN); 859 859 + wrmsrq(reg2->reg, NHMEX_M_PMON_MM_CFG_EN); 861 860 } 862 861 } 863 862 864 864 - wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0); 863 863 + wrmsrq(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0); 865 864 } 866 865 867 866 DEFINE_UNCORE_FORMAT_ATTR(count_mode, count_mode, "config:2-3"); ··· 1122 1121 1123 1122 switch (idx % 6) { 1124 1123 case 0: 1125 1125 - wrmsrl(NHMEX_R_MSR_PORTN_IPERF_CFG0(port), reg1->config); 1124 1124 + wrmsrq(NHMEX_R_MSR_PORTN_IPERF_CFG0(port), reg1->config); 1126 1125 break; 1127 1126 case 1: 1128 1128 - wrmsrl(NHMEX_R_MSR_PORTN_IPERF_CFG1(port), reg1->config); 1127 1127 + wrmsrq(NHMEX_R_MSR_PORTN_IPERF_CFG1(port), reg1->config); 1129 1128 break; 1130 1129 case 2: 1131 1130 case 3: 1132 1132 - wrmsrl(NHMEX_R_MSR_PORTN_QLX_CFG(port), 1131 1131 + wrmsrq(NHMEX_R_MSR_PORTN_QLX_CFG(port), 1133 1132 uncore_shared_reg_config(box, 2 + (idx / 6) * 5)); 1134 1133 break; 1135 1134 case 4: 1136 1136 - wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(port), 1135 1135 + wrmsrq(NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(port), 1137 1136 hwc->config >> 32); 1138 1138 - wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET1_MATCH(port), reg1->config); 1139 1139 - wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET1_MASK(port), reg2->config); 1137 1137 + wrmsrq(NHMEX_R_MSR_PORTN_XBR_SET1_MATCH(port), reg1->config); 1138 1138 + wrmsrq(NHMEX_R_MSR_PORTN_XBR_SET1_MASK(port), reg2->config); 1140 1139 break; 1141 1140 case 5: 1142 1142 - wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(port), 1141 1141 + wrmsrq(NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(port), 1143 1142 hwc->config >> 32); 1144 1144 - wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MATCH(port), reg1->config); 1145 1145 - wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MASK(port), reg2->config); 1143 1143 + wrmsrq(NHMEX_R_MSR_PORTN_XBR_SET2_MATCH(port), reg1->config); 1144 1144 + wrmsrq(NHMEX_R_MSR_PORTN_XBR_SET2_MASK(port), reg2->config); 1146 1145 break; 1147 1146 } 1148 1147 1149 1149 - wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0 | 1148 1148 + wrmsrq(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0 | 1150 1149 (hwc->config & NHMEX_R_PMON_CTL_EV_SEL_MASK)); 1151 1150 } 1152 1151

+22 -21

arch/x86/events/intel/uncore_snb.c

reviewed

··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 2 /* Nehalem/SandBridge/Haswell/Broadwell/Skylake uncore support */ 3 3 + #include <asm/msr.h> 3 4 #include "uncore.h" 4 5 #include "uncore_discovery.h" 5 6 ··· 261 260 struct hw_perf_event *hwc = &event->hw; 262 261 263 262 if (hwc->idx < UNCORE_PMC_IDX_FIXED) 264 264 - wrmsrl(hwc->config_base, hwc->config | SNB_UNC_CTL_EN); 263 263 + wrmsrq(hwc->config_base, hwc->config | SNB_UNC_CTL_EN); 265 264 else 266 266 - wrmsrl(hwc->config_base, SNB_UNC_CTL_EN); 265 265 + wrmsrq(hwc->config_base, SNB_UNC_CTL_EN); 267 266 } 268 267 269 268 static void snb_uncore_msr_disable_event(struct intel_uncore_box *box, struct perf_event *event) 270 269 { 271 271 - wrmsrl(event->hw.config_base, 0); 270 270 + wrmsrq(event->hw.config_base, 0); 272 271 } 273 272 274 273 static void snb_uncore_msr_init_box(struct intel_uncore_box *box) 275 274 { 276 275 if (box->pmu->pmu_idx == 0) { 277 277 - wrmsrl(SNB_UNC_PERF_GLOBAL_CTL, 276 276 + wrmsrq(SNB_UNC_PERF_GLOBAL_CTL, 278 277 SNB_UNC_GLOBAL_CTL_EN | SNB_UNC_GLOBAL_CTL_CORE_ALL); 279 278 } 280 279 } 281 280 282 281 static void snb_uncore_msr_enable_box(struct intel_uncore_box *box) 283 282 { 284 284 - wrmsrl(SNB_UNC_PERF_GLOBAL_CTL, 283 283 + wrmsrq(SNB_UNC_PERF_GLOBAL_CTL, 285 284 SNB_UNC_GLOBAL_CTL_EN | SNB_UNC_GLOBAL_CTL_CORE_ALL); 286 285 } 287 286 288 287 static void snb_uncore_msr_exit_box(struct intel_uncore_box *box) 289 288 { 290 289 if (box->pmu->pmu_idx == 0) 291 291 - wrmsrl(SNB_UNC_PERF_GLOBAL_CTL, 0); 290 290 + wrmsrq(SNB_UNC_PERF_GLOBAL_CTL, 0); 292 291 } 293 292 294 293 static struct uncore_event_desc snb_uncore_events[] = { ··· 373 372 static void skl_uncore_msr_init_box(struct intel_uncore_box *box) 374 373 { 375 374 if (box->pmu->pmu_idx == 0) { 376 376 - wrmsrl(SKL_UNC_PERF_GLOBAL_CTL, 375 375 + wrmsrq(SKL_UNC_PERF_GLOBAL_CTL, 377 376 SNB_UNC_GLOBAL_CTL_EN | SKL_UNC_GLOBAL_CTL_CORE_ALL); 378 377 } 379 378 ··· 384 383 385 384 static void skl_uncore_msr_enable_box(struct intel_uncore_box *box) 386 385 { 387 387 - wrmsrl(SKL_UNC_PERF_GLOBAL_CTL, 386 386 + wrmsrq(SKL_UNC_PERF_GLOBAL_CTL, 388 387 SNB_UNC_GLOBAL_CTL_EN | SKL_UNC_GLOBAL_CTL_CORE_ALL); 389 388 } 390 389 391 390 static void skl_uncore_msr_exit_box(struct intel_uncore_box *box) 392 391 { 393 392 if (box->pmu->pmu_idx == 0) 394 394 - wrmsrl(SKL_UNC_PERF_GLOBAL_CTL, 0); 393 393 + wrmsrq(SKL_UNC_PERF_GLOBAL_CTL, 0); 395 394 } 396 395 397 396 static struct intel_uncore_ops skl_uncore_msr_ops = { ··· 505 504 { 506 505 u64 num_boxes; 507 506 508 508 - rdmsrl(ICL_UNC_CBO_CONFIG, num_boxes); 507 507 + rdmsrq(ICL_UNC_CBO_CONFIG, num_boxes); 509 508 510 509 return num_boxes & ICL_UNC_NUM_CBO_MASK; 511 510 } ··· 526 525 static void rkl_uncore_msr_init_box(struct intel_uncore_box *box) 527 526 { 528 527 if (box->pmu->pmu_idx == 0) 529 529 - wrmsrl(SKL_UNC_PERF_GLOBAL_CTL, SNB_UNC_GLOBAL_CTL_EN); 528 528 + wrmsrq(SKL_UNC_PERF_GLOBAL_CTL, SNB_UNC_GLOBAL_CTL_EN); 530 529 } 531 530 532 531 void tgl_uncore_cpu_init(void) ··· 542 541 static void adl_uncore_msr_init_box(struct intel_uncore_box *box) 543 542 { 544 543 if (box->pmu->pmu_idx == 0) 545 545 - wrmsrl(ADL_UNC_PERF_GLOBAL_CTL, SNB_UNC_GLOBAL_CTL_EN); 544 544 + wrmsrq(ADL_UNC_PERF_GLOBAL_CTL, SNB_UNC_GLOBAL_CTL_EN); 546 545 } 547 546 548 547 static void adl_uncore_msr_enable_box(struct intel_uncore_box *box) 549 548 { 550 550 - wrmsrl(ADL_UNC_PERF_GLOBAL_CTL, SNB_UNC_GLOBAL_CTL_EN); 549 549 + wrmsrq(ADL_UNC_PERF_GLOBAL_CTL, SNB_UNC_GLOBAL_CTL_EN); 551 550 } 552 551 553 552 static void adl_uncore_msr_disable_box(struct intel_uncore_box *box) 554 553 { 555 554 if (box->pmu->pmu_idx == 0) 556 556 - wrmsrl(ADL_UNC_PERF_GLOBAL_CTL, 0); 555 555 + wrmsrq(ADL_UNC_PERF_GLOBAL_CTL, 0); 557 556 } 558 557 559 558 static void adl_uncore_msr_exit_box(struct intel_uncore_box *box) 560 559 { 561 560 if (box->pmu->pmu_idx == 0) 562 562 - wrmsrl(ADL_UNC_PERF_GLOBAL_CTL, 0); 561 561 + wrmsrq(ADL_UNC_PERF_GLOBAL_CTL, 0); 563 562 } 564 563 565 564 static struct intel_uncore_ops adl_uncore_msr_ops = { ··· 692 691 693 692 static void mtl_uncore_msr_init_box(struct intel_uncore_box *box) 694 693 { 695 695 - wrmsrl(uncore_msr_box_ctl(box), SNB_UNC_GLOBAL_CTL_EN); 694 694 + wrmsrq(uncore_msr_box_ctl(box), SNB_UNC_GLOBAL_CTL_EN); 696 695 } 697 696 698 697 static struct intel_uncore_ops mtl_uncore_msr_ops = { ··· 759 758 static void lnl_uncore_msr_init_box(struct intel_uncore_box *box) 760 759 { 761 760 if (box->pmu->pmu_idx == 0) 762 762 - wrmsrl(LNL_UNC_MSR_GLOBAL_CTL, SNB_UNC_GLOBAL_CTL_EN); 761 761 + wrmsrq(LNL_UNC_MSR_GLOBAL_CTL, SNB_UNC_GLOBAL_CTL_EN); 763 762 } 764 763 765 764 static struct intel_uncore_ops lnl_uncore_msr_ops = { ··· 1307 1306 /* Nehalem uncore support */ 1308 1307 static void nhm_uncore_msr_disable_box(struct intel_uncore_box *box) 1309 1308 { 1310 1310 - wrmsrl(NHM_UNC_PERF_GLOBAL_CTL, 0); 1309 1309 + wrmsrq(NHM_UNC_PERF_GLOBAL_CTL, 0); 1311 1310 } 1312 1311 1313 1312 static void nhm_uncore_msr_enable_box(struct intel_uncore_box *box) 1314 1313 { 1315 1315 - wrmsrl(NHM_UNC_PERF_GLOBAL_CTL, NHM_UNC_GLOBAL_CTL_EN_PC_ALL | NHM_UNC_GLOBAL_CTL_EN_FC); 1314 1314 + wrmsrq(NHM_UNC_PERF_GLOBAL_CTL, NHM_UNC_GLOBAL_CTL_EN_PC_ALL | NHM_UNC_GLOBAL_CTL_EN_FC); 1316 1315 } 1317 1316 1318 1317 static void nhm_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event) ··· 1320 1319 struct hw_perf_event *hwc = &event->hw; 1321 1320 1322 1321 if (hwc->idx < UNCORE_PMC_IDX_FIXED) 1323 1323 - wrmsrl(hwc->config_base, hwc->config | SNB_UNC_CTL_EN); 1322 1322 + wrmsrq(hwc->config_base, hwc->config | SNB_UNC_CTL_EN); 1324 1323 else 1325 1325 - wrmsrl(hwc->config_base, NHM_UNC_FIXED_CTR_CTL_EN); 1324 1324 + wrmsrq(hwc->config_base, NHM_UNC_FIXED_CTR_CTL_EN); 1326 1325 } 1327 1326 1328 1327 static struct attribute *nhm_uncore_formats_attr[] = {

+26 -25

arch/x86/events/intel/uncore_snbep.c

reviewed

··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 2 /* SandyBridge-EP/IvyTown uncore support */ 3 3 #include <asm/cpu_device_id.h> 4 4 + #include <asm/msr.h> 4 5 #include "uncore.h" 5 6 #include "uncore_discovery.h" 6 7 ··· 619 618 620 619 msr = uncore_msr_box_ctl(box); 621 620 if (msr) { 622 622 - rdmsrl(msr, config); 621 621 + rdmsrq(msr, config); 623 622 config |= SNBEP_PMON_BOX_CTL_FRZ; 624 624 - wrmsrl(msr, config); 623 623 + wrmsrq(msr, config); 625 624 } 626 625 } 627 626 ··· 632 631 633 632 msr = uncore_msr_box_ctl(box); 634 633 if (msr) { 635 635 - rdmsrl(msr, config); 634 634 + rdmsrq(msr, config); 636 635 config &= ~SNBEP_PMON_BOX_CTL_FRZ; 637 637 - wrmsrl(msr, config); 636 636 + wrmsrq(msr, config); 638 637 } 639 638 } 640 639 ··· 644 643 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; 645 644 646 645 if (reg1->idx != EXTRA_REG_NONE) 647 647 - wrmsrl(reg1->reg, uncore_shared_reg_config(box, 0)); 646 646 + wrmsrq(reg1->reg, uncore_shared_reg_config(box, 0)); 648 647 649 649 - wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); 648 648 + wrmsrq(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); 650 649 } 651 650 652 651 static void snbep_uncore_msr_disable_event(struct intel_uncore_box *box, ··· 654 653 { 655 654 struct hw_perf_event *hwc = &event->hw; 656 655 657 657 - wrmsrl(hwc->config_base, hwc->config); 656 656 + wrmsrq(hwc->config_base, hwc->config); 658 657 } 659 658 660 659 static void snbep_uncore_msr_init_box(struct intel_uncore_box *box) ··· 662 661 unsigned msr = uncore_msr_box_ctl(box); 663 662 664 663 if (msr) 665 665 - wrmsrl(msr, SNBEP_PMON_BOX_CTL_INT); 664 664 + wrmsrq(msr, SNBEP_PMON_BOX_CTL_INT); 666 665 } 667 666 668 667 static struct attribute *snbep_uncore_formats_attr[] = { ··· 1533 1532 { 1534 1533 unsigned msr = uncore_msr_box_ctl(box); 1535 1534 if (msr) 1536 1536 - wrmsrl(msr, IVBEP_PMON_BOX_CTL_INT); 1535 1535 + wrmsrq(msr, IVBEP_PMON_BOX_CTL_INT); 1537 1536 } 1538 1537 1539 1538 static void ivbep_uncore_pci_init_box(struct intel_uncore_box *box) ··· 1784 1783 1785 1784 if (reg1->idx != EXTRA_REG_NONE) { 1786 1785 u64 filter = uncore_shared_reg_config(box, 0); 1787 1787 - wrmsrl(reg1->reg, filter & 0xffffffff); 1788 1788 - wrmsrl(reg1->reg + 6, filter >> 32); 1786 1786 + wrmsrq(reg1->reg, filter & 0xffffffff); 1787 1787 + wrmsrq(reg1->reg + 6, filter >> 32); 1789 1788 } 1790 1789 1791 1791 - wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); 1790 1790 + wrmsrq(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); 1792 1791 } 1793 1792 1794 1793 static struct intel_uncore_ops ivbep_uncore_cbox_ops = { ··· 2768 2767 2769 2768 if (reg1->idx != EXTRA_REG_NONE) { 2770 2769 u64 filter = uncore_shared_reg_config(box, 0); 2771 2771 - wrmsrl(reg1->reg, filter & 0xffffffff); 2772 2772 - wrmsrl(reg1->reg + 1, filter >> 32); 2770 2770 + wrmsrq(reg1->reg, filter & 0xffffffff); 2771 2771 + wrmsrq(reg1->reg + 1, filter >> 32); 2773 2772 } 2774 2773 2775 2775 - wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); 2774 2774 + wrmsrq(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); 2776 2775 } 2777 2776 2778 2777 static struct intel_uncore_ops hswep_uncore_cbox_ops = { ··· 2817 2816 2818 2817 for_each_set_bit(i, (unsigned long *)&init, 64) { 2819 2818 flags |= (1ULL << i); 2820 2820 - wrmsrl(msr, flags); 2819 2819 + wrmsrq(msr, flags); 2821 2820 } 2822 2821 } 2823 2822 } ··· 3709 3708 { 3710 3709 struct hw_perf_event *hwc = &event->hw; 3711 3710 3712 3712 - wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); 3711 3711 + wrmsrq(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); 3713 3712 } 3714 3713 3715 3714 static struct intel_uncore_ops skx_uncore_iio_ops = { ··· 3766 3765 { 3767 3766 u64 msr_value; 3768 3767 3769 3769 - if (rdmsrl_on_cpu(cpu, SKX_MSR_CPU_BUS_NUMBER, &msr_value) || 3768 3768 + if (rdmsrq_on_cpu(cpu, SKX_MSR_CPU_BUS_NUMBER, &msr_value) || 3770 3769 !(msr_value & SKX_MSR_CPU_BUS_VALID_BIT)) 3771 3770 return -ENXIO; 3772 3771 ··· 4656 4655 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; 4657 4656 4658 4657 if (reg1->idx != EXTRA_REG_NONE) 4659 4659 - wrmsrl(reg1->reg, reg1->config); 4658 4658 + wrmsrq(reg1->reg, reg1->config); 4660 4659 4661 4661 - wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); 4660 4660 + wrmsrq(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); 4662 4661 } 4663 4662 4664 4663 static struct intel_uncore_ops snr_uncore_chabox_ops = { ··· 5883 5882 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; 5884 5883 5885 5884 if (reg1->idx != EXTRA_REG_NONE) 5886 5886 - wrmsrl(reg1->reg, reg1->config); 5885 5885 + wrmsrq(reg1->reg, reg1->config); 5887 5886 5888 5888 - wrmsrl(hwc->config_base, hwc->config); 5887 5887 + wrmsrq(hwc->config_base, hwc->config); 5889 5888 } 5890 5889 5891 5890 static void spr_uncore_msr_disable_event(struct intel_uncore_box *box, ··· 5895 5894 struct hw_perf_event_extra *reg1 = &hwc->extra_reg; 5896 5895 5897 5896 if (reg1->idx != EXTRA_REG_NONE) 5898 5898 - wrmsrl(reg1->reg, 0); 5897 5897 + wrmsrq(reg1->reg, 0); 5899 5898 5900 5900 - wrmsrl(hwc->config_base, 0); 5899 5899 + wrmsrq(hwc->config_base, 0); 5901 5900 } 5902 5901 5903 5902 static int spr_cha_hw_config(struct intel_uncore_box *box, struct perf_event *event) ··· 6486 6485 * of UNCORE_SPR_CHA) is incorrect on some SPR variants because of a 6487 6486 * firmware bug. Using the value from SPR_MSR_UNC_CBO_CONFIG to replace it. 6488 6487 */ 6489 6489 - rdmsrl(SPR_MSR_UNC_CBO_CONFIG, num_cbo); 6488 6488 + rdmsrq(SPR_MSR_UNC_CBO_CONFIG, num_cbo); 6490 6489 /* 6491 6490 * The MSR doesn't work on the EMR XCC, but the firmware bug doesn't impact 6492 6491 * the EMR XCC. Don't let the value from the MSR replace the existing value.

+3 -1

arch/x86/events/msr.c

reviewed

··· 3 3 #include <linux/sysfs.h> 4 4 #include <linux/nospec.h> 5 5 #include <asm/cpu_device_id.h> 6 6 + #include <asm/msr.h> 7 7 + 6 8 #include "probe.h" 7 9 8 10 enum perf_msr_id { ··· 233 231 u64 now; 234 232 235 233 if (event->hw.event_base) 236 236 - rdmsrl(event->hw.event_base, now); 234 234 + rdmsrq(event->hw.event_base, now); 237 235 else 238 236 now = rdtsc_ordered(); 239 237

+14 -13

arch/x86/events/perf_event.h

reviewed

··· 17 17 #include <asm/fpu/xstate.h> 18 18 #include <asm/intel_ds.h> 19 19 #include <asm/cpu.h> 20 20 + #include <asm/msr.h> 20 21 21 22 /* To enable MSR tracing please use the generic trace points. */ 22 23 ··· 1206 1205 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask); 1207 1206 1208 1207 if (hwc->extra_reg.reg) 1209 1209 - wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config); 1208 1208 + wrmsrq(hwc->extra_reg.reg, hwc->extra_reg.config); 1210 1209 1211 1210 /* 1212 1211 * Add enabled Merge event on next counter 1213 1212 * if large increment event being enabled on this counter 1214 1213 */ 1215 1214 if (is_counter_pair(hwc)) 1216 1216 - wrmsrl(x86_pmu_config_addr(hwc->idx + 1), x86_pmu.perf_ctr_pair_en); 1215 1215 + wrmsrq(x86_pmu_config_addr(hwc->idx + 1), x86_pmu.perf_ctr_pair_en); 1217 1216 1218 1218 - wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask); 1217 1217 + wrmsrq(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask); 1219 1218 } 1220 1219 1221 1220 void x86_pmu_enable_all(int added); ··· 1231 1230 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask); 1232 1231 struct hw_perf_event *hwc = &event->hw; 1233 1232 1234 1234 - wrmsrl(hwc->config_base, hwc->config & ~disable_mask); 1233 1233 + wrmsrq(hwc->config_base, hwc->config & ~disable_mask); 1235 1234 1236 1235 if (is_counter_pair(hwc)) 1237 1237 - wrmsrl(x86_pmu_config_addr(hwc->idx + 1), 0); 1236 1236 + wrmsrq(x86_pmu_config_addr(hwc->idx + 1), 0); 1238 1237 } 1239 1238 1240 1239 void x86_pmu_enable_event(struct perf_event *event); ··· 1402 1401 { 1403 1402 u64 dbg_ctl, dbg_extn_cfg; 1404 1403 1405 1405 - rdmsrl(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg); 1406 1406 - wrmsrl(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg & ~DBG_EXTN_CFG_LBRV2EN); 1404 1404 + rdmsrq(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg); 1405 1405 + wrmsrq(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg & ~DBG_EXTN_CFG_LBRV2EN); 1407 1406 1408 1407 if (cpu_feature_enabled(X86_FEATURE_AMD_LBR_PMC_FREEZE)) { 1409 1409 - rdmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl); 1410 1410 - wrmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl & ~DEBUGCTLMSR_FREEZE_LBRS_ON_PMI); 1408 1408 + rdmsrq(MSR_IA32_DEBUGCTLMSR, dbg_ctl); 1409 1409 + wrmsrq(MSR_IA32_DEBUGCTLMSR, dbg_ctl & ~DEBUGCTLMSR_FREEZE_LBRS_ON_PMI); 1411 1410 } 1412 1411 } 1413 1412 ··· 1539 1538 1540 1539 static __always_inline void __intel_pmu_pebs_disable_all(void) 1541 1540 { 1542 1542 - wrmsrl(MSR_IA32_PEBS_ENABLE, 0); 1541 1541 + wrmsrq(MSR_IA32_PEBS_ENABLE, 0); 1543 1542 } 1544 1543 1545 1544 static __always_inline void __intel_pmu_arch_lbr_disable(void) 1546 1545 { 1547 1547 - wrmsrl(MSR_ARCH_LBR_CTL, 0); 1546 1546 + wrmsrq(MSR_ARCH_LBR_CTL, 0); 1548 1547 } 1549 1548 1550 1549 static __always_inline void __intel_pmu_lbr_disable(void) 1551 1550 { 1552 1551 u64 debugctl; 1553 1552 1554 1554 - rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 1553 1553 + rdmsrq(MSR_IA32_DEBUGCTLMSR, debugctl); 1555 1554 debugctl &= ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI); 1556 1556 - wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 1555 1555 + wrmsrq(MSR_IA32_DEBUGCTLMSR, debugctl); 1557 1556 } 1558 1557 1559 1558 int intel_pmu_save_and_restart(struct perf_event *event);

+3 -1

arch/x86/events/probe.c

reviewed

··· 2 2 #include <linux/export.h> 3 3 #include <linux/types.h> 4 4 #include <linux/bits.h> 5 5 + 6 6 + #include <asm/msr.h> 5 7 #include "probe.h" 6 8 7 9 static umode_t ··· 45 43 if (msr[bit].test && !msr[bit].test(bit, data)) 46 44 continue; 47 45 /* Virt sucks; you cannot tell if a R/O MSR is present :/ */ 48 48 - if (rdmsrl_safe(msr[bit].msr, &val)) 46 46 + if (rdmsrq_safe(msr[bit].msr, &val)) 49 47 continue; 50 48 51 49 mask = msr[bit].mask;

+5 -4

arch/x86/events/rapl.c

reviewed

··· 65 65 #include <linux/nospec.h> 66 66 #include <asm/cpu_device_id.h> 67 67 #include <asm/intel-family.h> 68 68 + #include <asm/msr.h> 68 69 #include "perf_event.h" 69 70 #include "probe.h" 70 71 ··· 193 192 static inline u64 rapl_read_counter(struct perf_event *event) 194 193 { 195 194 u64 raw; 196 196 - rdmsrl(event->hw.event_base, raw); 195 195 + rdmsrq(event->hw.event_base, raw); 197 196 return raw; 198 197 } 199 198 ··· 222 221 223 222 prev_raw_count = local64_read(&hwc->prev_count); 224 223 do { 225 225 - rdmsrl(event->hw.event_base, new_raw_count); 224 224 + rdmsrq(event->hw.event_base, new_raw_count); 226 225 } while (!local64_try_cmpxchg(&hwc->prev_count, 227 226 &prev_raw_count, new_raw_count)); 228 227 ··· 611 610 u64 msr_rapl_power_unit_bits; 612 611 int i; 613 612 614 614 - /* protect rdmsrl() to handle virtualization */ 615 615 - if (rdmsrl_safe(rapl_model->msr_power_unit, &msr_rapl_power_unit_bits)) 613 613 + /* protect rdmsrq() to handle virtualization */ 614 614 + if (rdmsrq_safe(rapl_model->msr_power_unit, &msr_rapl_power_unit_bits)) 616 615 return -1; 617 616 for (i = 0; i < NR_RAPL_PKG_DOMAINS; i++) 618 617 rapl_pkg_hw_unit[i] = (msr_rapl_power_unit_bits >> 8) & 0x1FULL;

+1

arch/x86/events/utils.c

reviewed

··· 2 2 #include <asm/insn.h> 3 3 #include <linux/mm.h> 4 4 5 5 + #include <asm/msr.h> 5 6 #include "perf_event.h" 6 7 7 8 static int decode_branch_type(struct insn *insn)

+9 -8

arch/x86/events/zhaoxin/core.c

reviewed

··· 15 15 #include <asm/cpufeature.h> 16 16 #include <asm/hardirq.h> 17 17 #include <asm/apic.h> 18 18 + #include <asm/msr.h> 18 19 19 20 #include "../perf_event.h" 20 21 ··· 255 254 256 255 static void zhaoxin_pmu_disable_all(void) 257 256 { 258 258 - wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); 257 257 + wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0); 259 258 } 260 259 261 260 static void zhaoxin_pmu_enable_all(int added) 262 261 { 263 263 - wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl); 262 262 + wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl); 264 263 } 265 264 266 265 static inline u64 zhaoxin_pmu_get_status(void) 267 266 { 268 267 u64 status; 269 268 270 270 - rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); 269 269 + rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS, status); 271 270 272 271 return status; 273 272 } 274 273 275 274 static inline void zhaoxin_pmu_ack_status(u64 ack) 276 275 { 277 277 - wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); 276 276 + wrmsrq(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); 278 277 } 279 278 280 279 static inline void zxc_pmu_ack_status(u64 ack) ··· 294 293 295 294 mask = 0xfULL << (idx * 4); 296 295 297 297 - rdmsrl(hwc->config_base, ctrl_val); 296 296 + rdmsrq(hwc->config_base, ctrl_val); 298 297 ctrl_val &= ~mask; 299 299 - wrmsrl(hwc->config_base, ctrl_val); 298 298 + wrmsrq(hwc->config_base, ctrl_val); 300 299 } 301 300 302 301 static void zhaoxin_pmu_disable_event(struct perf_event *event) ··· 330 329 bits <<= (idx * 4); 331 330 mask = 0xfULL << (idx * 4); 332 331 333 333 - rdmsrl(hwc->config_base, ctrl_val); 332 332 + rdmsrq(hwc->config_base, ctrl_val); 334 333 ctrl_val &= ~mask; 335 334 ctrl_val |= bits; 336 336 - wrmsrl(hwc->config_base, ctrl_val); 335 335 + wrmsrq(hwc->config_base, ctrl_val); 337 336 } 338 337 339 338 static void zhaoxin_pmu_enable_event(struct perf_event *event)

+6 -5

arch/x86/hyperv/hv_apic.c

reviewed

··· 28 28 #include <asm/hypervisor.h> 29 29 #include <asm/mshyperv.h> 30 30 #include <asm/apic.h> 31 31 + #include <asm/msr.h> 31 32 32 33 #include <asm/trace/hyperv.h> 33 34 ··· 38 37 { 39 38 u64 reg_val; 40 39 41 41 - rdmsrl(HV_X64_MSR_ICR, reg_val); 40 40 + rdmsrq(HV_X64_MSR_ICR, reg_val); 42 41 return reg_val; 43 42 } 44 43 ··· 50 49 reg_val = reg_val << 32; 51 50 reg_val |= low; 52 51 53 53 - wrmsrl(HV_X64_MSR_ICR, reg_val); 52 52 + wrmsrq(HV_X64_MSR_ICR, reg_val); 54 53 } 55 54 56 55 static u32 hv_apic_read(u32 reg) ··· 76 75 { 77 76 switch (reg) { 78 77 case APIC_EOI: 79 79 - wrmsr(HV_X64_MSR_EOI, val, 0); 78 78 + wrmsrq(HV_X64_MSR_EOI, val); 80 79 break; 81 80 case APIC_TASKPRI: 82 82 - wrmsr(HV_X64_MSR_TPR, val, 0); 81 81 + wrmsrq(HV_X64_MSR_TPR, val); 83 82 break; 84 83 default: 85 84 native_apic_mem_write(reg, val); ··· 93 92 if (hvp && (xchg(&hvp->apic_assist, 0) & 0x1)) 94 93 return; 95 94 96 96 - wrmsr(HV_X64_MSR_EOI, APIC_EOI_ACK, 0); 95 95 + wrmsrq(HV_X64_MSR_EOI, APIC_EOI_ACK); 97 96 } 98 97 99 98 static bool cpu_is_self(int cpu)

+34 -33

arch/x86/hyperv/hv_init.c

reviewed

··· 21 21 #include <asm/hypervisor.h> 22 22 #include <hyperv/hvhdk.h> 23 23 #include <asm/mshyperv.h> 24 24 + #include <asm/msr.h> 24 25 #include <asm/idtentry.h> 25 26 #include <asm/set_memory.h> 26 27 #include <linux/kexec.h> ··· 63 62 * returned by MSR_AMD64_SEV_ES_GHCB is above shared 64 63 * memory boundary and map it here. 65 64 */ 66 66 - rdmsrl(MSR_AMD64_SEV_ES_GHCB, ghcb_gpa); 65 65 + rdmsrq(MSR_AMD64_SEV_ES_GHCB, ghcb_gpa); 67 66 68 67 /* Mask out vTOM bit. ioremap_cache() maps decrypted */ 69 68 ghcb_gpa &= ~ms_hyperv.shared_gpa_boundary; ··· 96 95 * For root partition we get the hypervisor provided VP assist 97 96 * page, instead of allocating a new page. 98 97 */ 99 99 - rdmsrl(HV_X64_MSR_VP_ASSIST_PAGE, msr.as_uint64); 98 98 + rdmsrq(HV_X64_MSR_VP_ASSIST_PAGE, msr.as_uint64); 100 99 *hvp = memremap(msr.pfn << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT, 101 100 PAGE_SIZE, MEMREMAP_WB); 102 101 } else { ··· 129 128 } 130 129 if (!WARN_ON(!(*hvp))) { 131 130 msr.enable = 1; 132 132 - wrmsrl(HV_X64_MSR_VP_ASSIST_PAGE, msr.as_uint64); 131 131 + wrmsrq(HV_X64_MSR_VP_ASSIST_PAGE, msr.as_uint64); 133 132 } 134 133 135 134 return hyperv_init_ghcb(); ··· 141 140 { 142 141 struct hv_tsc_emulation_status emu_status; 143 142 144 144 - rdmsrl(HV_X64_MSR_TSC_EMULATION_STATUS, *(u64 *)&emu_status); 143 143 + rdmsrq(HV_X64_MSR_TSC_EMULATION_STATUS, *(u64 *)&emu_status); 145 144 146 145 /* Don't issue the callback if TSC accesses are not emulated */ 147 146 if (hv_reenlightenment_cb && emu_status.inprogress) ··· 154 153 u64 freq; 155 154 struct hv_tsc_emulation_status emu_status; 156 155 157 157 - rdmsrl(HV_X64_MSR_TSC_EMULATION_STATUS, *(u64 *)&emu_status); 156 156 + rdmsrq(HV_X64_MSR_TSC_EMULATION_STATUS, *(u64 *)&emu_status); 158 157 emu_status.inprogress = 0; 159 159 - wrmsrl(HV_X64_MSR_TSC_EMULATION_STATUS, *(u64 *)&emu_status); 158 158 + wrmsrq(HV_X64_MSR_TSC_EMULATION_STATUS, *(u64 *)&emu_status); 160 159 161 161 - rdmsrl(HV_X64_MSR_TSC_FREQUENCY, freq); 160 160 + rdmsrq(HV_X64_MSR_TSC_FREQUENCY, freq); 162 161 tsc_khz = div64_u64(freq, 1000); 163 162 } 164 163 EXPORT_SYMBOL_GPL(hyperv_stop_tsc_emulation); ··· 204 203 205 204 re_ctrl.target_vp = hv_vp_index[get_cpu()]; 206 205 207 207 - wrmsrl(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *((u64 *)&re_ctrl)); 208 208 - wrmsrl(HV_X64_MSR_TSC_EMULATION_CONTROL, *((u64 *)&emu_ctrl)); 206 206 + wrmsrq(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *((u64 *)&re_ctrl)); 207 207 + wrmsrq(HV_X64_MSR_TSC_EMULATION_CONTROL, *((u64 *)&emu_ctrl)); 209 208 210 209 put_cpu(); 211 210 } ··· 218 217 if (!hv_reenlightenment_available()) 219 218 return; 220 219 221 221 - rdmsrl(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *(u64 *)&re_ctrl); 220 220 + rdmsrq(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *(u64 *)&re_ctrl); 222 221 re_ctrl.enabled = 0; 223 223 - wrmsrl(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *(u64 *)&re_ctrl); 222 222 + wrmsrq(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *(u64 *)&re_ctrl); 224 223 225 224 hv_reenlightenment_cb = NULL; 226 225 } ··· 252 251 */ 253 252 memunmap(hv_vp_assist_page[cpu]); 254 253 hv_vp_assist_page[cpu] = NULL; 255 255 - rdmsrl(HV_X64_MSR_VP_ASSIST_PAGE, msr.as_uint64); 254 254 + rdmsrq(HV_X64_MSR_VP_ASSIST_PAGE, msr.as_uint64); 256 255 msr.enable = 0; 257 256 } 258 258 - wrmsrl(HV_X64_MSR_VP_ASSIST_PAGE, msr.as_uint64); 257 257 + wrmsrq(HV_X64_MSR_VP_ASSIST_PAGE, msr.as_uint64); 259 258 } 260 259 261 260 if (hv_reenlightenment_cb == NULL) 262 261 return 0; 263 262 264 264 - rdmsrl(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *((u64 *)&re_ctrl)); 263 263 + rdmsrq(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *((u64 *)&re_ctrl)); 265 264 if (re_ctrl.target_vp == hv_vp_index[cpu]) { 266 265 /* 267 266 * Reassign reenlightenment notifications to some other online ··· 275 274 else 276 275 re_ctrl.enabled = 0; 277 276 278 278 - wrmsrl(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *((u64 *)&re_ctrl)); 277 277 + wrmsrq(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *((u64 *)&re_ctrl)); 279 278 } 280 279 281 280 return 0; ··· 332 331 hv_hypercall_pg = NULL; 333 332 334 333 /* Disable the hypercall page in the hypervisor */ 335 335 - rdmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); 334 334 + rdmsrq(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); 336 335 hypercall_msr.enable = 0; 337 337 - wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); 336 336 + wrmsrq(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); 338 337 339 338 ret = hv_cpu_die(0); 340 339 return ret; ··· 349 348 WARN_ON(ret); 350 349 351 350 /* Re-enable the hypercall page */ 352 352 - rdmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); 351 351 + rdmsrq(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); 353 352 hypercall_msr.enable = 1; 354 353 hypercall_msr.guest_physical_address = 355 354 vmalloc_to_pfn(hv_hypercall_pg_saved); 356 356 - wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); 355 355 + wrmsrq(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); 357 356 358 357 hv_hypercall_pg = hv_hypercall_pg_saved; 359 358 hv_hypercall_pg_saved = NULL; ··· 500 499 * in such a VM and is only used in such a VM. 501 500 */ 502 501 guest_id = hv_generate_guest_id(LINUX_VERSION_CODE); 503 503 - wrmsrl(HV_X64_MSR_GUEST_OS_ID, guest_id); 502 502 + wrmsrq(HV_X64_MSR_GUEST_OS_ID, guest_id); 504 503 505 504 /* With the paravisor, the VM must also write the ID via GHCB/GHCI */ 506 505 hv_ivm_msr_write(HV_X64_MSR_GUEST_OS_ID, guest_id); ··· 516 515 if (hv_hypercall_pg == NULL) 517 516 goto clean_guest_os_id; 518 517 519 519 - rdmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); 518 518 + rdmsrq(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); 520 519 hypercall_msr.enable = 1; 521 520 522 521 if (hv_root_partition()) { ··· 533 532 * so it is populated with code, then copy the code to an 534 533 * executable page. 535 534 */ 536 536 - wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); 535 535 + wrmsrq(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); 537 536 538 537 pg = vmalloc_to_page(hv_hypercall_pg); 539 538 src = memremap(hypercall_msr.guest_physical_address << PAGE_SHIFT, PAGE_SIZE, ··· 545 544 hv_remap_tsc_clocksource(); 546 545 } else { 547 546 hypercall_msr.guest_physical_address = vmalloc_to_pfn(hv_hypercall_pg); 548 548 - wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); 547 547 + wrmsrq(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); 549 548 } 550 549 551 550 skip_hypercall_pg_init: ··· 609 608 return; 610 609 611 610 clean_guest_os_id: 612 612 - wrmsrl(HV_X64_MSR_GUEST_OS_ID, 0); 611 611 + wrmsrq(HV_X64_MSR_GUEST_OS_ID, 0); 613 612 hv_ivm_msr_write(HV_X64_MSR_GUEST_OS_ID, 0); 614 613 cpuhp_remove_state(CPUHP_AP_HYPERV_ONLINE); 615 614 free_ghcb_page: ··· 630 629 union hv_reference_tsc_msr tsc_msr; 631 630 632 631 /* Reset our OS id */ 633 633 - wrmsrl(HV_X64_MSR_GUEST_OS_ID, 0); 632 632 + wrmsrq(HV_X64_MSR_GUEST_OS_ID, 0); 634 633 hv_ivm_msr_write(HV_X64_MSR_GUEST_OS_ID, 0); 635 634 636 635 /* ··· 668 667 return; 669 668 panic_reported = true; 670 669 671 671 - rdmsrl(HV_X64_MSR_GUEST_OS_ID, guest_id); 670 670 + rdmsrq(HV_X64_MSR_GUEST_OS_ID, guest_id); 672 671 673 673 - wrmsrl(HV_X64_MSR_CRASH_P0, err); 674 674 - wrmsrl(HV_X64_MSR_CRASH_P1, guest_id); 675 675 - wrmsrl(HV_X64_MSR_CRASH_P2, regs->ip); 676 676 - wrmsrl(HV_X64_MSR_CRASH_P3, regs->ax); 677 677 - wrmsrl(HV_X64_MSR_CRASH_P4, regs->sp); 672 672 + wrmsrq(HV_X64_MSR_CRASH_P0, err); 673 673 + wrmsrq(HV_X64_MSR_CRASH_P1, guest_id); 674 674 + wrmsrq(HV_X64_MSR_CRASH_P2, regs->ip); 675 675 + wrmsrq(HV_X64_MSR_CRASH_P3, regs->ax); 676 676 + wrmsrq(HV_X64_MSR_CRASH_P4, regs->sp); 678 677 679 678 /* 680 679 * Let Hyper-V know there is crash data available 681 680 */ 682 682 - wrmsrl(HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_CRASH_NOTIFY); 681 681 + wrmsrq(HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_CRASH_NOTIFY); 683 682 } 684 683 EXPORT_SYMBOL_GPL(hyperv_report_panic); 685 684 ··· 702 701 * that the hypercall page is setup 703 702 */ 704 703 hypercall_msr.as_uint64 = 0; 705 705 - rdmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); 704 704 + rdmsrq(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); 706 705 707 706 return hypercall_msr.enable; 708 707 }

+4 -3

arch/x86/hyperv/hv_spinlock.c

reviewed

··· 15 15 #include <asm/mshyperv.h> 16 16 #include <asm/paravirt.h> 17 17 #include <asm/apic.h> 18 18 + #include <asm/msr.h> 18 19 19 20 static bool hv_pvspin __initdata = true; 20 21 ··· 40 39 * To prevent a race against the unlock path it is required to 41 40 * disable interrupts before accessing the HV_X64_MSR_GUEST_IDLE 42 41 * MSR. Otherwise, if the IPI from hv_qlock_kick() arrives between 43 43 - * the lock value check and the rdmsrl() then the vCPU might be put 42 42 + * the lock value check and the rdmsrq() then the vCPU might be put 44 43 * into 'idle' state by the hypervisor and kept in that state for 45 44 * an unspecified amount of time. 46 45 */ 47 46 local_irq_save(flags); 48 47 /* 49 49 - * Only issue the rdmsrl() when the lock state has not changed. 48 48 + * Only issue the rdmsrq() when the lock state has not changed. 50 49 */ 51 50 if (READ_ONCE(*byte) == val) { 52 51 unsigned long msr_val; 53 52 54 54 - rdmsrl(HV_X64_MSR_GUEST_IDLE, msr_val); 53 53 + rdmsrq(HV_X64_MSR_GUEST_IDLE, msr_val); 55 54 56 55 (void)msr_val; 57 56 }

+3 -2

arch/x86/hyperv/hv_vtl.c

reviewed

··· 11 11 #include <asm/desc.h> 12 12 #include <asm/i8259.h> 13 13 #include <asm/mshyperv.h> 14 14 + #include <asm/msr.h> 14 15 #include <asm/realmode.h> 15 16 #include <asm/reboot.h> 16 17 #include <../kernel/smpboot.h> ··· 150 149 input->vp_context.rip = rip; 151 150 input->vp_context.rsp = rsp; 152 151 input->vp_context.rflags = 0x0000000000000002; 153 153 - input->vp_context.efer = __rdmsr(MSR_EFER); 152 152 + input->vp_context.efer = native_rdmsrq(MSR_EFER); 154 153 input->vp_context.cr0 = native_read_cr0(); 155 154 input->vp_context.cr3 = __native_read_cr3(); 156 155 input->vp_context.cr4 = native_read_cr4(); 157 157 - input->vp_context.msr_cr_pat = __rdmsr(MSR_IA32_CR_PAT); 156 156 + input->vp_context.msr_cr_pat = native_rdmsrq(MSR_IA32_CR_PAT); 158 157 input->vp_context.idtr.limit = idt_ptr.size; 159 158 input->vp_context.idtr.base = idt_ptr.address; 160 159 input->vp_context.gdtr.limit = gdt_ptr.size;

+3 -2

arch/x86/hyperv/ivm.c

reviewed

··· 22 22 #include <asm/realmode.h> 23 23 #include <asm/e820/api.h> 24 24 #include <asm/desc.h> 25 25 + #include <asm/msr.h> 25 26 #include <uapi/asm/vmx.h> 26 27 27 28 #ifdef CONFIG_AMD_MEM_ENCRYPT ··· 111 110 112 111 static inline u64 rd_ghcb_msr(void) 113 112 { 114 114 - return __rdmsr(MSR_AMD64_SEV_ES_GHCB); 113 113 + return native_rdmsrq(MSR_AMD64_SEV_ES_GHCB); 115 114 } 116 115 117 116 static inline void wr_ghcb_msr(u64 val) 118 117 { 119 119 - native_wrmsrl(MSR_AMD64_SEV_ES_GHCB, val); 118 118 + native_wrmsrq(MSR_AMD64_SEV_ES_GHCB, val); 120 119 } 121 120 122 121 static enum es_result hv_ghcb_hv_call(struct ghcb *ghcb, u64 exit_code,

+6 -6

arch/x86/include/asm/apic.h

reviewed

··· 120 120 { 121 121 u64 msr; 122 122 123 123 - if (rdmsrl_safe(MSR_IA32_APICBASE, &msr)) 123 123 + if (rdmsrq_safe(MSR_IA32_APICBASE, &msr)) 124 124 return false; 125 125 return msr & X2APIC_ENABLE; 126 126 } ··· 209 209 reg == APIC_LVR) 210 210 return; 211 211 212 212 - wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 212 212 + wrmsrq(APIC_BASE_MSR + (reg >> 4), v); 213 213 } 214 214 215 215 static inline void native_apic_msr_eoi(void) 216 216 { 217 217 - __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); 217 217 + native_wrmsrq(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK); 218 218 } 219 219 220 220 static inline u32 native_apic_msr_read(u32 reg) ··· 224 224 if (reg == APIC_DFR) 225 225 return -1; 226 226 227 227 - rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); 227 227 + rdmsrq(APIC_BASE_MSR + (reg >> 4), msr); 228 228 return (u32)msr; 229 229 } 230 230 231 231 static inline void native_x2apic_icr_write(u32 low, u32 id) 232 232 { 233 233 - wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 233 233 + wrmsrq(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 234 234 } 235 235 236 236 static inline u64 native_x2apic_icr_read(void) 237 237 { 238 238 unsigned long val; 239 239 240 240 - rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 240 240 + rdmsrq(APIC_BASE_MSR + (APIC_ICR >> 4), val); 241 241 return val; 242 242 } 243 243

+19

arch/x86/include/asm/asm.h

reviewed

··· 238 238 #define _ASM_EXTABLE_FAULT(from, to) \ 239 239 _ASM_EXTABLE_TYPE(from, to, EX_TYPE_FAULT) 240 240 241 241 + /* 242 242 + * Both i386 and x86_64 returns 64-bit values in edx:eax for certain 243 243 + * instructions, but GCC's "A" constraint has different meanings. 244 244 + * For i386, "A" means exactly edx:eax, while for x86_64 it 245 245 + * means rax *or* rdx. 246 246 + * 247 247 + * These helpers wrapping these semantic differences save one instruction 248 248 + * clearing the high half of 'low': 249 249 + */ 250 250 + #ifdef CONFIG_X86_64 251 251 + # define EAX_EDX_DECLARE_ARGS(val, low, high) unsigned long low, high 252 252 + # define EAX_EDX_VAL(val, low, high) ((low) | (high) << 32) 253 253 + # define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high) 254 254 + #else 255 255 + # define EAX_EDX_DECLARE_ARGS(val, low, high) u64 val 256 256 + # define EAX_EDX_VAL(val, low, high) (val) 257 257 + # define EAX_EDX_RET(val, low, high) "=A" (val) 258 258 + #endif 259 259 + 241 260 #endif /* __KERNEL__ */ 242 261 #endif /* _ASM_X86_ASM_H */

+2 -2

arch/x86/include/asm/debugreg.h

reviewed

··· 169 169 if (boot_cpu_data.x86 < 6) 170 170 return 0; 171 171 #endif 172 172 - rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 172 172 + rdmsrq(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 173 173 174 174 return debugctlmsr; 175 175 } ··· 180 180 if (boot_cpu_data.x86 < 6) 181 181 return; 182 182 #endif 183 183 - wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 183 183 + wrmsrq(MSR_IA32_DEBUGCTLMSR, debugctlmsr); 184 184 } 185 185 186 186 #endif /* _ASM_X86_DEBUGREG_H */

+1

arch/x86/include/asm/fred.h

reviewed

··· 9 9 #include <linux/const.h> 10 10 11 11 #include <asm/asm.h> 12 12 + #include <asm/msr.h> 12 13 #include <asm/trapnr.h> 13 14 14 15 /*

+2 -2

arch/x86/include/asm/fsgsbase.h

reviewed

··· 60 60 if (boot_cpu_has(X86_FEATURE_FSGSBASE)) 61 61 fsbase = rdfsbase(); 62 62 else 63 63 - rdmsrl(MSR_FS_BASE, fsbase); 63 63 + rdmsrq(MSR_FS_BASE, fsbase); 64 64 65 65 return fsbase; 66 66 } ··· 70 70 if (boot_cpu_has(X86_FEATURE_FSGSBASE)) 71 71 wrfsbase(fsbase); 72 72 else 73 73 - wrmsrl(MSR_FS_BASE, fsbase); 73 73 + wrmsrq(MSR_FS_BASE, fsbase); 74 74 } 75 75 76 76 extern unsigned long x86_gsbase_read_cpu_inactive(void);

+2 -1

arch/x86/include/asm/kvm_host.h

reviewed

··· 34 34 #include <asm/desc.h> 35 35 #include <asm/mtrr.h> 36 36 #include <asm/msr-index.h> 37 37 + #include <asm/msr.h> 37 38 #include <asm/asm.h> 38 39 #include <asm/irq_remapping.h> 39 40 #include <asm/kvm_page_track.h> ··· 2279 2278 { 2280 2279 u64 value; 2281 2280 2282 2282 - rdmsrl(msr, value); 2281 2281 + rdmsrq(msr, value); 2283 2282 return value; 2284 2283 } 2285 2284 #endif

+3 -1

arch/x86/include/asm/microcode.h

reviewed

··· 2 2 #ifndef _ASM_X86_MICROCODE_H 3 3 #define _ASM_X86_MICROCODE_H 4 4 5 5 + #include <asm/msr.h> 6 6 + 5 7 struct cpu_signature { 6 8 unsigned int sig; 7 9 unsigned int pf; ··· 65 63 { 66 64 u32 rev, dummy; 67 65 68 68 - native_wrmsrl(MSR_IA32_UCODE_REV, 0); 66 66 + native_wrmsrq(MSR_IA32_UCODE_REV, 0); 69 67 70 68 /* As documented in the SDM: Do a CPUID 1 here */ 71 69 native_cpuid_eax(1);

+2 -1

arch/x86/include/asm/mshyperv.h

reviewed

··· 8 8 #include <linux/io.h> 9 9 #include <asm/nospec-branch.h> 10 10 #include <asm/paravirt.h> 11 11 + #include <asm/msr.h> 11 12 #include <hyperv/hvhdk.h> 12 13 13 14 /* ··· 305 304 306 305 static __always_inline u64 hv_raw_get_msr(unsigned int reg) 307 306 { 308 308 - return __rdmsr(reg); 307 307 + return native_rdmsrq(reg); 309 308 } 310 309 311 310 #else /* CONFIG_HYPERV */

+6 -6

arch/x86/include/asm/msr-index.h

reviewed

··· 525 525 #define MSR_HWP_CAPABILITIES 0x00000771 526 526 #define MSR_HWP_REQUEST_PKG 0x00000772 527 527 #define MSR_HWP_INTERRUPT 0x00000773 528 528 - #define MSR_HWP_REQUEST 0x00000774 528 528 + #define MSR_HWP_REQUEST 0x00000774 529 529 #define MSR_HWP_STATUS 0x00000777 530 530 531 531 /* CPUID.6.EAX */ ··· 542 542 #define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff) 543 543 544 544 /* IA32_HWP_REQUEST */ 545 545 - #define HWP_MIN_PERF(x) (x & 0xff) 546 546 - #define HWP_MAX_PERF(x) ((x & 0xff) << 8) 545 545 + #define HWP_MIN_PERF(x) (x & 0xff) 546 546 + #define HWP_MAX_PERF(x) ((x & 0xff) << 8) 547 547 #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) 548 548 - #define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24) 548 548 + #define HWP_ENERGY_PERF_PREFERENCE(x) (((u64)x & 0xff) << 24) 549 549 #define HWP_EPP_PERFORMANCE 0x00 550 550 #define HWP_EPP_BALANCE_PERFORMANCE 0x80 551 551 #define HWP_EPP_BALANCE_POWERSAVE 0xC0 552 552 #define HWP_EPP_POWERSAVE 0xFF 553 553 - #define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32) 554 554 - #define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42) 553 553 + #define HWP_ACTIVITY_WINDOW(x) ((u64)(x & 0xff3) << 32) 554 554 + #define HWP_PACKAGE_CONTROL(x) ((u64)(x & 0x1) << 42) 555 555 556 556 /* IA32_HWP_STATUS */ 557 557 #define HWP_GUARANTEED_CHANGE(x) (x & 0x1)

+76 -143

arch/x86/include/asm/msr.h

reviewed

··· 12 12 #include <uapi/asm/msr.h> 13 13 #include <asm/shared/msr.h> 14 14 15 15 + #include <linux/types.h> 15 16 #include <linux/percpu.h> 16 17 17 18 struct msr_info { ··· 38 37 }; 39 38 40 39 /* 41 41 - * both i386 and x86_64 returns 64-bit value in edx:eax, but gcc's "A" 42 42 - * constraint has different meanings. For i386, "A" means exactly 43 43 - * edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead, 44 44 - * it means rax *or* rdx. 45 45 - */ 46 46 - #ifdef CONFIG_X86_64 47 47 - /* Using 64-bit values saves one instruction clearing the high half of low */ 48 48 - #define DECLARE_ARGS(val, low, high) unsigned long low, high 49 49 - #define EAX_EDX_VAL(val, low, high) ((low) | (high) << 32) 50 50 - #define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high) 51 51 - #else 52 52 - #define DECLARE_ARGS(val, low, high) unsigned long long val 53 53 - #define EAX_EDX_VAL(val, low, high) (val) 54 54 - #define EAX_EDX_RET(val, low, high) "=A" (val) 55 55 - #endif 56 56 - 57 57 - /* 58 40 * Be very careful with includes. This header is prone to include loops. 59 41 */ 60 42 #include <asm/atomic.h> ··· 47 63 DECLARE_TRACEPOINT(read_msr); 48 64 DECLARE_TRACEPOINT(write_msr); 49 65 DECLARE_TRACEPOINT(rdpmc); 50 50 - extern void do_trace_write_msr(unsigned int msr, u64 val, int failed); 51 51 - extern void do_trace_read_msr(unsigned int msr, u64 val, int failed); 52 52 - extern void do_trace_rdpmc(unsigned int msr, u64 val, int failed); 66 66 + extern void do_trace_write_msr(u32 msr, u64 val, int failed); 67 67 + extern void do_trace_read_msr(u32 msr, u64 val, int failed); 68 68 + extern void do_trace_rdpmc(u32 msr, u64 val, int failed); 53 69 #else 54 54 - static inline void do_trace_write_msr(unsigned int msr, u64 val, int failed) {} 55 55 - static inline void do_trace_read_msr(unsigned int msr, u64 val, int failed) {} 56 56 - static inline void do_trace_rdpmc(unsigned int msr, u64 val, int failed) {} 70 70 + static inline void do_trace_write_msr(u32 msr, u64 val, int failed) {} 71 71 + static inline void do_trace_read_msr(u32 msr, u64 val, int failed) {} 72 72 + static inline void do_trace_rdpmc(u32 msr, u64 val, int failed) {} 57 73 #endif 58 74 59 75 /* ··· 63 79 * think of extending them - you will be slapped with a stinking trout or a frozen 64 80 * shark will reach you, wherever you are! You've been warned. 65 81 */ 66 66 - static __always_inline unsigned long long __rdmsr(unsigned int msr) 82 82 + static __always_inline u64 __rdmsr(u32 msr) 67 83 { 68 68 - DECLARE_ARGS(val, low, high); 84 84 + EAX_EDX_DECLARE_ARGS(val, low, high); 69 85 70 86 asm volatile("1: rdmsr\n" 71 87 "2:\n" ··· 75 91 return EAX_EDX_VAL(val, low, high); 76 92 } 77 93 78 78 - static __always_inline void __wrmsr(unsigned int msr, u32 low, u32 high) 94 94 + static __always_inline void __wrmsrq(u32 msr, u64 val) 79 95 { 80 96 asm volatile("1: wrmsr\n" 81 97 "2:\n" 82 98 _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_WRMSR) 83 83 - : : "c" (msr), "a"(low), "d" (high) : "memory"); 99 99 + : : "c" (msr), "a" ((u32)val), "d" ((u32)(val >> 32)) : "memory"); 84 100 } 85 101 86 102 #define native_rdmsr(msr, val1, val2) \ ··· 90 106 (void)((val2) = (u32)(__val >> 32)); \ 91 107 } while (0) 92 108 93 93 - #define native_wrmsr(msr, low, high) \ 94 94 - __wrmsr(msr, low, high) 95 95 - 96 96 - #define native_wrmsrl(msr, val) \ 97 97 - __wrmsr((msr), (u32)((u64)(val)), \ 98 98 - (u32)((u64)(val) >> 32)) 99 99 - 100 100 - static inline unsigned long long native_read_msr(unsigned int msr) 109 109 + static __always_inline u64 native_rdmsrq(u32 msr) 101 110 { 102 102 - unsigned long long val; 111 111 + return __rdmsr(msr); 112 112 + } 113 113 + 114 114 + #define native_wrmsr(msr, low, high) \ 115 115 + __wrmsrq((msr), (u64)(high) << 32 | (low)) 116 116 + 117 117 + #define native_wrmsrq(msr, val) \ 118 118 + __wrmsrq((msr), (val)) 119 119 + 120 120 + static inline u64 native_read_msr(u32 msr) 121 121 + { 122 122 + u64 val; 103 123 104 124 val = __rdmsr(msr); 105 125 ··· 113 125 return val; 114 126 } 115 127 116 116 - static inline unsigned long long native_read_msr_safe(unsigned int msr, 117 117 - int *err) 128 128 + static inline int native_read_msr_safe(u32 msr, u64 *p) 118 129 { 119 119 - DECLARE_ARGS(val, low, high); 130 130 + int err; 131 131 + EAX_EDX_DECLARE_ARGS(val, low, high); 120 132 121 133 asm volatile("1: rdmsr ; xor %[err],%[err]\n" 122 134 "2:\n\t" 123 135 _ASM_EXTABLE_TYPE_REG(1b, 2b, EX_TYPE_RDMSR_SAFE, %[err]) 124 124 - : [err] "=r" (*err), EAX_EDX_RET(val, low, high) 136 136 + : [err] "=r" (err), EAX_EDX_RET(val, low, high) 125 137 : "c" (msr)); 126 138 if (tracepoint_enabled(read_msr)) 127 127 - do_trace_read_msr(msr, EAX_EDX_VAL(val, low, high), *err); 128 128 - return EAX_EDX_VAL(val, low, high); 139 139 + do_trace_read_msr(msr, EAX_EDX_VAL(val, low, high), err); 140 140 + 141 141 + *p = EAX_EDX_VAL(val, low, high); 142 142 + 143 143 + return err; 129 144 } 130 145 131 146 /* Can be uninlined because referenced by paravirt */ 132 132 - static inline void notrace 133 133 - native_write_msr(unsigned int msr, u32 low, u32 high) 147 147 + static inline void notrace native_write_msr(u32 msr, u64 val) 134 148 { 135 135 - __wrmsr(msr, low, high); 149 149 + native_wrmsrq(msr, val); 136 150 137 151 if (tracepoint_enabled(write_msr)) 138 138 - do_trace_write_msr(msr, ((u64)high << 32 | low), 0); 152 152 + do_trace_write_msr(msr, val, 0); 139 153 } 140 154 141 155 /* Can be uninlined because referenced by paravirt */ 142 142 - static inline int notrace 143 143 - native_write_msr_safe(unsigned int msr, u32 low, u32 high) 156 156 + static inline int notrace native_write_msr_safe(u32 msr, u64 val) 144 157 { 145 158 int err; 146 159 ··· 149 160 "2:\n\t" 150 161 _ASM_EXTABLE_TYPE_REG(1b, 2b, EX_TYPE_WRMSR_SAFE, %[err]) 151 162 : [err] "=a" (err) 152 152 - : "c" (msr), "0" (low), "d" (high) 163 163 + : "c" (msr), "0" ((u32)val), "d" ((u32)(val >> 32)) 153 164 : "memory"); 154 165 if (tracepoint_enabled(write_msr)) 155 155 - do_trace_write_msr(msr, ((u64)high << 32 | low), err); 166 166 + do_trace_write_msr(msr, val, err); 156 167 return err; 157 168 } 158 169 159 170 extern int rdmsr_safe_regs(u32 regs[8]); 160 171 extern int wrmsr_safe_regs(u32 regs[8]); 161 172 162 162 - /** 163 163 - * rdtsc() - returns the current TSC without ordering constraints 164 164 - * 165 165 - * rdtsc() returns the result of RDTSC as a 64-bit integer. The 166 166 - * only ordering constraint it supplies is the ordering implied by 167 167 - * "asm volatile": it will put the RDTSC in the place you expect. The 168 168 - * CPU can and will speculatively execute that RDTSC, though, so the 169 169 - * results can be non-monotonic if compared on different CPUs. 170 170 - */ 171 171 - static __always_inline unsigned long long rdtsc(void) 173 173 + static inline u64 native_read_pmc(int counter) 172 174 { 173 173 - DECLARE_ARGS(val, low, high); 174 174 - 175 175 - asm volatile("rdtsc" : EAX_EDX_RET(val, low, high)); 176 176 - 177 177 - return EAX_EDX_VAL(val, low, high); 178 178 - } 179 179 - 180 180 - /** 181 181 - * rdtsc_ordered() - read the current TSC in program order 182 182 - * 183 183 - * rdtsc_ordered() returns the result of RDTSC as a 64-bit integer. 184 184 - * It is ordered like a load to a global in-memory counter. It should 185 185 - * be impossible to observe non-monotonic rdtsc_unordered() behavior 186 186 - * across multiple CPUs as long as the TSC is synced. 187 187 - */ 188 188 - static __always_inline unsigned long long rdtsc_ordered(void) 189 189 - { 190 190 - DECLARE_ARGS(val, low, high); 191 191 - 192 192 - /* 193 193 - * The RDTSC instruction is not ordered relative to memory 194 194 - * access. The Intel SDM and the AMD APM are both vague on this 195 195 - * point, but empirically an RDTSC instruction can be 196 196 - * speculatively executed before prior loads. An RDTSC 197 197 - * immediately after an appropriate barrier appears to be 198 198 - * ordered as a normal load, that is, it provides the same 199 199 - * ordering guarantees as reading from a global memory location 200 200 - * that some other imaginary CPU is updating continuously with a 201 201 - * time stamp. 202 202 - * 203 203 - * Thus, use the preferred barrier on the respective CPU, aiming for 204 204 - * RDTSCP as the default. 205 205 - */ 206 206 - asm volatile(ALTERNATIVE_2("rdtsc", 207 207 - "lfence; rdtsc", X86_FEATURE_LFENCE_RDTSC, 208 208 - "rdtscp", X86_FEATURE_RDTSCP) 209 209 - : EAX_EDX_RET(val, low, high) 210 210 - /* RDTSCP clobbers ECX with MSR_TSC_AUX. */ 211 211 - :: "ecx"); 212 212 - 213 213 - return EAX_EDX_VAL(val, low, high); 214 214 - } 215 215 - 216 216 - static inline unsigned long long native_read_pmc(int counter) 217 217 - { 218 218 - DECLARE_ARGS(val, low, high); 175 175 + EAX_EDX_DECLARE_ARGS(val, low, high); 219 176 220 177 asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter)); 221 178 if (tracepoint_enabled(rdpmc)) ··· 186 251 (void)((high) = (u32)(__val >> 32)); \ 187 252 } while (0) 188 253 189 189 - static inline void wrmsr(unsigned int msr, u32 low, u32 high) 254 254 + static inline void wrmsr(u32 msr, u32 low, u32 high) 190 255 { 191 191 - native_write_msr(msr, low, high); 256 256 + native_write_msr(msr, (u64)high << 32 | low); 192 257 } 193 258 194 194 - #define rdmsrl(msr, val) \ 259 259 + #define rdmsrq(msr, val) \ 195 260 ((val) = native_read_msr((msr))) 196 261 197 197 - static inline void wrmsrl(unsigned int msr, u64 val) 262 262 + static inline void wrmsrq(u32 msr, u64 val) 198 263 { 199 199 - native_write_msr(msr, (u32)(val & 0xffffffffULL), (u32)(val >> 32)); 264 264 + native_write_msr(msr, val); 200 265 } 201 266 202 267 /* wrmsr with exception handling */ 203 203 - static inline int wrmsr_safe(unsigned int msr, u32 low, u32 high) 268 268 + static inline int wrmsrq_safe(u32 msr, u64 val) 204 269 { 205 205 - return native_write_msr_safe(msr, low, high); 270 270 + return native_write_msr_safe(msr, val); 206 271 } 207 272 208 273 /* rdmsr with exception handling */ 209 274 #define rdmsr_safe(msr, low, high) \ 210 275 ({ \ 211 211 - int __err; \ 212 212 - u64 __val = native_read_msr_safe((msr), &__err); \ 276 276 + u64 __val; \ 277 277 + int __err = native_read_msr_safe((msr), &__val); \ 213 278 (*low) = (u32)__val; \ 214 279 (*high) = (u32)(__val >> 32); \ 215 280 __err; \ 216 281 }) 217 282 218 218 - static inline int rdmsrl_safe(unsigned int msr, unsigned long long *p) 283 283 + static inline int rdmsrq_safe(u32 msr, u64 *p) 219 284 { 220 220 - int err; 221 221 - 222 222 - *p = native_read_msr_safe(msr, &err); 223 223 - return err; 285 285 + return native_read_msr_safe(msr, p); 224 286 } 225 287 226 226 - #define rdpmc(counter, low, high) \ 227 227 - do { \ 228 228 - u64 _l = native_read_pmc((counter)); \ 229 229 - (low) = (u32)_l; \ 230 230 - (high) = (u32)(_l >> 32); \ 231 231 - } while (0) 232 232 - 233 233 - #define rdpmcl(counter, val) ((val) = native_read_pmc(counter)) 288 288 + static __always_inline u64 rdpmc(int counter) 289 289 + { 290 290 + return native_read_pmc(counter); 291 291 + } 234 292 235 293 #endif /* !CONFIG_PARAVIRT_XXL */ 236 294 ··· 243 315 } 244 316 245 317 /* 246 246 - * 64-bit version of wrmsr_safe(): 318 318 + * Dual u32 version of wrmsrq_safe(): 247 319 */ 248 248 - static inline int wrmsrl_safe(u32 msr, u64 val) 320 320 + static inline int wrmsr_safe(u32 msr, u32 low, u32 high) 249 321 { 250 250 - return wrmsr_safe(msr, (u32)val, (u32)(val >> 32)); 322 322 + return wrmsrq_safe(msr, (u64)high << 32 | low); 251 323 } 252 324 253 325 struct msr __percpu *msrs_alloc(void); ··· 258 330 #ifdef CONFIG_SMP 259 331 int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); 260 332 int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); 261 261 - int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); 262 262 - int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q); 333 333 + int rdmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); 334 334 + int wrmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 q); 263 335 void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr __percpu *msrs); 264 336 void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr __percpu *msrs); 265 337 int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); 266 338 int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); 267 267 - int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); 268 268 - int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q); 339 339 + int rdmsrq_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); 340 340 + int wrmsrq_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q); 269 341 int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); 270 342 int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); 271 343 #else /* CONFIG_SMP */ ··· 279 351 wrmsr(msr_no, l, h); 280 352 return 0; 281 353 } 282 282 - static inline int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) 354 354 + static inline int rdmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) 283 355 { 284 284 - rdmsrl(msr_no, *q); 356 356 + rdmsrq(msr_no, *q); 285 357 return 0; 286 358 } 287 287 - static inline int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q) 359 359 + static inline int wrmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 q) 288 360 { 289 289 - wrmsrl(msr_no, q); 361 361 + wrmsrq(msr_no, q); 290 362 return 0; 291 363 } 292 364 static inline void rdmsr_on_cpus(const struct cpumask *m, u32 msr_no, ··· 308 380 { 309 381 return wrmsr_safe(msr_no, l, h); 310 382 } 311 311 - static inline int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) 383 383 + static inline int rdmsrq_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) 312 384 { 313 313 - return rdmsrl_safe(msr_no, q); 385 385 + return rdmsrq_safe(msr_no, q); 314 386 } 315 315 - static inline int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q) 387 387 + static inline int wrmsrq_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q) 316 388 { 317 317 - return wrmsrl_safe(msr_no, q); 389 389 + return wrmsrq_safe(msr_no, q); 318 390 } 319 391 static inline int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) 320 392 { ··· 325 397 return wrmsr_safe_regs(regs); 326 398 } 327 399 #endif /* CONFIG_SMP */ 400 400 + 401 401 + /* Compatibility wrappers: */ 402 402 + #define rdmsrl(msr, val) rdmsrq(msr, val) 403 403 + #define wrmsrl(msr, val) wrmsrq(msr, val) 404 404 + 328 405 #endif /* __ASSEMBLER__ */ 329 406 #endif /* _ASM_X86_MSR_H */

+24 -35

arch/x86/include/asm/paravirt.h

reviewed

··· 175 175 PVOP_VCALL1(cpu.write_cr4, x); 176 176 } 177 177 178 178 - static inline u64 paravirt_read_msr(unsigned msr) 178 178 + static inline u64 paravirt_read_msr(u32 msr) 179 179 { 180 180 return PVOP_CALL1(u64, cpu.read_msr, msr); 181 181 } 182 182 183 183 - static inline void paravirt_write_msr(unsigned msr, 184 184 - unsigned low, unsigned high) 183 183 + static inline void paravirt_write_msr(u32 msr, u64 val) 185 184 { 186 186 - PVOP_VCALL3(cpu.write_msr, msr, low, high); 185 185 + PVOP_VCALL2(cpu.write_msr, msr, val); 187 186 } 188 187 189 189 - static inline u64 paravirt_read_msr_safe(unsigned msr, int *err) 188 188 + static inline int paravirt_read_msr_safe(u32 msr, u64 *val) 190 189 { 191 191 - return PVOP_CALL2(u64, cpu.read_msr_safe, msr, err); 190 190 + return PVOP_CALL2(int, cpu.read_msr_safe, msr, val); 192 191 } 193 192 194 194 - static inline int paravirt_write_msr_safe(unsigned msr, 195 195 - unsigned low, unsigned high) 193 193 + static inline int paravirt_write_msr_safe(u32 msr, u64 val) 196 194 { 197 197 - return PVOP_CALL3(int, cpu.write_msr_safe, msr, low, high); 195 195 + return PVOP_CALL2(int, cpu.write_msr_safe, msr, val); 198 196 } 199 197 200 198 #define rdmsr(msr, val1, val2) \ ··· 202 204 val2 = _l >> 32; \ 203 205 } while (0) 204 206 205 205 - #define wrmsr(msr, val1, val2) \ 206 206 - do { \ 207 207 - paravirt_write_msr(msr, val1, val2); \ 208 208 - } while (0) 207 207 + static __always_inline void wrmsr(u32 msr, u32 low, u32 high) 208 208 + { 209 209 + paravirt_write_msr(msr, (u64)high << 32 | low); 210 210 + } 209 211 210 210 - #define rdmsrl(msr, val) \ 212 212 + #define rdmsrq(msr, val) \ 211 213 do { \ 212 214 val = paravirt_read_msr(msr); \ 213 215 } while (0) 214 216 215 215 - static inline void wrmsrl(unsigned msr, u64 val) 217 217 + static inline void wrmsrq(u32 msr, u64 val) 216 218 { 217 217 - wrmsr(msr, (u32)val, (u32)(val>>32)); 219 219 + paravirt_write_msr(msr, val); 218 220 } 219 221 220 220 - #define wrmsr_safe(msr, a, b) paravirt_write_msr_safe(msr, a, b) 222 222 + static inline int wrmsrq_safe(u32 msr, u64 val) 223 223 + { 224 224 + return paravirt_write_msr_safe(msr, val); 225 225 + } 221 226 222 227 /* rdmsr with exception handling */ 223 228 #define rdmsr_safe(msr, a, b) \ 224 229 ({ \ 225 225 - int _err; \ 226 226 - u64 _l = paravirt_read_msr_safe(msr, &_err); \ 230 230 + u64 _l; \ 231 231 + int _err = paravirt_read_msr_safe((msr), &_l); \ 227 232 (*a) = (u32)_l; \ 228 228 - (*b) = _l >> 32; \ 233 233 + (*b) = (u32)(_l >> 32); \ 229 234 _err; \ 230 235 }) 231 236 232 232 - static inline int rdmsrl_safe(unsigned msr, unsigned long long *p) 237 237 + static __always_inline int rdmsrq_safe(u32 msr, u64 *p) 233 238 { 234 234 - int err; 235 235 - 236 236 - *p = paravirt_read_msr_safe(msr, &err); 237 237 - return err; 239 239 + return paravirt_read_msr_safe(msr, p); 238 240 } 239 241 240 240 - static inline unsigned long long paravirt_read_pmc(int counter) 242 242 + static __always_inline u64 rdpmc(int counter) 241 243 { 242 244 return PVOP_CALL1(u64, cpu.read_pmc, counter); 243 245 } 244 244 - 245 245 - #define rdpmc(counter, low, high) \ 246 246 - do { \ 247 247 - u64 _l = paravirt_read_pmc(counter); \ 248 248 - low = (u32)_l; \ 249 249 - high = _l >> 32; \ 250 250 - } while (0) 251 251 - 252 252 - #define rdpmcl(counter, val) ((val) = paravirt_read_pmc(counter)) 253 246 254 247 static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries) 255 248 {

+5 -5

arch/x86/include/asm/paravirt_types.h

reviewed

··· 91 91 unsigned int *ecx, unsigned int *edx); 92 92 93 93 /* Unsafe MSR operations. These will warn or panic on failure. */ 94 94 - u64 (*read_msr)(unsigned int msr); 95 95 - void (*write_msr)(unsigned int msr, unsigned low, unsigned high); 94 94 + u64 (*read_msr)(u32 msr); 95 95 + void (*write_msr)(u32 msr, u64 val); 96 96 97 97 /* 98 98 * Safe MSR operations. 99 99 - * read sets err to 0 or -EIO. write returns 0 or -EIO. 99 99 + * Returns 0 or -EIO. 100 100 */ 101 101 - u64 (*read_msr_safe)(unsigned int msr, int *err); 102 102 - int (*write_msr_safe)(unsigned int msr, unsigned low, unsigned high); 101 101 + int (*read_msr_safe)(u32 msr, u64 *val); 102 102 + int (*write_msr_safe)(u32 msr, u64 val); 103 103 104 104 u64 (*read_pmc)(int counter); 105 105

+2

arch/x86/include/asm/resctrl.h

reviewed

··· 9 9 #include <linux/resctrl_types.h> 10 10 #include <linux/sched.h> 11 11 12 12 + #include <asm/msr.h> 13 13 + 12 14 /* 13 15 * This value can never be a valid CLOSID, and is used when mapping a 14 16 * (closid, rmid) pair to an index and back. On x86 only the RMID is

+1 -1

arch/x86/include/asm/sev-internal.h

reviewed

··· 84 84 85 85 static inline u64 sev_es_rd_ghcb_msr(void) 86 86 { 87 87 - return __rdmsr(MSR_AMD64_SEV_ES_GHCB); 87 87 + return native_rdmsrq(MSR_AMD64_SEV_ES_GHCB); 88 88 } 89 89 90 90 static __always_inline void sev_es_wr_ghcb_msr(u64 val)

+1 -1

arch/x86/include/asm/spec-ctrl.h

reviewed

··· 84 84 static __always_inline void __update_spec_ctrl(u64 val) 85 85 { 86 86 __this_cpu_write(x86_spec_ctrl_current, val); 87 87 - native_wrmsrl(MSR_IA32_SPEC_CTRL, val); 87 87 + native_wrmsrq(MSR_IA32_SPEC_CTRL, val); 88 88 } 89 89 90 90 #ifdef CONFIG_SMP

+1

arch/x86/include/asm/suspend_32.h

reviewed

··· 9 9 10 10 #include <asm/desc.h> 11 11 #include <asm/fpu/api.h> 12 12 + #include <asm/msr.h> 12 13 13 14 /* image of the saved processor state */ 14 15 struct saved_context {

+1

arch/x86/include/asm/suspend_64.h

reviewed

··· 9 9 10 10 #include <asm/desc.h> 11 11 #include <asm/fpu/api.h> 12 12 + #include <asm/msr.h> 12 13 13 14 /* 14 15 * Image of the saved processor state, used by the low level ACPI suspend to

+3 -1

arch/x86/include/asm/switch_to.h

reviewed

··· 52 52 } while (0) 53 53 54 54 #ifdef CONFIG_X86_32 55 55 + #include <asm/msr.h> 56 56 + 55 57 static inline void refresh_sysenter_cs(struct thread_struct *thread) 56 58 { 57 59 /* Only happens when SEP is enabled, no need to test "SEP"arately: */ ··· 61 59 return; 62 60 63 61 this_cpu_write(cpu_tss_rw.x86_tss.ss1, thread->sysenter_cs); 64 64 - wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0); 62 62 + wrmsrq(MSR_IA32_SYSENTER_CS, thread->sysenter_cs); 65 63 } 66 64 #endif 67 65

+55

arch/x86/include/asm/tsc.h

reviewed

··· 5 5 #ifndef _ASM_X86_TSC_H 6 6 #define _ASM_X86_TSC_H 7 7 8 8 + #include <asm/asm.h> 8 9 #include <asm/cpufeature.h> 9 10 #include <asm/processor.h> 10 11 #include <asm/msr.h> 12 12 + 13 13 + /** 14 14 + * rdtsc() - returns the current TSC without ordering constraints 15 15 + * 16 16 + * rdtsc() returns the result of RDTSC as a 64-bit integer. The 17 17 + * only ordering constraint it supplies is the ordering implied by 18 18 + * "asm volatile": it will put the RDTSC in the place you expect. The 19 19 + * CPU can and will speculatively execute that RDTSC, though, so the 20 20 + * results can be non-monotonic if compared on different CPUs. 21 21 + */ 22 22 + static __always_inline u64 rdtsc(void) 23 23 + { 24 24 + EAX_EDX_DECLARE_ARGS(val, low, high); 25 25 + 26 26 + asm volatile("rdtsc" : EAX_EDX_RET(val, low, high)); 27 27 + 28 28 + return EAX_EDX_VAL(val, low, high); 29 29 + } 30 30 + 31 31 + /** 32 32 + * rdtsc_ordered() - read the current TSC in program order 33 33 + * 34 34 + * rdtsc_ordered() returns the result of RDTSC as a 64-bit integer. 35 35 + * It is ordered like a load to a global in-memory counter. It should 36 36 + * be impossible to observe non-monotonic rdtsc_unordered() behavior 37 37 + * across multiple CPUs as long as the TSC is synced. 38 38 + */ 39 39 + static __always_inline u64 rdtsc_ordered(void) 40 40 + { 41 41 + EAX_EDX_DECLARE_ARGS(val, low, high); 42 42 + 43 43 + /* 44 44 + * The RDTSC instruction is not ordered relative to memory 45 45 + * access. The Intel SDM and the AMD APM are both vague on this 46 46 + * point, but empirically an RDTSC instruction can be 47 47 + * speculatively executed before prior loads. An RDTSC 48 48 + * immediately after an appropriate barrier appears to be 49 49 + * ordered as a normal load, that is, it provides the same 50 50 + * ordering guarantees as reading from a global memory location 51 51 + * that some other imaginary CPU is updating continuously with a 52 52 + * time stamp. 53 53 + * 54 54 + * Thus, use the preferred barrier on the respective CPU, aiming for 55 55 + * RDTSCP as the default. 56 56 + */ 57 57 + asm volatile(ALTERNATIVE_2("rdtsc", 58 58 + "lfence; rdtsc", X86_FEATURE_LFENCE_RDTSC, 59 59 + "rdtscp", X86_FEATURE_RDTSCP) 60 60 + : EAX_EDX_RET(val, low, high) 61 61 + /* RDTSCP clobbers ECX with MSR_TSC_AUX. */ 62 62 + :: "ecx"); 63 63 + 64 64 + return EAX_EDX_VAL(val, low, high); 65 65 + } 11 66 12 67 /* 13 68 * Standard way to access the cycle counter.

+4 -4

arch/x86/kernel/acpi/cppc.c

reviewed

··· 49 49 { 50 50 int err; 51 51 52 52 - err = rdmsrl_safe_on_cpu(cpunum, reg->address, val); 52 52 + err = rdmsrq_safe_on_cpu(cpunum, reg->address, val); 53 53 if (!err) { 54 54 u64 mask = GENMASK_ULL(reg->bit_offset + reg->bit_width - 1, 55 55 reg->bit_offset); ··· 65 65 u64 rd_val; 66 66 int err; 67 67 68 68 - err = rdmsrl_safe_on_cpu(cpunum, reg->address, &rd_val); 68 68 + err = rdmsrq_safe_on_cpu(cpunum, reg->address, &rd_val); 69 69 if (!err) { 70 70 u64 mask = GENMASK_ULL(reg->bit_offset + reg->bit_width - 1, 71 71 reg->bit_offset); ··· 74 74 val &= mask; 75 75 rd_val &= ~mask; 76 76 rd_val |= val; 77 77 - err = wrmsrl_safe_on_cpu(cpunum, reg->address, rd_val); 77 77 + err = wrmsrq_safe_on_cpu(cpunum, reg->address, rd_val); 78 78 } 79 79 return err; 80 80 } ··· 147 147 int ret; 148 148 149 149 if (cpu_feature_enabled(X86_FEATURE_CPPC)) { 150 150 - ret = rdmsrl_safe_on_cpu(cpu, MSR_AMD_CPPC_CAP1, &val); 150 150 + ret = rdmsrq_safe_on_cpu(cpu, MSR_AMD_CPPC_CAP1, &val); 151 151 if (ret) 152 152 goto out; 153 153

+1

arch/x86/kernel/acpi/sleep.c

reviewed

··· 16 16 #include <asm/cacheflush.h> 17 17 #include <asm/realmode.h> 18 18 #include <asm/hypervisor.h> 19 19 + #include <asm/msr.h> 19 20 #include <asm/smp.h> 20 21 21 22 #include <linux/ftrace.h>

+1 -1

arch/x86/kernel/amd_nb.c

reviewed

··· 150 150 151 151 /* Assume CPUs from Fam10h have mmconfig, although not all VMs do */ 152 152 if (boot_cpu_data.x86 < 0x10 || 153 153 - rdmsrl_safe(MSR_FAM10H_MMIO_CONF_BASE, &msr)) 153 153 + rdmsrq_safe(MSR_FAM10H_MMIO_CONF_BASE, &msr)) 154 154 return NULL; 155 155 156 156 /* mmconfig is not enabled */

+9 -8

arch/x86/kernel/apic/apic.c

reviewed

··· 59 59 #include <asm/time.h> 60 60 #include <asm/smp.h> 61 61 #include <asm/mce.h> 62 62 + #include <asm/msr.h> 62 63 #include <asm/tsc.h> 63 64 #include <asm/hypervisor.h> 64 65 #include <asm/cpu_device_id.h> ··· 426 425 weak_wrmsr_fence(); 427 426 428 427 tsc = rdtsc(); 429 429 - wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); 428 428 + wrmsrq(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); 430 429 return 0; 431 430 } 432 431 ··· 450 449 * the timer _and_ zero the counter registers: 451 450 */ 452 451 if (v & APIC_LVT_TIMER_TSCDEADLINE) 453 453 - wrmsrl(MSR_IA32_TSC_DEADLINE, 0); 452 452 + wrmsrq(MSR_IA32_TSC_DEADLINE, 0); 454 453 else 455 454 apic_write(APIC_TMICT, 0); 456 455 ··· 1695 1694 1696 1695 x86_arch_cap_msr = x86_read_arch_cap_msr(); 1697 1696 if (x86_arch_cap_msr & ARCH_CAP_XAPIC_DISABLE) { 1698 1698 - rdmsrl(MSR_IA32_XAPIC_DISABLE_STATUS, msr); 1697 1697 + rdmsrq(MSR_IA32_XAPIC_DISABLE_STATUS, msr); 1699 1698 return (msr & LEGACY_XAPIC_DISABLED); 1700 1699 } 1701 1700 return false; ··· 1708 1707 if (!boot_cpu_has(X86_FEATURE_APIC)) 1709 1708 return; 1710 1709 1711 1711 - rdmsrl(MSR_IA32_APICBASE, msr); 1710 1710 + rdmsrq(MSR_IA32_APICBASE, msr); 1712 1711 if (!(msr & X2APIC_ENABLE)) 1713 1712 return; 1714 1713 /* Disable xapic and x2apic first and then reenable xapic mode */ 1715 1715 - wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); 1716 1716 - wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); 1714 1714 + wrmsrq(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); 1715 1715 + wrmsrq(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); 1717 1716 printk_once(KERN_INFO "x2apic disabled\n"); 1718 1717 } 1719 1718 ··· 1721 1720 { 1722 1721 u64 msr; 1723 1722 1724 1724 - rdmsrl(MSR_IA32_APICBASE, msr); 1723 1723 + rdmsrq(MSR_IA32_APICBASE, msr); 1725 1724 if (msr & X2APIC_ENABLE) 1726 1725 return; 1727 1727 - wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); 1726 1726 + wrmsrq(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); 1728 1727 printk_once(KERN_INFO "x2apic enabled\n"); 1729 1728 } 1730 1729

+4 -3

arch/x86/kernel/apic/apic_numachip.c

reviewed

··· 14 14 #include <linux/init.h> 15 15 #include <linux/pgtable.h> 16 16 17 17 + #include <asm/msr.h> 17 18 #include <asm/numachip/numachip.h> 18 19 #include <asm/numachip/numachip_csr.h> 19 20 ··· 32 31 unsigned int id = (x >> 24) & 0xff; 33 32 34 33 if (static_cpu_has(X86_FEATURE_NODEID_MSR)) { 35 35 - rdmsrl(MSR_FAM10H_NODE_ID, value); 34 34 + rdmsrq(MSR_FAM10H_NODE_ID, value); 36 35 id |= (value << 2) & 0xff00; 37 36 } 38 37 ··· 43 42 { 44 43 u64 mcfg; 45 44 46 46 - rdmsrl(MSR_FAM10H_MMIO_CONF_BASE, mcfg); 45 45 + rdmsrq(MSR_FAM10H_MMIO_CONF_BASE, mcfg); 47 46 return ((mcfg >> (28 - 8)) & 0xfff00) | (x >> 24); 48 47 } 49 48 ··· 151 150 152 151 /* Account for nodes per socket in multi-core-module processors */ 153 152 if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) { 154 154 - rdmsrl(MSR_FAM10H_NODE_ID, val); 153 153 + rdmsrq(MSR_FAM10H_NODE_ID, val); 155 154 nodes = ((val >> 3) & 7) + 1; 156 155 } 157 156

+2 -1

arch/x86/kernel/cet.c

reviewed

··· 2 2 3 3 #include <linux/ptrace.h> 4 4 #include <asm/bugs.h> 5 5 + #include <asm/msr.h> 5 6 #include <asm/traps.h> 6 7 7 8 enum cp_error_code { ··· 56 55 * will be whatever is live in userspace. So read the SSP before enabling 57 56 * interrupts so locking the fpregs to do it later is not required. 58 57 */ 59 59 - rdmsrl(MSR_IA32_PL3_SSP, ssp); 58 58 + rdmsrq(MSR_IA32_PL3_SSP, ssp); 60 59 61 60 cond_local_irq_enable(regs); 62 61

+16 -15

arch/x86/kernel/cpu/amd.c

reviewed

··· 21 21 #include <asm/delay.h> 22 22 #include <asm/debugreg.h> 23 23 #include <asm/resctrl.h> 24 24 + #include <asm/msr.h> 24 25 #include <asm/sev.h> 25 26 26 27 #ifdef CONFIG_X86_64 ··· 32 31 33 32 u16 invlpgb_count_max __ro_after_init; 34 33 35 35 - static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) 34 34 + static inline int rdmsrq_amd_safe(unsigned msr, u64 *p) 36 35 { 37 36 u32 gprs[8] = { 0 }; 38 37 int err; ··· 50 49 return err; 51 50 } 52 51 53 53 - static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val) 52 52 + static inline int wrmsrq_amd_safe(unsigned msr, u64 val) 54 53 { 55 54 u32 gprs[8] = { 0 }; 56 55 ··· 384 383 (c->x86 == 0x10 && c->x86_model >= 0x2)) { 385 384 u64 val; 386 385 387 387 - rdmsrl(MSR_K7_HWCR, val); 386 386 + rdmsrq(MSR_K7_HWCR, val); 388 387 if (!(val & BIT(24))) 389 388 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n"); 390 389 } ··· 423 422 * Try to cache the base value so further operations can 424 423 * avoid RMW. If that faults, do not enable SSBD. 425 424 */ 426 426 - if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) { 425 425 + if (!rdmsrq_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) { 427 426 setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD); 428 427 setup_force_cpu_cap(X86_FEATURE_SSBD); 429 428 x86_amd_ls_cfg_ssbd_mask = 1ULL << bit; ··· 509 508 */ 510 509 if (cpu_has(c, X86_FEATURE_SME) || cpu_has(c, X86_FEATURE_SEV)) { 511 510 /* Check if memory encryption is enabled */ 512 512 - rdmsrl(MSR_AMD64_SYSCFG, msr); 511 511 + rdmsrq(MSR_AMD64_SYSCFG, msr); 513 512 if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT)) 514 513 goto clear_all; 515 514 ··· 526 525 if (!sme_me_mask) 527 526 setup_clear_cpu_cap(X86_FEATURE_SME); 528 527 529 529 - rdmsrl(MSR_K7_HWCR, msr); 528 528 + rdmsrq(MSR_K7_HWCR, msr); 530 529 if (!(msr & MSR_K7_HWCR_SMMLOCK)) 531 530 goto clear_sev; 532 531 ··· 613 612 if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && !cpu_has(c, X86_FEATURE_IBPB_BRTYPE)) { 614 613 if (c->x86 == 0x17 && boot_cpu_has(X86_FEATURE_AMD_IBPB)) 615 614 setup_force_cpu_cap(X86_FEATURE_IBPB_BRTYPE); 616 616 - else if (c->x86 >= 0x19 && !wrmsrl_safe(MSR_IA32_PRED_CMD, PRED_CMD_SBPB)) { 615 615 + else if (c->x86 >= 0x19 && !wrmsrq_safe(MSR_IA32_PRED_CMD, PRED_CMD_SBPB)) { 617 616 setup_force_cpu_cap(X86_FEATURE_IBPB_BRTYPE); 618 617 setup_force_cpu_cap(X86_FEATURE_SBPB); 619 618 } ··· 637 636 */ 638 637 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM) && !cpu_has(c, X86_FEATURE_HYPERVISOR)) { 639 638 clear_cpu_cap(c, X86_FEATURE_LAHF_LM); 640 640 - if (!rdmsrl_amd_safe(0xc001100d, &value)) { 639 639 + if (!rdmsrq_amd_safe(0xc001100d, &value)) { 641 640 value &= ~BIT_64(32); 642 642 - wrmsrl_amd_safe(0xc001100d, value); 641 641 + wrmsrq_amd_safe(0xc001100d, value); 643 642 } 644 643 } 645 644 ··· 789 788 * Disable it on the affected CPUs. 790 789 */ 791 790 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) { 792 792 - if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) { 791 791 + if (!rdmsrq_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) { 793 792 value |= 0x1E; 794 794 - wrmsrl_safe(MSR_F15H_IC_CFG, value); 793 793 + wrmsrq_safe(MSR_F15H_IC_CFG, value); 795 794 } 796 795 } 797 796 ··· 840 839 * suppresses non-branch predictions. 841 840 */ 842 841 if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) { 843 843 - if (!rdmsrl_safe(MSR_ZEN2_SPECTRAL_CHICKEN, &value)) { 842 842 + if (!rdmsrq_safe(MSR_ZEN2_SPECTRAL_CHICKEN, &value)) { 844 843 value |= MSR_ZEN2_SPECTRAL_CHICKEN_BIT; 845 845 - wrmsrl_safe(MSR_ZEN2_SPECTRAL_CHICKEN, value); 844 844 + wrmsrq_safe(MSR_ZEN2_SPECTRAL_CHICKEN, value); 846 845 } 847 846 } 848 847 #endif ··· 1026 1025 init_amd_cacheinfo(c); 1027 1026 1028 1027 if (cpu_has(c, X86_FEATURE_SVM)) { 1029 1029 - rdmsrl(MSR_VM_CR, vm_cr); 1028 1028 + rdmsrq(MSR_VM_CR, vm_cr); 1030 1029 if (vm_cr & SVM_VM_CR_SVM_DIS_MASK) { 1031 1030 pr_notice_once("SVM disabled (by BIOS) in MSR_VM_CR\n"); 1032 1031 clear_cpu_cap(c, X86_FEATURE_SVM); ··· 1207 1206 if (per_cpu(amd_dr_addr_mask, cpu)[dr] == mask) 1208 1207 return; 1209 1208 1210 1210 - wrmsr(amd_msr_dr_addr_masks[dr], mask, 0); 1209 1209 + wrmsrq(amd_msr_dr_addr_masks[dr], mask); 1211 1210 per_cpu(amd_dr_addr_mask, cpu)[dr] = mask; 1212 1211 } 1213 1212

+15 -14

arch/x86/kernel/cpu/aperfmperf.c

reviewed

··· 20 20 #include <asm/cpu.h> 21 21 #include <asm/cpu_device_id.h> 22 22 #include <asm/intel-family.h> 23 23 + #include <asm/msr.h> 23 24 24 25 #include "cpu.h" 25 26 ··· 41 40 { 42 41 u64 aperf, mperf; 43 42 44 44 - rdmsrl(MSR_IA32_APERF, aperf); 45 45 - rdmsrl(MSR_IA32_MPERF, mperf); 43 43 + rdmsrq(MSR_IA32_APERF, aperf); 44 44 + rdmsrq(MSR_IA32_MPERF, mperf); 46 45 47 46 this_cpu_write(cpu_samples.aperf, aperf); 48 47 this_cpu_write(cpu_samples.mperf, mperf); ··· 100 99 u64 misc_en; 101 100 int err; 102 101 103 103 - err = rdmsrl_safe(MSR_IA32_MISC_ENABLE, &misc_en); 102 102 + err = rdmsrq_safe(MSR_IA32_MISC_ENABLE, &misc_en); 104 103 if (err) 105 104 return false; 106 105 ··· 111 110 { 112 111 int err; 113 112 114 114 - err = rdmsrl_safe(MSR_ATOM_CORE_RATIOS, base_freq); 113 113 + err = rdmsrq_safe(MSR_ATOM_CORE_RATIOS, base_freq); 115 114 if (err) 116 115 return false; 117 116 118 118 - err = rdmsrl_safe(MSR_ATOM_CORE_TURBO_RATIOS, turbo_freq); 117 117 + err = rdmsrq_safe(MSR_ATOM_CORE_TURBO_RATIOS, turbo_freq); 119 118 if (err) 120 119 return false; 121 120 ··· 153 152 int err, i; 154 153 u64 msr; 155 154 156 156 - err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq); 155 155 + err = rdmsrq_safe(MSR_PLATFORM_INFO, base_freq); 157 156 if (err) 158 157 return false; 159 158 160 159 *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */ 161 160 162 162 - err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &msr); 161 161 + err = rdmsrq_safe(MSR_TURBO_RATIO_LIMIT, &msr); 163 162 if (err) 164 163 return false; 165 164 ··· 191 190 u32 group_size; 192 191 int err, i; 193 192 194 194 - err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq); 193 193 + err = rdmsrq_safe(MSR_PLATFORM_INFO, base_freq); 195 194 if (err) 196 195 return false; 197 196 198 197 *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */ 199 198 200 200 - err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &ratios); 199 199 + err = rdmsrq_safe(MSR_TURBO_RATIO_LIMIT, &ratios); 201 200 if (err) 202 201 return false; 203 202 204 204 - err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT1, &counts); 203 203 + err = rdmsrq_safe(MSR_TURBO_RATIO_LIMIT1, &counts); 205 204 if (err) 206 205 return false; 207 206 ··· 221 220 u64 msr; 222 221 int err; 223 222 224 224 - err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq); 223 223 + err = rdmsrq_safe(MSR_PLATFORM_INFO, base_freq); 225 224 if (err) 226 225 return false; 227 226 228 228 - err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &msr); 227 227 + err = rdmsrq_safe(MSR_TURBO_RATIO_LIMIT, &msr); 229 228 if (err) 230 229 return false; 231 230 ··· 475 474 if (!cpu_feature_enabled(X86_FEATURE_APERFMPERF)) 476 475 return; 477 476 478 478 - rdmsrl(MSR_IA32_APERF, aperf); 479 479 - rdmsrl(MSR_IA32_MPERF, mperf); 477 477 + rdmsrq(MSR_IA32_APERF, aperf); 478 478 + rdmsrq(MSR_IA32_MPERF, mperf); 480 479 acnt = aperf - s->aperf; 481 480 mcnt = mperf - s->mperf; 482 481

+12 -12

arch/x86/kernel/cpu/bugs.c

reviewed

··· 112 112 static void update_spec_ctrl(u64 val) 113 113 { 114 114 this_cpu_write(x86_spec_ctrl_current, val); 115 115 - wrmsrl(MSR_IA32_SPEC_CTRL, val); 115 115 + wrmsrq(MSR_IA32_SPEC_CTRL, val); 116 116 } 117 117 118 118 /* ··· 131 131 * forced the update can be delayed until that time. 132 132 */ 133 133 if (!cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS)) 134 134 - wrmsrl(MSR_IA32_SPEC_CTRL, val); 134 134 + wrmsrq(MSR_IA32_SPEC_CTRL, val); 135 135 } 136 136 137 137 noinstr u64 spec_ctrl_current(void) ··· 185 185 * init code as it is not enumerated and depends on the family. 186 186 */ 187 187 if (cpu_feature_enabled(X86_FEATURE_MSR_SPEC_CTRL)) { 188 188 - rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); 188 188 + rdmsrq(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); 189 189 190 190 /* 191 191 * Previously running kernel (kexec), may have some controls ··· 303 303 u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask; 304 304 305 305 if (boot_cpu_has(X86_FEATURE_VIRT_SSBD)) 306 306 - wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD); 306 306 + wrmsrq(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD); 307 307 else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD)) 308 308 - wrmsrl(MSR_AMD64_LS_CFG, msrval); 308 308 + wrmsrq(MSR_AMD64_LS_CFG, msrval); 309 309 } 310 310 311 311 #undef pr_fmt ··· 761 761 if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL)) 762 762 return; 763 763 764 764 - rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); 764 764 + rdmsrq(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); 765 765 766 766 switch (srbds_mitigation) { 767 767 case SRBDS_MITIGATION_OFF: ··· 775 775 break; 776 776 } 777 777 778 778 - wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); 778 778 + wrmsrq(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); 779 779 } 780 780 781 781 static void __init srbds_select_mitigation(void) ··· 891 891 892 892 switch (gds_mitigation) { 893 893 case GDS_MITIGATION_OFF: 894 894 - rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); 894 894 + rdmsrq(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); 895 895 mcu_ctrl |= GDS_MITG_DIS; 896 896 break; 897 897 case GDS_MITIGATION_FULL_LOCKED: ··· 901 901 * CPUs. 902 902 */ 903 903 case GDS_MITIGATION_FULL: 904 904 - rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); 904 904 + rdmsrq(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); 905 905 mcu_ctrl &= ~GDS_MITG_DIS; 906 906 break; 907 907 case GDS_MITIGATION_FORCE: ··· 911 911 return; 912 912 } 913 913 914 914 - wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); 914 914 + wrmsrq(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); 915 915 916 916 /* 917 917 * Check to make sure that the WRMSR value was not ignored. Writes to 918 918 * GDS_MITG_DIS will be ignored if this processor is locked but the boot 919 919 * processor was not. 920 920 */ 921 921 - rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl_after); 921 921 + rdmsrq(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl_after); 922 922 WARN_ON_ONCE(mcu_ctrl != mcu_ctrl_after); 923 923 } 924 924 ··· 952 952 if (gds_mitigation == GDS_MITIGATION_FORCE) 953 953 gds_mitigation = GDS_MITIGATION_FULL; 954 954 955 955 - rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); 955 955 + rdmsrq(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); 956 956 if (mcu_ctrl & GDS_MITG_LOCKED) { 957 957 if (gds_mitigation == GDS_MITIGATION_OFF) 958 958 pr_warn("Mitigation locked. Disable failed.\n");

+10 -9

arch/x86/kernel/cpu/bus_lock.c

reviewed

··· 10 10 #include <asm/cmdline.h> 11 11 #include <asm/traps.h> 12 12 #include <asm/cpu.h> 13 13 + #include <asm/msr.h> 13 14 14 15 enum split_lock_detect_state { 15 16 sld_off = 0, ··· 96 95 { 97 96 u64 ctrl, tmp; 98 97 99 99 - if (rdmsrl_safe(MSR_TEST_CTRL, &ctrl)) 98 98 + if (rdmsrq_safe(MSR_TEST_CTRL, &ctrl)) 100 99 return false; 101 100 if (on) 102 101 ctrl |= MSR_TEST_CTRL_SPLIT_LOCK_DETECT; 103 102 else 104 103 ctrl &= ~MSR_TEST_CTRL_SPLIT_LOCK_DETECT; 105 105 - if (wrmsrl_safe(MSR_TEST_CTRL, ctrl)) 104 104 + if (wrmsrq_safe(MSR_TEST_CTRL, ctrl)) 106 105 return false; 107 107 - rdmsrl(MSR_TEST_CTRL, tmp); 106 106 + rdmsrq(MSR_TEST_CTRL, tmp); 108 107 return ctrl == tmp; 109 108 } 110 109 ··· 138 137 return; 139 138 } 140 139 141 141 - rdmsrl(MSR_TEST_CTRL, msr_test_ctrl_cache); 140 140 + rdmsrq(MSR_TEST_CTRL, msr_test_ctrl_cache); 142 141 143 142 if (!split_lock_verify_msr(true)) { 144 143 pr_info("MSR access failed: Disabled\n"); ··· 146 145 } 147 146 148 147 /* Restore the MSR to its cached value. */ 149 149 - wrmsrl(MSR_TEST_CTRL, msr_test_ctrl_cache); 148 148 + wrmsrq(MSR_TEST_CTRL, msr_test_ctrl_cache); 150 149 151 150 setup_force_cpu_cap(X86_FEATURE_SPLIT_LOCK_DETECT); 152 151 } ··· 163 162 if (on) 164 163 test_ctrl_val |= MSR_TEST_CTRL_SPLIT_LOCK_DETECT; 165 164 166 166 - wrmsrl(MSR_TEST_CTRL, test_ctrl_val); 165 165 + wrmsrq(MSR_TEST_CTRL, test_ctrl_val); 167 166 } 168 167 169 168 void split_lock_init(void) ··· 298 297 if (!boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT)) 299 298 return; 300 299 301 301 - rdmsrl(MSR_IA32_DEBUGCTLMSR, val); 300 300 + rdmsrq(MSR_IA32_DEBUGCTLMSR, val); 302 301 303 302 if ((boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT) && 304 303 (sld_state == sld_warn || sld_state == sld_fatal)) || ··· 312 311 val |= DEBUGCTLMSR_BUS_LOCK_DETECT; 313 312 } 314 313 315 315 - wrmsrl(MSR_IA32_DEBUGCTLMSR, val); 314 314 + wrmsrq(MSR_IA32_DEBUGCTLMSR, val); 316 315 } 317 316 318 317 bool handle_user_split_lock(struct pt_regs *regs, long error_code) ··· 376 375 * MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT is. All CPUs that set 377 376 * it have split lock detection. 378 377 */ 379 379 - rdmsrl(MSR_IA32_CORE_CAPS, ia32_core_caps); 378 378 + rdmsrq(MSR_IA32_CORE_CAPS, ia32_core_caps); 380 379 if (ia32_core_caps & MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT) 381 380 goto supported; 382 381

+39 -39

arch/x86/kernel/cpu/common.c

reviewed

··· 148 148 */ 149 149 info = (struct ppin_info *)id->driver_data; 150 150 151 151 - if (rdmsrl_safe(info->msr_ppin_ctl, &val)) 151 151 + if (rdmsrq_safe(info->msr_ppin_ctl, &val)) 152 152 goto clear_ppin; 153 153 154 154 if ((val & 3UL) == 1UL) { ··· 158 158 159 159 /* If PPIN is disabled, try to enable */ 160 160 if (!(val & 2UL)) { 161 161 - wrmsrl_safe(info->msr_ppin_ctl, val | 2UL); 162 162 - rdmsrl_safe(info->msr_ppin_ctl, &val); 161 161 + wrmsrq_safe(info->msr_ppin_ctl, val | 2UL); 162 162 + rdmsrq_safe(info->msr_ppin_ctl, &val); 163 163 } 164 164 165 165 /* Is the enable bit set? */ 166 166 if (val & 2UL) { 167 167 - c->ppin = __rdmsr(info->msr_ppin); 167 167 + c->ppin = native_rdmsrq(info->msr_ppin); 168 168 set_cpu_cap(c, info->feature); 169 169 return; 170 170 } ··· 563 563 u64 msr = 0; 564 564 565 565 if (cpu_feature_enabled(X86_FEATURE_IBT)) { 566 566 - rdmsrl(MSR_IA32_S_CET, msr); 566 566 + rdmsrq(MSR_IA32_S_CET, msr); 567 567 if (disable) 568 568 - wrmsrl(MSR_IA32_S_CET, msr & ~CET_ENDBR_EN); 568 568 + wrmsrq(MSR_IA32_S_CET, msr & ~CET_ENDBR_EN); 569 569 } 570 570 571 571 return msr; ··· 576 576 u64 msr; 577 577 578 578 if (cpu_feature_enabled(X86_FEATURE_IBT)) { 579 579 - rdmsrl(MSR_IA32_S_CET, msr); 579 579 + rdmsrq(MSR_IA32_S_CET, msr); 580 580 msr &= ~CET_ENDBR_EN; 581 581 msr |= (save & CET_ENDBR_EN); 582 582 - wrmsrl(MSR_IA32_S_CET, msr); 582 582 + wrmsrq(MSR_IA32_S_CET, msr); 583 583 } 584 584 } 585 585 ··· 603 603 set_cpu_cap(c, X86_FEATURE_USER_SHSTK); 604 604 605 605 if (kernel_ibt) 606 606 - wrmsrl(MSR_IA32_S_CET, CET_ENDBR_EN); 606 606 + wrmsrq(MSR_IA32_S_CET, CET_ENDBR_EN); 607 607 else 608 608 - wrmsrl(MSR_IA32_S_CET, 0); 608 608 + wrmsrq(MSR_IA32_S_CET, 0); 609 609 610 610 cr4_set_bits(X86_CR4_CET); 611 611 612 612 if (kernel_ibt && ibt_selftest()) { 613 613 pr_err("IBT selftest: Failed!\n"); 614 614 - wrmsrl(MSR_IA32_S_CET, 0); 614 614 + wrmsrq(MSR_IA32_S_CET, 0); 615 615 setup_clear_cpu_cap(X86_FEATURE_IBT); 616 616 } 617 617 } ··· 622 622 cpu_feature_enabled(X86_FEATURE_SHSTK))) 623 623 return; 624 624 625 625 - wrmsrl(MSR_IA32_S_CET, 0); 626 626 - wrmsrl(MSR_IA32_U_CET, 0); 625 625 + wrmsrq(MSR_IA32_S_CET, 0); 626 626 + wrmsrq(MSR_IA32_U_CET, 0); 627 627 } 628 628 629 629 /* ··· 752 752 * No need to load %gs. It is already correct. 753 753 * 754 754 * Writing %gs on 64bit would zero GSBASE which would make any per 755 755 - * CPU operation up to the point of the wrmsrl() fault. 755 755 + * CPU operation up to the point of the wrmsrq() fault. 756 756 * 757 757 - * Set GSBASE to the new offset. Until the wrmsrl() happens the 757 757 + * Set GSBASE to the new offset. Until the wrmsrq() happens the 758 758 * early mapping is still valid. That means the GSBASE update will 759 759 * lose any prior per CPU data which was not copied over in 760 760 * setup_per_cpu_areas(). ··· 762 762 * This works even with stackprotector enabled because the 763 763 * per CPU stack canary is 0 in both per CPU areas. 764 764 */ 765 765 - wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu)); 765 765 + wrmsrq(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu)); 766 766 #else 767 767 /* 768 768 * %fs is already set to __KERNEL_PERCPU, but after switching GDT ··· 1290 1290 u64 x86_arch_cap_msr = 0; 1291 1291 1292 1292 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 1293 1293 - rdmsrl(MSR_IA32_ARCH_CAPABILITIES, x86_arch_cap_msr); 1293 1293 + rdmsrq(MSR_IA32_ARCH_CAPABILITIES, x86_arch_cap_msr); 1294 1294 1295 1295 return x86_arch_cap_msr; 1296 1296 } ··· 1788 1788 */ 1789 1789 1790 1790 unsigned long old_base, tmp; 1791 1791 - rdmsrl(MSR_FS_BASE, old_base); 1792 1792 - wrmsrl(MSR_FS_BASE, 1); 1791 1791 + rdmsrq(MSR_FS_BASE, old_base); 1792 1792 + wrmsrq(MSR_FS_BASE, 1); 1793 1793 loadsegment(fs, 0); 1794 1794 - rdmsrl(MSR_FS_BASE, tmp); 1795 1795 - wrmsrl(MSR_FS_BASE, old_base); 1794 1794 + rdmsrq(MSR_FS_BASE, tmp); 1795 1795 + wrmsrq(MSR_FS_BASE, old_base); 1796 1796 return tmp == 0; 1797 1797 } 1798 1798 ··· 2021 2021 */ 2022 2022 2023 2023 tss->x86_tss.ss1 = __KERNEL_CS; 2024 2024 - wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); 2025 2025 - wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0); 2026 2026 - wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); 2024 2024 + wrmsrq(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1); 2025 2025 + wrmsrq(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1)); 2026 2026 + wrmsrq(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32); 2027 2027 2028 2028 put_cpu(); 2029 2029 } ··· 2130 2130 DEFINE_PER_CPU_CACHE_HOT(u64, __x86_call_depth); 2131 2131 EXPORT_PER_CPU_SYMBOL(__x86_call_depth); 2132 2132 2133 2133 - static void wrmsrl_cstar(unsigned long val) 2133 2133 + static void wrmsrq_cstar(unsigned long val) 2134 2134 { 2135 2135 /* 2136 2136 * Intel CPUs do not support 32-bit SYSCALL. Writing to MSR_CSTAR ··· 2138 2138 * guest. Avoid the pointless write on all Intel CPUs. 2139 2139 */ 2140 2140 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 2141 2141 - wrmsrl(MSR_CSTAR, val); 2141 2141 + wrmsrq(MSR_CSTAR, val); 2142 2142 } 2143 2143 2144 2144 static inline void idt_syscall_init(void) 2145 2145 { 2146 2146 - wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); 2146 2146 + wrmsrq(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); 2147 2147 2148 2148 if (ia32_enabled()) { 2149 2149 - wrmsrl_cstar((unsigned long)entry_SYSCALL_compat); 2149 2149 + wrmsrq_cstar((unsigned long)entry_SYSCALL_compat); 2150 2150 /* 2151 2151 * This only works on Intel CPUs. 2152 2152 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. 2153 2153 * This does not cause SYSENTER to jump to the wrong location, because 2154 2154 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). 2155 2155 */ 2156 2156 - wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 2157 2157 - wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 2156 2156 + wrmsrq_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); 2157 2157 + wrmsrq_safe(MSR_IA32_SYSENTER_ESP, 2158 2158 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1)); 2159 2159 - wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); 2159 2159 + wrmsrq_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); 2160 2160 } else { 2161 2161 - wrmsrl_cstar((unsigned long)entry_SYSCALL32_ignore); 2162 2162 - wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); 2163 2163 - wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 2164 2164 - wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); 2161 2161 + wrmsrq_cstar((unsigned long)entry_SYSCALL32_ignore); 2162 2162 + wrmsrq_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); 2163 2163 + wrmsrq_safe(MSR_IA32_SYSENTER_ESP, 0ULL); 2164 2164 + wrmsrq_safe(MSR_IA32_SYSENTER_EIP, 0ULL); 2165 2165 } 2166 2166 2167 2167 /* 2168 2168 * Flags to clear on syscall; clear as much as possible 2169 2169 * to minimize user space-kernel interference. 2170 2170 */ 2171 2171 - wrmsrl(MSR_SYSCALL_MASK, 2171 2171 + wrmsrq(MSR_SYSCALL_MASK, 2172 2172 X86_EFLAGS_CF|X86_EFLAGS_PF|X86_EFLAGS_AF| 2173 2173 X86_EFLAGS_ZF|X86_EFLAGS_SF|X86_EFLAGS_TF| 2174 2174 X86_EFLAGS_IF|X86_EFLAGS_DF|X86_EFLAGS_OF| ··· 2237 2237 struct desc_struct d = { }; 2238 2238 2239 2239 if (boot_cpu_has(X86_FEATURE_RDTSCP) || boot_cpu_has(X86_FEATURE_RDPID)) 2240 2240 - wrmsr(MSR_TSC_AUX, cpudata, 0); 2240 2240 + wrmsrq(MSR_TSC_AUX, cpudata); 2241 2241 2242 2242 /* Store CPU and node number in limit. */ 2243 2243 d.limit0 = cpudata; ··· 2352 2352 memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); 2353 2353 syscall_init(); 2354 2354 2355 2355 - wrmsrl(MSR_FS_BASE, 0); 2356 2356 - wrmsrl(MSR_KERNEL_GS_BASE, 0); 2355 2355 + wrmsrq(MSR_FS_BASE, 0); 2356 2356 + wrmsrq(MSR_KERNEL_GS_BASE, 0); 2357 2357 barrier(); 2358 2358 2359 2359 x2apic_setup();

+3 -2

arch/x86/kernel/cpu/feat_ctl.c

reviewed

··· 4 4 #include <asm/cpu.h> 5 5 #include <asm/cpufeature.h> 6 6 #include <asm/msr-index.h> 7 7 + #include <asm/msr.h> 7 8 #include <asm/processor.h> 8 9 #include <asm/vmx.h> 9 10 ··· 119 118 bool enable_vmx; 120 119 u64 msr; 121 120 122 122 - if (rdmsrl_safe(MSR_IA32_FEAT_CTL, &msr)) { 121 121 + if (rdmsrq_safe(MSR_IA32_FEAT_CTL, &msr)) { 123 122 clear_cpu_cap(c, X86_FEATURE_VMX); 124 123 clear_cpu_cap(c, X86_FEATURE_SGX); 125 124 return; ··· 166 165 msr |= FEAT_CTL_SGX_LC_ENABLED; 167 166 } 168 167 169 169 - wrmsrl(MSR_IA32_FEAT_CTL, msr); 168 168 + wrmsrq(MSR_IA32_FEAT_CTL, msr); 170 169 171 170 update_caps: 172 171 set_cpu_cap(c, X86_FEATURE_MSR_IA32_FEAT_CTL);

+4 -3

arch/x86/kernel/cpu/hygon.c

reviewed

··· 15 15 #include <asm/cacheinfo.h> 16 16 #include <asm/spec-ctrl.h> 17 17 #include <asm/delay.h> 18 18 + #include <asm/msr.h> 18 19 19 20 #include "cpu.h" 20 21 ··· 97 96 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { 98 97 u64 val; 99 98 100 100 - rdmsrl(MSR_K7_HWCR, val); 99 99 + rdmsrq(MSR_K7_HWCR, val); 101 100 if (!(val & BIT(24))) 102 101 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n"); 103 102 } ··· 111 110 * Try to cache the base value so further operations can 112 111 * avoid RMW. If that faults, do not enable SSBD. 113 112 */ 114 114 - if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) { 113 113 + if (!rdmsrq_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) { 115 114 setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD); 116 115 setup_force_cpu_cap(X86_FEATURE_SSBD); 117 116 x86_amd_ls_cfg_ssbd_mask = 1ULL << 10; ··· 195 194 init_hygon_cacheinfo(c); 196 195 197 196 if (cpu_has(c, X86_FEATURE_SVM)) { 198 198 - rdmsrl(MSR_VM_CR, vm_cr); 197 197 + rdmsrq(MSR_VM_CR, vm_cr); 199 198 if (vm_cr & SVM_VM_CR_SVM_DIS_MASK) { 200 199 pr_notice_once("SVM disabled (by BIOS) in MSR_VM_CR\n"); 201 200 clear_cpu_cap(c, X86_FEATURE_SVM);

+5 -5

arch/x86/kernel/cpu/intel.c

reviewed

··· 159 159 u64 tme_activate; 160 160 int keyid_bits; 161 161 162 162 - rdmsrl(MSR_IA32_TME_ACTIVATE, tme_activate); 162 162 + rdmsrq(MSR_IA32_TME_ACTIVATE, tme_activate); 163 163 164 164 if (!TME_ACTIVATE_LOCKED(tme_activate) || !TME_ACTIVATE_ENABLED(tme_activate)) { 165 165 pr_info_once("x86/tme: not enabled by BIOS\n"); ··· 301 301 * string flag and enhanced fast string capabilities accordingly. 302 302 */ 303 303 if (c->x86_vfm >= INTEL_PENTIUM_M_DOTHAN) { 304 304 - rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); 304 304 + rdmsrq(MSR_IA32_MISC_ENABLE, misc_enable); 305 305 if (misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) { 306 306 /* X86_FEATURE_ERMS is set based on CPUID */ 307 307 set_cpu_cap(c, X86_FEATURE_REP_GOOD); ··· 490 490 { 491 491 u64 msr; 492 492 493 493 - if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) { 493 493 + if (!rdmsrq_safe(MSR_PLATFORM_INFO, &msr)) { 494 494 if (msr & MSR_PLATFORM_INFO_CPUID_FAULT) 495 495 set_cpu_cap(c, X86_FEATURE_CPUID_FAULT); 496 496 } ··· 500 500 { 501 501 u64 msr; 502 502 503 503 - if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr)) 503 503 + if (rdmsrq_safe(MSR_MISC_FEATURES_ENABLES, &msr)) 504 504 return; 505 505 506 506 /* Clear all MISC features */ ··· 511 511 probe_xeon_phi_r3mwait(c); 512 512 513 513 msr = this_cpu_read(msr_misc_features_shadow); 514 514 - wrmsrl(MSR_MISC_FEATURES_ENABLES, msr); 514 514 + wrmsrq(MSR_MISC_FEATURES_ENABLES, msr); 515 515 } 516 516 517 517 /*

+6 -6

arch/x86/kernel/cpu/intel_epb.c

reviewed

··· 79 79 { 80 80 u64 epb; 81 81 82 82 - rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb); 82 82 + rdmsrq(MSR_IA32_ENERGY_PERF_BIAS, epb); 83 83 /* 84 84 * Ensure that saved_epb will always be nonzero after this write even if 85 85 * the EPB value read from the MSR is 0. ··· 94 94 u64 val = this_cpu_read(saved_epb); 95 95 u64 epb; 96 96 97 97 - rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb); 97 97 + rdmsrq(MSR_IA32_ENERGY_PERF_BIAS, epb); 98 98 if (val) { 99 99 val &= EPB_MASK; 100 100 } else { ··· 111 111 pr_warn_once("ENERGY_PERF_BIAS: Set to 'normal', was 'performance'\n"); 112 112 } 113 113 } 114 114 - wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, (epb & ~EPB_MASK) | val); 114 114 + wrmsrq(MSR_IA32_ENERGY_PERF_BIAS, (epb & ~EPB_MASK) | val); 115 115 } 116 116 117 117 static struct syscore_ops intel_epb_syscore_ops = { ··· 135 135 u64 epb; 136 136 int ret; 137 137 138 138 - ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 138 138 + ret = rdmsrq_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 139 139 if (ret < 0) 140 140 return ret; 141 141 ··· 157 157 else if (kstrtou64(buf, 0, &val) || val > MAX_EPB) 158 158 return -EINVAL; 159 159 160 160 - ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 160 160 + ret = rdmsrq_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 161 161 if (ret < 0) 162 162 return ret; 163 163 164 164 - ret = wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, 164 164 + ret = wrmsrq_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, 165 165 (epb & ~EPB_MASK) | val); 166 166 if (ret < 0) 167 167 return ret;

+11 -11

arch/x86/kernel/cpu/mce/amd.c

reviewed

··· 662 662 return; 663 663 } 664 664 665 665 - rdmsrl(MSR_K7_HWCR, hwcr); 665 665 + rdmsrq(MSR_K7_HWCR, hwcr); 666 666 667 667 /* McStatusWrEn has to be set */ 668 668 need_toggle = !(hwcr & BIT(18)); 669 669 if (need_toggle) 670 670 - wrmsrl(MSR_K7_HWCR, hwcr | BIT(18)); 670 670 + wrmsrq(MSR_K7_HWCR, hwcr | BIT(18)); 671 671 672 672 /* Clear CntP bit safely */ 673 673 for (i = 0; i < num_msrs; i++) ··· 675 675 676 676 /* restore old settings */ 677 677 if (need_toggle) 678 678 - wrmsrl(MSR_K7_HWCR, hwcr); 678 678 + wrmsrq(MSR_K7_HWCR, hwcr); 679 679 } 680 680 681 681 /* cpu init entry point, called from mce.c with preempt off */ ··· 805 805 } 806 806 807 807 if (mce_flags.smca) { 808 808 - rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m->ipid); 808 808 + rdmsrq(MSR_AMD64_SMCA_MCx_IPID(bank), m->ipid); 809 809 810 810 if (m->status & MCI_STATUS_SYNDV) { 811 811 - rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m->synd); 812 812 - rdmsrl(MSR_AMD64_SMCA_MCx_SYND1(bank), err.vendor.amd.synd1); 813 813 - rdmsrl(MSR_AMD64_SMCA_MCx_SYND2(bank), err.vendor.amd.synd2); 811 811 + rdmsrq(MSR_AMD64_SMCA_MCx_SYND(bank), m->synd); 812 812 + rdmsrq(MSR_AMD64_SMCA_MCx_SYND1(bank), err.vendor.amd.synd1); 813 813 + rdmsrq(MSR_AMD64_SMCA_MCx_SYND2(bank), err.vendor.amd.synd2); 814 814 } 815 815 } 816 816 ··· 834 834 { 835 835 u64 status, addr = 0; 836 836 837 837 - rdmsrl(msr_stat, status); 837 837 + rdmsrq(msr_stat, status); 838 838 if (!(status & MCI_STATUS_VAL)) 839 839 return false; 840 840 841 841 if (status & MCI_STATUS_ADDRV) 842 842 - rdmsrl(msr_addr, addr); 842 842 + rdmsrq(msr_addr, addr); 843 843 844 844 __log_error(bank, status, addr, misc); 845 845 846 846 - wrmsrl(msr_stat, 0); 846 846 + wrmsrq(msr_stat, 0); 847 847 848 848 return status & MCI_STATUS_DEFERRED; 849 849 } ··· 862 862 return true; 863 863 864 864 /* Clear MCA_DESTAT if the deferred error was logged from MCA_STATUS. */ 865 865 - wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0); 865 865 + wrmsrq(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0); 866 866 return true; 867 867 } 868 868

+33 -33

arch/x86/kernel/cpu/mce/core.c

reviewed

··· 121 121 { 122 122 m->cpuid = cpuid_eax(1); 123 123 m->cpuvendor = boot_cpu_data.x86_vendor; 124 124 - m->mcgcap = __rdmsr(MSR_IA32_MCG_CAP); 124 124 + m->mcgcap = native_rdmsrq(MSR_IA32_MCG_CAP); 125 125 /* need the internal __ version to avoid deadlocks */ 126 126 m->time = __ktime_get_real_seconds(); 127 127 } ··· 388 388 } 389 389 390 390 /* MSR access wrappers used for error injection */ 391 391 - noinstr u64 mce_rdmsrl(u32 msr) 391 391 + noinstr u64 mce_rdmsrq(u32 msr) 392 392 { 393 393 - DECLARE_ARGS(val, low, high); 393 393 + EAX_EDX_DECLARE_ARGS(val, low, high); 394 394 395 395 if (__this_cpu_read(injectm.finished)) { 396 396 int offset; ··· 423 423 return EAX_EDX_VAL(val, low, high); 424 424 } 425 425 426 426 - static noinstr void mce_wrmsrl(u32 msr, u64 v) 426 426 + static noinstr void mce_wrmsrq(u32 msr, u64 v) 427 427 { 428 428 u32 low, high; 429 429 ··· 444 444 low = (u32)v; 445 445 high = (u32)(v >> 32); 446 446 447 447 - /* See comment in mce_rdmsrl() */ 447 447 + /* See comment in mce_rdmsrq() */ 448 448 asm volatile("1: wrmsr\n" 449 449 "2:\n" 450 450 _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_WRMSR_IN_MCE) ··· 468 468 instrumentation_end(); 469 469 470 470 m = &err->m; 471 471 - m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); 471 471 + m->mcgstatus = mce_rdmsrq(MSR_IA32_MCG_STATUS); 472 472 if (regs) { 473 473 /* 474 474 * Get the address of the instruction at the time of ··· 488 488 } 489 489 /* Use accurate RIP reporting if available. */ 490 490 if (mca_cfg.rip_msr) 491 491 - m->ip = mce_rdmsrl(mca_cfg.rip_msr); 491 491 + m->ip = mce_rdmsrq(mca_cfg.rip_msr); 492 492 } 493 493 } 494 494 ··· 684 684 struct mce *m = &err->m; 685 685 686 686 if (m->status & MCI_STATUS_MISCV) 687 687 - m->misc = mce_rdmsrl(mca_msr_reg(i, MCA_MISC)); 687 687 + m->misc = mce_rdmsrq(mca_msr_reg(i, MCA_MISC)); 688 688 689 689 if (m->status & MCI_STATUS_ADDRV) { 690 690 - m->addr = mce_rdmsrl(mca_msr_reg(i, MCA_ADDR)); 690 690 + m->addr = mce_rdmsrq(mca_msr_reg(i, MCA_ADDR)); 691 691 692 692 /* 693 693 * Mask the reported address by the reported granularity. ··· 702 702 } 703 703 704 704 if (mce_flags.smca) { 705 705 - m->ipid = mce_rdmsrl(MSR_AMD64_SMCA_MCx_IPID(i)); 705 705 + m->ipid = mce_rdmsrq(MSR_AMD64_SMCA_MCx_IPID(i)); 706 706 707 707 if (m->status & MCI_STATUS_SYNDV) { 708 708 - m->synd = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND(i)); 709 709 - err->vendor.amd.synd1 = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND1(i)); 710 710 - err->vendor.amd.synd2 = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND2(i)); 708 708 + m->synd = mce_rdmsrq(MSR_AMD64_SMCA_MCx_SYND(i)); 709 709 + err->vendor.amd.synd1 = mce_rdmsrq(MSR_AMD64_SMCA_MCx_SYND1(i)); 710 710 + err->vendor.amd.synd2 = mce_rdmsrq(MSR_AMD64_SMCA_MCx_SYND2(i)); 711 711 } 712 712 } 713 713 } ··· 753 753 m->bank = i; 754 754 755 755 barrier(); 756 756 - m->status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS)); 756 756 + m->status = mce_rdmsrq(mca_msr_reg(i, MCA_STATUS)); 757 757 758 758 /* 759 759 * Update storm tracking here, before checking for the ··· 829 829 /* 830 830 * Clear state for this bank. 831 831 */ 832 832 - mce_wrmsrl(mca_msr_reg(i, MCA_STATUS), 0); 832 832 + mce_wrmsrq(mca_msr_reg(i, MCA_STATUS), 0); 833 833 } 834 834 835 835 /* ··· 887 887 */ 888 888 static noinstr bool quirk_skylake_repmov(void) 889 889 { 890 890 - u64 mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); 891 891 - u64 misc_enable = mce_rdmsrl(MSR_IA32_MISC_ENABLE); 890 890 + u64 mcgstatus = mce_rdmsrq(MSR_IA32_MCG_STATUS); 891 891 + u64 misc_enable = mce_rdmsrq(MSR_IA32_MISC_ENABLE); 892 892 u64 mc1_status; 893 893 894 894 /* ··· 899 899 !(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) 900 900 return false; 901 901 902 902 - mc1_status = mce_rdmsrl(MSR_IA32_MCx_STATUS(1)); 902 902 + mc1_status = mce_rdmsrq(MSR_IA32_MCx_STATUS(1)); 903 903 904 904 /* Check for a software-recoverable data fetch error. */ 905 905 if ((mc1_status & ··· 910 910 MCI_STATUS_ADDRV | MCI_STATUS_MISCV | 911 911 MCI_STATUS_AR | MCI_STATUS_S)) { 912 912 misc_enable &= ~MSR_IA32_MISC_ENABLE_FAST_STRING; 913 913 - mce_wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable); 914 914 - mce_wrmsrl(MSR_IA32_MCx_STATUS(1), 0); 913 913 + mce_wrmsrq(MSR_IA32_MISC_ENABLE, misc_enable); 914 914 + mce_wrmsrq(MSR_IA32_MCx_STATUS(1), 0); 915 915 916 916 instrumentation_begin(); 917 917 pr_err_once("Erratum detected, disable fast string copy instructions.\n"); ··· 955 955 int i; 956 956 957 957 for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 958 958 - m->status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS)); 958 958 + m->status = mce_rdmsrq(mca_msr_reg(i, MCA_STATUS)); 959 959 if (!(m->status & MCI_STATUS_VAL)) 960 960 continue; 961 961 ··· 1274 1274 1275 1275 for (i = 0; i < this_cpu_read(mce_num_banks); i++) { 1276 1276 if (arch_test_bit(i, toclear)) 1277 1277 - mce_wrmsrl(mca_msr_reg(i, MCA_STATUS), 0); 1277 1277 + mce_wrmsrq(mca_msr_reg(i, MCA_STATUS), 0); 1278 1278 } 1279 1279 } 1280 1280 ··· 1298 1298 (crashing_cpu != -1 && crashing_cpu != cpu)) { 1299 1299 u64 mcgstatus; 1300 1300 1301 1301 - mcgstatus = __rdmsr(MSR_IA32_MCG_STATUS); 1301 1301 + mcgstatus = native_rdmsrq(MSR_IA32_MCG_STATUS); 1302 1302 1303 1303 if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) { 1304 1304 if (mcgstatus & MCG_STATUS_LMCES) ··· 1306 1306 } 1307 1307 1308 1308 if (mcgstatus & MCG_STATUS_RIPV) { 1309 1309 - __wrmsr(MSR_IA32_MCG_STATUS, 0, 0); 1309 1309 + native_wrmsrq(MSR_IA32_MCG_STATUS, 0); 1310 1310 return true; 1311 1311 } 1312 1312 } ··· 1335 1335 m->addr = 0; 1336 1336 m->bank = i; 1337 1337 1338 1338 - m->status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS)); 1338 1338 + m->status = mce_rdmsrq(mca_msr_reg(i, MCA_STATUS)); 1339 1339 if (!(m->status & MCI_STATUS_VAL)) 1340 1340 continue; 1341 1341 ··· 1693 1693 instrumentation_end(); 1694 1694 1695 1695 clear: 1696 1696 - mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); 1696 1696 + mce_wrmsrq(MSR_IA32_MCG_STATUS, 0); 1697 1697 } 1698 1698 EXPORT_SYMBOL_GPL(do_machine_check); 1699 1699 ··· 1822 1822 u64 cap; 1823 1823 u8 b; 1824 1824 1825 1825 - rdmsrl(MSR_IA32_MCG_CAP, cap); 1825 1825 + rdmsrq(MSR_IA32_MCG_CAP, cap); 1826 1826 1827 1827 b = cap & MCG_BANKCNT_MASK; 1828 1828 ··· 1863 1863 1864 1864 cr4_set_bits(X86_CR4_MCE); 1865 1865 1866 1866 - rdmsrl(MSR_IA32_MCG_CAP, cap); 1866 1866 + rdmsrq(MSR_IA32_MCG_CAP, cap); 1867 1867 if (cap & MCG_CTL_P) 1868 1868 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); 1869 1869 } ··· 1878 1878 1879 1879 if (!b->init) 1880 1880 continue; 1881 1881 - wrmsrl(mca_msr_reg(i, MCA_CTL), b->ctl); 1882 1882 - wrmsrl(mca_msr_reg(i, MCA_STATUS), 0); 1881 1881 + wrmsrq(mca_msr_reg(i, MCA_CTL), b->ctl); 1882 1882 + wrmsrq(mca_msr_reg(i, MCA_STATUS), 0); 1883 1883 } 1884 1884 } 1885 1885 ··· 1905 1905 if (!b->init) 1906 1906 continue; 1907 1907 1908 1908 - rdmsrl(mca_msr_reg(i, MCA_CTL), msrval); 1908 1908 + rdmsrq(mca_msr_reg(i, MCA_CTL), msrval); 1909 1909 b->init = !!msrval; 1910 1910 } 1911 1911 } ··· 2436 2436 struct mce_bank *b = &mce_banks[i]; 2437 2437 2438 2438 if (b->init) 2439 2439 - wrmsrl(mca_msr_reg(i, MCA_CTL), 0); 2439 2439 + wrmsrq(mca_msr_reg(i, MCA_CTL), 0); 2440 2440 } 2441 2441 return; 2442 2442 } ··· 2786 2786 struct mce_bank *b = &mce_banks[i]; 2787 2787 2788 2788 if (b->init) 2789 2789 - wrmsrl(mca_msr_reg(i, MCA_CTL), b->ctl); 2789 2789 + wrmsrq(mca_msr_reg(i, MCA_CTL), b->ctl); 2790 2790 } 2791 2791 } 2792 2792

+17 -16

arch/x86/kernel/cpu/mce/inject.c

reviewed

··· 28 28 #include <asm/apic.h> 29 29 #include <asm/irq_vectors.h> 30 30 #include <asm/mce.h> 31 31 + #include <asm/msr.h> 31 32 #include <asm/nmi.h> 32 33 #include <asm/smp.h> 33 34 ··· 476 475 struct mce m = *(struct mce *)info; 477 476 u8 b = m.bank; 478 477 479 479 - wrmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus); 478 478 + wrmsrq(MSR_IA32_MCG_STATUS, m.mcgstatus); 480 479 481 480 if (boot_cpu_has(X86_FEATURE_SMCA)) { 482 481 if (m.inject_flags == DFR_INT_INJ) { 483 483 - wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(b), m.status); 484 484 - wrmsrl(MSR_AMD64_SMCA_MCx_DEADDR(b), m.addr); 482 482 + wrmsrq(MSR_AMD64_SMCA_MCx_DESTAT(b), m.status); 483 483 + wrmsrq(MSR_AMD64_SMCA_MCx_DEADDR(b), m.addr); 485 484 } else { 486 486 - wrmsrl(MSR_AMD64_SMCA_MCx_STATUS(b), m.status); 487 487 - wrmsrl(MSR_AMD64_SMCA_MCx_ADDR(b), m.addr); 485 485 + wrmsrq(MSR_AMD64_SMCA_MCx_STATUS(b), m.status); 486 486 + wrmsrq(MSR_AMD64_SMCA_MCx_ADDR(b), m.addr); 488 487 } 489 488 490 490 - wrmsrl(MSR_AMD64_SMCA_MCx_SYND(b), m.synd); 489 489 + wrmsrq(MSR_AMD64_SMCA_MCx_SYND(b), m.synd); 491 490 492 491 if (m.misc) 493 493 - wrmsrl(MSR_AMD64_SMCA_MCx_MISC(b), m.misc); 492 492 + wrmsrq(MSR_AMD64_SMCA_MCx_MISC(b), m.misc); 494 493 } else { 495 495 - wrmsrl(MSR_IA32_MCx_STATUS(b), m.status); 496 496 - wrmsrl(MSR_IA32_MCx_ADDR(b), m.addr); 494 494 + wrmsrq(MSR_IA32_MCx_STATUS(b), m.status); 495 495 + wrmsrq(MSR_IA32_MCx_ADDR(b), m.addr); 497 496 498 497 if (m.misc) 499 499 - wrmsrl(MSR_IA32_MCx_MISC(b), m.misc); 498 498 + wrmsrq(MSR_IA32_MCx_MISC(b), m.misc); 500 499 } 501 500 } 502 501 ··· 590 589 u64 cap; 591 590 592 591 /* Get bank count on target CPU so we can handle non-uniform values. */ 593 593 - rdmsrl_on_cpu(m->extcpu, MSR_IA32_MCG_CAP, &cap); 592 592 + rdmsrq_on_cpu(m->extcpu, MSR_IA32_MCG_CAP, &cap); 594 593 n_banks = cap & MCG_BANKCNT_MASK; 595 594 596 595 if (val >= n_banks) { ··· 614 613 if (cpu_feature_enabled(X86_FEATURE_SMCA)) { 615 614 u64 ipid; 616 615 617 617 - if (rdmsrl_on_cpu(m->extcpu, MSR_AMD64_SMCA_MCx_IPID(val), &ipid)) { 616 616 + if (rdmsrq_on_cpu(m->extcpu, MSR_AMD64_SMCA_MCx_IPID(val), &ipid)) { 618 617 pr_err("Error reading IPID on CPU%d\n", m->extcpu); 619 618 return -EINVAL; 620 619 } ··· 742 741 u64 status = MCI_STATUS_VAL, ipid; 743 742 744 743 /* Check whether bank is populated */ 745 745 - rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), ipid); 744 744 + rdmsrq(MSR_AMD64_SMCA_MCx_IPID(bank), ipid); 746 745 if (!ipid) 747 746 continue; 748 747 749 748 toggle_hw_mce_inject(cpu, true); 750 749 751 751 - wrmsrl_safe(mca_msr_reg(bank, MCA_STATUS), status); 752 752 - rdmsrl_safe(mca_msr_reg(bank, MCA_STATUS), &status); 753 753 - wrmsrl_safe(mca_msr_reg(bank, MCA_STATUS), 0); 750 750 + wrmsrq_safe(mca_msr_reg(bank, MCA_STATUS), status); 751 751 + rdmsrq_safe(mca_msr_reg(bank, MCA_STATUS), &status); 752 752 + wrmsrq_safe(mca_msr_reg(bank, MCA_STATUS), 0); 754 753 755 754 if (!status) { 756 755 hw_injection_possible = false;

+16 -16

arch/x86/kernel/cpu/mce/intel.c

reviewed

··· 94 94 if (!boot_cpu_has(X86_FEATURE_APIC) || lapic_get_maxlvt() < 6) 95 95 return false; 96 96 97 97 - rdmsrl(MSR_IA32_MCG_CAP, cap); 97 97 + rdmsrq(MSR_IA32_MCG_CAP, cap); 98 98 *banks = min_t(unsigned, MAX_NR_BANKS, cap & MCG_BANKCNT_MASK); 99 99 return !!(cap & MCG_CMCI_P); 100 100 } ··· 106 106 if (mca_cfg.lmce_disabled) 107 107 return false; 108 108 109 109 - rdmsrl(MSR_IA32_MCG_CAP, tmp); 109 109 + rdmsrq(MSR_IA32_MCG_CAP, tmp); 110 110 111 111 /* 112 112 * LMCE depends on recovery support in the processor. Hence both ··· 123 123 * WARN if the MSR isn't locked as init_ia32_feat_ctl() unconditionally 124 124 * locks the MSR in the event that it wasn't already locked by BIOS. 125 125 */ 126 126 - rdmsrl(MSR_IA32_FEAT_CTL, tmp); 126 126 + rdmsrq(MSR_IA32_FEAT_CTL, tmp); 127 127 if (WARN_ON_ONCE(!(tmp & FEAT_CTL_LOCKED))) 128 128 return false; 129 129 ··· 141 141 u64 val; 142 142 143 143 raw_spin_lock_irqsave(&cmci_discover_lock, flags); 144 144 - rdmsrl(MSR_IA32_MCx_CTL2(bank), val); 144 144 + rdmsrq(MSR_IA32_MCx_CTL2(bank), val); 145 145 val &= ~MCI_CTL2_CMCI_THRESHOLD_MASK; 146 146 - wrmsrl(MSR_IA32_MCx_CTL2(bank), val | thresh); 146 146 + wrmsrq(MSR_IA32_MCx_CTL2(bank), val | thresh); 147 147 raw_spin_unlock_irqrestore(&cmci_discover_lock, flags); 148 148 } 149 149 ··· 184 184 if (test_bit(bank, mce_banks_ce_disabled)) 185 185 return true; 186 186 187 187 - rdmsrl(MSR_IA32_MCx_CTL2(bank), *val); 187 187 + rdmsrq(MSR_IA32_MCx_CTL2(bank), *val); 188 188 189 189 /* Already owned by someone else? */ 190 190 if (*val & MCI_CTL2_CMCI_EN) { ··· 232 232 struct mca_storm_desc *storm = this_cpu_ptr(&storm_desc); 233 233 234 234 val |= MCI_CTL2_CMCI_EN; 235 235 - wrmsrl(MSR_IA32_MCx_CTL2(bank), val); 236 236 - rdmsrl(MSR_IA32_MCx_CTL2(bank), val); 235 235 + wrmsrq(MSR_IA32_MCx_CTL2(bank), val); 236 236 + rdmsrq(MSR_IA32_MCx_CTL2(bank), val); 237 237 238 238 /* If the enable bit did not stick, this bank should be polled. */ 239 239 if (!(val & MCI_CTL2_CMCI_EN)) { ··· 324 324 325 325 if (!test_bit(bank, this_cpu_ptr(mce_banks_owned))) 326 326 return; 327 327 - rdmsrl(MSR_IA32_MCx_CTL2(bank), val); 327 327 + rdmsrq(MSR_IA32_MCx_CTL2(bank), val); 328 328 val &= ~MCI_CTL2_CMCI_EN; 329 329 - wrmsrl(MSR_IA32_MCx_CTL2(bank), val); 329 329 + wrmsrq(MSR_IA32_MCx_CTL2(bank), val); 330 330 __clear_bit(bank, this_cpu_ptr(mce_banks_owned)); 331 331 332 332 if ((val & MCI_CTL2_CMCI_THRESHOLD_MASK) == CMCI_STORM_THRESHOLD) ··· 430 430 if (!lmce_supported()) 431 431 return; 432 432 433 433 - rdmsrl(MSR_IA32_MCG_EXT_CTL, val); 433 433 + rdmsrq(MSR_IA32_MCG_EXT_CTL, val); 434 434 435 435 if (!(val & MCG_EXT_CTL_LMCE_EN)) 436 436 - wrmsrl(MSR_IA32_MCG_EXT_CTL, val | MCG_EXT_CTL_LMCE_EN); 436 436 + wrmsrq(MSR_IA32_MCG_EXT_CTL, val | MCG_EXT_CTL_LMCE_EN); 437 437 } 438 438 439 439 void intel_clear_lmce(void) ··· 443 443 if (!lmce_supported()) 444 444 return; 445 445 446 446 - rdmsrl(MSR_IA32_MCG_EXT_CTL, val); 446 446 + rdmsrq(MSR_IA32_MCG_EXT_CTL, val); 447 447 val &= ~MCG_EXT_CTL_LMCE_EN; 448 448 - wrmsrl(MSR_IA32_MCG_EXT_CTL, val); 448 448 + wrmsrq(MSR_IA32_MCG_EXT_CTL, val); 449 449 } 450 450 451 451 /* ··· 460 460 case INTEL_SANDYBRIDGE_X: 461 461 case INTEL_IVYBRIDGE_X: 462 462 case INTEL_HASWELL_X: 463 463 - if (rdmsrl_safe(MSR_ERROR_CONTROL, &error_control)) 463 463 + if (rdmsrq_safe(MSR_ERROR_CONTROL, &error_control)) 464 464 return; 465 465 error_control |= 2; 466 466 - wrmsrl_safe(MSR_ERROR_CONTROL, error_control); 466 466 + wrmsrq_safe(MSR_ERROR_CONTROL, error_control); 467 467 break; 468 468 } 469 469 }

+1 -1

arch/x86/kernel/cpu/mce/internal.h

reviewed

··· 312 312 static __always_inline void winchip_machine_check(struct pt_regs *regs) {} 313 313 #endif 314 314 315 315 - noinstr u64 mce_rdmsrl(u32 msr); 315 315 + noinstr u64 mce_rdmsrq(u32 msr); 316 316 317 317 static __always_inline u32 mca_msr_reg(int bank, enum mca_msr reg) 318 318 {

+1 -1

arch/x86/kernel/cpu/microcode/amd.c

reviewed

··· 604 604 if (!verify_sha256_digest(mc->hdr.patch_id, *cur_rev, (const u8 *)p_addr, psize)) 605 605 return false; 606 606 607 607 - native_wrmsrl(MSR_AMD64_PATCH_LOADER, p_addr); 607 607 + native_wrmsrq(MSR_AMD64_PATCH_LOADER, p_addr); 608 608 609 609 if (x86_family(bsp_cpuid_1_eax) == 0x17) { 610 610 unsigned long p_addr_end = p_addr + psize - 1;

+1

arch/x86/kernel/cpu/microcode/core.c

reviewed

··· 37 37 #include <asm/perf_event.h> 38 38 #include <asm/processor.h> 39 39 #include <asm/cmdline.h> 40 40 + #include <asm/msr.h> 40 41 #include <asm/setup.h> 41 42 42 43 #include "internal.h"

+1 -1

arch/x86/kernel/cpu/microcode/intel.c

reviewed

··· 320 320 } 321 321 322 322 /* write microcode via MSR 0x79 */ 323 323 - native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); 323 323 + native_wrmsrq(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); 324 324 325 325 rev = intel_get_microcode_revision(); 326 326 if (rev != mc->hdr.rev)

+7 -6

arch/x86/kernel/cpu/mshyperv.c

reviewed

··· 30 30 #include <asm/reboot.h> 31 31 #include <asm/nmi.h> 32 32 #include <clocksource/hyperv_timer.h> 33 33 + #include <asm/msr.h> 33 34 #include <asm/numa.h> 34 35 #include <asm/svm.h> 35 36 ··· 71 70 if (hv_is_synic_msr(reg) && ms_hyperv.paravisor_present) 72 71 hv_ivm_msr_read(reg, &value); 73 72 else 74 74 - rdmsrl(reg, value); 73 73 + rdmsrq(reg, value); 75 74 return value; 76 75 } 77 76 EXPORT_SYMBOL_GPL(hv_get_non_nested_msr); ··· 83 82 84 83 /* Write proxy bit via wrmsl instruction */ 85 84 if (hv_is_sint_msr(reg)) 86 86 - wrmsrl(reg, value | 1 << 20); 85 85 + wrmsrq(reg, value | 1 << 20); 87 86 } else { 88 88 - wrmsrl(reg, value); 87 87 + wrmsrq(reg, value); 89 88 } 90 89 } 91 90 EXPORT_SYMBOL_GPL(hv_set_non_nested_msr); ··· 346 345 { 347 346 unsigned long freq; 348 347 349 349 - rdmsrl(HV_X64_MSR_TSC_FREQUENCY, freq); 348 348 + rdmsrq(HV_X64_MSR_TSC_FREQUENCY, freq); 350 349 351 350 return freq / 1000; 352 351 } ··· 542 541 */ 543 542 u64 hv_lapic_frequency; 544 543 545 545 - rdmsrl(HV_X64_MSR_APIC_FREQUENCY, hv_lapic_frequency); 544 544 + rdmsrq(HV_X64_MSR_APIC_FREQUENCY, hv_lapic_frequency); 546 545 hv_lapic_frequency = div_u64(hv_lapic_frequency, HZ); 547 546 lapic_timer_period = hv_lapic_frequency; 548 547 pr_info("Hyper-V: LAPIC Timer Frequency: %#x\n", ··· 575 574 * setting of this MSR bit should happen before init_intel() 576 575 * is called. 577 576 */ 578 578 - wrmsrl(HV_X64_MSR_TSC_INVARIANT_CONTROL, HV_EXPOSE_INVARIANT_TSC); 577 577 + wrmsrq(HV_X64_MSR_TSC_INVARIANT_CONTROL, HV_EXPOSE_INVARIANT_TSC); 579 578 setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE); 580 579 } 581 580

+6 -5

arch/x86/kernel/cpu/resctrl/core.c

reviewed

··· 22 22 #include <linux/cpuhotplug.h> 23 23 24 24 #include <asm/cpu_device_id.h> 25 25 + #include <asm/msr.h> 25 26 #include <asm/resctrl.h> 26 27 #include "internal.h" 27 28 ··· 146 145 struct rdt_resource *r = &hw_res->r_resctrl; 147 146 u64 max_cbm = BIT_ULL_MASK(20) - 1, l3_cbm_0; 148 147 149 149 - if (wrmsrl_safe(MSR_IA32_L3_CBM_BASE, max_cbm)) 148 148 + if (wrmsrq_safe(MSR_IA32_L3_CBM_BASE, max_cbm)) 150 149 return; 151 150 152 152 - rdmsrl(MSR_IA32_L3_CBM_BASE, l3_cbm_0); 151 151 + rdmsrq(MSR_IA32_L3_CBM_BASE, l3_cbm_0); 153 152 154 153 /* If all the bits were set in MSR, return success */ 155 154 if (l3_cbm_0 != max_cbm) ··· 310 309 unsigned int i; 311 310 312 311 for (i = m->low; i < m->high; i++) 313 313 - wrmsrl(hw_res->msr_base + i, hw_dom->ctrl_val[i]); 312 312 + wrmsrq(hw_res->msr_base + i, hw_dom->ctrl_val[i]); 314 313 } 315 314 316 315 /* ··· 335 334 336 335 /* Write the delay values for mba. */ 337 336 for (i = m->low; i < m->high; i++) 338 338 - wrmsrl(hw_res->msr_base + i, delay_bw_map(hw_dom->ctrl_val[i], m->res)); 337 337 + wrmsrq(hw_res->msr_base + i, delay_bw_map(hw_dom->ctrl_val[i], m->res)); 339 338 } 340 339 341 340 static void cat_wrmsr(struct msr_param *m) ··· 345 344 unsigned int i; 346 345 347 346 for (i = m->low; i < m->high; i++) 348 348 - wrmsrl(hw_res->msr_base + i, hw_dom->ctrl_val[i]); 347 347 + wrmsrq(hw_res->msr_base + i, hw_dom->ctrl_val[i]); 349 348 } 350 349 351 350 u32 resctrl_arch_get_num_closid(struct rdt_resource *r)

+2 -1

arch/x86/kernel/cpu/resctrl/monitor.c

reviewed

··· 23 23 #include <linux/slab.h> 24 24 25 25 #include <asm/cpu_device_id.h> 26 26 + #include <asm/msr.h> 26 27 #include <asm/resctrl.h> 27 28 28 29 #include "internal.h" ··· 239 238 * are error bits. 240 239 */ 241 240 wrmsr(MSR_IA32_QM_EVTSEL, eventid, prmid); 242 242 - rdmsrl(MSR_IA32_QM_CTR, msr_val); 241 241 + rdmsrq(MSR_IA32_QM_CTR, msr_val); 243 242 244 243 if (msr_val & RMID_VAL_ERROR) 245 244 return -EIO;

+14 -13

arch/x86/kernel/cpu/resctrl/pseudo_lock.c

reviewed

··· 25 25 #include <asm/cpu_device_id.h> 26 26 #include <asm/resctrl.h> 27 27 #include <asm/perf_event.h> 28 28 + #include <asm/msr.h> 28 29 29 30 #include "../../events/perf_event.h" /* For X86_CONFIG() */ 30 31 #include "internal.h" ··· 482 481 * the buffer and evict pseudo-locked memory read earlier from the 483 482 * cache. 484 483 */ 485 485 - saved_msr = __rdmsr(MSR_MISC_FEATURE_CONTROL); 486 486 - __wrmsr(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits, 0x0); 484 484 + saved_msr = native_rdmsrq(MSR_MISC_FEATURE_CONTROL); 485 485 + native_wrmsrq(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits); 487 486 closid_p = this_cpu_read(pqr_state.cur_closid); 488 487 rmid_p = this_cpu_read(pqr_state.cur_rmid); 489 488 mem_r = plr->kmem; ··· 495 494 * pseudo-locked followed by reading of kernel memory to load it 496 495 * into the cache. 497 496 */ 498 498 - __wrmsr(MSR_IA32_PQR_ASSOC, rmid_p, plr->closid); 497 497 + native_wrmsr(MSR_IA32_PQR_ASSOC, rmid_p, plr->closid); 499 498 500 499 /* 501 500 * Cache was flushed earlier. Now access kernel memory to read it ··· 532 531 * Critical section end: restore closid with capacity bitmask that 533 532 * does not overlap with pseudo-locked region. 534 533 */ 535 535 - __wrmsr(MSR_IA32_PQR_ASSOC, rmid_p, closid_p); 534 534 + native_wrmsr(MSR_IA32_PQR_ASSOC, rmid_p, closid_p); 536 535 537 536 /* Re-enable the hardware prefetcher(s) */ 538 538 - wrmsrl(MSR_MISC_FEATURE_CONTROL, saved_msr); 537 537 + wrmsrq(MSR_MISC_FEATURE_CONTROL, saved_msr); 539 538 local_irq_enable(); 540 539 541 540 plr->thread_done = 1; ··· 905 904 * Disable hardware prefetchers. 906 905 */ 907 906 rdmsr(MSR_MISC_FEATURE_CONTROL, saved_low, saved_high); 908 908 - wrmsr(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits, 0x0); 907 907 + wrmsrq(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits); 909 908 mem_r = READ_ONCE(plr->kmem); 910 909 /* 911 910 * Dummy execute of the time measurement to load the needed ··· 1001 1000 * Disable hardware prefetchers. 1002 1001 */ 1003 1002 rdmsr(MSR_MISC_FEATURE_CONTROL, saved_low, saved_high); 1004 1004 - wrmsr(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits, 0x0); 1003 1003 + wrmsrq(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits); 1005 1004 1006 1005 /* Initialize rest of local variables */ 1007 1006 /* ··· 1019 1018 * used in L1 cache, second to capture accurate value that does not 1020 1019 * include cache misses incurred because of instruction loads. 1021 1020 */ 1022 1022 - rdpmcl(hit_pmcnum, hits_before); 1023 1023 - rdpmcl(miss_pmcnum, miss_before); 1021 1021 + hits_before = rdpmc(hit_pmcnum); 1022 1022 + miss_before = rdpmc(miss_pmcnum); 1024 1023 /* 1025 1024 * From SDM: Performing back-to-back fast reads are not guaranteed 1026 1025 * to be monotonic. ··· 1028 1027 * before proceeding. 1029 1028 */ 1030 1029 rmb(); 1031 1031 - rdpmcl(hit_pmcnum, hits_before); 1032 1032 - rdpmcl(miss_pmcnum, miss_before); 1030 1030 + hits_before = rdpmc(hit_pmcnum); 1031 1031 + miss_before = rdpmc(miss_pmcnum); 1033 1032 /* 1034 1033 * Use LFENCE to ensure all previous instructions are retired 1035 1034 * before proceeding. ··· 1051 1050 * before proceeding. 1052 1051 */ 1053 1052 rmb(); 1054 1054 - rdpmcl(hit_pmcnum, hits_after); 1055 1055 - rdpmcl(miss_pmcnum, miss_after); 1053 1053 + hits_after = rdpmc(hit_pmcnum); 1054 1054 + miss_after = rdpmc(miss_pmcnum); 1056 1055 /* 1057 1056 * Use LFENCE to ensure all previous instructions are retired 1058 1057 * before proceeding.

+5 -4

arch/x86/kernel/cpu/resctrl/rdtgroup.c

reviewed

··· 28 28 29 29 #include <uapi/linux/magic.h> 30 30 31 31 + #include <asm/msr.h> 31 32 #include <asm/resctrl.h> 32 33 #include "internal.h" 33 34 ··· 1636 1635 pr_warn_once("Invalid event id %d\n", config_info->evtid); 1637 1636 return; 1638 1637 } 1639 1639 - rdmsrl(MSR_IA32_EVT_CFG_BASE + index, msrval); 1638 1638 + rdmsrq(MSR_IA32_EVT_CFG_BASE + index, msrval); 1640 1639 1641 1640 /* Report only the valid event configuration bits */ 1642 1641 config_info->mon_config = msrval & MAX_EVT_CONFIG_BITS; ··· 1708 1707 pr_warn_once("Invalid event id %d\n", config_info->evtid); 1709 1708 return; 1710 1709 } 1711 1711 - wrmsr(MSR_IA32_EVT_CFG_BASE + index, config_info->mon_config, 0); 1710 1710 + wrmsrq(MSR_IA32_EVT_CFG_BASE + index, config_info->mon_config); 1712 1711 } 1713 1712 1714 1713 static void mbm_config_write_domain(struct rdt_resource *r, ··· 2327 2326 { 2328 2327 bool *enable = arg; 2329 2328 2330 2330 - wrmsrl(MSR_IA32_L3_QOS_CFG, *enable ? L3_QOS_CDP_ENABLE : 0ULL); 2329 2329 + wrmsrq(MSR_IA32_L3_QOS_CFG, *enable ? L3_QOS_CDP_ENABLE : 0ULL); 2331 2330 } 2332 2331 2333 2332 static void l2_qos_cfg_update(void *arg) 2334 2333 { 2335 2334 bool *enable = arg; 2336 2335 2337 2337 - wrmsrl(MSR_IA32_L2_QOS_CFG, *enable ? L2_QOS_CDP_ENABLE : 0ULL); 2336 2336 + wrmsrq(MSR_IA32_L2_QOS_CFG, *enable ? L2_QOS_CDP_ENABLE : 0ULL); 2338 2337 } 2339 2338 2340 2339 static inline bool is_mba_linear(void)

+2 -1

arch/x86/kernel/cpu/sgx/main.c

reviewed

··· 14 14 #include <linux/slab.h> 15 15 #include <linux/sysfs.h> 16 16 #include <linux/vmalloc.h> 17 17 + #include <asm/msr.h> 17 18 #include <asm/sgx.h> 18 19 #include "driver.h" 19 20 #include "encl.h" ··· 872 871 WARN_ON_ONCE(preemptible()); 873 872 874 873 for (i = 0; i < 4; i++) 875 875 - wrmsrl(MSR_IA32_SGXLEPUBKEYHASH0 + i, lepubkeyhash[i]); 874 874 + wrmsrq(MSR_IA32_SGXLEPUBKEYHASH0 + i, lepubkeyhash[i]); 876 875 } 877 876 878 877 const struct file_operations sgx_provision_fops = {

+2 -1

arch/x86/kernel/cpu/topology.c

reviewed

··· 30 30 #include <asm/hypervisor.h> 31 31 #include <asm/io_apic.h> 32 32 #include <asm/mpspec.h> 33 33 + #include <asm/msr.h> 33 34 #include <asm/smp.h> 34 35 35 36 #include "cpu.h" ··· 155 154 * kernel must rely on the firmware enumeration order. 156 155 */ 157 156 if (has_apic_base) { 158 158 - rdmsrl(MSR_IA32_APICBASE, msr); 157 157 + rdmsrq(MSR_IA32_APICBASE, msr); 159 158 is_bsp = !!(msr & MSR_IA32_APICBASE_BSP); 160 159 } 161 160

+3 -2

arch/x86/kernel/cpu/topology_amd.c

reviewed

··· 3 3 4 4 #include <asm/apic.h> 5 5 #include <asm/memtype.h> 6 6 + #include <asm/msr.h> 6 7 #include <asm/processor.h> 7 8 8 9 #include "cpu.h" ··· 134 133 if (!boot_cpu_has(X86_FEATURE_NODEID_MSR)) 135 134 return; 136 135 137 137 - rdmsrl(MSR_FAM10H_NODE_ID, nid.msr); 136 136 + rdmsrq(MSR_FAM10H_NODE_ID, nid.msr); 138 137 store_node(tscan, nid.nodes_per_pkg + 1, nid.node_id); 139 138 tscan->c->topo.llc_id = nid.node_id; 140 139 } ··· 161 160 if (msr_set_bit(0xc0011005, 54) <= 0) 162 161 return; 163 162 164 164 - rdmsrl(0xc0011005, msrval); 163 163 + rdmsrq(0xc0011005, msrval); 165 164 if (msrval & BIT_64(54)) { 166 165 set_cpu_cap(c, X86_FEATURE_TOPOEXT); 167 166 pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n");

+11 -10

arch/x86/kernel/cpu/tsx.c

reviewed

··· 12 12 13 13 #include <asm/cmdline.h> 14 14 #include <asm/cpu.h> 15 15 + #include <asm/msr.h> 15 16 16 17 #include "cpu.h" 17 18 ··· 25 24 { 26 25 u64 tsx; 27 26 28 28 - rdmsrl(MSR_IA32_TSX_CTRL, tsx); 27 27 + rdmsrq(MSR_IA32_TSX_CTRL, tsx); 29 28 30 29 /* Force all transactions to immediately abort */ 31 30 tsx |= TSX_CTRL_RTM_DISABLE; ··· 38 37 */ 39 38 tsx |= TSX_CTRL_CPUID_CLEAR; 40 39 41 41 - wrmsrl(MSR_IA32_TSX_CTRL, tsx); 40 40 + wrmsrq(MSR_IA32_TSX_CTRL, tsx); 42 41 } 43 42 44 43 static void tsx_enable(void) 45 44 { 46 45 u64 tsx; 47 46 48 48 - rdmsrl(MSR_IA32_TSX_CTRL, tsx); 47 47 + rdmsrq(MSR_IA32_TSX_CTRL, tsx); 49 48 50 49 /* Enable the RTM feature in the cpu */ 51 50 tsx &= ~TSX_CTRL_RTM_DISABLE; ··· 57 56 */ 58 57 tsx &= ~TSX_CTRL_CPUID_CLEAR; 59 58 60 60 - wrmsrl(MSR_IA32_TSX_CTRL, tsx); 59 59 + wrmsrq(MSR_IA32_TSX_CTRL, tsx); 61 60 } 62 61 63 62 static enum tsx_ctrl_states x86_get_tsx_auto_mode(void) ··· 116 115 */ 117 116 if (boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT) && 118 117 boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT)) { 119 119 - rdmsrl(MSR_TSX_FORCE_ABORT, msr); 118 118 + rdmsrq(MSR_TSX_FORCE_ABORT, msr); 120 119 msr |= MSR_TFA_TSX_CPUID_CLEAR; 121 121 - wrmsrl(MSR_TSX_FORCE_ABORT, msr); 120 120 + wrmsrq(MSR_TSX_FORCE_ABORT, msr); 122 121 } else if (cpu_feature_enabled(X86_FEATURE_MSR_TSX_CTRL)) { 123 123 - rdmsrl(MSR_IA32_TSX_CTRL, msr); 122 122 + rdmsrq(MSR_IA32_TSX_CTRL, msr); 124 123 msr |= TSX_CTRL_CPUID_CLEAR; 125 125 - wrmsrl(MSR_IA32_TSX_CTRL, msr); 124 124 + wrmsrq(MSR_IA32_TSX_CTRL, msr); 126 125 } 127 126 } 128 127 ··· 147 146 !cpu_feature_enabled(X86_FEATURE_SRBDS_CTRL)) 148 147 return; 149 148 150 150 - rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_opt_ctrl); 149 149 + rdmsrq(MSR_IA32_MCU_OPT_CTRL, mcu_opt_ctrl); 151 150 152 151 if (mcu_opt_ctrl & RTM_ALLOW) { 153 152 mcu_opt_ctrl &= ~RTM_ALLOW; 154 154 - wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_opt_ctrl); 153 153 + wrmsrq(MSR_IA32_MCU_OPT_CTRL, mcu_opt_ctrl); 155 154 setup_force_cpu_cap(X86_FEATURE_RTM_ALWAYS_ABORT); 156 155 } 157 156 }

+3 -3

arch/x86/kernel/cpu/umwait.c

reviewed

··· 33 33 static void umwait_update_control_msr(void * unused) 34 34 { 35 35 lockdep_assert_irqs_disabled(); 36 36 - wrmsr(MSR_IA32_UMWAIT_CONTROL, READ_ONCE(umwait_control_cached), 0); 36 36 + wrmsrq(MSR_IA32_UMWAIT_CONTROL, READ_ONCE(umwait_control_cached)); 37 37 } 38 38 39 39 /* ··· 71 71 * the original control MSR value in umwait_init(). So there 72 72 * is no race condition here. 73 73 */ 74 74 - wrmsr(MSR_IA32_UMWAIT_CONTROL, orig_umwait_control_cached, 0); 74 74 + wrmsrq(MSR_IA32_UMWAIT_CONTROL, orig_umwait_control_cached); 75 75 76 76 return 0; 77 77 } ··· 214 214 * changed. This is the only place where orig_umwait_control_cached 215 215 * is modified. 216 216 */ 217 217 - rdmsrl(MSR_IA32_UMWAIT_CONTROL, orig_umwait_control_cached); 217 217 + rdmsrq(MSR_IA32_UMWAIT_CONTROL, orig_umwait_control_cached); 218 218 219 219 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "umwait:online", 220 220 umwait_cpu_online, umwait_cpu_offline);

+1

arch/x86/kernel/cpu/zhaoxin.c

reviewed

··· 4 4 5 5 #include <asm/cpu.h> 6 6 #include <asm/cpufeature.h> 7 7 + #include <asm/msr.h> 7 8 8 9 #include "cpu.h" 9 10

+2 -1

arch/x86/kernel/fpu/core.c

reviewed

··· 11 11 #include <asm/fpu/sched.h> 12 12 #include <asm/fpu/signal.h> 13 13 #include <asm/fpu/types.h> 14 14 + #include <asm/msr.h> 14 15 #include <asm/traps.h> 15 16 #include <asm/irq_regs.h> 16 17 ··· 335 334 336 335 lockdep_assert_irqs_disabled(); 337 336 if (fpu_state_size_dynamic()) { 338 338 - rdmsrl(MSR_IA32_XFD, fpstate->xfd); 337 337 + rdmsrq(MSR_IA32_XFD, fpstate->xfd); 339 338 __this_cpu_write(xfd_state, fpstate->xfd); 340 339 } 341 340 }

+6 -5

arch/x86/kernel/fpu/xstate.c

reviewed

··· 22 22 #include <asm/fpu/xcr.h> 23 23 24 24 #include <asm/cpuid.h> 25 25 + #include <asm/msr.h> 25 26 #include <asm/tlbflush.h> 26 27 #include <asm/prctl.h> 27 28 #include <asm/elf.h> ··· 228 227 * MSR_IA32_XSS sets supervisor states managed by XSAVES. 229 228 */ 230 229 if (boot_cpu_has(X86_FEATURE_XSAVES)) { 231 231 - wrmsrl(MSR_IA32_XSS, xfeatures_mask_supervisor() | 230 230 + wrmsrq(MSR_IA32_XSS, xfeatures_mask_supervisor() | 232 231 xfeatures_mask_independent()); 233 232 } 234 233 } ··· 680 679 return get_compacted_size(); 681 680 682 681 /* Disable independent features. */ 683 683 - wrmsrl(MSR_IA32_XSS, xfeatures_mask_supervisor()); 682 682 + wrmsrq(MSR_IA32_XSS, xfeatures_mask_supervisor()); 684 683 685 684 /* 686 685 * Ask the hardware what size is required of the buffer. ··· 689 688 size = get_compacted_size(); 690 689 691 690 /* Re-enable independent features so XSAVES will work on them again. */ 692 692 - wrmsrl(MSR_IA32_XSS, xfeatures_mask_supervisor() | mask); 691 691 + wrmsrq(MSR_IA32_XSS, xfeatures_mask_supervisor() | mask); 693 692 694 693 return size; 695 694 } ··· 955 954 * of XSAVES and MSR_IA32_XSS. 956 955 */ 957 956 if (cpu_feature_enabled(X86_FEATURE_XSAVES)) { 958 958 - wrmsrl(MSR_IA32_XSS, xfeatures_mask_supervisor() | 957 957 + wrmsrq(MSR_IA32_XSS, xfeatures_mask_supervisor() | 959 958 xfeatures_mask_independent()); 960 959 } 961 960 962 961 if (fpu_state_size_dynamic()) 963 963 - wrmsrl(MSR_IA32_XFD, x86_task_fpu(current)->fpstate->xfd); 962 962 + wrmsrq(MSR_IA32_XFD, x86_task_fpu(current)->fpstate->xfd); 964 963 } 965 964 966 965 /*

+2 -1

arch/x86/kernel/fpu/xstate.h

reviewed

··· 5 5 #include <asm/cpufeature.h> 6 6 #include <asm/fpu/xstate.h> 7 7 #include <asm/fpu/xcr.h> 8 8 + #include <asm/msr.h> 8 9 9 10 #ifdef CONFIG_X86_64 10 11 DECLARE_PER_CPU(u64, xfd_state); ··· 182 181 #ifdef CONFIG_X86_64 183 182 static inline void xfd_set_state(u64 xfd) 184 183 { 185 185 - wrmsrl(MSR_IA32_XFD, xfd); 184 184 + wrmsrq(MSR_IA32_XFD, xfd); 186 185 __this_cpu_write(xfd_state, xfd); 187 186 } 188 187

+11 -10

arch/x86/kernel/fred.c

reviewed

··· 3 3 4 4 #include <asm/desc.h> 5 5 #include <asm/fred.h> 6 6 + #include <asm/msr.h> 6 7 #include <asm/tlbflush.h> 7 8 #include <asm/traps.h> 8 9 ··· 44 43 */ 45 44 loadsegment(ss, __KERNEL_DS); 46 45 47 47 - wrmsrl(MSR_IA32_FRED_CONFIG, 46 46 + wrmsrq(MSR_IA32_FRED_CONFIG, 48 47 /* Reserve for CALL emulation */ 49 48 FRED_CONFIG_REDZONE | 50 49 FRED_CONFIG_INT_STKLVL(0) | 51 50 FRED_CONFIG_ENTRYPOINT(asm_fred_entrypoint_user)); 52 51 53 53 - wrmsrl(MSR_IA32_FRED_STKLVLS, 0); 52 52 + wrmsrq(MSR_IA32_FRED_STKLVLS, 0); 54 53 55 54 /* 56 55 * Ater a CPU offline/online cycle, the FRED RSP0 MSR should be 57 56 * resynchronized with its per-CPU cache. 58 57 */ 59 59 - wrmsrl(MSR_IA32_FRED_RSP0, __this_cpu_read(fred_rsp0)); 58 58 + wrmsrq(MSR_IA32_FRED_RSP0, __this_cpu_read(fred_rsp0)); 60 59 61 61 - wrmsrl(MSR_IA32_FRED_RSP1, 0); 62 62 - wrmsrl(MSR_IA32_FRED_RSP2, 0); 63 63 - wrmsrl(MSR_IA32_FRED_RSP3, 0); 60 60 + wrmsrq(MSR_IA32_FRED_RSP1, 0); 61 61 + wrmsrq(MSR_IA32_FRED_RSP2, 0); 62 62 + wrmsrq(MSR_IA32_FRED_RSP3, 0); 64 63 65 64 /* Enable FRED */ 66 65 cr4_set_bits(X86_CR4_FRED); ··· 80 79 * (remember that user space faults are always taken on stack level 0) 81 80 * is to avoid overflowing the kernel stack. 82 81 */ 83 83 - wrmsrl(MSR_IA32_FRED_STKLVLS, 82 82 + wrmsrq(MSR_IA32_FRED_STKLVLS, 84 83 FRED_STKLVL(X86_TRAP_DB, FRED_DB_STACK_LEVEL) | 85 84 FRED_STKLVL(X86_TRAP_NMI, FRED_NMI_STACK_LEVEL) | 86 85 FRED_STKLVL(X86_TRAP_MC, FRED_MC_STACK_LEVEL) | 87 86 FRED_STKLVL(X86_TRAP_DF, FRED_DF_STACK_LEVEL)); 88 87 89 88 /* The FRED equivalents to IST stacks... */ 90 90 - wrmsrl(MSR_IA32_FRED_RSP1, __this_cpu_ist_top_va(DB)); 91 91 - wrmsrl(MSR_IA32_FRED_RSP2, __this_cpu_ist_top_va(NMI)); 92 92 - wrmsrl(MSR_IA32_FRED_RSP3, __this_cpu_ist_top_va(DF)); 89 89 + wrmsrq(MSR_IA32_FRED_RSP1, __this_cpu_ist_top_va(DB)); 90 90 + wrmsrq(MSR_IA32_FRED_RSP2, __this_cpu_ist_top_va(NMI)); 91 91 + wrmsrq(MSR_IA32_FRED_RSP3, __this_cpu_ist_top_va(DF)); 93 92 }

+2 -1

arch/x86/kernel/hpet.c

reviewed

··· 12 12 #include <asm/hpet.h> 13 13 #include <asm/time.h> 14 14 #include <asm/mwait.h> 15 15 + #include <asm/msr.h> 15 16 16 17 #undef pr_fmt 17 18 #define pr_fmt(fmt) "hpet: " fmt ··· 971 970 return false; 972 971 973 972 /* Check whether PC10 is enabled in PKG C-state limit */ 974 974 - rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, pcfg); 973 973 + rdmsrq(MSR_PKG_CST_CONFIG_CONTROL, pcfg); 975 974 if ((pcfg & 0xF) < 8) 976 975 return false; 977 976

+16 -15

arch/x86/kernel/kvm.c

reviewed

··· 40 40 #include <asm/mtrr.h> 41 41 #include <asm/tlb.h> 42 42 #include <asm/cpuidle_haltpoll.h> 43 43 + #include <asm/msr.h> 43 44 #include <asm/ptrace.h> 44 45 #include <asm/reboot.h> 45 46 #include <asm/svm.h> ··· 302 301 token = __this_cpu_read(apf_reason.token); 303 302 kvm_async_pf_task_wake(token); 304 303 __this_cpu_write(apf_reason.token, 0); 305 305 - wrmsrl(MSR_KVM_ASYNC_PF_ACK, 1); 304 304 + wrmsrq(MSR_KVM_ASYNC_PF_ACK, 1); 306 305 } 307 306 308 307 set_irq_regs(old_regs); ··· 328 327 if (!has_steal_clock) 329 328 return; 330 329 331 331 - wrmsrl(MSR_KVM_STEAL_TIME, (slow_virt_to_phys(st) | KVM_MSR_ENABLED)); 330 330 + wrmsrq(MSR_KVM_STEAL_TIME, (slow_virt_to_phys(st) | KVM_MSR_ENABLED)); 332 331 pr_debug("stealtime: cpu %d, msr %llx\n", cpu, 333 332 (unsigned long long) slow_virt_to_phys(st)); 334 333 } ··· 362 361 if (kvm_para_has_feature(KVM_FEATURE_ASYNC_PF_VMEXIT)) 363 362 pa |= KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; 364 363 365 365 - wrmsrl(MSR_KVM_ASYNC_PF_INT, HYPERVISOR_CALLBACK_VECTOR); 364 364 + wrmsrq(MSR_KVM_ASYNC_PF_INT, HYPERVISOR_CALLBACK_VECTOR); 366 365 367 367 - wrmsrl(MSR_KVM_ASYNC_PF_EN, pa); 366 366 + wrmsrq(MSR_KVM_ASYNC_PF_EN, pa); 368 367 __this_cpu_write(async_pf_enabled, true); 369 368 pr_debug("setup async PF for cpu %d\n", smp_processor_id()); 370 369 } ··· 377 376 __this_cpu_write(kvm_apic_eoi, 0); 378 377 pa = slow_virt_to_phys(this_cpu_ptr(&kvm_apic_eoi)) 379 378 | KVM_MSR_ENABLED; 380 380 - wrmsrl(MSR_KVM_PV_EOI_EN, pa); 379 379 + wrmsrq(MSR_KVM_PV_EOI_EN, pa); 381 380 } 382 381 383 382 if (has_steal_clock) ··· 389 388 if (!__this_cpu_read(async_pf_enabled)) 390 389 return; 391 390 392 392 - wrmsrl(MSR_KVM_ASYNC_PF_EN, 0); 391 391 + wrmsrq(MSR_KVM_ASYNC_PF_EN, 0); 393 392 __this_cpu_write(async_pf_enabled, false); 394 393 395 394 pr_debug("disable async PF for cpu %d\n", smp_processor_id()); ··· 400 399 if (!has_steal_clock) 401 400 return; 402 401 403 403 - wrmsr(MSR_KVM_STEAL_TIME, 0, 0); 402 402 + wrmsrq(MSR_KVM_STEAL_TIME, 0); 404 403 } 405 404 406 405 static u64 kvm_steal_clock(int cpu) ··· 452 451 { 453 452 kvm_disable_steal_time(); 454 453 if (kvm_para_has_feature(KVM_FEATURE_PV_EOI)) 455 455 - wrmsrl(MSR_KVM_PV_EOI_EN, 0); 454 454 + wrmsrq(MSR_KVM_PV_EOI_EN, 0); 456 455 if (kvm_para_has_feature(KVM_FEATURE_MIGRATION_CONTROL)) 457 457 - wrmsrl(MSR_KVM_MIGRATION_CONTROL, 0); 456 456 + wrmsrq(MSR_KVM_MIGRATION_CONTROL, 0); 458 457 kvm_pv_disable_apf(); 459 458 if (!shutdown) 460 459 apf_task_wake_all(); ··· 616 615 } 617 616 618 617 pr_info("%s : live migration enabled in EFI\n", __func__); 619 619 - wrmsrl(MSR_KVM_MIGRATION_CONTROL, KVM_MIGRATION_READY); 618 618 + wrmsrq(MSR_KVM_MIGRATION_CONTROL, KVM_MIGRATION_READY); 620 619 621 620 return 1; 622 621 } ··· 729 728 730 729 #ifdef CONFIG_ARCH_CPUIDLE_HALTPOLL 731 730 if (kvm_para_has_feature(KVM_FEATURE_POLL_CONTROL)) 732 732 - rdmsrl(MSR_KVM_POLL_CONTROL, val); 731 731 + rdmsrq(MSR_KVM_POLL_CONTROL, val); 733 732 has_guest_poll = !(val & 1); 734 733 #endif 735 734 return 0; ··· 741 740 742 741 #ifdef CONFIG_ARCH_CPUIDLE_HALTPOLL 743 742 if (kvm_para_has_feature(KVM_FEATURE_POLL_CONTROL) && has_guest_poll) 744 744 - wrmsrl(MSR_KVM_POLL_CONTROL, 0); 743 743 + wrmsrq(MSR_KVM_POLL_CONTROL, 0); 745 744 #endif 746 745 } 747 746 ··· 976 975 * If not booted using EFI, enable Live migration support. 977 976 */ 978 977 if (!efi_enabled(EFI_BOOT)) 979 979 - wrmsrl(MSR_KVM_MIGRATION_CONTROL, 978 978 + wrmsrq(MSR_KVM_MIGRATION_CONTROL, 980 979 KVM_MIGRATION_READY); 981 980 } 982 981 kvmclock_init(); ··· 1125 1124 1126 1125 static void kvm_disable_host_haltpoll(void *i) 1127 1126 { 1128 1128 - wrmsrl(MSR_KVM_POLL_CONTROL, 0); 1127 1127 + wrmsrq(MSR_KVM_POLL_CONTROL, 0); 1129 1128 } 1130 1129 1131 1130 static void kvm_enable_host_haltpoll(void *i) 1132 1131 { 1133 1133 - wrmsrl(MSR_KVM_POLL_CONTROL, 1); 1132 1132 + wrmsrq(MSR_KVM_POLL_CONTROL, 1); 1134 1133 } 1135 1134 1136 1135 void arch_haltpoll_enable(unsigned int cpu)

+3 -3

arch/x86/kernel/kvmclock.c

reviewed

··· 60 60 */ 61 61 static void kvm_get_wallclock(struct timespec64 *now) 62 62 { 63 63 - wrmsrl(msr_kvm_wall_clock, slow_virt_to_phys(&wall_clock)); 63 63 + wrmsrq(msr_kvm_wall_clock, slow_virt_to_phys(&wall_clock)); 64 64 preempt_disable(); 65 65 pvclock_read_wallclock(&wall_clock, this_cpu_pvti(), now); 66 66 preempt_enable(); ··· 173 173 return; 174 174 175 175 pa = slow_virt_to_phys(&src->pvti) | 0x01ULL; 176 176 - wrmsrl(msr_kvm_system_time, pa); 176 176 + wrmsrq(msr_kvm_system_time, pa); 177 177 pr_debug("kvm-clock: cpu %d, msr %llx, %s", smp_processor_id(), pa, txt); 178 178 } 179 179 ··· 196 196 void kvmclock_disable(void) 197 197 { 198 198 if (msr_kvm_system_time) 199 199 - native_write_msr(msr_kvm_system_time, 0, 0); 199 199 + native_write_msr(msr_kvm_system_time, 0); 200 200 } 201 201 202 202 static void __init kvmclock_init_mem(void)

+4 -4

arch/x86/kernel/mmconf-fam10h_64.c

reviewed

··· 97 97 98 98 /* SYS_CFG */ 99 99 address = MSR_AMD64_SYSCFG; 100 100 - rdmsrl(address, val); 100 100 + rdmsrq(address, val); 101 101 102 102 /* TOP_MEM2 is not enabled? */ 103 103 if (!(val & (1<<21))) { ··· 105 105 } else { 106 106 /* TOP_MEM2 */ 107 107 address = MSR_K8_TOP_MEM2; 108 108 - rdmsrl(address, val); 108 108 + rdmsrq(address, val); 109 109 tom2 = max(val & 0xffffff800000ULL, 1ULL << 32); 110 110 } 111 111 ··· 177 177 return; 178 178 179 179 address = MSR_FAM10H_MMIO_CONF_BASE; 180 180 - rdmsrl(address, val); 180 180 + rdmsrq(address, val); 181 181 182 182 /* try to make sure that AP's setting is identical to BSP setting */ 183 183 if (val & FAM10H_MMIO_CONF_ENABLE) { ··· 212 212 (FAM10H_MMIO_CONF_BUSRANGE_MASK<<FAM10H_MMIO_CONF_BUSRANGE_SHIFT)); 213 213 val |= fam10h_pci_mmconf_base | (8 << FAM10H_MMIO_CONF_BUSRANGE_SHIFT) | 214 214 FAM10H_MMIO_CONF_ENABLE; 215 215 - wrmsrl(address, val); 215 215 + wrmsrq(address, val); 216 216 } 217 217 218 218 static int __init set_check_enable_amd_mmconf(const struct dmi_system_id *d)

+1

arch/x86/kernel/paravirt.c

reviewed

··· 33 33 #include <asm/tlb.h> 34 34 #include <asm/io_bitmap.h> 35 35 #include <asm/gsseg.h> 36 36 + #include <asm/msr.h> 36 37 37 38 /* stub always returning 0. */ 38 39 DEFINE_ASM_FUNC(paravirt_ret0, "xor %eax,%eax", .entry.text);

+9 -8

arch/x86/kernel/process.c

reviewed

··· 52 52 #include <asm/unwind.h> 53 53 #include <asm/tdx.h> 54 54 #include <asm/mmu_context.h> 55 55 + #include <asm/msr.h> 55 56 #include <asm/shstk.h> 56 57 57 58 #include "process.h" ··· 339 338 msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT; 340 339 msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT); 341 340 this_cpu_write(msr_misc_features_shadow, msrval); 342 342 - wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval); 341 341 + wrmsrq(MSR_MISC_FEATURES_ENABLES, msrval); 343 342 } 344 343 345 344 static void disable_cpuid(void) ··· 556 555 557 556 if (!static_cpu_has(X86_FEATURE_ZEN)) { 558 557 msr |= ssbd_tif_to_amd_ls_cfg(tifn); 559 559 - wrmsrl(MSR_AMD64_LS_CFG, msr); 558 558 + wrmsrq(MSR_AMD64_LS_CFG, msr); 560 559 return; 561 560 } 562 561 ··· 573 572 raw_spin_lock(&st->shared_state->lock); 574 573 /* First sibling enables SSBD: */ 575 574 if (!st->shared_state->disable_state) 576 576 - wrmsrl(MSR_AMD64_LS_CFG, msr); 575 575 + wrmsrq(MSR_AMD64_LS_CFG, msr); 577 576 st->shared_state->disable_state++; 578 577 raw_spin_unlock(&st->shared_state->lock); 579 578 } else { ··· 583 582 raw_spin_lock(&st->shared_state->lock); 584 583 st->shared_state->disable_state--; 585 584 if (!st->shared_state->disable_state) 586 586 - wrmsrl(MSR_AMD64_LS_CFG, msr); 585 585 + wrmsrq(MSR_AMD64_LS_CFG, msr); 587 586 raw_spin_unlock(&st->shared_state->lock); 588 587 } 589 588 } ··· 592 591 { 593 592 u64 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn); 594 593 595 595 - wrmsrl(MSR_AMD64_LS_CFG, msr); 594 594 + wrmsrq(MSR_AMD64_LS_CFG, msr); 596 595 } 597 596 #endif 598 597 ··· 602 601 * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL, 603 602 * so ssbd_tif_to_spec_ctrl() just works. 604 603 */ 605 605 - wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn)); 604 604 + wrmsrq(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn)); 606 605 } 607 606 608 607 /* ··· 705 704 arch_has_block_step()) { 706 705 unsigned long debugctl, msk; 707 706 708 708 - rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 707 707 + rdmsrq(MSR_IA32_DEBUGCTLMSR, debugctl); 709 708 debugctl &= ~DEBUGCTLMSR_BTF; 710 709 msk = tifn & _TIF_BLOCKSTEP; 711 710 debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT; 712 712 - wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 711 711 + wrmsrq(MSR_IA32_DEBUGCTLMSR, debugctl); 713 712 } 714 713 715 714 if ((tifp ^ tifn) & _TIF_NOTSC)

+11 -10

arch/x86/kernel/process_64.c

reviewed

··· 57 57 #include <asm/unistd.h> 58 58 #include <asm/fsgsbase.h> 59 59 #include <asm/fred.h> 60 60 + #include <asm/msr.h> 60 61 #ifdef CONFIG_IA32_EMULATION 61 62 /* Not included via unistd.h */ 62 63 #include <asm/unistd_32_ia32.h> ··· 96 95 return; 97 96 98 97 if (mode == SHOW_REGS_USER) { 99 99 - rdmsrl(MSR_FS_BASE, fs); 100 100 - rdmsrl(MSR_KERNEL_GS_BASE, shadowgs); 98 98 + rdmsrq(MSR_FS_BASE, fs); 99 99 + rdmsrq(MSR_KERNEL_GS_BASE, shadowgs); 101 100 printk("%sFS: %016lx GS: %016lx\n", 102 101 log_lvl, fs, shadowgs); 103 102 return; ··· 108 107 asm("movl %%fs,%0" : "=r" (fsindex)); 109 108 asm("movl %%gs,%0" : "=r" (gsindex)); 110 109 111 111 - rdmsrl(MSR_FS_BASE, fs); 112 112 - rdmsrl(MSR_GS_BASE, gs); 113 113 - rdmsrl(MSR_KERNEL_GS_BASE, shadowgs); 110 110 + rdmsrq(MSR_FS_BASE, fs); 111 111 + rdmsrq(MSR_GS_BASE, gs); 112 112 + rdmsrq(MSR_KERNEL_GS_BASE, shadowgs); 114 113 115 114 cr0 = read_cr0(); 116 115 cr2 = read_cr2(); ··· 196 195 native_swapgs(); 197 196 } else { 198 197 instrumentation_begin(); 199 199 - rdmsrl(MSR_KERNEL_GS_BASE, gsbase); 198 198 + rdmsrq(MSR_KERNEL_GS_BASE, gsbase); 200 199 instrumentation_end(); 201 200 } 202 201 ··· 222 221 native_swapgs(); 223 222 } else { 224 223 instrumentation_begin(); 225 225 - wrmsrl(MSR_KERNEL_GS_BASE, gsbase); 224 224 + wrmsrq(MSR_KERNEL_GS_BASE, gsbase); 226 225 instrumentation_end(); 227 226 } 228 227 } ··· 354 353 } else { 355 354 if (prev_index != next_index) 356 355 loadseg(which, next_index); 357 357 - wrmsrl(which == FS ? MSR_FS_BASE : MSR_KERNEL_GS_BASE, 356 356 + wrmsrq(which == FS ? MSR_FS_BASE : MSR_KERNEL_GS_BASE, 358 357 next_base); 359 358 } 360 359 } else { ··· 464 463 gsbase = __rdgsbase_inactive(); 465 464 local_irq_restore(flags); 466 465 } else { 467 467 - rdmsrl(MSR_KERNEL_GS_BASE, gsbase); 466 466 + rdmsrq(MSR_KERNEL_GS_BASE, gsbase); 468 467 } 469 468 470 469 return gsbase; ··· 479 478 __wrgsbase_inactive(gsbase); 480 479 local_irq_restore(flags); 481 480 } else { 482 482 - wrmsrl(MSR_KERNEL_GS_BASE, gsbase); 481 481 + wrmsrq(MSR_KERNEL_GS_BASE, gsbase); 483 482 } 484 483 } 485 484

+1 -1

arch/x86/kernel/reboot_fixups_32.c

reviewed

··· 27 27 static void cs5536_warm_reset(struct pci_dev *dev) 28 28 { 29 29 /* writing 1 to the LSB of this MSR causes a hard reset */ 30 30 - wrmsrl(MSR_DIVIL_SOFT_RESET, 1ULL); 30 30 + wrmsrq(MSR_DIVIL_SOFT_RESET, 1ULL); 31 31 udelay(50); /* shouldn't get here but be safe and spin a while */ 32 32 } 33 33

+9 -9

arch/x86/kernel/shstk.c

reviewed

··· 173 173 return PTR_ERR((void *)addr); 174 174 175 175 fpregs_lock_and_load(); 176 176 - wrmsrl(MSR_IA32_PL3_SSP, addr + size); 177 177 - wrmsrl(MSR_IA32_U_CET, CET_SHSTK_EN); 176 176 + wrmsrq(MSR_IA32_PL3_SSP, addr + size); 177 177 + wrmsrq(MSR_IA32_U_CET, CET_SHSTK_EN); 178 178 fpregs_unlock(); 179 179 180 180 shstk->base = addr; ··· 239 239 240 240 fpregs_lock_and_load(); 241 241 242 242 - rdmsrl(MSR_IA32_PL3_SSP, ssp); 242 242 + rdmsrq(MSR_IA32_PL3_SSP, ssp); 243 243 244 244 fpregs_unlock(); 245 245 ··· 372 372 return -EFAULT; 373 373 374 374 fpregs_lock_and_load(); 375 375 - wrmsrl(MSR_IA32_PL3_SSP, ssp); 375 375 + wrmsrq(MSR_IA32_PL3_SSP, ssp); 376 376 fpregs_unlock(); 377 377 378 378 return 0; ··· 396 396 return err; 397 397 398 398 fpregs_lock_and_load(); 399 399 - wrmsrl(MSR_IA32_PL3_SSP, ssp); 399 399 + wrmsrq(MSR_IA32_PL3_SSP, ssp); 400 400 fpregs_unlock(); 401 401 402 402 return 0; ··· 460 460 return 0; 461 461 462 462 fpregs_lock_and_load(); 463 463 - rdmsrl(MSR_IA32_U_CET, msrval); 463 463 + rdmsrq(MSR_IA32_U_CET, msrval); 464 464 465 465 if (enable) { 466 466 features_set(ARCH_SHSTK_WRSS); ··· 473 473 msrval &= ~CET_WRSS_EN; 474 474 } 475 475 476 476 - wrmsrl(MSR_IA32_U_CET, msrval); 476 476 + wrmsrq(MSR_IA32_U_CET, msrval); 477 477 478 478 unlock: 479 479 fpregs_unlock(); ··· 492 492 493 493 fpregs_lock_and_load(); 494 494 /* Disable WRSS too when disabling shadow stack */ 495 495 - wrmsrl(MSR_IA32_U_CET, 0); 496 496 - wrmsrl(MSR_IA32_PL3_SSP, 0); 495 495 + wrmsrq(MSR_IA32_U_CET, 0); 496 496 + wrmsrq(MSR_IA32_PL3_SSP, 0); 497 497 fpregs_unlock(); 498 498 499 499 shstk_free(current);

+1 -1

arch/x86/kernel/trace_clock.c

reviewed

··· 4 4 */ 5 5 #include <asm/trace_clock.h> 6 6 #include <asm/barrier.h> 7 7 - #include <asm/msr.h> 7 7 + #include <asm/tsc.h> 8 8 9 9 /* 10 10 * trace_clock_x86_tsc(): A clock that is just the cycle counter.

+6 -5

arch/x86/kernel/traps.c

reviewed

··· 68 68 #include <asm/vdso.h> 69 69 #include <asm/tdx.h> 70 70 #include <asm/cfi.h> 71 71 + #include <asm/msr.h> 71 72 72 73 #ifdef CONFIG_X86_64 73 74 #include <asm/x86_init.h> ··· 750 749 if (current->pasid_activated) 751 750 return false; 752 751 753 753 - wrmsrl(MSR_IA32_PASID, pasid | MSR_IA32_PASID_VALID); 752 752 + wrmsrq(MSR_IA32_PASID, pasid | MSR_IA32_PASID_VALID); 754 753 current->pasid_activated = 1; 755 754 756 755 return true; ··· 1121 1120 */ 1122 1121 unsigned long debugctl; 1123 1122 1124 1124 - rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 1123 1123 + rdmsrq(MSR_IA32_DEBUGCTLMSR, debugctl); 1125 1124 debugctl |= DEBUGCTLMSR_BTF; 1126 1126 - wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 1125 1125 + wrmsrq(MSR_IA32_DEBUGCTLMSR, debugctl); 1127 1126 } 1128 1127 1129 1128 /* ··· 1387 1386 if (!IS_ENABLED(CONFIG_X86_64) || !cpu_feature_enabled(X86_FEATURE_XFD)) 1388 1387 return false; 1389 1388 1390 1390 - rdmsrl(MSR_IA32_XFD_ERR, xfd_err); 1389 1389 + rdmsrq(MSR_IA32_XFD_ERR, xfd_err); 1391 1390 if (!xfd_err) 1392 1391 return false; 1393 1392 1394 1394 - wrmsrl(MSR_IA32_XFD_ERR, 0); 1393 1393 + wrmsrq(MSR_IA32_XFD_ERR, 0); 1395 1394 1396 1395 /* Die if that happens in kernel space */ 1397 1396 if (WARN_ON(!user_mode(regs)))

+2 -1

arch/x86/kernel/tsc.c

reviewed

··· 29 29 #include <asm/apic.h> 30 30 #include <asm/cpu_device_id.h> 31 31 #include <asm/i8259.h> 32 32 + #include <asm/msr.h> 32 33 #include <asm/topology.h> 33 34 #include <asm/uv/uv.h> 34 35 #include <asm/sev.h> ··· 1099 1098 if (art_base_clk.denominator < ART_MIN_DENOMINATOR) 1100 1099 return; 1101 1100 1102 1102 - rdmsrl(MSR_IA32_TSC_ADJUST, art_base_clk.offset); 1101 1101 + rdmsrq(MSR_IA32_TSC_ADJUST, art_base_clk.offset); 1103 1102 1104 1103 /* Make this sticky over multiple CPU init calls */ 1105 1104 setup_force_cpu_cap(X86_FEATURE_ART);

+8 -7

arch/x86/kernel/tsc_sync.c

reviewed

··· 21 21 #include <linux/kernel.h> 22 22 #include <linux/smp.h> 23 23 #include <linux/nmi.h> 24 24 + #include <asm/msr.h> 24 25 #include <asm/tsc.h> 25 26 26 27 struct tsc_adjust { ··· 66 65 67 66 adj->nextcheck = jiffies + HZ; 68 67 69 69 - rdmsrl(MSR_IA32_TSC_ADJUST, curval); 68 68 + rdmsrq(MSR_IA32_TSC_ADJUST, curval); 70 69 if (adj->adjusted == curval) 71 70 return; 72 71 73 72 /* Restore the original value */ 74 74 - wrmsrl(MSR_IA32_TSC_ADJUST, adj->adjusted); 73 73 + wrmsrq(MSR_IA32_TSC_ADJUST, adj->adjusted); 75 74 76 75 if (!adj->warned || resume) { 77 76 pr_warn(FW_BUG "TSC ADJUST differs: CPU%u %lld --> %lld. Restoring\n", ··· 143 142 if (likely(!tsc_async_resets)) { 144 143 pr_warn(FW_BUG "TSC ADJUST: CPU%u: %lld force to 0\n", 145 144 cpu, bootval); 146 146 - wrmsrl(MSR_IA32_TSC_ADJUST, 0); 145 145 + wrmsrq(MSR_IA32_TSC_ADJUST, 0); 147 146 bootval = 0; 148 147 } else { 149 148 pr_info("TSC ADJUST: CPU%u: %lld NOT forced to 0\n", ··· 166 165 if (check_tsc_unstable()) 167 166 return false; 168 167 169 169 - rdmsrl(MSR_IA32_TSC_ADJUST, bootval); 168 168 + rdmsrq(MSR_IA32_TSC_ADJUST, bootval); 170 169 cur->bootval = bootval; 171 170 cur->nextcheck = jiffies + HZ; 172 171 tsc_sanitize_first_cpu(cur, bootval, smp_processor_id(), bootcpu); ··· 188 187 if (!boot_cpu_has(X86_FEATURE_TSC_ADJUST)) 189 188 return false; 190 189 191 191 - rdmsrl(MSR_IA32_TSC_ADJUST, bootval); 190 190 + rdmsrq(MSR_IA32_TSC_ADJUST, bootval); 192 191 cur->bootval = bootval; 193 192 cur->nextcheck = jiffies + HZ; 194 193 cur->warned = false; ··· 230 229 */ 231 230 if (bootval != ref->adjusted) { 232 231 cur->adjusted = ref->adjusted; 233 233 - wrmsrl(MSR_IA32_TSC_ADJUST, ref->adjusted); 232 232 + wrmsrq(MSR_IA32_TSC_ADJUST, ref->adjusted); 234 233 } 235 234 /* 236 235 * We have the TSCs forced to be in sync on this package. Skip sync ··· 519 518 pr_warn("TSC ADJUST compensate: CPU%u observed %lld warp. Adjust: %lld\n", 520 519 cpu, cur_max_warp, cur->adjusted); 521 520 522 522 - wrmsrl(MSR_IA32_TSC_ADJUST, cur->adjusted); 521 521 + wrmsrq(MSR_IA32_TSC_ADJUST, cur->adjusted); 523 522 goto retry; 524 523 525 524 }

+2 -1

arch/x86/kvm/svm/avic.c

reviewed

··· 20 20 #include <linux/kvm_host.h> 21 21 22 22 #include <asm/irq_remapping.h> 23 23 + #include <asm/msr.h> 23 24 24 25 #include "trace.h" 25 26 #include "lapic.h" ··· 331 330 int cpu = READ_ONCE(vcpu->cpu); 332 331 333 332 if (cpu != get_cpu()) { 334 334 - wrmsrl(MSR_AMD64_SVM_AVIC_DOORBELL, kvm_cpu_get_apicid(cpu)); 333 333 + wrmsrq(MSR_AMD64_SVM_AVIC_DOORBELL, kvm_cpu_get_apicid(cpu)); 335 334 trace_kvm_avic_doorbell(vcpu->vcpu_id, kvm_cpu_get_apicid(cpu)); 336 335 } 337 336 put_cpu();

+2 -1

arch/x86/kvm/svm/sev.c

reviewed

··· 26 26 #include <asm/fpu/xcr.h> 27 27 #include <asm/fpu/xstate.h> 28 28 #include <asm/debugreg.h> 29 29 + #include <asm/msr.h> 29 30 #include <asm/sev.h> 30 31 31 32 #include "mmu.h" ··· 3120 3119 * back to WBINVD if this faults so as not to make any problems worse 3121 3120 * by leaving stale encrypted data in the cache. 3122 3121 */ 3123 3123 - if (WARN_ON_ONCE(wrmsrl_safe(MSR_AMD64_VM_PAGE_FLUSH, addr | asid))) 3122 3122 + if (WARN_ON_ONCE(wrmsrq_safe(MSR_AMD64_VM_PAGE_FLUSH, addr | asid))) 3124 3123 goto do_wbinvd; 3125 3124 3126 3125 return;

+19 -32

arch/x86/kvm/svm/svm.c

reviewed

··· 31 31 #include <linux/string_choices.h> 32 32 33 33 #include <asm/apic.h> 34 34 + #include <asm/msr.h> 34 35 #include <asm/perf_event.h> 35 36 #include <asm/tlbflush.h> 36 37 #include <asm/desc.h> ··· 476 475 477 476 static void svm_init_erratum_383(void) 478 477 { 479 479 - u32 low, high; 480 480 - int err; 481 478 u64 val; 482 479 483 480 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH)) 484 481 return; 485 482 486 483 /* Use _safe variants to not break nested virtualization */ 487 487 - val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err); 488 488 - if (err) 484 484 + if (native_read_msr_safe(MSR_AMD64_DC_CFG, &val)) 489 485 return; 490 486 491 487 val |= (1ULL << 47); 492 488 493 493 - low = lower_32_bits(val); 494 494 - high = upper_32_bits(val); 495 495 - 496 496 - native_write_msr_safe(MSR_AMD64_DC_CFG, low, high); 489 489 + native_write_msr_safe(MSR_AMD64_DC_CFG, val); 497 490 498 491 erratum_383_found = true; 499 492 } ··· 561 566 if (multiplier == __this_cpu_read(current_tsc_ratio)) 562 567 return; 563 568 564 564 - wrmsrl(MSR_AMD64_TSC_RATIO, multiplier); 569 569 + wrmsrq(MSR_AMD64_TSC_RATIO, multiplier); 565 570 __this_cpu_write(current_tsc_ratio, multiplier); 566 571 } 567 572 ··· 574 579 { 575 580 uint64_t efer; 576 581 577 577 - wrmsrl(MSR_VM_HSAVE_PA, 0); 578 578 - rdmsrl(MSR_EFER, efer); 582 582 + wrmsrq(MSR_VM_HSAVE_PA, 0); 583 583 + rdmsrq(MSR_EFER, efer); 579 584 if (efer & EFER_SVME) { 580 585 /* 581 586 * Force GIF=1 prior to disabling SVM, e.g. to ensure INIT and 582 587 * NMI aren't blocked. 583 588 */ 584 589 stgi(); 585 585 - wrmsrl(MSR_EFER, efer & ~EFER_SVME); 590 590 + wrmsrq(MSR_EFER, efer & ~EFER_SVME); 586 591 } 587 592 } 588 593 ··· 611 616 uint64_t efer; 612 617 int me = raw_smp_processor_id(); 613 618 614 614 - rdmsrl(MSR_EFER, efer); 619 619 + rdmsrq(MSR_EFER, efer); 615 620 if (efer & EFER_SVME) 616 621 return -EBUSY; 617 622 ··· 621 626 sd->next_asid = sd->max_asid + 1; 622 627 sd->min_asid = max_sev_asid + 1; 623 628 624 624 - wrmsrl(MSR_EFER, efer | EFER_SVME); 629 629 + wrmsrq(MSR_EFER, efer | EFER_SVME); 625 630 626 626 - wrmsrl(MSR_VM_HSAVE_PA, sd->save_area_pa); 631 631 + wrmsrq(MSR_VM_HSAVE_PA, sd->save_area_pa); 627 632 628 633 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) { 629 634 /* ··· 644 649 * erratum is present everywhere). 645 650 */ 646 651 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) { 647 647 - uint64_t len, status = 0; 652 652 + u64 len, status = 0; 648 653 int err; 649 654 650 650 - len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err); 655 655 + err = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &len); 651 656 if (!err) 652 652 - status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS, 653 653 - &err); 657 657 + err = native_read_msr_safe(MSR_AMD64_OSVW_STATUS, &status); 654 658 655 659 if (err) 656 660 osvw_status = osvw_len = 0; ··· 2199 2205 2200 2206 static bool is_erratum_383(void) 2201 2207 { 2202 2202 - int err, i; 2208 2208 + int i; 2203 2209 u64 value; 2204 2210 2205 2211 if (!erratum_383_found) 2206 2212 return false; 2207 2213 2208 2208 - value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err); 2209 2209 - if (err) 2214 2214 + if (native_read_msr_safe(MSR_IA32_MC0_STATUS, &value)) 2210 2215 return false; 2211 2216 2212 2217 /* Bit 62 may or may not be set for this mce */ ··· 2216 2223 2217 2224 /* Clear MCi_STATUS registers */ 2218 2225 for (i = 0; i < 6; ++i) 2219 2219 - native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0); 2226 2226 + native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0); 2220 2227 2221 2221 - value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err); 2222 2222 - if (!err) { 2223 2223 - u32 low, high; 2224 2224 - 2228 2228 + if (!native_read_msr_safe(MSR_IA32_MCG_STATUS, &value)) { 2225 2229 value &= ~(1ULL << 2); 2226 2226 - low = lower_32_bits(value); 2227 2227 - high = upper_32_bits(value); 2228 2228 - 2229 2229 - native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high); 2230 2230 + native_write_msr_safe(MSR_IA32_MCG_STATUS, value); 2230 2231 } 2231 2232 2232 2233 /* Flush tlb to evict multi-match entries */ ··· 5282 5295 return; 5283 5296 5284 5297 /* If memory encryption is not enabled, use existing mask */ 5285 5285 - rdmsrl(MSR_AMD64_SYSCFG, msr); 5298 5298 + rdmsrq(MSR_AMD64_SYSCFG, msr); 5286 5299 if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT)) 5287 5300 return; 5288 5301

+3 -2

arch/x86/kvm/vmx/nested.c

reviewed

··· 6 6 7 7 #include <asm/debugreg.h> 8 8 #include <asm/mmu_context.h> 9 9 + #include <asm/msr.h> 9 10 10 11 #include "x86.h" 11 12 #include "cpuid.h" ··· 7203 7202 msrs->cr4_fixed0 = VMXON_CR4_ALWAYSON; 7204 7203 7205 7204 /* These MSRs specify bits which the guest must keep fixed off. */ 7206 7206 - rdmsrl(MSR_IA32_VMX_CR0_FIXED1, msrs->cr0_fixed1); 7207 7207 - rdmsrl(MSR_IA32_VMX_CR4_FIXED1, msrs->cr4_fixed1); 7205 7205 + rdmsrq(MSR_IA32_VMX_CR0_FIXED1, msrs->cr0_fixed1); 7206 7206 + rdmsrq(MSR_IA32_VMX_CR4_FIXED1, msrs->cr4_fixed1); 7208 7207 7209 7208 if (vmx_umip_emulated()) 7210 7209 msrs->cr4_fixed1 |= X86_CR4_UMIP;

+3 -2

arch/x86/kvm/vmx/pmu_intel.c

reviewed

··· 13 13 #include <linux/types.h> 14 14 #include <linux/kvm_host.h> 15 15 #include <linux/perf_event.h> 16 16 + #include <asm/msr.h> 16 17 #include <asm/perf_event.h> 17 18 #include "x86.h" 18 19 #include "cpuid.h" ··· 280 279 local_irq_disable(); 281 280 if (lbr_desc->event->state == PERF_EVENT_STATE_ACTIVE) { 282 281 if (read) 283 283 - rdmsrl(index, msr_info->data); 282 282 + rdmsrq(index, msr_info->data); 284 283 else 285 285 - wrmsrl(index, msr_info->data); 284 284 + wrmsrq(index, msr_info->data); 286 285 __set_bit(INTEL_PMC_IDX_FIXED_VLBR, vcpu_to_pmu(vcpu)->pmc_in_use); 287 286 local_irq_enable(); 288 287 return true;

+5 -4

arch/x86/kvm/vmx/sgx.c

reviewed

··· 2 2 /* Copyright(c) 2021 Intel Corporation. */ 3 3 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 4 4 5 5 + #include <asm/msr.h> 5 6 #include <asm/sgx.h> 6 7 7 8 #include "x86.h" ··· 412 411 * MSRs exist but are read-only (locked and not writable). 413 412 */ 414 413 if (!enable_sgx || boot_cpu_has(X86_FEATURE_SGX_LC) || 415 415 - rdmsrl_safe(MSR_IA32_SGXLEPUBKEYHASH0, &sgx_pubkey_hash[0])) { 414 414 + rdmsrq_safe(MSR_IA32_SGXLEPUBKEYHASH0, &sgx_pubkey_hash[0])) { 416 415 sgx_pubkey_hash[0] = 0xa6053e051270b7acULL; 417 416 sgx_pubkey_hash[1] = 0x6cfbe8ba8b3b413dULL; 418 417 sgx_pubkey_hash[2] = 0xc4916d99f2b3735dULL; 419 418 sgx_pubkey_hash[3] = 0xd4f8c05909f9bb3bULL; 420 419 } else { 421 420 /* MSR_IA32_SGXLEPUBKEYHASH0 is read above */ 422 422 - rdmsrl(MSR_IA32_SGXLEPUBKEYHASH1, sgx_pubkey_hash[1]); 423 423 - rdmsrl(MSR_IA32_SGXLEPUBKEYHASH2, sgx_pubkey_hash[2]); 424 424 - rdmsrl(MSR_IA32_SGXLEPUBKEYHASH3, sgx_pubkey_hash[3]); 421 421 + rdmsrq(MSR_IA32_SGXLEPUBKEYHASH1, sgx_pubkey_hash[1]); 422 422 + rdmsrq(MSR_IA32_SGXLEPUBKEYHASH2, sgx_pubkey_hash[2]); 423 423 + rdmsrq(MSR_IA32_SGXLEPUBKEYHASH3, sgx_pubkey_hash[3]); 425 424 } 426 425 } 427 426

+36 -35

arch/x86/kvm/vmx/vmx.c

reviewed

··· 46 46 #include <asm/perf_event.h> 47 47 #include <asm/mmu_context.h> 48 48 #include <asm/mshyperv.h> 49 49 + #include <asm/msr.h> 49 50 #include <asm/mwait.h> 50 51 #include <asm/spec-ctrl.h> 51 52 #include <asm/vmx.h> ··· 382 381 if (!vmx->disable_fb_clear) 383 382 return; 384 383 385 385 - msr = __rdmsr(MSR_IA32_MCU_OPT_CTRL); 384 384 + msr = native_rdmsrq(MSR_IA32_MCU_OPT_CTRL); 386 385 msr |= FB_CLEAR_DIS; 387 387 - native_wrmsrl(MSR_IA32_MCU_OPT_CTRL, msr); 386 386 + native_wrmsrq(MSR_IA32_MCU_OPT_CTRL, msr); 388 387 /* Cache the MSR value to avoid reading it later */ 389 388 vmx->msr_ia32_mcu_opt_ctrl = msr; 390 389 } ··· 395 394 return; 396 395 397 396 vmx->msr_ia32_mcu_opt_ctrl &= ~FB_CLEAR_DIS; 398 398 - native_wrmsrl(MSR_IA32_MCU_OPT_CTRL, vmx->msr_ia32_mcu_opt_ctrl); 397 397 + native_wrmsrq(MSR_IA32_MCU_OPT_CTRL, vmx->msr_ia32_mcu_opt_ctrl); 399 398 } 400 399 401 400 static void vmx_update_fb_clear_dis(struct kvm_vcpu *vcpu, struct vcpu_vmx *vmx) ··· 1065 1064 * provide that period, so a CPU could write host's record into 1066 1065 * guest's memory. 1067 1066 */ 1068 1068 - wrmsrl(MSR_IA32_PEBS_ENABLE, 0); 1067 1067 + wrmsrq(MSR_IA32_PEBS_ENABLE, 0); 1069 1068 } 1070 1069 1071 1070 i = vmx_find_loadstore_msr_slot(&m->guest, msr); ··· 1194 1193 { 1195 1194 u32 i; 1196 1195 1197 1197 - wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status); 1198 1198 - wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base); 1199 1199 - wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); 1200 1200 - wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match); 1196 1196 + wrmsrq(MSR_IA32_RTIT_STATUS, ctx->status); 1197 1197 + wrmsrq(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base); 1198 1198 + wrmsrq(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); 1199 1199 + wrmsrq(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match); 1201 1200 for (i = 0; i < addr_range; i++) { 1202 1202 - wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]); 1203 1203 - wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]); 1201 1201 + wrmsrq(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]); 1202 1202 + wrmsrq(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]); 1204 1203 } 1205 1204 } 1206 1205 ··· 1208 1207 { 1209 1208 u32 i; 1210 1209 1211 1211 - rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status); 1212 1212 - rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base); 1213 1213 - rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); 1214 1214 - rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match); 1210 1210 + rdmsrq(MSR_IA32_RTIT_STATUS, ctx->status); 1211 1211 + rdmsrq(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base); 1212 1212 + rdmsrq(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); 1213 1213 + rdmsrq(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match); 1215 1214 for (i = 0; i < addr_range; i++) { 1216 1216 - rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]); 1217 1217 - rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]); 1215 1215 + rdmsrq(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]); 1216 1216 + rdmsrq(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]); 1218 1217 } 1219 1218 } 1220 1219 ··· 1227 1226 * GUEST_IA32_RTIT_CTL is already set in the VMCS. 1228 1227 * Save host state before VM entry. 1229 1228 */ 1230 1230 - rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl); 1229 1229 + rdmsrq(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl); 1231 1230 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) { 1232 1232 - wrmsrl(MSR_IA32_RTIT_CTL, 0); 1231 1231 + wrmsrq(MSR_IA32_RTIT_CTL, 0); 1233 1232 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.num_address_ranges); 1234 1233 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.num_address_ranges); 1235 1234 } ··· 1250 1249 * i.e. RTIT_CTL is always cleared on VM-Exit. Restore it if necessary. 1251 1250 */ 1252 1251 if (vmx->pt_desc.host.ctl) 1253 1253 - wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl); 1252 1252 + wrmsrq(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl); 1254 1253 } 1255 1254 1256 1255 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel, ··· 1340 1339 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE); 1341 1340 } 1342 1341 1343 1343 - wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1342 1342 + wrmsrq(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1344 1343 #else 1345 1344 savesegment(fs, fs_sel); 1346 1345 savesegment(gs, gs_sel); ··· 1364 1363 ++vmx->vcpu.stat.host_state_reload; 1365 1364 1366 1365 #ifdef CONFIG_X86_64 1367 1367 - rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1366 1366 + rdmsrq(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1368 1367 #endif 1369 1368 if (host_state->ldt_sel || (host_state->gs_sel & 7)) { 1370 1369 kvm_load_ldt(host_state->ldt_sel); ··· 1384 1383 #endif 1385 1384 invalidate_tss_limit(); 1386 1385 #ifdef CONFIG_X86_64 1387 1387 - wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); 1386 1386 + wrmsrq(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); 1388 1387 #endif 1389 1388 load_fixmap_gdt(raw_smp_processor_id()); 1390 1389 vmx->guest_state_loaded = false; ··· 1396 1395 { 1397 1396 preempt_disable(); 1398 1397 if (vmx->guest_state_loaded) 1399 1399 - rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1398 1398 + rdmsrq(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1400 1399 preempt_enable(); 1401 1400 return vmx->msr_guest_kernel_gs_base; 1402 1401 } ··· 1405 1404 { 1406 1405 preempt_disable(); 1407 1406 if (vmx->guest_state_loaded) 1408 1408 - wrmsrl(MSR_KERNEL_GS_BASE, data); 1407 1407 + wrmsrq(MSR_KERNEL_GS_BASE, data); 1409 1408 preempt_enable(); 1410 1409 vmx->msr_guest_kernel_gs_base = data; 1411 1410 } ··· 2576 2575 { 2577 2576 u64 allowed; 2578 2577 2579 2579 - rdmsrl(msr, allowed); 2578 2578 + rdmsrq(msr, allowed); 2580 2579 2581 2580 return ctl_opt & allowed; 2582 2581 } ··· 2748 2747 break; 2749 2748 } 2750 2749 2751 2751 - rdmsrl(MSR_IA32_VMX_BASIC, basic_msr); 2750 2750 + rdmsrq(MSR_IA32_VMX_BASIC, basic_msr); 2752 2751 2753 2752 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ 2754 2753 if (vmx_basic_vmcs_size(basic_msr) > PAGE_SIZE) ··· 2768 2767 if (vmx_basic_vmcs_mem_type(basic_msr) != X86_MEMTYPE_WB) 2769 2768 return -EIO; 2770 2769 2771 2771 - rdmsrl(MSR_IA32_VMX_MISC, misc_msr); 2770 2770 + rdmsrq(MSR_IA32_VMX_MISC, misc_msr); 2772 2771 2773 2772 vmcs_conf->basic = basic_msr; 2774 2773 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; ··· 2852 2851 2853 2852 fault: 2854 2853 WARN_ONCE(1, "VMXON faulted, MSR_IA32_FEAT_CTL (0x3a) = 0x%llx\n", 2855 2855 - rdmsrl_safe(MSR_IA32_FEAT_CTL, &msr) ? 0xdeadbeef : msr); 2854 2854 + rdmsrq_safe(MSR_IA32_FEAT_CTL, &msr) ? 0xdeadbeef : msr); 2856 2855 cr4_clear_bits(X86_CR4_VMXE); 2857 2856 2858 2857 return -EFAULT; ··· 4393 4392 if (!IS_ENABLED(CONFIG_IA32_EMULATION) && !IS_ENABLED(CONFIG_X86_32)) 4394 4393 vmcs_writel(HOST_IA32_SYSENTER_ESP, 0); 4395 4394 4396 4396 - rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl); 4395 4395 + rdmsrq(MSR_IA32_SYSENTER_EIP, tmpl); 4397 4396 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */ 4398 4397 4399 4398 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) { ··· 6747 6746 vcpu->stat.l1d_flush++; 6748 6747 6749 6748 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) { 6750 6750 - native_wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH); 6749 6749 + native_wrmsrq(MSR_IA32_FLUSH_CMD, L1D_FLUSH); 6751 6750 return; 6752 6751 } 6753 6752 ··· 7054 7053 * the #NM exception. 7055 7054 */ 7056 7055 if (is_xfd_nm_fault(vcpu)) 7057 7057 - rdmsrl(MSR_IA32_XFD_ERR, vcpu->arch.guest_fpu.xfd_err); 7056 7056 + rdmsrq(MSR_IA32_XFD_ERR, vcpu->arch.guest_fpu.xfd_err); 7058 7057 } 7059 7058 7060 7059 static void handle_exception_irqoff(struct kvm_vcpu *vcpu, u32 intr_info) ··· 7309 7308 return; 7310 7309 7311 7310 if (flags & VMX_RUN_SAVE_SPEC_CTRL) 7312 7312 - vmx->spec_ctrl = __rdmsr(MSR_IA32_SPEC_CTRL); 7311 7311 + vmx->spec_ctrl = native_rdmsrq(MSR_IA32_SPEC_CTRL); 7313 7312 7314 7313 /* 7315 7314 * If the guest/host SPEC_CTRL values differ, restore the host value. ··· 7320 7319 */ 7321 7320 if (cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS) || 7322 7321 vmx->spec_ctrl != hostval) 7323 7323 - native_wrmsrl(MSR_IA32_SPEC_CTRL, hostval); 7322 7322 + native_wrmsrq(MSR_IA32_SPEC_CTRL, hostval); 7324 7323 7325 7324 barrier_nospec(); 7326 7325 } ··· 7966 7965 return 0; 7967 7966 7968 7967 if (boot_cpu_has(X86_FEATURE_PDCM)) 7969 7969 - rdmsrl(MSR_IA32_PERF_CAPABILITIES, host_perf_cap); 7968 7968 + rdmsrq(MSR_IA32_PERF_CAPABILITIES, host_perf_cap); 7970 7969 7971 7970 if (!cpu_feature_enabled(X86_FEATURE_ARCH_LBR)) { 7972 7971 x86_perf_get_lbr(&vmx_lbr_caps); ··· 8515 8514 kvm_enable_efer_bits(EFER_NX); 8516 8515 8517 8516 if (boot_cpu_has(X86_FEATURE_MPX)) { 8518 8518 - rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs); 8517 8517 + rdmsrq(MSR_IA32_BNDCFGS, host_bndcfgs); 8519 8518 WARN_ONCE(host_bndcfgs, "BNDCFGS in host will be lost"); 8520 8519 } 8521 8520

+19 -19

arch/x86/kvm/x86.c

reviewed

··· 578 578 for (slot = 0; slot < kvm_nr_uret_msrs; ++slot) { 579 579 values = &msrs->values[slot]; 580 580 if (values->host != values->curr) { 581 581 - wrmsrl(kvm_uret_msrs_list[slot], values->host); 581 581 + wrmsrq(kvm_uret_msrs_list[slot], values->host); 582 582 values->curr = values->host; 583 583 } 584 584 } ··· 590 590 int ret; 591 591 592 592 preempt_disable(); 593 593 - ret = rdmsrl_safe(msr, &val); 593 593 + ret = rdmsrq_safe(msr, &val); 594 594 if (ret) 595 595 goto out; 596 596 - ret = wrmsrl_safe(msr, val); 596 596 + ret = wrmsrq_safe(msr, val); 597 597 out: 598 598 preempt_enable(); 599 599 return ret; ··· 630 630 int i; 631 631 632 632 for (i = 0; i < kvm_nr_uret_msrs; ++i) { 633 633 - rdmsrl_safe(kvm_uret_msrs_list[i], &value); 633 633 + rdmsrq_safe(kvm_uret_msrs_list[i], &value); 634 634 msrs->values[i].host = value; 635 635 msrs->values[i].curr = value; 636 636 } ··· 644 644 value = (value & mask) | (msrs->values[slot].host & ~mask); 645 645 if (value == msrs->values[slot].curr) 646 646 return 0; 647 647 - err = wrmsrl_safe(kvm_uret_msrs_list[slot], value); 647 647 + err = wrmsrq_safe(kvm_uret_msrs_list[slot], value); 648 648 if (err) 649 649 return 1; 650 650 ··· 1174 1174 1175 1175 if (guest_cpu_cap_has(vcpu, X86_FEATURE_XSAVES) && 1176 1176 vcpu->arch.ia32_xss != kvm_host.xss) 1177 1177 - wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss); 1177 1177 + wrmsrq(MSR_IA32_XSS, vcpu->arch.ia32_xss); 1178 1178 } 1179 1179 1180 1180 if (cpu_feature_enabled(X86_FEATURE_PKU) && ··· 1205 1205 1206 1206 if (guest_cpu_cap_has(vcpu, X86_FEATURE_XSAVES) && 1207 1207 vcpu->arch.ia32_xss != kvm_host.xss) 1208 1208 - wrmsrl(MSR_IA32_XSS, kvm_host.xss); 1208 1208 + wrmsrq(MSR_IA32_XSS, kvm_host.xss); 1209 1209 } 1210 1210 1211 1211 } ··· 1660 1660 *data = MSR_PLATFORM_INFO_CPUID_FAULT; 1661 1661 break; 1662 1662 case MSR_IA32_UCODE_REV: 1663 1663 - rdmsrl_safe(index, data); 1663 1663 + rdmsrq_safe(index, data); 1664 1664 break; 1665 1665 default: 1666 1666 return kvm_x86_call(get_feature_msr)(index, data); ··· 3827 3827 if (!data) 3828 3828 break; 3829 3829 3830 3830 - wrmsrl(MSR_IA32_PRED_CMD, data); 3830 3830 + wrmsrq(MSR_IA32_PRED_CMD, data); 3831 3831 break; 3832 3832 } 3833 3833 case MSR_IA32_FLUSH_CMD: ··· 3840 3840 if (!data) 3841 3841 break; 3842 3842 3843 3843 - wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH); 3843 3843 + wrmsrq(MSR_IA32_FLUSH_CMD, L1D_FLUSH); 3844 3844 break; 3845 3845 case MSR_EFER: 3846 3846 return set_efer(vcpu, msr_info); ··· 9736 9736 * with an exception. PAT[0] is set to WB on RESET and also by the 9737 9737 * kernel, i.e. failure indicates a kernel bug or broken firmware. 9738 9738 */ 9739 9739 - if (rdmsrl_safe(MSR_IA32_CR_PAT, &host_pat) || 9739 9739 + if (rdmsrq_safe(MSR_IA32_CR_PAT, &host_pat) || 9740 9740 (host_pat & GENMASK(2, 0)) != 6) { 9741 9741 pr_err("host PAT[0] is not WB\n"); 9742 9742 return -EIO; ··· 9770 9770 kvm_caps.supported_xcr0 = kvm_host.xcr0 & KVM_SUPPORTED_XCR0; 9771 9771 } 9772 9772 9773 9773 - rdmsrl_safe(MSR_EFER, &kvm_host.efer); 9773 9773 + rdmsrq_safe(MSR_EFER, &kvm_host.efer); 9774 9774 9775 9775 if (boot_cpu_has(X86_FEATURE_XSAVES)) 9776 9776 - rdmsrl(MSR_IA32_XSS, kvm_host.xss); 9776 9776 + rdmsrq(MSR_IA32_XSS, kvm_host.xss); 9777 9777 9778 9778 kvm_init_pmu_capability(ops->pmu_ops); 9779 9779 9780 9780 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) 9781 9781 - rdmsrl(MSR_IA32_ARCH_CAPABILITIES, kvm_host.arch_capabilities); 9781 9781 + rdmsrq(MSR_IA32_ARCH_CAPABILITIES, kvm_host.arch_capabilities); 9782 9782 9783 9783 r = ops->hardware_setup(); 9784 9784 if (r != 0) ··· 10974 10974 switch_fpu_return(); 10975 10975 10976 10976 if (vcpu->arch.guest_fpu.xfd_err) 10977 10977 - wrmsrl(MSR_IA32_XFD_ERR, vcpu->arch.guest_fpu.xfd_err); 10977 10977 + wrmsrq(MSR_IA32_XFD_ERR, vcpu->arch.guest_fpu.xfd_err); 10978 10978 10979 10979 if (unlikely(vcpu->arch.switch_db_regs)) { 10980 10980 set_debugreg(0, 7); ··· 11060 11060 kvm_x86_call(handle_exit_irqoff)(vcpu); 11061 11061 11062 11062 if (vcpu->arch.guest_fpu.xfd_err) 11063 11063 - wrmsrl(MSR_IA32_XFD_ERR, 0); 11063 11063 + wrmsrq(MSR_IA32_XFD_ERR, 0); 11064 11064 11065 11065 /* 11066 11066 * Consume any pending interrupts, including the possible source of ··· 13666 13666 13667 13667 local_irq_save(flags); 13668 13668 13669 13669 - if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value)) 13669 13669 + if (rdmsrq_safe(MSR_IA32_SPEC_CTRL, &saved_value)) 13670 13670 ret = 1; 13671 13671 - else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value)) 13671 13671 + else if (wrmsrq_safe(MSR_IA32_SPEC_CTRL, value)) 13672 13672 ret = 1; 13673 13673 else 13674 13674 - wrmsrl(MSR_IA32_SPEC_CTRL, saved_value); 13674 13674 + wrmsrq(MSR_IA32_SPEC_CTRL, saved_value); 13675 13675 13676 13676 local_irq_restore(flags); 13677 13677

+4 -3

arch/x86/lib/insn-eval.c

reviewed

··· 13 13 #include <asm/insn.h> 14 14 #include <asm/insn-eval.h> 15 15 #include <asm/ldt.h> 16 16 + #include <asm/msr.h> 16 17 #include <asm/vm86.h> 17 18 18 19 #undef pr_fmt ··· 710 709 unsigned long base; 711 710 712 711 if (seg_reg_idx == INAT_SEG_REG_FS) { 713 713 - rdmsrl(MSR_FS_BASE, base); 712 712 + rdmsrq(MSR_FS_BASE, base); 714 713 } else if (seg_reg_idx == INAT_SEG_REG_GS) { 715 714 /* 716 715 * swapgs was called at the kernel entry point. Thus, 717 716 * MSR_KERNEL_GS_BASE will have the user-space GS base. 718 717 */ 719 718 if (user_mode(regs)) 720 720 - rdmsrl(MSR_KERNEL_GS_BASE, base); 719 719 + rdmsrq(MSR_KERNEL_GS_BASE, base); 721 720 else 722 722 - rdmsrl(MSR_GS_BASE, base); 721 721 + rdmsrq(MSR_GS_BASE, base); 723 722 } else { 724 723 base = 0; 725 724 }

+1 -1

arch/x86/lib/kaslr.c

reviewed

··· 8 8 */ 9 9 #include <asm/asm.h> 10 10 #include <asm/kaslr.h> 11 11 - #include <asm/msr.h> 11 11 + #include <asm/tsc.h> 12 12 #include <asm/archrandom.h> 13 13 #include <asm/e820/api.h> 14 14 #include <asm/shared/io.h>

+8 -8

arch/x86/lib/msr-smp.c

reviewed

··· 47 47 } 48 48 EXPORT_SYMBOL(rdmsr_on_cpu); 49 49 50 50 - int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) 50 50 + int rdmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) 51 51 { 52 52 int err; 53 53 struct msr_info rv; ··· 60 60 61 61 return err; 62 62 } 63 63 - EXPORT_SYMBOL(rdmsrl_on_cpu); 63 63 + EXPORT_SYMBOL(rdmsrq_on_cpu); 64 64 65 65 int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) 66 66 { ··· 78 78 } 79 79 EXPORT_SYMBOL(wrmsr_on_cpu); 80 80 81 81 - int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q) 81 81 + int wrmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 q) 82 82 { 83 83 int err; 84 84 struct msr_info rv; ··· 92 92 93 93 return err; 94 94 } 95 95 - EXPORT_SYMBOL(wrmsrl_on_cpu); 95 95 + EXPORT_SYMBOL(wrmsrq_on_cpu); 96 96 97 97 static void __rwmsr_on_cpus(const struct cpumask *mask, u32 msr_no, 98 98 struct msr __percpu *msrs, ··· 204 204 } 205 205 EXPORT_SYMBOL(wrmsr_safe_on_cpu); 206 206 207 207 - int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q) 207 207 + int wrmsrq_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q) 208 208 { 209 209 int err; 210 210 struct msr_info rv; ··· 218 218 219 219 return err ? err : rv.err; 220 220 } 221 221 - EXPORT_SYMBOL(wrmsrl_safe_on_cpu); 221 221 + EXPORT_SYMBOL(wrmsrq_safe_on_cpu); 222 222 223 223 - int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) 223 223 + int rdmsrq_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) 224 224 { 225 225 u32 low, high; 226 226 int err; ··· 230 230 231 231 return err; 232 232 } 233 233 - EXPORT_SYMBOL(rdmsrl_safe_on_cpu); 233 233 + EXPORT_SYMBOL(rdmsrq_safe_on_cpu); 234 234 235 235 /* 236 236 * These variants are significantly slower, but allows control over

+6 -6

arch/x86/lib/msr.c

reviewed

··· 41 41 int err; 42 42 u64 val; 43 43 44 44 - err = rdmsrl_safe(msr, &val); 44 44 + err = rdmsrq_safe(msr, &val); 45 45 if (!err) 46 46 m->q = val; 47 47 ··· 58 58 */ 59 59 static int msr_write(u32 msr, struct msr *m) 60 60 { 61 61 - return wrmsrl_safe(msr, m->q); 61 61 + return wrmsrq_safe(msr, m->q); 62 62 } 63 63 64 64 static inline int __flip_bit(u32 msr, u8 bit, bool set) ··· 122 122 EXPORT_SYMBOL_GPL(msr_clear_bit); 123 123 124 124 #ifdef CONFIG_TRACEPOINTS 125 125 - void do_trace_write_msr(unsigned int msr, u64 val, int failed) 125 125 + void do_trace_write_msr(u32 msr, u64 val, int failed) 126 126 { 127 127 trace_write_msr(msr, val, failed); 128 128 } 129 129 EXPORT_SYMBOL(do_trace_write_msr); 130 130 EXPORT_TRACEPOINT_SYMBOL(write_msr); 131 131 132 132 - void do_trace_read_msr(unsigned int msr, u64 val, int failed) 132 132 + void do_trace_read_msr(u32 msr, u64 val, int failed) 133 133 { 134 134 trace_read_msr(msr, val, failed); 135 135 } 136 136 EXPORT_SYMBOL(do_trace_read_msr); 137 137 EXPORT_TRACEPOINT_SYMBOL(read_msr); 138 138 139 139 - void do_trace_rdpmc(unsigned counter, u64 val, int failed) 139 139 + void do_trace_rdpmc(u32 msr, u64 val, int failed) 140 140 { 141 141 - trace_rdpmc(counter, val, failed); 141 141 + trace_rdpmc(msr, val, failed); 142 142 } 143 143 EXPORT_SYMBOL(do_trace_rdpmc); 144 144 EXPORT_TRACEPOINT_SYMBOL(rdpmc);

+2 -2

arch/x86/mm/pat/memtype.c

reviewed

··· 233 233 panic("x86/PAT: PAT enabled, but not supported by secondary CPU\n"); 234 234 } 235 235 236 236 - wrmsrl(MSR_IA32_CR_PAT, pat_msr_val); 236 236 + wrmsrq(MSR_IA32_CR_PAT, pat_msr_val); 237 237 238 238 __flush_tlb_all(); 239 239 } ··· 257 257 if (!cpu_feature_enabled(X86_FEATURE_PAT)) 258 258 pat_disable("PAT not supported by the CPU."); 259 259 else 260 260 - rdmsrl(MSR_IA32_CR_PAT, pat_msr_val); 260 260 + rdmsrq(MSR_IA32_CR_PAT, pat_msr_val); 261 261 262 262 if (!pat_msr_val) { 263 263 pat_disable("PAT support disabled by the firmware.");

+2 -1

arch/x86/mm/tlb.c

reviewed

··· 19 19 #include <asm/cache.h> 20 20 #include <asm/cacheflush.h> 21 21 #include <asm/apic.h> 22 22 + #include <asm/msr.h> 22 23 #include <asm/perf_event.h> 23 24 #include <asm/tlb.h> 24 25 ··· 629 628 { 630 629 /* Flush L1D if the outgoing task requests it */ 631 630 if (prev_mm & LAST_USER_MM_L1D_FLUSH) 632 632 - wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH); 631 631 + wrmsrq(MSR_IA32_FLUSH_CMD, L1D_FLUSH); 633 632 634 633 /* Check whether the incoming task opted in for L1D flush */ 635 634 if (likely(!(next_mm & LAST_USER_MM_L1D_FLUSH)))

+5 -5

arch/x86/pci/amd_bus.c

reviewed

··· 202 202 203 203 /* need to take out [0, TOM) for RAM*/ 204 204 address = MSR_K8_TOP_MEM1; 205 205 - rdmsrl(address, val); 205 205 + rdmsrq(address, val); 206 206 end = (val & 0xffffff800000ULL); 207 207 printk(KERN_INFO "TOM: %016llx aka %lldM\n", end, end>>20); 208 208 if (end < (1ULL<<32)) ··· 293 293 /* need to take out [4G, TOM2) for RAM*/ 294 294 /* SYS_CFG */ 295 295 address = MSR_AMD64_SYSCFG; 296 296 - rdmsrl(address, val); 296 296 + rdmsrq(address, val); 297 297 /* TOP_MEM2 is enabled? */ 298 298 if (val & (1<<21)) { 299 299 /* TOP_MEM2 */ 300 300 address = MSR_K8_TOP_MEM2; 301 301 - rdmsrl(address, val); 301 301 + rdmsrq(address, val); 302 302 end = (val & 0xffffff800000ULL); 303 303 printk(KERN_INFO "TOM2: %016llx aka %lldM\n", end, end>>20); 304 304 subtract_range(range, RANGE_NUM, 1ULL<<32, end); ··· 341 341 { 342 342 u64 reg; 343 343 344 344 - rdmsrl(MSR_AMD64_NB_CFG, reg); 344 344 + rdmsrq(MSR_AMD64_NB_CFG, reg); 345 345 if (!(reg & ENABLE_CF8_EXT_CFG)) { 346 346 reg |= ENABLE_CF8_EXT_CFG; 347 347 - wrmsrl(MSR_AMD64_NB_CFG, reg); 347 347 + wrmsrq(MSR_AMD64_NB_CFG, reg); 348 348 } 349 349 return 0; 350 350 }

+3 -2

arch/x86/pci/mmconfig-shared.c

reviewed

··· 22 22 #include <linux/slab.h> 23 23 #include <linux/mutex.h> 24 24 #include <linux/rculist.h> 25 25 - #include <asm/e820/api.h> 26 26 - #include <asm/pci_x86.h> 27 25 #include <asm/acpi.h> 26 26 + #include <asm/e820/api.h> 27 27 + #include <asm/msr.h> 28 28 + #include <asm/pci_x86.h> 28 29 29 30 /* Indicate if the ECAM resources have been placed into the resource table */ 30 31 static bool pci_mmcfg_running_state;

+3 -3

arch/x86/platform/olpc/olpc-xo1-rtc.c

reviewed

··· 64 64 of_node_put(node); 65 65 66 66 pr_info("olpc-xo1-rtc: Initializing OLPC XO-1 RTC\n"); 67 67 - rdmsrl(MSR_RTC_DOMA_OFFSET, rtc_info.rtc_day_alarm); 68 68 - rdmsrl(MSR_RTC_MONA_OFFSET, rtc_info.rtc_mon_alarm); 69 69 - rdmsrl(MSR_RTC_CEN_OFFSET, rtc_info.rtc_century); 67 67 + rdmsrq(MSR_RTC_DOMA_OFFSET, rtc_info.rtc_day_alarm); 68 68 + rdmsrq(MSR_RTC_MONA_OFFSET, rtc_info.rtc_mon_alarm); 69 69 + rdmsrq(MSR_RTC_CEN_OFFSET, rtc_info.rtc_century); 70 70 71 71 r = platform_device_register(&xo1_rtc_device); 72 72 if (r)

+1 -1

arch/x86/platform/olpc/olpc-xo1-sci.c

reviewed

··· 325 325 dev_info(&pdev->dev, "SCI unmapped. Mapping to IRQ 3\n"); 326 326 sci_irq = 3; 327 327 lo |= 0x00300000; 328 328 - wrmsrl(0x51400020, lo); 328 328 + wrmsrq(0x51400020, lo); 329 329 } 330 330 331 331 /* Select level triggered in PIC */

+14 -13

arch/x86/power/cpu.c

reviewed

··· 27 27 #include <asm/mmu_context.h> 28 28 #include <asm/cpu_device_id.h> 29 29 #include <asm/microcode.h> 30 30 + #include <asm/msr.h> 30 31 #include <asm/fred.h> 31 32 32 33 #ifdef CONFIG_X86_32 ··· 45 44 46 45 while (msr < end) { 47 46 if (msr->valid) 48 48 - rdmsrl(msr->info.msr_no, msr->info.reg.q); 47 47 + rdmsrq(msr->info.msr_no, msr->info.reg.q); 49 48 msr++; 50 49 } 51 50 } ··· 57 56 58 57 while (msr < end) { 59 58 if (msr->valid) 60 60 - wrmsrl(msr->info.msr_no, msr->info.reg.q); 59 59 + wrmsrq(msr->info.msr_no, msr->info.reg.q); 61 60 msr++; 62 61 } 63 62 } ··· 111 110 savesegment(ds, ctxt->ds); 112 111 savesegment(es, ctxt->es); 113 112 114 114 - rdmsrl(MSR_FS_BASE, ctxt->fs_base); 115 115 - rdmsrl(MSR_GS_BASE, ctxt->kernelmode_gs_base); 116 116 - rdmsrl(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base); 113 113 + rdmsrq(MSR_FS_BASE, ctxt->fs_base); 114 114 + rdmsrq(MSR_GS_BASE, ctxt->kernelmode_gs_base); 115 115 + rdmsrq(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base); 117 116 mtrr_save_fixed_ranges(NULL); 118 117 119 119 - rdmsrl(MSR_EFER, ctxt->efer); 118 118 + rdmsrq(MSR_EFER, ctxt->efer); 120 119 #endif 121 120 122 121 /* ··· 126 125 ctxt->cr2 = read_cr2(); 127 126 ctxt->cr3 = __read_cr3(); 128 127 ctxt->cr4 = __read_cr4(); 129 129 - ctxt->misc_enable_saved = !rdmsrl_safe(MSR_IA32_MISC_ENABLE, 128 128 + ctxt->misc_enable_saved = !rdmsrq_safe(MSR_IA32_MISC_ENABLE, 130 129 &ctxt->misc_enable); 131 130 msr_save_context(ctxt); 132 131 } ··· 199 198 struct cpuinfo_x86 *c; 200 199 201 200 if (ctxt->misc_enable_saved) 202 202 - wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable); 201 201 + wrmsrq(MSR_IA32_MISC_ENABLE, ctxt->misc_enable); 203 202 /* 204 203 * control registers 205 204 */ ··· 209 208 __write_cr4(ctxt->cr4); 210 209 #else 211 210 /* CONFIG X86_64 */ 212 212 - wrmsrl(MSR_EFER, ctxt->efer); 211 211 + wrmsrq(MSR_EFER, ctxt->efer); 213 212 __write_cr4(ctxt->cr4); 214 213 #endif 215 214 write_cr3(ctxt->cr3); ··· 232 231 * handlers or in complicated helpers like load_gs_index(). 233 232 */ 234 233 #ifdef CONFIG_X86_64 235 235 - wrmsrl(MSR_GS_BASE, ctxt->kernelmode_gs_base); 234 234 + wrmsrq(MSR_GS_BASE, ctxt->kernelmode_gs_base); 236 235 237 236 /* 238 237 * Reinitialize FRED to ensure the FRED MSRs contain the same values ··· 268 267 * restoring the selectors clobbers the bases. Keep in mind 269 268 * that MSR_KERNEL_GS_BASE is horribly misnamed. 270 269 */ 271 271 - wrmsrl(MSR_FS_BASE, ctxt->fs_base); 272 272 - wrmsrl(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base); 270 270 + wrmsrq(MSR_FS_BASE, ctxt->fs_base); 271 271 + wrmsrq(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base); 273 272 #else 274 273 loadsegment(gs, ctxt->gs); 275 274 #endif ··· 415 414 u64 dummy; 416 415 417 416 msr_array[i].info.msr_no = msr_id[j]; 418 418 - msr_array[i].valid = !rdmsrl_safe(msr_id[j], &dummy); 417 417 + msr_array[i].valid = !rdmsrq_safe(msr_id[j], &dummy); 419 418 msr_array[i].info.reg.q = 0; 420 419 } 421 420 saved_msrs->num = total_num;

+2 -1

arch/x86/realmode/init.c

reviewed

··· 9 9 #include <asm/realmode.h> 10 10 #include <asm/tlbflush.h> 11 11 #include <asm/crash.h> 12 12 + #include <asm/msr.h> 12 13 #include <asm/sev.h> 13 14 14 15 struct real_mode_header *real_mode_header; ··· 146 145 * Some AMD processors will #GP(0) if EFER.LMA is set in WRMSR 147 146 * so we need to mask it out. 148 147 */ 149 149 - rdmsrl(MSR_EFER, efer); 148 148 + rdmsrq(MSR_EFER, efer); 150 149 trampoline_header->efer = efer & ~EFER_LMA; 151 150 152 151 trampoline_header->start = (u64) secondary_startup_64;

+11 -10

arch/x86/virt/svm/sev.c

reviewed

··· 30 30 #include <asm/cpuid.h> 31 31 #include <asm/cmdline.h> 32 32 #include <asm/iommu.h> 33 33 + #include <asm/msr.h> 33 34 34 35 /* 35 36 * The RMP entry information as returned by the RMPREAD instruction. ··· 137 136 if (!cc_platform_has(CC_ATTR_HOST_SEV_SNP)) 138 137 return 0; 139 138 140 140 - rdmsrl(MSR_AMD64_SYSCFG, val); 139 139 + rdmsrq(MSR_AMD64_SYSCFG, val); 141 140 142 141 val |= MSR_AMD64_SYSCFG_MFDM; 143 142 144 144 - wrmsrl(MSR_AMD64_SYSCFG, val); 143 143 + wrmsrq(MSR_AMD64_SYSCFG, val); 145 144 146 145 return 0; 147 146 } ··· 158 157 if (!cc_platform_has(CC_ATTR_HOST_SEV_SNP)) 159 158 return 0; 160 159 161 161 - rdmsrl(MSR_AMD64_SYSCFG, val); 160 160 + rdmsrq(MSR_AMD64_SYSCFG, val); 162 161 163 162 val |= MSR_AMD64_SYSCFG_SNP_EN; 164 163 val |= MSR_AMD64_SYSCFG_SNP_VMPL_EN; 165 164 166 166 - wrmsrl(MSR_AMD64_SYSCFG, val); 165 165 + wrmsrq(MSR_AMD64_SYSCFG, val); 167 166 168 167 return 0; 169 168 } ··· 523 522 * Check if SEV-SNP is already enabled, this can happen in case of 524 523 * kexec boot. 525 524 */ 526 526 - rdmsrl(MSR_AMD64_SYSCFG, val); 525 525 + rdmsrq(MSR_AMD64_SYSCFG, val); 527 526 if (val & MSR_AMD64_SYSCFG_SNP_EN) 528 527 goto skip_enable; 529 528 ··· 577 576 { 578 577 u64 rmp_sz, rmp_base, rmp_end; 579 578 580 580 - rdmsrl(MSR_AMD64_RMP_BASE, rmp_base); 581 581 - rdmsrl(MSR_AMD64_RMP_END, rmp_end); 579 579 + rdmsrq(MSR_AMD64_RMP_BASE, rmp_base); 580 580 + rdmsrq(MSR_AMD64_RMP_END, rmp_end); 582 581 583 582 if (!(rmp_base & RMP_ADDR_MASK) || !(rmp_end & RMP_ADDR_MASK)) { 584 583 pr_err("Memory for the RMP table has not been reserved by BIOS\n"); ··· 611 610 unsigned int eax, ebx, segment_shift, segment_shift_min, segment_shift_max; 612 611 u64 rmp_base, rmp_end; 613 612 614 614 - rdmsrl(MSR_AMD64_RMP_BASE, rmp_base); 613 613 + rdmsrq(MSR_AMD64_RMP_BASE, rmp_base); 615 614 if (!(rmp_base & RMP_ADDR_MASK)) { 616 615 pr_err("Memory for the RMP table has not been reserved by BIOS\n"); 617 616 return false; 618 617 } 619 618 620 620 - rdmsrl(MSR_AMD64_RMP_END, rmp_end); 619 619 + rdmsrq(MSR_AMD64_RMP_END, rmp_end); 621 620 WARN_ONCE(rmp_end & RMP_ADDR_MASK, 622 621 "Segmented RMP enabled but RMP_END MSR is non-zero\n"); 623 622 ··· 653 652 bool snp_probe_rmptable_info(void) 654 653 { 655 654 if (cpu_feature_enabled(X86_FEATURE_SEGMENTED_RMP)) 656 656 - rdmsrl(MSR_AMD64_RMP_CFG, rmp_cfg); 655 655 + rdmsrq(MSR_AMD64_RMP_CFG, rmp_cfg); 657 656 658 657 if (rmp_cfg & MSR_AMD64_SEG_RMP_ENABLED) 659 658 return probe_segmented_rmptable_info();

+27 -32

arch/x86/xen/enlighten_pv.c

reviewed

··· 61 61 #include <asm/processor.h> 62 62 #include <asm/proto.h> 63 63 #include <asm/msr-index.h> 64 64 + #include <asm/msr.h> 64 65 #include <asm/traps.h> 65 66 #include <asm/setup.h> 66 67 #include <asm/desc.h> ··· 1087 1086 native_write_cr4(cr4); 1088 1087 } 1089 1088 1090 1090 - static u64 xen_do_read_msr(unsigned int msr, int *err) 1089 1089 + static u64 xen_do_read_msr(u32 msr, int *err) 1091 1090 { 1092 1091 u64 val = 0; /* Avoid uninitialized value for safe variant. */ 1093 1092 1094 1094 - if (pmu_msr_read(msr, &val, err)) 1093 1093 + if (pmu_msr_chk_emulated(msr, &val, true)) 1095 1094 return val; 1096 1095 1097 1096 if (err) 1098 1098 - val = native_read_msr_safe(msr, err); 1097 1097 + *err = native_read_msr_safe(msr, &val); 1099 1098 else 1100 1099 val = native_read_msr(msr); 1101 1100 ··· 1111 1110 return val; 1112 1111 } 1113 1112 1114 1114 - static void set_seg(unsigned int which, unsigned int low, unsigned int high, 1115 1115 - int *err) 1113 1113 + static void set_seg(u32 which, u64 base) 1116 1114 { 1117 1117 - u64 base = ((u64)high << 32) | low; 1118 1118 - 1119 1119 - if (HYPERVISOR_set_segment_base(which, base) == 0) 1120 1120 - return; 1121 1121 - 1122 1122 - if (err) 1123 1123 - *err = -EIO; 1124 1124 - else 1115 1115 + if (HYPERVISOR_set_segment_base(which, base)) 1125 1116 WARN(1, "Xen set_segment_base(%u, %llx) failed\n", which, base); 1126 1117 } 1127 1118 ··· 1122 1129 * With err == NULL write_msr() semantics are selected. 1123 1130 * Supplying an err pointer requires err to be pre-initialized with 0. 1124 1131 */ 1125 1125 - static void xen_do_write_msr(unsigned int msr, unsigned int low, 1126 1126 - unsigned int high, int *err) 1132 1132 + static void xen_do_write_msr(u32 msr, u64 val, int *err) 1127 1133 { 1128 1134 switch (msr) { 1129 1135 case MSR_FS_BASE: 1130 1130 - set_seg(SEGBASE_FS, low, high, err); 1136 1136 + set_seg(SEGBASE_FS, val); 1131 1137 break; 1132 1138 1133 1139 case MSR_KERNEL_GS_BASE: 1134 1134 - set_seg(SEGBASE_GS_USER, low, high, err); 1140 1140 + set_seg(SEGBASE_GS_USER, val); 1135 1141 break; 1136 1142 1137 1143 case MSR_GS_BASE: 1138 1138 - set_seg(SEGBASE_GS_KERNEL, low, high, err); 1144 1144 + set_seg(SEGBASE_GS_KERNEL, val); 1139 1145 break; 1140 1146 1141 1147 case MSR_STAR: ··· 1150 1158 break; 1151 1159 1152 1160 default: 1153 1153 - if (!pmu_msr_write(msr, low, high, err)) { 1154 1154 - if (err) 1155 1155 - *err = native_write_msr_safe(msr, low, high); 1156 1156 - else 1157 1157 - native_write_msr(msr, low, high); 1158 1158 - } 1161 1161 + if (pmu_msr_chk_emulated(msr, &val, false)) 1162 1162 + return; 1163 1163 + 1164 1164 + if (err) 1165 1165 + *err = native_write_msr_safe(msr, val); 1166 1166 + else 1167 1167 + native_write_msr(msr, val); 1159 1168 } 1160 1169 } 1161 1170 1162 1162 - static u64 xen_read_msr_safe(unsigned int msr, int *err) 1171 1171 + static int xen_read_msr_safe(u32 msr, u64 *val) 1163 1172 { 1164 1164 - return xen_do_read_msr(msr, err); 1173 1173 + int err; 1174 1174 + 1175 1175 + *val = xen_do_read_msr(msr, &err); 1176 1176 + return err; 1165 1177 } 1166 1178 1167 1167 - static int xen_write_msr_safe(unsigned int msr, unsigned int low, 1168 1168 - unsigned int high) 1179 1179 + static int xen_write_msr_safe(u32 msr, u64 val) 1169 1180 { 1170 1181 int err = 0; 1171 1182 1172 1172 - xen_do_write_msr(msr, low, high, &err); 1183 1183 + xen_do_write_msr(msr, val, &err); 1173 1184 1174 1185 return err; 1175 1186 } 1176 1187 1177 1177 - static u64 xen_read_msr(unsigned int msr) 1188 1188 + static u64 xen_read_msr(u32 msr) 1178 1189 { 1179 1190 int err; 1180 1191 1181 1192 return xen_do_read_msr(msr, xen_msr_safe ? &err : NULL); 1182 1193 } 1183 1194 1184 1184 - static void xen_write_msr(unsigned int msr, unsigned low, unsigned high) 1195 1195 + static void xen_write_msr(u32 msr, u64 val) 1185 1196 { 1186 1197 int err; 1187 1198 1188 1188 - xen_do_write_msr(msr, low, high, xen_msr_safe ? &err : NULL); 1199 1199 + xen_do_write_msr(msr, val, xen_msr_safe ? &err : NULL); 1189 1200 } 1190 1201 1191 1202 /* This is called once we have the cpu_possible_mask */

+21 -54

arch/x86/xen/pmu.c

reviewed

··· 2 2 #include <linux/types.h> 3 3 #include <linux/interrupt.h> 4 4 5 5 + #include <asm/msr.h> 5 6 #include <asm/xen/hypercall.h> 6 7 #include <xen/xen.h> 7 8 #include <xen/page.h> ··· 129 128 return addr; 130 129 } 131 130 132 132 - static inline bool is_amd_pmu_msr(unsigned int msr) 131 131 + static bool is_amd_pmu_msr(u32 msr) 133 132 { 134 133 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD && 135 134 boot_cpu_data.x86_vendor != X86_VENDOR_HYGON) ··· 195 194 } 196 195 } 197 196 198 198 - static bool xen_intel_pmu_emulate(unsigned int msr, u64 *val, int type, 199 199 - int index, bool is_read) 197 197 + static bool xen_intel_pmu_emulate(u32 msr, u64 *val, int type, int index, bool is_read) 200 198 { 201 199 uint64_t *reg = NULL; 202 200 struct xen_pmu_intel_ctxt *ctxt; ··· 257 257 return false; 258 258 } 259 259 260 260 - static bool xen_amd_pmu_emulate(unsigned int msr, u64 *val, bool is_read) 260 260 + static bool xen_amd_pmu_emulate(u32 msr, u64 *val, bool is_read) 261 261 { 262 262 uint64_t *reg = NULL; 263 263 int i, off = 0; ··· 298 298 return false; 299 299 } 300 300 301 301 - static bool pmu_msr_chk_emulated(unsigned int msr, uint64_t *val, bool is_read, 302 302 - bool *emul) 301 301 + bool pmu_msr_chk_emulated(u32 msr, u64 *val, bool is_read) 303 302 { 304 303 int type, index = 0; 305 304 306 305 if (is_amd_pmu_msr(msr)) 307 307 - *emul = xen_amd_pmu_emulate(msr, val, is_read); 308 308 - else if (is_intel_pmu_msr(msr, &type, &index)) 309 309 - *emul = xen_intel_pmu_emulate(msr, val, type, index, is_read); 310 310 - else 311 311 - return false; 306 306 + return xen_amd_pmu_emulate(msr, val, is_read); 312 307 313 313 - return true; 308 308 + if (is_intel_pmu_msr(msr, &type, &index)) 309 309 + return xen_intel_pmu_emulate(msr, val, type, index, is_read); 310 310 + 311 311 + return false; 314 312 } 315 313 316 316 - bool pmu_msr_read(unsigned int msr, uint64_t *val, int *err) 317 317 - { 318 318 - bool emulated; 319 319 - 320 320 - if (!pmu_msr_chk_emulated(msr, val, true, &emulated)) 321 321 - return false; 322 322 - 323 323 - if (!emulated) { 324 324 - *val = err ? native_read_msr_safe(msr, err) 325 325 - : native_read_msr(msr); 326 326 - } 327 327 - 328 328 - return true; 329 329 - } 330 330 - 331 331 - bool pmu_msr_write(unsigned int msr, uint32_t low, uint32_t high, int *err) 332 332 - { 333 333 - uint64_t val = ((uint64_t)high << 32) | low; 334 334 - bool emulated; 335 335 - 336 336 - if (!pmu_msr_chk_emulated(msr, &val, false, &emulated)) 337 337 - return false; 338 338 - 339 339 - if (!emulated) { 340 340 - if (err) 341 341 - *err = native_write_msr_safe(msr, low, high); 342 342 - else 343 343 - native_write_msr(msr, low, high); 344 344 - } 345 345 - 346 346 - return true; 347 347 - } 348 348 - 349 349 - static unsigned long long xen_amd_read_pmc(int counter) 314 314 + static u64 xen_amd_read_pmc(int counter) 350 315 { 351 316 struct xen_pmu_amd_ctxt *ctxt; 352 317 uint64_t *counter_regs; ··· 319 354 uint8_t xenpmu_flags = get_xenpmu_flags(); 320 355 321 356 if (!xenpmu_data || !(xenpmu_flags & XENPMU_IRQ_PROCESSING)) { 322 322 - uint32_t msr; 323 323 - int err; 357 357 + u32 msr; 358 358 + u64 val; 324 359 325 360 msr = amd_counters_base + (counter * amd_msr_step); 326 326 - return native_read_msr_safe(msr, &err); 361 361 + native_read_msr_safe(msr, &val); 362 362 + return val; 327 363 } 328 364 329 365 ctxt = &xenpmu_data->pmu.c.amd; ··· 332 366 return counter_regs[counter]; 333 367 } 334 368 335 335 - static unsigned long long xen_intel_read_pmc(int counter) 369 369 + static u64 xen_intel_read_pmc(int counter) 336 370 { 337 371 struct xen_pmu_intel_ctxt *ctxt; 338 372 uint64_t *fixed_counters; ··· 341 375 uint8_t xenpmu_flags = get_xenpmu_flags(); 342 376 343 377 if (!xenpmu_data || !(xenpmu_flags & XENPMU_IRQ_PROCESSING)) { 344 344 - uint32_t msr; 345 345 - int err; 378 378 + u32 msr; 379 379 + u64 val; 346 380 347 381 if (counter & (1 << INTEL_PMC_TYPE_SHIFT)) 348 382 msr = MSR_CORE_PERF_FIXED_CTR0 + (counter & 0xffff); 349 383 else 350 384 msr = MSR_IA32_PERFCTR0 + counter; 351 385 352 352 - return native_read_msr_safe(msr, &err); 386 386 + native_read_msr_safe(msr, &val); 387 387 + return val; 353 388 } 354 389 355 390 ctxt = &xenpmu_data->pmu.c.intel; ··· 363 396 return arch_cntr_pair[counter].counter; 364 397 } 365 398 366 366 - unsigned long long xen_read_pmc(int counter) 399 399 + u64 xen_read_pmc(int counter) 367 400 { 368 401 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 369 402 return xen_amd_read_pmc(counter);

+4 -3

arch/x86/xen/suspend.c

reviewed

··· 13 13 #include <asm/xen/hypercall.h> 14 14 #include <asm/xen/page.h> 15 15 #include <asm/fixmap.h> 16 16 + #include <asm/msr.h> 16 17 17 18 #include "xen-ops.h" 18 19 ··· 40 39 static void xen_vcpu_notify_restore(void *data) 41 40 { 42 41 if (xen_pv_domain() && boot_cpu_has(X86_FEATURE_SPEC_CTRL)) 43 43 - wrmsrl(MSR_IA32_SPEC_CTRL, this_cpu_read(spec_ctrl)); 42 42 + wrmsrq(MSR_IA32_SPEC_CTRL, this_cpu_read(spec_ctrl)); 44 43 45 44 /* Boot processor notified via generic timekeeping_resume() */ 46 45 if (smp_processor_id() == 0) ··· 56 55 tick_suspend_local(); 57 56 58 57 if (xen_pv_domain() && boot_cpu_has(X86_FEATURE_SPEC_CTRL)) { 59 59 - rdmsrl(MSR_IA32_SPEC_CTRL, tmp); 58 58 + rdmsrq(MSR_IA32_SPEC_CTRL, tmp); 60 59 this_cpu_write(spec_ctrl, tmp); 61 61 - wrmsrl(MSR_IA32_SPEC_CTRL, 0); 60 60 + wrmsrq(MSR_IA32_SPEC_CTRL, 0); 62 61 } 63 62 } 64 63

+2 -3

arch/x86/xen/xen-ops.h

reviewed

··· 271 271 static inline void xen_pmu_init(int cpu) {} 272 272 static inline void xen_pmu_finish(int cpu) {} 273 273 #endif 274 274 - bool pmu_msr_read(unsigned int msr, uint64_t *val, int *err); 275 275 - bool pmu_msr_write(unsigned int msr, uint32_t low, uint32_t high, int *err); 274 274 + bool pmu_msr_chk_emulated(u32 msr, u64 *val, bool is_read); 276 275 int pmu_apic_update(uint32_t reg); 277 277 - unsigned long long xen_read_pmc(int counter); 276 276 + u64 xen_read_pmc(int counter); 278 277 279 278 #ifdef CONFIG_SMP 280 279

+1 -1

drivers/accel/habanalabs/Kconfig

reviewed

··· 6 6 config DRM_ACCEL_HABANALABS 7 7 tristate "HabanaLabs AI accelerators" 8 8 depends on DRM_ACCEL 9 9 - depends on X86_64 9 9 + depends on X86 && X86_64 10 10 depends on PCI && HAS_IOMEM 11 11 select GENERIC_ALLOCATOR 12 12 select HWMON

-2

drivers/accel/habanalabs/common/habanalabs_ioctl.c

reviewed

··· 17 17 #include <linux/uaccess.h> 18 18 #include <linux/vmalloc.h> 19 19 20 20 - #include <asm/msr.h> 21 21 - 22 20 /* make sure there is space for all the signed info */ 23 21 static_assert(sizeof(struct cpucp_info) <= SEC_DEV_INFO_BUF_SZ); 24 22

+2 -1

drivers/acpi/acpi_extlog.c

reviewed

··· 15 15 #include <acpi/ghes.h> 16 16 #include <asm/cpu.h> 17 17 #include <asm/mce.h> 18 18 + #include <asm/msr.h> 18 19 19 20 #include "apei/apei-internal.h" 20 21 #include <ras/ras_event.h> ··· 235 234 u64 cap; 236 235 int rc; 237 236 238 238 - if (rdmsrl_safe(MSR_IA32_MCG_CAP, &cap) || 237 237 + if (rdmsrq_safe(MSR_IA32_MCG_CAP, &cap) || 239 238 !(cap & MCG_ELOG_P) || 240 239 !extlog_get_l1addr()) 241 240 return -ENODEV;

+1 -1

drivers/acpi/acpi_lpit.c

reviewed

··· 39 39 return 0; 40 40 } 41 41 42 42 - err = rdmsrl_safe(residency_info_ffh.gaddr.address, counter); 42 42 + err = rdmsrq_safe(residency_info_ffh.gaddr.address, counter); 43 43 if (!err) { 44 44 u64 mask = GENMASK_ULL(residency_info_ffh.gaddr.bit_offset + 45 45 residency_info_ffh.gaddr. bit_width - 1,

+1

drivers/acpi/processor_perflib.c

reviewed

··· 20 20 #include <acpi/processor.h> 21 21 #ifdef CONFIG_X86 22 22 #include <asm/cpufeature.h> 23 23 + #include <asm/msr.h> 23 24 #endif 24 25 25 26 #define ACPI_PROCESSOR_FILE_PERFORMANCE "performance"

+5 -1

drivers/acpi/processor_throttling.c

reviewed

··· 18 18 #include <linux/sched.h> 19 19 #include <linux/cpufreq.h> 20 20 #include <linux/acpi.h> 21 21 + #include <linux/uaccess.h> 21 22 #include <acpi/processor.h> 22 23 #include <asm/io.h> 23 23 - #include <linux/uaccess.h> 24 24 + #include <asm/asm.h> 25 25 + #ifdef CONFIG_X86 26 26 + #include <asm/msr.h> 27 27 + #endif 24 28 25 29 /* ignore_tpc: 26 30 * 0 -> acpi processor driver doesn't ignore _TPC values

+1

drivers/char/agp/nvidia-agp.c

reviewed

··· 11 11 #include <linux/page-flags.h> 12 12 #include <linux/mm.h> 13 13 #include <linux/jiffies.h> 14 14 + #include <asm/msr.h> 14 15 #include "agp.h" 15 16 16 17 /* NVIDIA registers */

+4 -4

drivers/cpufreq/acpi-cpufreq.c

reviewed

··· 79 79 case X86_VENDOR_INTEL: 80 80 case X86_VENDOR_CENTAUR: 81 81 case X86_VENDOR_ZHAOXIN: 82 82 - rdmsrl_on_cpu(cpu, MSR_IA32_MISC_ENABLE, &msr); 82 82 + rdmsrq_on_cpu(cpu, MSR_IA32_MISC_ENABLE, &msr); 83 83 return !(msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE); 84 84 case X86_VENDOR_HYGON: 85 85 case X86_VENDOR_AMD: 86 86 - rdmsrl_on_cpu(cpu, MSR_K7_HWCR, &msr); 86 86 + rdmsrq_on_cpu(cpu, MSR_K7_HWCR, &msr); 87 87 return !(msr & MSR_K7_HWCR_CPB_DIS); 88 88 } 89 89 return false; ··· 110 110 return -EINVAL; 111 111 } 112 112 113 113 - rdmsrl(msr_addr, val); 113 113 + rdmsrq(msr_addr, val); 114 114 115 115 if (enable) 116 116 val &= ~msr_mask; 117 117 else 118 118 val |= msr_mask; 119 119 120 120 - wrmsrl(msr_addr, val); 120 120 + wrmsrq(msr_addr, val); 121 121 return 0; 122 122 } 123 123

+5 -3

drivers/cpufreq/amd-pstate-ut.c

reviewed

··· 31 31 32 32 #include <acpi/cppc_acpi.h> 33 33 34 34 + #include <asm/msr.h> 35 35 + 34 36 #include "amd-pstate.h" 35 37 36 38 ··· 92 90 if (get_shared_mem()) 93 91 return 0; 94 92 95 95 - ret = rdmsrl_safe(MSR_AMD_CPPC_ENABLE, &cppc_enable); 93 93 + ret = rdmsrq_safe(MSR_AMD_CPPC_ENABLE, &cppc_enable); 96 94 if (ret) { 97 97 - pr_err("%s rdmsrl_safe MSR_AMD_CPPC_ENABLE ret=%d error!\n", __func__, ret); 95 95 + pr_err("%s rdmsrq_safe MSR_AMD_CPPC_ENABLE ret=%d error!\n", __func__, ret); 98 96 return ret; 99 97 } 100 98 ··· 139 137 lowest_nonlinear_perf = cppc_perf.lowest_nonlinear_perf; 140 138 lowest_perf = cppc_perf.lowest_perf; 141 139 } else { 142 142 - ret = rdmsrl_safe_on_cpu(cpu, MSR_AMD_CPPC_CAP1, &cap1); 140 140 + ret = rdmsrq_safe_on_cpu(cpu, MSR_AMD_CPPC_CAP1, &cap1); 143 141 if (ret) { 144 142 pr_err("%s read CPPC_CAP1 ret=%d error!\n", __func__, ret); 145 143 return ret;

+11 -11

drivers/cpufreq/amd-pstate.c

reviewed

··· 197 197 u64 value; 198 198 int ret; 199 199 200 200 - ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &value); 200 200 + ret = rdmsrq_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &value); 201 201 if (ret < 0) { 202 202 pr_debug("Could not retrieve energy perf value (%d)\n", ret); 203 203 return ret; ··· 258 258 return 0; 259 259 260 260 if (fast_switch) { 261 261 - wrmsrl(MSR_AMD_CPPC_REQ, value); 261 261 + wrmsrq(MSR_AMD_CPPC_REQ, value); 262 262 return 0; 263 263 } else { 264 264 - int ret = wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); 264 264 + int ret = wrmsrq_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); 265 265 266 266 if (ret) 267 267 return ret; ··· 309 309 if (value == prev) 310 310 return 0; 311 311 312 312 - ret = wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); 312 312 + ret = wrmsrq_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); 313 313 if (ret) { 314 314 pr_err("failed to set energy perf value (%d)\n", ret); 315 315 return ret; ··· 371 371 372 372 static inline int msr_cppc_enable(struct cpufreq_policy *policy) 373 373 { 374 374 - return wrmsrl_safe_on_cpu(policy->cpu, MSR_AMD_CPPC_ENABLE, 1); 374 374 + return wrmsrq_safe_on_cpu(policy->cpu, MSR_AMD_CPPC_ENABLE, 1); 375 375 } 376 376 377 377 static int shmem_cppc_enable(struct cpufreq_policy *policy) ··· 391 391 union perf_cached perf = READ_ONCE(cpudata->perf); 392 392 u64 cap1, numerator; 393 393 394 394 - int ret = rdmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1, 394 394 + int ret = rdmsrq_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1, 395 395 &cap1); 396 396 if (ret) 397 397 return ret; ··· 518 518 unsigned long flags; 519 519 520 520 local_irq_save(flags); 521 521 - rdmsrl(MSR_IA32_APERF, aperf); 522 522 - rdmsrl(MSR_IA32_MPERF, mperf); 521 521 + rdmsrq(MSR_IA32_APERF, aperf); 522 522 + rdmsrq(MSR_IA32_MPERF, mperf); 523 523 tsc = rdtsc(); 524 524 525 525 if (cpudata->prev.mperf == mperf || cpudata->prev.tsc == tsc) { ··· 772 772 goto exit_err; 773 773 } 774 774 775 775 - ret = rdmsrl_on_cpu(cpudata->cpu, MSR_K7_HWCR, &boost_val); 775 775 + ret = rdmsrq_on_cpu(cpudata->cpu, MSR_K7_HWCR, &boost_val); 776 776 if (ret) { 777 777 pr_err_once("failed to read initial CPU boost state!\n"); 778 778 ret = -EIO; ··· 791 791 792 792 static void amd_perf_ctl_reset(unsigned int cpu) 793 793 { 794 794 - wrmsrl_on_cpu(cpu, MSR_AMD_PERF_CTL, 0); 794 794 + wrmsrq_on_cpu(cpu, MSR_AMD_PERF_CTL, 0); 795 795 } 796 796 797 797 #define CPPC_MAX_PERF U8_MAX ··· 1485 1485 } 1486 1486 1487 1487 if (cpu_feature_enabled(X86_FEATURE_CPPC)) { 1488 1488 - ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &value); 1488 1488 + ret = rdmsrq_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &value); 1489 1489 if (ret) 1490 1490 return ret; 1491 1491 WRITE_ONCE(cpudata->cppc_req_cached, value);

+1 -1

drivers/cpufreq/amd_freq_sensitivity.c

reviewed

··· 129 129 pci_dev_put(pcidev); 130 130 } 131 131 132 132 - if (rdmsrl_safe(MSR_AMD64_FREQ_SENSITIVITY_ACTUAL, &val)) 132 132 + if (rdmsrq_safe(MSR_AMD64_FREQ_SENSITIVITY_ACTUAL, &val)) 133 133 return -ENODEV; 134 134 135 135 if (!(val >> CLASS_CODE_SHIFT))

+3 -3

drivers/cpufreq/e_powersaver.c

reviewed

··· 225 225 return -ENODEV; 226 226 } 227 227 /* Enable Enhanced PowerSaver */ 228 228 - rdmsrl(MSR_IA32_MISC_ENABLE, val); 228 228 + rdmsrq(MSR_IA32_MISC_ENABLE, val); 229 229 if (!(val & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) { 230 230 val |= MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP; 231 231 - wrmsrl(MSR_IA32_MISC_ENABLE, val); 231 231 + wrmsrq(MSR_IA32_MISC_ENABLE, val); 232 232 /* Can be locked at 0 */ 233 233 - rdmsrl(MSR_IA32_MISC_ENABLE, val); 233 233 + rdmsrq(MSR_IA32_MISC_ENABLE, val); 234 234 if (!(val & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) { 235 235 pr_info("Can't enable Enhanced PowerSaver\n"); 236 236 return -ENODEV;

-1

drivers/cpufreq/elanfreq.c

reviewed

··· 21 21 #include <linux/cpufreq.h> 22 22 23 23 #include <asm/cpu_device_id.h> 24 24 - #include <asm/msr.h> 25 24 #include <linux/timex.h> 26 25 #include <linux/io.h> 27 26

+54 -54

drivers/cpufreq/intel_pstate.c

reviewed

··· 601 601 if (!cpu_feature_enabled(X86_FEATURE_IDA)) 602 602 return true; 603 603 604 604 - rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); 604 604 + rdmsrq(MSR_IA32_MISC_ENABLE, misc_en); 605 605 606 606 return !!(misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE); 607 607 } ··· 623 623 if (!boot_cpu_has(X86_FEATURE_EPB)) 624 624 return -ENXIO; 625 625 626 626 - ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 626 626 + ret = rdmsrq_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 627 627 if (ret) 628 628 return (s16)ret; 629 629 ··· 640 640 * MSR_HWP_REQUEST, so need to read and get EPP. 641 641 */ 642 642 if (!hwp_req_data) { 643 643 - epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, 643 643 + epp = rdmsrq_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, 644 644 &hwp_req_data); 645 645 if (epp) 646 646 return epp; ··· 662 662 if (!boot_cpu_has(X86_FEATURE_EPB)) 663 663 return -ENXIO; 664 664 665 665 - ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 665 665 + ret = rdmsrq_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); 666 666 if (ret) 667 667 return ret; 668 668 669 669 epb = (epb & ~0x0f) | pref; 670 670 - wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb); 670 670 + wrmsrq_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb); 671 671 672 672 return 0; 673 673 } ··· 765 765 * function, so it cannot run in parallel with the update below. 766 766 */ 767 767 WRITE_ONCE(cpu->hwp_req_cached, value); 768 768 - ret = wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 768 768 + ret = wrmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 769 769 if (!ret) 770 770 cpu->epp_cached = epp; 771 771 ··· 919 919 if (ratio <= 0) { 920 920 u64 cap; 921 921 922 922 - rdmsrl_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap); 922 922 + rdmsrq_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap); 923 923 ratio = HWP_GUARANTEED_PERF(cap); 924 924 } 925 925 ··· 1091 1091 { 1092 1092 u64 cap; 1093 1093 1094 1094 - rdmsrl_on_cpu(cpu->cpu, MSR_HWP_CAPABILITIES, &cap); 1094 1094 + rdmsrq_on_cpu(cpu->cpu, MSR_HWP_CAPABILITIES, &cap); 1095 1095 WRITE_ONCE(cpu->hwp_cap_cached, cap); 1096 1096 cpu->pstate.max_pstate = HWP_GUARANTEED_PERF(cap); 1097 1097 cpu->pstate.turbo_pstate = HWP_HIGHEST_PERF(cap); ··· 1165 1165 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) 1166 1166 min = max; 1167 1167 1168 1168 - rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value); 1168 1168 + rdmsrq_on_cpu(cpu, MSR_HWP_REQUEST, &value); 1169 1169 1170 1170 value &= ~HWP_MIN_PERF(~0L); 1171 1171 value |= HWP_MIN_PERF(min); ··· 1212 1212 } 1213 1213 skip_epp: 1214 1214 WRITE_ONCE(cpu_data->hwp_req_cached, value); 1215 1215 - wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); 1215 1215 + wrmsrq_on_cpu(cpu, MSR_HWP_REQUEST, value); 1216 1216 } 1217 1217 1218 1218 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata); ··· 1259 1259 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) 1260 1260 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE); 1261 1261 1262 1262 - wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 1262 1262 + wrmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 1263 1263 1264 1264 mutex_lock(&hybrid_capacity_lock); 1265 1265 ··· 1288 1288 u64 power_ctl; 1289 1289 1290 1290 mutex_lock(&intel_pstate_driver_lock); 1291 1291 - rdmsrl(MSR_IA32_POWER_CTL, power_ctl); 1291 1291 + rdmsrq(MSR_IA32_POWER_CTL, power_ctl); 1292 1292 if (input) { 1293 1293 power_ctl &= ~BIT(MSR_IA32_POWER_CTL_BIT_EE); 1294 1294 power_ctl_ee_state = POWER_CTL_EE_ENABLE; ··· 1296 1296 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE); 1297 1297 power_ctl_ee_state = POWER_CTL_EE_DISABLE; 1298 1298 } 1299 1299 - wrmsrl(MSR_IA32_POWER_CTL, power_ctl); 1299 1299 + wrmsrq(MSR_IA32_POWER_CTL, power_ctl); 1300 1300 mutex_unlock(&intel_pstate_driver_lock); 1301 1301 } 1302 1302 ··· 1305 1305 static void intel_pstate_hwp_reenable(struct cpudata *cpu) 1306 1306 { 1307 1307 intel_pstate_hwp_enable(cpu); 1308 1308 - wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached)); 1308 1308 + wrmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached)); 1309 1309 } 1310 1310 1311 1311 static int intel_pstate_suspend(struct cpufreq_policy *policy) ··· 1706 1706 u64 power_ctl; 1707 1707 int enable; 1708 1708 1709 1709 - rdmsrl(MSR_IA32_POWER_CTL, power_ctl); 1709 1709 + rdmsrq(MSR_IA32_POWER_CTL, power_ctl); 1710 1710 enable = !!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE)); 1711 1711 return sprintf(buf, "%d\n", !enable); 1712 1712 } ··· 1858 1858 hybrid_update_capacity(cpudata); 1859 1859 } 1860 1860 1861 1861 - wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0); 1861 1861 + wrmsrq_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0); 1862 1862 } 1863 1863 1864 1864 static DEFINE_RAW_SPINLOCK(hwp_notify_lock); ··· 1880 1880 if (cpu_feature_enabled(X86_FEATURE_HWP_HIGHEST_PERF_CHANGE)) 1881 1881 status_mask |= HWP_HIGHEST_PERF_CHANGE_STATUS; 1882 1882 1883 1883 - rdmsrl_safe(MSR_HWP_STATUS, &value); 1883 1883 + rdmsrq_safe(MSR_HWP_STATUS, &value); 1884 1884 if (!(value & status_mask)) 1885 1885 return; 1886 1886 ··· 1897 1897 return; 1898 1898 1899 1899 ack_intr: 1900 1900 - wrmsrl_safe(MSR_HWP_STATUS, 0); 1900 1900 + wrmsrq_safe(MSR_HWP_STATUS, 0); 1901 1901 raw_spin_unlock_irqrestore(&hwp_notify_lock, flags); 1902 1902 } 1903 1903 ··· 1908 1908 if (!cpu_feature_enabled(X86_FEATURE_HWP_NOTIFY)) 1909 1909 return; 1910 1910 1911 1911 - /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */ 1912 1912 - wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 1911 1911 + /* wrmsrq_on_cpu has to be outside spinlock as this can result in IPC */ 1912 1912 + wrmsrq_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 1913 1913 1914 1914 raw_spin_lock_irq(&hwp_notify_lock); 1915 1915 cancel_work = cpumask_test_and_clear_cpu(cpudata->cpu, &hwp_intr_enable_mask); ··· 1936 1936 if (cpu_feature_enabled(X86_FEATURE_HWP_HIGHEST_PERF_CHANGE)) 1937 1937 interrupt_mask |= HWP_HIGHEST_PERF_CHANGE_REQ; 1938 1938 1939 1939 - /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */ 1940 1940 - wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, interrupt_mask); 1941 1941 - wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0); 1939 1939 + /* wrmsrq_on_cpu has to be outside spinlock as this can result in IPC */ 1940 1940 + wrmsrq_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, interrupt_mask); 1941 1941 + wrmsrq_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0); 1942 1942 } 1943 1943 } 1944 1944 ··· 1977 1977 { 1978 1978 /* First disable HWP notification interrupt till we activate again */ 1979 1979 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) 1980 1980 - wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 1980 1980 + wrmsrq_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); 1981 1981 1982 1982 - wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); 1982 1982 + wrmsrq_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); 1983 1983 1984 1984 intel_pstate_enable_hwp_interrupt(cpudata); 1985 1985 ··· 1993 1993 { 1994 1994 u64 value; 1995 1995 1996 1996 - rdmsrl(MSR_ATOM_CORE_RATIOS, value); 1996 1996 + rdmsrq(MSR_ATOM_CORE_RATIOS, value); 1997 1997 return (value >> 8) & 0x7F; 1998 1998 } 1999 1999 ··· 2001 2001 { 2002 2002 u64 value; 2003 2003 2004 2004 - rdmsrl(MSR_ATOM_CORE_RATIOS, value); 2004 2004 + rdmsrq(MSR_ATOM_CORE_RATIOS, value); 2005 2005 return (value >> 16) & 0x7F; 2006 2006 } 2007 2007 ··· 2009 2009 { 2010 2010 u64 value; 2011 2011 2012 2012 - rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value); 2012 2012 + rdmsrq(MSR_ATOM_CORE_TURBO_RATIOS, value); 2013 2013 return value & 0x7F; 2014 2014 } 2015 2015 ··· 2044 2044 static int silvermont_freq_table[] = { 2045 2045 83300, 100000, 133300, 116700, 80000}; 2046 2046 2047 2047 - rdmsrl(MSR_FSB_FREQ, value); 2047 2047 + rdmsrq(MSR_FSB_FREQ, value); 2048 2048 i = value & 0x7; 2049 2049 WARN_ON(i > 4); 2050 2050 ··· 2060 2060 83300, 100000, 133300, 116700, 80000, 2061 2061 93300, 90000, 88900, 87500}; 2062 2062 2063 2063 - rdmsrl(MSR_FSB_FREQ, value); 2063 2063 + rdmsrq(MSR_FSB_FREQ, value); 2064 2064 i = value & 0xF; 2065 2065 WARN_ON(i > 8); 2066 2066 ··· 2071 2071 { 2072 2072 u64 value; 2073 2073 2074 2074 - rdmsrl(MSR_ATOM_CORE_VIDS, value); 2074 2074 + rdmsrq(MSR_ATOM_CORE_VIDS, value); 2075 2075 cpudata->vid.min = int_tofp((value >> 8) & 0x7f); 2076 2076 cpudata->vid.max = int_tofp((value >> 16) & 0x7f); 2077 2077 cpudata->vid.ratio = div_fp( ··· 2079 2079 int_tofp(cpudata->pstate.max_pstate - 2080 2080 cpudata->pstate.min_pstate)); 2081 2081 2082 2082 - rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value); 2082 2082 + rdmsrq(MSR_ATOM_CORE_TURBO_VIDS, value); 2083 2083 cpudata->vid.turbo = value & 0x7f; 2084 2084 } 2085 2085 ··· 2087 2087 { 2088 2088 u64 value; 2089 2089 2090 2090 - rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value); 2090 2090 + rdmsrq_on_cpu(cpu, MSR_PLATFORM_INFO, &value); 2091 2091 return (value >> 40) & 0xFF; 2092 2092 } 2093 2093 ··· 2095 2095 { 2096 2096 u64 value; 2097 2097 2098 2098 - rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value); 2098 2098 + rdmsrq_on_cpu(cpu, MSR_PLATFORM_INFO, &value); 2099 2099 return (value >> 8) & 0xFF; 2100 2100 } 2101 2101 ··· 2109 2109 int err; 2110 2110 2111 2111 /* Get the TDP level (0, 1, 2) to get ratios */ 2112 2112 - err = rdmsrl_safe_on_cpu(cpu, MSR_CONFIG_TDP_CONTROL, &tdp_ctrl); 2112 2112 + err = rdmsrq_safe_on_cpu(cpu, MSR_CONFIG_TDP_CONTROL, &tdp_ctrl); 2113 2113 if (err) 2114 2114 return err; 2115 2115 2116 2116 /* TDP MSR are continuous starting at 0x648 */ 2117 2117 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03); 2118 2118 - err = rdmsrl_safe_on_cpu(cpu, tdp_msr, &tdp_ratio); 2118 2118 + err = rdmsrq_safe_on_cpu(cpu, tdp_msr, &tdp_ratio); 2119 2119 if (err) 2120 2120 return err; 2121 2121 ··· 2140 2140 int tdp_ratio; 2141 2141 int err; 2142 2142 2143 2143 - rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &plat_info); 2143 2143 + rdmsrq_on_cpu(cpu, MSR_PLATFORM_INFO, &plat_info); 2144 2144 max_pstate = (plat_info >> 8) & 0xFF; 2145 2145 2146 2146 tdp_ratio = core_get_tdp_ratio(cpu, plat_info); ··· 2152 2152 return tdp_ratio; 2153 2153 } 2154 2154 2155 2155 - err = rdmsrl_safe_on_cpu(cpu, MSR_TURBO_ACTIVATION_RATIO, &tar); 2155 2155 + err = rdmsrq_safe_on_cpu(cpu, MSR_TURBO_ACTIVATION_RATIO, &tar); 2156 2156 if (!err) { 2157 2157 int tar_levels; 2158 2158 ··· 2172 2172 u64 value; 2173 2173 int nont, ret; 2174 2174 2175 2175 - rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value); 2175 2175 + rdmsrq_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value); 2176 2176 nont = core_get_max_pstate(cpu); 2177 2177 ret = (value) & 255; 2178 2178 if (ret <= nont) ··· 2201 2201 u64 value; 2202 2202 int nont, ret; 2203 2203 2204 2204 - rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value); 2204 2204 + rdmsrq_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value); 2205 2205 nont = core_get_max_pstate(cpu); 2206 2206 ret = (((value) >> 8) & 0xFF); 2207 2207 if (ret <= nont) ··· 2247 2247 * the CPU being updated, so force the register update to run on the 2248 2248 * right CPU. 2249 2249 */ 2250 2250 - wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 2250 2250 + wrmsrq_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 2251 2251 pstate_funcs.get_val(cpu, pstate)); 2252 2252 } 2253 2253 ··· 2354 2354 return; 2355 2355 2356 2356 hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min; 2357 2357 - wrmsrl(MSR_HWP_REQUEST, hwp_req); 2357 2357 + wrmsrq(MSR_HWP_REQUEST, hwp_req); 2358 2358 cpu->last_update = cpu->sample.time; 2359 2359 } 2360 2360 ··· 2367 2367 expired = time_after64(cpu->sample.time, cpu->last_update + 2368 2368 hwp_boost_hold_time_ns); 2369 2369 if (expired) { 2370 2370 - wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached); 2370 2370 + wrmsrq(MSR_HWP_REQUEST, cpu->hwp_req_cached); 2371 2371 cpu->hwp_boost_min = 0; 2372 2372 } 2373 2373 } ··· 2428 2428 u64 tsc; 2429 2429 2430 2430 local_irq_save(flags); 2431 2431 - rdmsrl(MSR_IA32_APERF, aperf); 2432 2432 - rdmsrl(MSR_IA32_MPERF, mperf); 2431 2431 + rdmsrq(MSR_IA32_APERF, aperf); 2432 2432 + rdmsrq(MSR_IA32_MPERF, mperf); 2433 2433 tsc = rdtsc(); 2434 2434 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) { 2435 2435 local_irq_restore(flags); ··· 2523 2523 return; 2524 2524 2525 2525 cpu->pstate.current_pstate = pstate; 2526 2526 - wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate)); 2526 2526 + wrmsrq(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate)); 2527 2527 } 2528 2528 2529 2529 static void intel_pstate_adjust_pstate(struct cpudata *cpu) ··· 3103 3103 3104 3104 WRITE_ONCE(cpu->hwp_req_cached, value); 3105 3105 if (fast_switch) 3106 3106 - wrmsrl(MSR_HWP_REQUEST, value); 3106 3106 + wrmsrq(MSR_HWP_REQUEST, value); 3107 3107 else 3108 3108 - wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 3108 3108 + wrmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 3109 3109 } 3110 3110 3111 3111 static void intel_cpufreq_perf_ctl_update(struct cpudata *cpu, 3112 3112 u32 target_pstate, bool fast_switch) 3113 3113 { 3114 3114 if (fast_switch) 3115 3115 - wrmsrl(MSR_IA32_PERF_CTL, 3115 3115 + wrmsrq(MSR_IA32_PERF_CTL, 3116 3116 pstate_funcs.get_val(cpu, target_pstate)); 3117 3117 else 3118 3118 - wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 3118 3118 + wrmsrq_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, 3119 3119 pstate_funcs.get_val(cpu, target_pstate)); 3120 3120 } 3121 3121 ··· 3259 3259 3260 3260 intel_pstate_get_hwp_cap(cpu); 3261 3261 3262 3262 - rdmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value); 3262 3262 + rdmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value); 3263 3263 WRITE_ONCE(cpu->hwp_req_cached, value); 3264 3264 3265 3265 cpu->epp_cached = intel_pstate_get_epp(cpu, value); ··· 3326 3326 * written by it may not be suitable. 3327 3327 */ 3328 3328 value &= ~HWP_DESIRED_PERF(~0L); 3329 3329 - wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 3329 3329 + wrmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value); 3330 3330 WRITE_ONCE(cpu->hwp_req_cached, value); 3331 3331 } 3332 3332 ··· 3576 3576 3577 3577 id = x86_match_cpu(intel_pstate_cpu_oob_ids); 3578 3578 if (id) { 3579 3579 - rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); 3579 3579 + rdmsrq(MSR_MISC_PWR_MGMT, misc_pwr); 3580 3580 if (misc_pwr & BITMASK_OOB) { 3581 3581 pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n"); 3582 3582 pr_debug("P states are controlled in Out of Band mode by the firmware/hardware\n"); ··· 3632 3632 { 3633 3633 u64 value; 3634 3634 3635 3635 - rdmsrl(MSR_PM_ENABLE, value); 3635 3635 + rdmsrq(MSR_PM_ENABLE, value); 3636 3636 return !!(value & 0x1); 3637 3637 } 3638 3638

+12 -12

drivers/cpufreq/longhaul.c

reviewed

··· 136 136 { 137 137 union msr_bcr2 bcr2; 138 138 139 139 - rdmsrl(MSR_VIA_BCR2, bcr2.val); 139 139 + rdmsrq(MSR_VIA_BCR2, bcr2.val); 140 140 /* Enable software clock multiplier */ 141 141 bcr2.bits.ESOFTBF = 1; 142 142 bcr2.bits.CLOCKMUL = mults_index & 0xff; ··· 144 144 /* Sync to timer tick */ 145 145 safe_halt(); 146 146 /* Change frequency on next halt or sleep */ 147 147 - wrmsrl(MSR_VIA_BCR2, bcr2.val); 147 147 + wrmsrq(MSR_VIA_BCR2, bcr2.val); 148 148 /* Invoke transition */ 149 149 ACPI_FLUSH_CPU_CACHE(); 150 150 halt(); 151 151 152 152 /* Disable software clock multiplier */ 153 153 local_irq_disable(); 154 154 - rdmsrl(MSR_VIA_BCR2, bcr2.val); 154 154 + rdmsrq(MSR_VIA_BCR2, bcr2.val); 155 155 bcr2.bits.ESOFTBF = 0; 156 156 - wrmsrl(MSR_VIA_BCR2, bcr2.val); 156 156 + wrmsrq(MSR_VIA_BCR2, bcr2.val); 157 157 } 158 158 159 159 /* For processor with Longhaul MSR */ ··· 164 164 union msr_longhaul longhaul; 165 165 u32 t; 166 166 167 167 - rdmsrl(MSR_VIA_LONGHAUL, longhaul.val); 167 167 + rdmsrq(MSR_VIA_LONGHAUL, longhaul.val); 168 168 /* Setup new frequency */ 169 169 if (!revid_errata) 170 170 longhaul.bits.RevisionKey = longhaul.bits.RevisionID; ··· 180 180 /* Raise voltage if necessary */ 181 181 if (can_scale_voltage && dir) { 182 182 longhaul.bits.EnableSoftVID = 1; 183 183 - wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); 183 183 + wrmsrq(MSR_VIA_LONGHAUL, longhaul.val); 184 184 /* Change voltage */ 185 185 if (!cx_address) { 186 186 ACPI_FLUSH_CPU_CACHE(); ··· 194 194 t = inl(acpi_gbl_FADT.xpm_timer_block.address); 195 195 } 196 196 longhaul.bits.EnableSoftVID = 0; 197 197 - wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); 197 197 + wrmsrq(MSR_VIA_LONGHAUL, longhaul.val); 198 198 } 199 199 200 200 /* Change frequency on next halt or sleep */ 201 201 longhaul.bits.EnableSoftBusRatio = 1; 202 202 - wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); 202 202 + wrmsrq(MSR_VIA_LONGHAUL, longhaul.val); 203 203 if (!cx_address) { 204 204 ACPI_FLUSH_CPU_CACHE(); 205 205 halt(); ··· 212 212 } 213 213 /* Disable bus ratio bit */ 214 214 longhaul.bits.EnableSoftBusRatio = 0; 215 215 - wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); 215 215 + wrmsrq(MSR_VIA_LONGHAUL, longhaul.val); 216 216 217 217 /* Reduce voltage if necessary */ 218 218 if (can_scale_voltage && !dir) { 219 219 longhaul.bits.EnableSoftVID = 1; 220 220 - wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); 220 220 + wrmsrq(MSR_VIA_LONGHAUL, longhaul.val); 221 221 /* Change voltage */ 222 222 if (!cx_address) { 223 223 ACPI_FLUSH_CPU_CACHE(); ··· 231 231 t = inl(acpi_gbl_FADT.xpm_timer_block.address); 232 232 } 233 233 longhaul.bits.EnableSoftVID = 0; 234 234 - wrmsrl(MSR_VIA_LONGHAUL, longhaul.val); 234 234 + wrmsrq(MSR_VIA_LONGHAUL, longhaul.val); 235 235 } 236 236 } 237 237 ··· 534 534 unsigned int j, speed, pos, kHz_step, numvscales; 535 535 int min_vid_speed; 536 536 537 537 - rdmsrl(MSR_VIA_LONGHAUL, longhaul.val); 537 537 + rdmsrq(MSR_VIA_LONGHAUL, longhaul.val); 538 538 if (!(longhaul.bits.RevisionID & 1)) { 539 539 pr_info("Voltage scaling not supported by CPU\n"); 540 540 return;

+7 -7

drivers/cpufreq/powernow-k7.c

reviewed

··· 219 219 { 220 220 union msr_fidvidctl fidvidctl; 221 221 222 222 - rdmsrl(MSR_K7_FID_VID_CTL, fidvidctl.val); 222 222 + rdmsrq(MSR_K7_FID_VID_CTL, fidvidctl.val); 223 223 if (fidvidctl.bits.FID != fid) { 224 224 fidvidctl.bits.SGTC = latency; 225 225 fidvidctl.bits.FID = fid; 226 226 fidvidctl.bits.VIDC = 0; 227 227 fidvidctl.bits.FIDC = 1; 228 228 - wrmsrl(MSR_K7_FID_VID_CTL, fidvidctl.val); 228 228 + wrmsrq(MSR_K7_FID_VID_CTL, fidvidctl.val); 229 229 } 230 230 } 231 231 ··· 234 234 { 235 235 union msr_fidvidctl fidvidctl; 236 236 237 237 - rdmsrl(MSR_K7_FID_VID_CTL, fidvidctl.val); 237 237 + rdmsrq(MSR_K7_FID_VID_CTL, fidvidctl.val); 238 238 if (fidvidctl.bits.VID != vid) { 239 239 fidvidctl.bits.SGTC = latency; 240 240 fidvidctl.bits.VID = vid; 241 241 fidvidctl.bits.FIDC = 0; 242 242 fidvidctl.bits.VIDC = 1; 243 243 - wrmsrl(MSR_K7_FID_VID_CTL, fidvidctl.val); 243 243 + wrmsrq(MSR_K7_FID_VID_CTL, fidvidctl.val); 244 244 } 245 245 } 246 246 ··· 260 260 fid = powernow_table[index].driver_data & 0xFF; 261 261 vid = (powernow_table[index].driver_data & 0xFF00) >> 8; 262 262 263 263 - rdmsrl(MSR_K7_FID_VID_STATUS, fidvidstatus.val); 263 263 + rdmsrq(MSR_K7_FID_VID_STATUS, fidvidstatus.val); 264 264 cfid = fidvidstatus.bits.CFID; 265 265 freqs.old = fsb * fid_codes[cfid] / 10; 266 266 ··· 557 557 558 558 if (cpu) 559 559 return 0; 560 560 - rdmsrl(MSR_K7_FID_VID_STATUS, fidvidstatus.val); 560 560 + rdmsrq(MSR_K7_FID_VID_STATUS, fidvidstatus.val); 561 561 cfid = fidvidstatus.bits.CFID; 562 562 563 563 return fsb * fid_codes[cfid] / 10; ··· 598 598 if (policy->cpu != 0) 599 599 return -ENODEV; 600 600 601 601 - rdmsrl(MSR_K7_FID_VID_STATUS, fidvidstatus.val); 601 601 + rdmsrq(MSR_K7_FID_VID_STATUS, fidvidstatus.val); 602 602 603 603 recalibrate_cpu_khz(); 604 604

-1

drivers/cpufreq/sc520_freq.c

reviewed

··· 21 21 #include <linux/io.h> 22 22 23 23 #include <asm/cpu_device_id.h> 24 24 - #include <asm/msr.h> 25 24 26 25 #define MMCR_BASE 0xfffef000 /* The default base address */ 27 26 #define OFFS_CPUCTL 0x2 /* CPU Control Register */

+2 -1

drivers/crypto/ccp/sev-dev.c

reviewed

··· 33 33 #include <asm/cacheflush.h> 34 34 #include <asm/e820/types.h> 35 35 #include <asm/sev.h> 36 36 + #include <asm/msr.h> 36 37 37 38 #include "psp-dev.h" 38 39 #include "sev-dev.h" ··· 1061 1060 1062 1061 static void snp_set_hsave_pa(void *arg) 1063 1062 { 1064 1064 - wrmsrl(MSR_VM_HSAVE_PA, 0); 1063 1063 + wrmsrq(MSR_VM_HSAVE_PA, 0); 1065 1064 } 1066 1065 1067 1066 static int snp_filter_reserved_mem_regions(struct resource *rs, void *arg)

+3 -3

drivers/edac/amd64_edac.c

reviewed

··· 2942 2942 * Retrieve TOP_MEM and TOP_MEM2; no masking off of reserved bits since 2943 2943 * those are Read-As-Zero. 2944 2944 */ 2945 2945 - rdmsrl(MSR_K8_TOP_MEM1, pvt->top_mem); 2945 2945 + rdmsrq(MSR_K8_TOP_MEM1, pvt->top_mem); 2946 2946 edac_dbg(0, " TOP_MEM: 0x%016llx\n", pvt->top_mem); 2947 2947 2948 2948 /* Check first whether TOP_MEM2 is enabled: */ 2949 2949 - rdmsrl(MSR_AMD64_SYSCFG, msr_val); 2949 2949 + rdmsrq(MSR_AMD64_SYSCFG, msr_val); 2950 2950 if (msr_val & BIT(21)) { 2951 2951 - rdmsrl(MSR_K8_TOP_MEM2, pvt->top_mem2); 2951 2951 + rdmsrq(MSR_K8_TOP_MEM2, pvt->top_mem2); 2952 2952 edac_dbg(0, " TOP_MEM2: 0x%016llx\n", pvt->top_mem2); 2953 2953 } else { 2954 2954 edac_dbg(0, " TOP_MEM2 disabled\n");

+1

drivers/edac/ie31200_edac.c

reviewed

··· 52 52 53 53 #include <linux/io-64-nonatomic-lo-hi.h> 54 54 #include <asm/mce.h> 55 55 + #include <asm/msr.h> 55 56 #include "edac_module.h" 56 57 57 58 #define EDAC_MOD_STR "ie31200_edac"

+1

drivers/edac/mce_amd.c

reviewed

··· 3 3 #include <linux/slab.h> 4 4 5 5 #include <asm/cpu.h> 6 6 + #include <asm/msr.h> 6 7 7 8 #include "mce_amd.h" 8 9

+2 -2

drivers/gpu/drm/i915/selftests/librapl.c

reviewed

··· 22 22 unsigned long long power; 23 23 u32 units; 24 24 25 25 - if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, &power)) 25 25 + if (rdmsrq_safe(MSR_RAPL_POWER_UNIT, &power)) 26 26 return 0; 27 27 28 28 units = (power & 0x1f00) >> 8; 29 29 30 30 - if (rdmsrl_safe(MSR_PP1_ENERGY_STATUS, &power)) 30 30 + if (rdmsrq_safe(MSR_PP1_ENERGY_STATUS, &power)) 31 31 return 0; 32 32 33 33 return (1000000 * power) >> units; /* convert to uJ */

+3 -3

drivers/hwmon/fam15h_power.c

reviewed

··· 143 143 */ 144 144 cu = topology_core_id(smp_processor_id()); 145 145 146 146 - rdmsrl_safe(MSR_F15H_CU_PWR_ACCUMULATOR, &data->cu_acc_power[cu]); 147 147 - rdmsrl_safe(MSR_F15H_PTSC, &data->cpu_sw_pwr_ptsc[cu]); 146 146 + rdmsrq_safe(MSR_F15H_CU_PWR_ACCUMULATOR, &data->cu_acc_power[cu]); 147 147 + rdmsrq_safe(MSR_F15H_PTSC, &data->cpu_sw_pwr_ptsc[cu]); 148 148 149 149 data->cu_on[cu] = 1; 150 150 } ··· 424 424 */ 425 425 data->cpu_pwr_sample_ratio = cpuid_ecx(0x80000007); 426 426 427 427 - if (rdmsrl_safe(MSR_F15H_CU_MAX_PWR_ACCUMULATOR, &tmp)) { 427 427 + if (rdmsrq_safe(MSR_F15H_CU_MAX_PWR_ACCUMULATOR, &tmp)) { 428 428 pr_err("Failed to read max compute unit power accumulator MSR\n"); 429 429 return -ENODEV; 430 430 }

+4

drivers/hwmon/hwmon-vid.c

reviewed

··· 15 15 #include <linux/kernel.h> 16 16 #include <linux/hwmon-vid.h> 17 17 18 18 + #ifdef CONFIG_X86 19 19 + #include <asm/msr.h> 20 20 + #endif 21 21 + 18 22 /* 19 23 * Common code for decoding VID pins. 20 24 *

+18 -17

drivers/idle/intel_idle.c

reviewed

··· 56 56 #include <asm/intel-family.h> 57 57 #include <asm/mwait.h> 58 58 #include <asm/spec-ctrl.h> 59 59 + #include <asm/msr.h> 59 60 #include <asm/tsc.h> 60 61 #include <asm/fpu/api.h> 61 62 #include <asm/smp.h> ··· 1929 1928 unsigned long long msr; 1930 1929 unsigned int usec; 1931 1930 1932 1932 - rdmsrl(MSR_PKGC6_IRTL, msr); 1931 1931 + rdmsrq(MSR_PKGC6_IRTL, msr); 1933 1932 usec = irtl_2_usec(msr); 1934 1933 if (usec) { 1935 1934 bxt_cstates[2].exit_latency = usec; 1936 1935 bxt_cstates[2].target_residency = usec; 1937 1936 } 1938 1937 1939 1939 - rdmsrl(MSR_PKGC7_IRTL, msr); 1938 1938 + rdmsrq(MSR_PKGC7_IRTL, msr); 1940 1939 usec = irtl_2_usec(msr); 1941 1940 if (usec) { 1942 1941 bxt_cstates[3].exit_latency = usec; 1943 1942 bxt_cstates[3].target_residency = usec; 1944 1943 } 1945 1944 1946 1946 - rdmsrl(MSR_PKGC8_IRTL, msr); 1945 1945 + rdmsrq(MSR_PKGC8_IRTL, msr); 1947 1946 usec = irtl_2_usec(msr); 1948 1947 if (usec) { 1949 1948 bxt_cstates[4].exit_latency = usec; 1950 1949 bxt_cstates[4].target_residency = usec; 1951 1950 } 1952 1951 1953 1953 - rdmsrl(MSR_PKGC9_IRTL, msr); 1952 1952 + rdmsrq(MSR_PKGC9_IRTL, msr); 1954 1953 usec = irtl_2_usec(msr); 1955 1954 if (usec) { 1956 1955 bxt_cstates[5].exit_latency = usec; 1957 1956 bxt_cstates[5].target_residency = usec; 1958 1957 } 1959 1958 1960 1960 - rdmsrl(MSR_PKGC10_IRTL, msr); 1959 1959 + rdmsrq(MSR_PKGC10_IRTL, msr); 1961 1960 usec = irtl_2_usec(msr); 1962 1961 if (usec) { 1963 1962 bxt_cstates[6].exit_latency = usec; ··· 1985 1984 if ((mwait_substates & (0xF << 28)) == 0) 1986 1985 return; 1987 1986 1988 1988 - rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr); 1987 1987 + rdmsrq(MSR_PKG_CST_CONFIG_CONTROL, msr); 1989 1988 1990 1989 /* PC10 is not enabled in PKG C-state limit */ 1991 1990 if ((msr & 0xF) != 8) ··· 1997 1996 /* if SGX is present */ 1998 1997 if (ebx & (1 << 2)) { 1999 1998 2000 2000 - rdmsrl(MSR_IA32_FEAT_CTL, msr); 1999 1999 + rdmsrq(MSR_IA32_FEAT_CTL, msr); 2001 2000 2002 2001 /* if SGX is enabled */ 2003 2002 if (msr & (1 << 18)) ··· 2016 2015 { 2017 2016 unsigned long long msr; 2018 2017 2019 2019 - rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr); 2018 2018 + rdmsrq(MSR_PKG_CST_CONFIG_CONTROL, msr); 2020 2019 2021 2020 /* 2022 2021 * 000b: C0/C1 (no package C-state support) ··· 2069 2068 * C6. However, if PC6 is disabled, we update the numbers to match 2070 2069 * core C6. 2071 2070 */ 2072 2072 - rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr); 2071 2071 + rdmsrq(MSR_PKG_CST_CONFIG_CONTROL, msr); 2073 2072 2074 2073 /* Limit value 2 and above allow for PC6. */ 2075 2074 if ((msr & 0x7) < 2) { ··· 2083 2082 */ 2084 2083 static void __init byt_cht_auto_demotion_disable(void) 2085 2084 { 2086 2086 - wrmsrl(MSR_CC6_DEMOTION_POLICY_CONFIG, 0); 2087 2087 - wrmsrl(MSR_MC6_DEMOTION_POLICY_CONFIG, 0); 2085 2085 + wrmsrq(MSR_CC6_DEMOTION_POLICY_CONFIG, 0); 2086 2086 + wrmsrq(MSR_MC6_DEMOTION_POLICY_CONFIG, 0); 2088 2087 } 2089 2088 2090 2089 static bool __init intel_idle_verify_cstate(unsigned int mwait_hint) ··· 2242 2241 { 2243 2242 unsigned long long msr_bits; 2244 2243 2245 2245 - rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_bits); 2244 2244 + rdmsrq(MSR_PKG_CST_CONFIG_CONTROL, msr_bits); 2246 2245 msr_bits &= ~auto_demotion_disable_flags; 2247 2247 - wrmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_bits); 2246 2246 + wrmsrq(MSR_PKG_CST_CONFIG_CONTROL, msr_bits); 2248 2247 } 2249 2248 2250 2249 static void c1e_promotion_enable(void) 2251 2250 { 2252 2251 unsigned long long msr_bits; 2253 2252 2254 2254 - rdmsrl(MSR_IA32_POWER_CTL, msr_bits); 2253 2253 + rdmsrq(MSR_IA32_POWER_CTL, msr_bits); 2255 2254 msr_bits |= 0x2; 2256 2256 - wrmsrl(MSR_IA32_POWER_CTL, msr_bits); 2255 2255 + wrmsrq(MSR_IA32_POWER_CTL, msr_bits); 2257 2256 } 2258 2257 2259 2258 static void c1e_promotion_disable(void) 2260 2259 { 2261 2260 unsigned long long msr_bits; 2262 2261 2263 2263 - rdmsrl(MSR_IA32_POWER_CTL, msr_bits); 2262 2262 + rdmsrq(MSR_IA32_POWER_CTL, msr_bits); 2264 2263 msr_bits &= ~0x2; 2265 2265 - wrmsrl(MSR_IA32_POWER_CTL, msr_bits); 2264 2264 + wrmsrq(MSR_IA32_POWER_CTL, msr_bits); 2266 2265 } 2267 2266 2268 2267 /**

+1

drivers/misc/cs5535-mfgpt.c

reviewed

··· 16 16 #include <linux/platform_device.h> 17 17 #include <linux/cs5535.h> 18 18 #include <linux/slab.h> 19 19 + #include <asm/msr.h> 19 20 20 21 #define DRV_NAME "cs5535-mfgpt" 21 22

+3 -3

drivers/mtd/nand/raw/cs553x_nand.c

reviewed

··· 351 351 return -ENXIO; 352 352 353 353 /* If it doesn't have the CS553[56], abort */ 354 354 - rdmsrl(MSR_DIVIL_GLD_CAP, val); 354 354 + rdmsrq(MSR_DIVIL_GLD_CAP, val); 355 355 val &= ~0xFFULL; 356 356 if (val != CAP_CS5535 && val != CAP_CS5536) 357 357 return -ENXIO; 358 358 359 359 /* If it doesn't have the NAND controller enabled, abort */ 360 360 - rdmsrl(MSR_DIVIL_BALL_OPTS, val); 360 360 + rdmsrq(MSR_DIVIL_BALL_OPTS, val); 361 361 if (val & PIN_OPT_IDE) { 362 362 pr_info("CS553x NAND controller: Flash I/O not enabled in MSR_DIVIL_BALL_OPTS.\n"); 363 363 return -ENXIO; 364 364 } 365 365 366 366 for (i = 0; i < NR_CS553X_CONTROLLERS; i++) { 367 367 - rdmsrl(MSR_DIVIL_LBAR_FLSH0 + i, val); 367 367 + rdmsrq(MSR_DIVIL_LBAR_FLSH0 + i, val); 368 368 369 369 if ((val & (FLSH_LBAR_EN|FLSH_NOR_NAND)) == (FLSH_LBAR_EN|FLSH_NOR_NAND)) 370 370 err = cs553x_init_one(i, !!(val & FLSH_MEM_IO), val & 0xFFFFFFFF);

+4

drivers/net/vmxnet3/vmxnet3_drv.c

reviewed

··· 27 27 #include <linux/module.h> 28 28 #include <net/ip6_checksum.h> 29 29 30 30 + #ifdef CONFIG_X86 31 31 + #include <asm/msr.h> 32 32 + #endif 33 33 + 30 34 #include "vmxnet3_int.h" 31 35 #include "vmxnet3_xdp.h" 32 36

+3 -2

drivers/platform/x86/intel/ifs/core.c

reviewed

··· 8 8 #include <linux/slab.h> 9 9 10 10 #include <asm/cpu_device_id.h> 11 11 + #include <asm/msr.h> 11 12 12 13 #include "ifs.h" 13 14 ··· 116 115 if (!m) 117 116 return -ENODEV; 118 117 119 119 - if (rdmsrl_safe(MSR_IA32_CORE_CAPS, &msrval)) 118 118 + if (rdmsrq_safe(MSR_IA32_CORE_CAPS, &msrval)) 120 119 return -ENODEV; 121 120 122 121 if (!(msrval & MSR_IA32_CORE_CAPS_INTEGRITY_CAPS)) 123 122 return -ENODEV; 124 123 125 125 - if (rdmsrl_safe(MSR_INTEGRITY_CAPS, &msrval)) 124 124 + if (rdmsrq_safe(MSR_INTEGRITY_CAPS, &msrval)) 126 125 return -ENODEV; 127 126 128 127 ifs_pkg_auth = kmalloc_array(topology_max_packages(), sizeof(bool), GFP_KERNEL);

+11 -10

drivers/platform/x86/intel/ifs/load.c

reviewed

··· 5 5 #include <linux/sizes.h> 6 6 #include <asm/cpu.h> 7 7 #include <asm/microcode.h> 8 8 + #include <asm/msr.h> 8 9 9 10 #include "ifs.h" 10 11 ··· 128 127 ifsd = ifs_get_data(dev); 129 128 msrs = ifs_get_test_msrs(dev); 130 129 /* run scan hash copy */ 131 131 - wrmsrl(msrs->copy_hashes, ifs_hash_ptr); 132 132 - rdmsrl(msrs->copy_hashes_status, hashes_status.data); 130 130 + wrmsrq(msrs->copy_hashes, ifs_hash_ptr); 131 131 + rdmsrq(msrs->copy_hashes_status, hashes_status.data); 133 132 134 133 /* enumerate the scan image information */ 135 134 num_chunks = hashes_status.num_chunks; ··· 150 149 linear_addr = base + i * chunk_size; 151 150 linear_addr |= i; 152 151 153 153 - wrmsrl(msrs->copy_chunks, linear_addr); 154 154 - rdmsrl(msrs->copy_chunks_status, chunk_status.data); 152 152 + wrmsrq(msrs->copy_chunks, linear_addr); 153 153 + rdmsrq(msrs->copy_chunks_status, chunk_status.data); 155 154 156 155 ifsd->valid_chunks = chunk_status.valid_chunks; 157 156 err_code = chunk_status.error_code; ··· 196 195 msrs = ifs_get_test_msrs(dev); 197 196 198 197 if (need_copy_scan_hashes(ifsd)) { 199 199 - wrmsrl(msrs->copy_hashes, ifs_hash_ptr); 200 200 - rdmsrl(msrs->copy_hashes_status, hashes_status.data); 198 198 + wrmsrq(msrs->copy_hashes, ifs_hash_ptr); 199 199 + rdmsrq(msrs->copy_hashes_status, hashes_status.data); 201 200 202 201 /* enumerate the scan image information */ 203 202 chunk_size = hashes_status.chunk_size * SZ_1K; ··· 217 216 } 218 217 219 218 if (ifsd->generation >= IFS_GEN_STRIDE_AWARE) { 220 220 - wrmsrl(msrs->test_ctrl, INVALIDATE_STRIDE); 221 221 - rdmsrl(msrs->copy_chunks_status, chunk_status.data); 219 219 + wrmsrq(msrs->test_ctrl, INVALIDATE_STRIDE); 220 220 + rdmsrq(msrs->copy_chunks_status, chunk_status.data); 222 221 if (chunk_status.valid_chunks != 0) { 223 222 dev_err(dev, "Couldn't invalidate installed stride - %d\n", 224 223 chunk_status.valid_chunks); ··· 239 238 chunk_table[1] = linear_addr; 240 239 do { 241 240 local_irq_disable(); 242 242 - wrmsrl(msrs->copy_chunks, (u64)chunk_table); 241 241 + wrmsrq(msrs->copy_chunks, (u64)chunk_table); 243 242 local_irq_enable(); 244 244 - rdmsrl(msrs->copy_chunks_status, chunk_status.data); 243 243 + rdmsrq(msrs->copy_chunks_status, chunk_status.data); 245 244 err_code = chunk_status.error_code; 246 245 } while (err_code == AUTH_INTERRUPTED_ERROR && --retry_count); 247 246

+9 -8

drivers/platform/x86/intel/ifs/runtest.c

reviewed

··· 7 7 #include <linux/nmi.h> 8 8 #include <linux/slab.h> 9 9 #include <linux/stop_machine.h> 10 10 + #include <asm/msr.h> 10 11 11 12 #include "ifs.h" 12 13 ··· 210 209 * take up to 200 milliseconds (in the case where all chunks 211 210 * are processed in a single pass) before it retires. 212 211 */ 213 213 - wrmsrl(MSR_ACTIVATE_SCAN, params->activate->data); 214 214 - rdmsrl(MSR_SCAN_STATUS, status.data); 212 212 + wrmsrq(MSR_ACTIVATE_SCAN, params->activate->data); 213 213 + rdmsrq(MSR_SCAN_STATUS, status.data); 215 214 216 215 trace_ifs_status(ifsd->cur_batch, start, stop, status.data); 217 216 ··· 322 321 first = cpumask_first(cpu_smt_mask(cpu)); 323 322 324 323 if (cpu == first) { 325 325 - wrmsrl(MSR_ARRAY_BIST, command->data); 324 324 + wrmsrq(MSR_ARRAY_BIST, command->data); 326 325 /* Pass back the result of the test */ 327 327 - rdmsrl(MSR_ARRAY_BIST, command->data); 326 326 + rdmsrq(MSR_ARRAY_BIST, command->data); 328 327 } 329 328 330 329 return 0; ··· 375 374 first = cpumask_first(cpu_smt_mask(cpu)); 376 375 377 376 if (cpu == first) { 378 378 - wrmsrl(MSR_ARRAY_TRIGGER, ARRAY_GEN1_TEST_ALL_ARRAYS); 379 379 - rdmsrl(MSR_ARRAY_STATUS, *((u64 *)status)); 377 377 + wrmsrq(MSR_ARRAY_TRIGGER, ARRAY_GEN1_TEST_ALL_ARRAYS); 378 378 + rdmsrq(MSR_ARRAY_STATUS, *((u64 *)status)); 380 379 } 381 380 382 381 return 0; ··· 527 526 * starts scan of each requested bundle. The core test happens 528 527 * during the "execution" of the WRMSR. 529 528 */ 530 530 - wrmsrl(MSR_ACTIVATE_SBAF, run_params->activate->data); 531 531 - rdmsrl(MSR_SBAF_STATUS, status.data); 529 529 + wrmsrq(MSR_ACTIVATE_SBAF, run_params->activate->data); 530 530 + rdmsrq(MSR_SBAF_STATUS, status.data); 532 531 trace_ifs_sbaf(ifsd->cur_batch, *run_params->activate, status); 533 532 534 533 /* Pass back the result of the test */

+4 -3

drivers/platform/x86/intel/pmc/cnp.c

reviewed

··· 10 10 11 11 #include <linux/smp.h> 12 12 #include <linux/suspend.h> 13 13 + #include <asm/msr.h> 13 14 #include "core.h" 14 15 15 16 /* Cannon Lake: PGD PFET Enable Ack Status Register(s) bitmap */ ··· 228 227 int cpunum = smp_processor_id(); 229 228 u64 val; 230 229 231 231 - rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, val); 230 230 + rdmsrq(MSR_PKG_CST_CONFIG_CONTROL, val); 232 231 per_cpu(pkg_cst_config, cpunum) = val; 233 232 val &= ~NHM_C1_AUTO_DEMOTE; 234 234 - wrmsrl(MSR_PKG_CST_CONFIG_CONTROL, val); 233 233 + wrmsrq(MSR_PKG_CST_CONFIG_CONTROL, val); 235 234 236 235 pr_debug("%s: cpu:%d cst %llx\n", __func__, cpunum, val); 237 236 } ··· 240 239 { 241 240 int cpunum = smp_processor_id(); 242 241 243 243 - wrmsrl(MSR_PKG_CST_CONFIG_CONTROL, per_cpu(pkg_cst_config, cpunum)); 242 242 + wrmsrq(MSR_PKG_CST_CONFIG_CONTROL, per_cpu(pkg_cst_config, cpunum)); 244 243 245 244 pr_debug("%s: cpu:%d cst %llx\n", __func__, cpunum, 246 245 per_cpu(pkg_cst_config, cpunum));

+4 -4

drivers/platform/x86/intel/pmc/core.c

reviewed

··· 1082 1082 unsigned int index; 1083 1083 1084 1084 for (index = 0; map[index].name ; index++) { 1085 1085 - if (rdmsrl_safe(map[index].bit_mask, &pcstate_count)) 1085 1085 + if (rdmsrq_safe(map[index].bit_mask, &pcstate_count)) 1086 1086 continue; 1087 1087 1088 1088 pcstate_count *= 1000; ··· 1587 1587 1588 1588 /* Save PKGC residency for checking later */ 1589 1589 for (i = 0; i < pmcdev->num_of_pkgc; i++) { 1590 1590 - if (rdmsrl_safe(msr_map[i].bit_mask, &pmcdev->pkgc_res_cnt[i])) 1590 1590 + if (rdmsrq_safe(msr_map[i].bit_mask, &pmcdev->pkgc_res_cnt[i])) 1591 1591 return -EIO; 1592 1592 } 1593 1593 ··· 1603 1603 u32 deepest_pkgc_msr = msr_map[pmcdev->num_of_pkgc - 1].bit_mask; 1604 1604 u64 deepest_pkgc_residency; 1605 1605 1606 1606 - if (rdmsrl_safe(deepest_pkgc_msr, &deepest_pkgc_residency)) 1606 1606 + if (rdmsrq_safe(deepest_pkgc_msr, &deepest_pkgc_residency)) 1607 1607 return false; 1608 1608 1609 1609 if (deepest_pkgc_residency == pmcdev->pkgc_res_cnt[pmcdev->num_of_pkgc - 1]) ··· 1655 1655 for (i = 0; i < pmcdev->num_of_pkgc; i++) { 1656 1656 u64 pc_cnt; 1657 1657 1658 1658 - if (!rdmsrl_safe(msr_map[i].bit_mask, &pc_cnt)) { 1658 1658 + if (!rdmsrq_safe(msr_map[i].bit_mask, &pc_cnt)) { 1659 1659 dev_info(dev, "Prev %s cnt = 0x%llx, Current %s cnt = 0x%llx\n", 1660 1660 msr_map[i].name, pmcdev->pkgc_res_cnt[i], 1661 1661 msr_map[i].name, pc_cnt);

+10 -9

drivers/platform/x86/intel/speed_select_if/isst_if_common.c

reviewed

··· 21 21 22 22 #include <asm/cpu_device_id.h> 23 23 #include <asm/intel-family.h> 24 24 + #include <asm/msr.h> 24 25 25 26 #include "isst_if_common.h" 26 27 ··· 192 191 if (cb->registered) 193 192 isst_mbox_resume_command(cb, sst_cmd); 194 193 } else { 195 195 - wrmsrl_safe_on_cpu(sst_cmd->cpu, sst_cmd->cmd, 194 194 + wrmsrq_safe_on_cpu(sst_cmd->cpu, sst_cmd->cmd, 196 195 sst_cmd->data); 197 196 } 198 197 } ··· 212 211 hash_for_each_possible(isst_hash, sst_cmd, hnode, 213 212 punit_msr_white_list[i]) { 214 213 if (!sst_cmd->mbox_cmd_type && sst_cmd->cpu == cpu) 215 215 - wrmsrl_safe(sst_cmd->cmd, sst_cmd->data); 214 214 + wrmsrq_safe(sst_cmd->cmd, sst_cmd->data); 216 215 } 217 216 } 218 217 mutex_unlock(&isst_hash_lock); ··· 407 406 408 407 isst_cpu_info[cpu].numa_node = cpu_to_node(cpu); 409 408 410 410 - ret = rdmsrl_safe(MSR_CPU_BUS_NUMBER, &data); 409 409 + ret = rdmsrq_safe(MSR_CPU_BUS_NUMBER, &data); 411 410 if (ret) { 412 411 /* This is not a fatal error on MSR mailbox only I/F */ 413 412 isst_cpu_info[cpu].bus_info[0] = -1; ··· 421 420 422 421 if (isst_hpm_support) { 423 422 424 424 - ret = rdmsrl_safe(MSR_PM_LOGICAL_ID, &data); 423 423 + ret = rdmsrq_safe(MSR_PM_LOGICAL_ID, &data); 425 424 if (!ret) 426 425 goto set_punit_id; 427 426 } 428 427 429 429 - ret = rdmsrl_safe(MSR_THREAD_ID_INFO, &data); 428 428 + ret = rdmsrq_safe(MSR_THREAD_ID_INFO, &data); 430 429 if (ret) { 431 430 isst_cpu_info[cpu].punit_cpu_id = -1; 432 431 return ret; ··· 525 524 if (!capable(CAP_SYS_ADMIN)) 526 525 return -EPERM; 527 526 528 528 - ret = wrmsrl_safe_on_cpu(msr_cmd->logical_cpu, 527 527 + ret = wrmsrq_safe_on_cpu(msr_cmd->logical_cpu, 529 528 msr_cmd->msr, 530 529 msr_cmd->data); 531 530 *write_only = 1; ··· 536 535 } else { 537 536 u64 data; 538 537 539 539 - ret = rdmsrl_safe_on_cpu(msr_cmd->logical_cpu, 538 538 + ret = rdmsrq_safe_on_cpu(msr_cmd->logical_cpu, 540 539 msr_cmd->msr, &data); 541 540 if (!ret) { 542 541 msr_cmd->data = data; ··· 832 831 u64 data; 833 832 834 833 /* Can fail only on some Skylake-X generations */ 835 835 - if (rdmsrl_safe(MSR_OS_MAILBOX_INTERFACE, &data) || 836 836 - rdmsrl_safe(MSR_OS_MAILBOX_DATA, &data)) 834 834 + if (rdmsrq_safe(MSR_OS_MAILBOX_INTERFACE, &data) || 835 835 + rdmsrq_safe(MSR_OS_MAILBOX_DATA, &data)) 837 836 return -ENODEV; 838 837 } 839 838

+8 -7

drivers/platform/x86/intel/speed_select_if/isst_if_mbox_msr.c

reviewed

··· 18 18 #include <uapi/linux/isst_if.h> 19 19 #include <asm/cpu_device_id.h> 20 20 #include <asm/intel-family.h> 21 21 + #include <asm/msr.h> 21 22 22 23 #include "isst_if_common.h" 23 24 ··· 40 39 /* Poll for rb bit == 0 */ 41 40 retries = OS_MAILBOX_RETRY_COUNT; 42 41 do { 43 43 - rdmsrl(MSR_OS_MAILBOX_INTERFACE, data); 42 42 + rdmsrq(MSR_OS_MAILBOX_INTERFACE, data); 44 43 if (data & BIT_ULL(MSR_OS_MAILBOX_BUSY_BIT)) { 45 44 ret = -EBUSY; 46 45 continue; ··· 53 52 return ret; 54 53 55 54 /* Write DATA register */ 56 56 - wrmsrl(MSR_OS_MAILBOX_DATA, command_data); 55 55 + wrmsrq(MSR_OS_MAILBOX_DATA, command_data); 57 56 58 57 /* Write command register */ 59 58 data = BIT_ULL(MSR_OS_MAILBOX_BUSY_BIT) | 60 59 (parameter & GENMASK_ULL(13, 0)) << 16 | 61 60 (sub_command << 8) | 62 61 command; 63 63 - wrmsrl(MSR_OS_MAILBOX_INTERFACE, data); 62 62 + wrmsrq(MSR_OS_MAILBOX_INTERFACE, data); 64 63 65 64 /* Poll for rb bit == 0 */ 66 65 retries = OS_MAILBOX_RETRY_COUNT; 67 66 do { 68 68 - rdmsrl(MSR_OS_MAILBOX_INTERFACE, data); 67 67 + rdmsrq(MSR_OS_MAILBOX_INTERFACE, data); 69 68 if (data & BIT_ULL(MSR_OS_MAILBOX_BUSY_BIT)) { 70 69 ret = -EBUSY; 71 70 continue; ··· 75 74 return -ENXIO; 76 75 77 76 if (response_data) { 78 78 - rdmsrl(MSR_OS_MAILBOX_DATA, data); 77 77 + rdmsrq(MSR_OS_MAILBOX_DATA, data); 79 78 *response_data = data; 80 79 } 81 80 ret = 0; ··· 177 176 return -ENODEV; 178 177 179 178 /* Check presence of mailbox MSRs */ 180 180 - ret = rdmsrl_safe(MSR_OS_MAILBOX_INTERFACE, &data); 179 179 + ret = rdmsrq_safe(MSR_OS_MAILBOX_INTERFACE, &data); 181 180 if (ret) 182 181 return ret; 183 182 184 184 - ret = rdmsrl_safe(MSR_OS_MAILBOX_DATA, &data); 183 183 + ret = rdmsrq_safe(MSR_OS_MAILBOX_DATA, &data); 185 184 if (ret) 186 185 return ret; 187 186

+2 -1

drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c

reviewed

··· 27 27 #include <linux/kernel.h> 28 28 #include <linux/minmax.h> 29 29 #include <linux/module.h> 30 30 + #include <asm/msr.h> 30 31 #include <uapi/linux/isst_if.h> 31 32 32 33 #include "isst_tpmi_core.h" ··· 557 556 { 558 557 u64 value; 559 558 560 560 - rdmsrl(MSR_PM_ENABLE, value); 559 559 + rdmsrq(MSR_PM_ENABLE, value); 561 560 return !(value & 0x1); 562 561 } 563 562

+2 -2

drivers/platform/x86/intel/tpmi_power_domains.c

reviewed

··· 157 157 u64 data; 158 158 int ret; 159 159 160 160 - ret = rdmsrl_safe(MSR_PM_LOGICAL_ID, &data); 160 160 + ret = rdmsrq_safe(MSR_PM_LOGICAL_ID, &data); 161 161 if (ret) 162 162 return ret; 163 163 ··· 203 203 return -ENODEV; 204 204 205 205 /* Check for MSR 0x54 presence */ 206 206 - ret = rdmsrl_safe(MSR_PM_LOGICAL_ID, &data); 206 206 + ret = rdmsrq_safe(MSR_PM_LOGICAL_ID, &data); 207 207 if (ret) 208 208 return ret; 209 209

+3 -2

drivers/platform/x86/intel/turbo_max_3.c

reviewed

··· 17 17 18 18 #include <asm/cpu_device_id.h> 19 19 #include <asm/intel-family.h> 20 20 + #include <asm/msr.h> 20 21 21 22 #define MSR_OC_MAILBOX 0x150 22 23 #define MSR_OC_MAILBOX_CMD_OFFSET 32 ··· 42 41 value = cmd << MSR_OC_MAILBOX_CMD_OFFSET; 43 42 /* Set the busy bit to indicate OS is trying to issue command */ 44 43 value |= BIT_ULL(MSR_OC_MAILBOX_BUSY_BIT); 45 45 - ret = wrmsrl_safe(MSR_OC_MAILBOX, value); 44 44 + ret = wrmsrq_safe(MSR_OC_MAILBOX, value); 46 45 if (ret) { 47 46 pr_debug("cpu %d OC mailbox write failed\n", cpu); 48 47 return ret; 49 48 } 50 49 51 50 for (i = 0; i < OC_MAILBOX_RETRY_COUNT; ++i) { 52 52 - ret = rdmsrl_safe(MSR_OC_MAILBOX, &value); 51 51 + ret = rdmsrq_safe(MSR_OC_MAILBOX, &value); 53 52 if (ret) { 54 53 pr_debug("cpu %d OC mailbox read failed\n", cpu); 55 54 break;

+6 -5

drivers/platform/x86/intel/uncore-frequency/uncore-frequency.c

reviewed

··· 21 21 #include <linux/suspend.h> 22 22 #include <asm/cpu_device_id.h> 23 23 #include <asm/intel-family.h> 24 24 + #include <asm/msr.h> 24 25 25 26 #include "uncore-frequency-common.h" 26 27 ··· 52 51 if (data->control_cpu < 0) 53 52 return -ENXIO; 54 53 55 55 - ret = rdmsrl_on_cpu(data->control_cpu, MSR_UNCORE_RATIO_LIMIT, &cap); 54 54 + ret = rdmsrq_on_cpu(data->control_cpu, MSR_UNCORE_RATIO_LIMIT, &cap); 56 55 if (ret) 57 56 return ret; 58 57 ··· 77 76 if (data->control_cpu < 0) 78 77 return -ENXIO; 79 78 80 80 - ret = rdmsrl_on_cpu(data->control_cpu, MSR_UNCORE_RATIO_LIMIT, &cap); 79 79 + ret = rdmsrq_on_cpu(data->control_cpu, MSR_UNCORE_RATIO_LIMIT, &cap); 81 80 if (ret) 82 81 return ret; 83 82 ··· 89 88 cap |= FIELD_PREP(UNCORE_MIN_RATIO_MASK, input); 90 89 } 91 90 92 92 - ret = wrmsrl_on_cpu(data->control_cpu, MSR_UNCORE_RATIO_LIMIT, cap); 91 91 + ret = wrmsrq_on_cpu(data->control_cpu, MSR_UNCORE_RATIO_LIMIT, cap); 93 92 if (ret) 94 93 return ret; 95 94 ··· 106 105 if (data->control_cpu < 0) 107 106 return -ENXIO; 108 107 109 109 - ret = rdmsrl_on_cpu(data->control_cpu, MSR_UNCORE_PERF_STATUS, &ratio); 108 108 + ret = rdmsrq_on_cpu(data->control_cpu, MSR_UNCORE_PERF_STATUS, &ratio); 110 109 if (ret) 111 110 return ret; 112 111 ··· 213 212 if (!data || !data->valid || !data->stored_uncore_data) 214 213 return 0; 215 214 216 216 - wrmsrl_on_cpu(data->control_cpu, MSR_UNCORE_RATIO_LIMIT, 215 215 + wrmsrq_on_cpu(data->control_cpu, MSR_UNCORE_RATIO_LIMIT, 217 216 data->stored_uncore_data); 218 217 } 219 218 break;

+18 -18

drivers/platform/x86/intel_ips.c

reviewed

··· 370 370 if (!ips->cpu_turbo_enabled) 371 371 return; 372 372 373 373 - rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); 373 373 + rdmsrq(TURBO_POWER_CURRENT_LIMIT, turbo_override); 374 374 375 375 cur_tdp_limit = turbo_override & TURBO_TDP_MASK; 376 376 new_tdp_limit = cur_tdp_limit + 8; /* 1W increase */ ··· 382 382 thm_writew(THM_MPCPC, (new_tdp_limit * 10) / 8); 383 383 384 384 turbo_override |= TURBO_TDC_OVR_EN | TURBO_TDP_OVR_EN; 385 385 - wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); 385 385 + wrmsrq(TURBO_POWER_CURRENT_LIMIT, turbo_override); 386 386 387 387 turbo_override &= ~TURBO_TDP_MASK; 388 388 turbo_override |= new_tdp_limit; 389 389 390 390 - wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); 390 390 + wrmsrq(TURBO_POWER_CURRENT_LIMIT, turbo_override); 391 391 } 392 392 393 393 /** ··· 405 405 u64 turbo_override; 406 406 u16 cur_limit, new_limit; 407 407 408 408 - rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); 408 408 + rdmsrq(TURBO_POWER_CURRENT_LIMIT, turbo_override); 409 409 410 410 cur_limit = turbo_override & TURBO_TDP_MASK; 411 411 new_limit = cur_limit - 8; /* 1W decrease */ ··· 417 417 thm_writew(THM_MPCPC, (new_limit * 10) / 8); 418 418 419 419 turbo_override |= TURBO_TDC_OVR_EN | TURBO_TDP_OVR_EN; 420 420 - wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); 420 420 + wrmsrq(TURBO_POWER_CURRENT_LIMIT, turbo_override); 421 421 422 422 turbo_override &= ~TURBO_TDP_MASK; 423 423 turbo_override |= new_limit; 424 424 425 425 - wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); 425 425 + wrmsrq(TURBO_POWER_CURRENT_LIMIT, turbo_override); 426 426 } 427 427 428 428 /** ··· 437 437 { 438 438 u64 perf_ctl; 439 439 440 440 - rdmsrl(IA32_PERF_CTL, perf_ctl); 440 440 + rdmsrq(IA32_PERF_CTL, perf_ctl); 441 441 if (perf_ctl & IA32_PERF_TURBO_DIS) { 442 442 perf_ctl &= ~IA32_PERF_TURBO_DIS; 443 443 - wrmsrl(IA32_PERF_CTL, perf_ctl); 443 443 + wrmsrq(IA32_PERF_CTL, perf_ctl); 444 444 } 445 445 } 446 446 ··· 475 475 { 476 476 u64 perf_ctl; 477 477 478 478 - rdmsrl(IA32_PERF_CTL, perf_ctl); 478 478 + rdmsrq(IA32_PERF_CTL, perf_ctl); 479 479 if (!(perf_ctl & IA32_PERF_TURBO_DIS)) { 480 480 perf_ctl |= IA32_PERF_TURBO_DIS; 481 481 - wrmsrl(IA32_PERF_CTL, perf_ctl); 481 481 + wrmsrq(IA32_PERF_CTL, perf_ctl); 482 482 } 483 483 } 484 484 ··· 1215 1215 u64 turbo_override; 1216 1216 int tdp, tdc; 1217 1217 1218 1218 - rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); 1218 1218 + rdmsrq(TURBO_POWER_CURRENT_LIMIT, turbo_override); 1219 1219 1220 1220 tdp = (int)(turbo_override & TURBO_TDP_MASK); 1221 1221 tdc = (int)((turbo_override & TURBO_TDC_MASK) >> TURBO_TDC_SHIFT); ··· 1290 1290 return NULL; 1291 1291 } 1292 1292 1293 1293 - rdmsrl(IA32_MISC_ENABLE, misc_en); 1293 1293 + rdmsrq(IA32_MISC_ENABLE, misc_en); 1294 1294 /* 1295 1295 * If the turbo enable bit isn't set, we shouldn't try to enable/disable 1296 1296 * turbo manually or we'll get an illegal MSR access, even though ··· 1312 1312 return NULL; 1313 1313 } 1314 1314 1315 1315 - rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_power); 1315 1315 + rdmsrq(TURBO_POWER_CURRENT_LIMIT, turbo_power); 1316 1316 tdp = turbo_power & TURBO_TDP_MASK; 1317 1317 1318 1318 /* Sanity check TDP against CPU */ ··· 1496 1496 * Check PLATFORM_INFO MSR to make sure this chip is 1497 1497 * turbo capable. 1498 1498 */ 1499 1499 - rdmsrl(PLATFORM_INFO, platform_info); 1499 1499 + rdmsrq(PLATFORM_INFO, platform_info); 1500 1500 if (!(platform_info & PLATFORM_TDP)) { 1501 1501 dev_err(&dev->dev, "platform indicates TDP override unavailable, aborting\n"); 1502 1502 return -ENODEV; ··· 1529 1529 ips->mgta_val = thm_readw(THM_MGTA); 1530 1530 1531 1531 /* Save turbo limits & ratios */ 1532 1532 - rdmsrl(TURBO_POWER_CURRENT_LIMIT, ips->orig_turbo_limit); 1532 1532 + rdmsrq(TURBO_POWER_CURRENT_LIMIT, ips->orig_turbo_limit); 1533 1533 1534 1534 ips_disable_cpu_turbo(ips); 1535 1535 ips->cpu_turbo_enabled = false; ··· 1596 1596 if (ips->gpu_turbo_disable) 1597 1597 symbol_put(i915_gpu_turbo_disable); 1598 1598 1599 1599 - rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); 1599 1599 + rdmsrq(TURBO_POWER_CURRENT_LIMIT, turbo_override); 1600 1600 turbo_override &= ~(TURBO_TDC_OVR_EN | TURBO_TDP_OVR_EN); 1601 1601 - wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); 1602 1602 - wrmsrl(TURBO_POWER_CURRENT_LIMIT, ips->orig_turbo_limit); 1601 1601 + wrmsrq(TURBO_POWER_CURRENT_LIMIT, turbo_override); 1602 1602 + wrmsrq(TURBO_POWER_CURRENT_LIMIT, ips->orig_turbo_limit); 1603 1603 1604 1604 free_irq(ips->irq, ips); 1605 1605 pci_free_irq_vectors(dev);

+1

drivers/powercap/intel_rapl_common.c

reviewed

··· 28 28 #include <asm/cpu_device_id.h> 29 29 #include <asm/intel-family.h> 30 30 #include <asm/iosf_mbi.h> 31 31 + #include <asm/msr.h> 31 32 32 33 /* bitmasks for RAPL MSRs, used by primitive access functions */ 33 34 #define ENERGY_STATUS_MASK 0xffffffff

+4 -3

drivers/powercap/intel_rapl_msr.c

reviewed

··· 24 24 25 25 #include <asm/cpu_device_id.h> 26 26 #include <asm/intel-family.h> 27 27 + #include <asm/msr.h> 27 28 28 29 /* Local defines */ 29 30 #define MSR_PLATFORM_POWER_LIMIT 0x0000065C ··· 104 103 105 104 static int rapl_msr_read_raw(int cpu, struct reg_action *ra) 106 105 { 107 107 - if (rdmsrl_safe_on_cpu(cpu, ra->reg.msr, &ra->value)) { 106 106 + if (rdmsrq_safe_on_cpu(cpu, ra->reg.msr, &ra->value)) { 108 107 pr_debug("failed to read msr 0x%x on cpu %d\n", ra->reg.msr, cpu); 109 108 return -EIO; 110 109 } ··· 117 116 struct reg_action *ra = info; 118 117 u64 val; 119 118 120 120 - ra->err = rdmsrl_safe(ra->reg.msr, &val); 119 119 + ra->err = rdmsrq_safe(ra->reg.msr, &val); 121 120 if (ra->err) 122 121 return; 123 122 124 123 val &= ~ra->mask; 125 124 val |= ra->value; 126 125 127 127 - ra->err = wrmsrl_safe(ra->reg.msr, val); 126 126 + ra->err = wrmsrq_safe(ra->reg.msr, val); 128 127 } 129 128 130 129 static int rapl_msr_write_raw(int cpu, struct reg_action *ra)

+2 -1

drivers/thermal/intel/int340x_thermal/processor_thermal_device.c

reviewed

··· 9 9 #include <linux/module.h> 10 10 #include <linux/pci.h> 11 11 #include <linux/thermal.h> 12 12 + #include <asm/msr.h> 12 13 #include "int340x_thermal_zone.h" 13 14 #include "processor_thermal_device.h" 14 15 #include "../intel_soc_dts_iosf.h" ··· 154 153 u64 val; 155 154 int err; 156 155 157 157 - err = rdmsrl_safe(MSR_PLATFORM_INFO, &val); 156 156 + err = rdmsrq_safe(MSR_PLATFORM_INFO, &val); 158 157 if (err) 159 158 return err; 160 159

+7 -7

drivers/thermal/intel/intel_hfi.c

reviewed

··· 284 284 if (!raw_spin_trylock(&hfi_instance->event_lock)) 285 285 return; 286 286 287 287 - rdmsrl(MSR_IA32_PACKAGE_THERM_STATUS, msr); 287 287 + rdmsrq(MSR_IA32_PACKAGE_THERM_STATUS, msr); 288 288 hfi = msr & PACKAGE_THERM_STATUS_HFI_UPDATED; 289 289 if (!hfi) { 290 290 raw_spin_unlock(&hfi_instance->event_lock); ··· 356 356 { 357 357 u64 msr_val; 358 358 359 359 - rdmsrl(MSR_IA32_HW_FEEDBACK_CONFIG, msr_val); 359 359 + rdmsrq(MSR_IA32_HW_FEEDBACK_CONFIG, msr_val); 360 360 msr_val |= HW_FEEDBACK_CONFIG_HFI_ENABLE_BIT; 361 361 - wrmsrl(MSR_IA32_HW_FEEDBACK_CONFIG, msr_val); 361 361 + wrmsrq(MSR_IA32_HW_FEEDBACK_CONFIG, msr_val); 362 362 } 363 363 364 364 static void hfi_set_hw_table(struct hfi_instance *hfi_instance) ··· 368 368 369 369 hw_table_pa = virt_to_phys(hfi_instance->hw_table); 370 370 msr_val = hw_table_pa | HW_FEEDBACK_PTR_VALID_BIT; 371 371 - wrmsrl(MSR_IA32_HW_FEEDBACK_PTR, msr_val); 371 371 + wrmsrq(MSR_IA32_HW_FEEDBACK_PTR, msr_val); 372 372 } 373 373 374 374 /* Caller must hold hfi_instance_lock. */ ··· 377 377 u64 msr_val; 378 378 int i; 379 379 380 380 - rdmsrl(MSR_IA32_HW_FEEDBACK_CONFIG, msr_val); 380 380 + rdmsrq(MSR_IA32_HW_FEEDBACK_CONFIG, msr_val); 381 381 msr_val &= ~HW_FEEDBACK_CONFIG_HFI_ENABLE_BIT; 382 382 - wrmsrl(MSR_IA32_HW_FEEDBACK_CONFIG, msr_val); 382 382 + wrmsrq(MSR_IA32_HW_FEEDBACK_CONFIG, msr_val); 383 383 384 384 /* 385 385 * Wait for hardware to acknowledge the disabling of HFI. Some ··· 388 388 * memory. 389 389 */ 390 390 for (i = 0; i < 2000; i++) { 391 391 - rdmsrl(MSR_IA32_PACKAGE_THERM_STATUS, msr_val); 391 391 + rdmsrq(MSR_IA32_PACKAGE_THERM_STATUS, msr_val); 392 392 if (msr_val & PACKAGE_THERM_STATUS_HFI_UPDATED) 393 393 break; 394 394

+2 -2

drivers/thermal/intel/intel_powerclamp.c

reviewed

··· 340 340 341 341 /* check if any one of the counter msrs exists */ 342 342 while (info->msr_index) { 343 343 - if (!rdmsrl_safe(info->msr_index, &val)) 343 343 + if (!rdmsrq_safe(info->msr_index, &val)) 344 344 return true; 345 345 info++; 346 346 } ··· 356 356 357 357 while (info->msr_index) { 358 358 if (!info->skip) { 359 359 - if (!rdmsrl_safe(info->msr_index, &val)) 359 359 + if (!rdmsrq_safe(info->msr_index, &val)) 360 360 count += val; 361 361 else 362 362 info->skip = true;

+3 -2

drivers/thermal/intel/intel_tcc_cooling.c

reviewed

··· 11 11 #include <linux/module.h> 12 12 #include <linux/thermal.h> 13 13 #include <asm/cpu_device_id.h> 14 14 + #include <asm/msr.h> 14 15 15 16 #define TCC_PROGRAMMABLE BIT(30) 16 17 #define TCC_LOCKED BIT(31) ··· 82 81 if (!id) 83 82 return -ENODEV; 84 83 85 85 - err = rdmsrl_safe(MSR_PLATFORM_INFO, &val); 84 84 + err = rdmsrq_safe(MSR_PLATFORM_INFO, &val); 86 85 if (err) 87 86 return err; 88 87 89 88 if (!(val & TCC_PROGRAMMABLE)) 90 89 return -ENODEV; 91 90 92 92 - err = rdmsrl_safe(MSR_IA32_TEMPERATURE_TARGET, &val); 91 91 + err = rdmsrq_safe(MSR_IA32_TEMPERATURE_TARGET, &val); 93 92 if (err) 94 93 return err; 95 94

+5 -5

drivers/thermal/intel/therm_throt.c

reviewed

··· 273 273 } 274 274 275 275 msr_val &= ~bit_mask; 276 276 - wrmsrl(msr, msr_val); 276 276 + wrmsrq(msr, msr_val); 277 277 } 278 278 EXPORT_SYMBOL_GPL(thermal_clear_package_intr_status); 279 279 ··· 287 287 else 288 288 msr = MSR_IA32_PACKAGE_THERM_STATUS; 289 289 290 290 - rdmsrl(msr, msr_val); 290 290 + rdmsrq(msr, msr_val); 291 291 if (msr_val & THERM_STATUS_PROCHOT_LOG) 292 292 *proc_hot = true; 293 293 else ··· 643 643 644 644 void __weak notify_hwp_interrupt(void) 645 645 { 646 646 - wrmsrl_safe(MSR_HWP_STATUS, 0); 646 646 + wrmsrq_safe(MSR_HWP_STATUS, 0); 647 647 } 648 648 649 649 /* Thermal transition interrupt handler */ ··· 654 654 if (static_cpu_has(X86_FEATURE_HWP)) 655 655 notify_hwp_interrupt(); 656 656 657 657 - rdmsrl(MSR_IA32_THERM_STATUS, msr_val); 657 657 + rdmsrq(MSR_IA32_THERM_STATUS, msr_val); 658 658 659 659 /* Check for violation of core thermal thresholds*/ 660 660 notify_thresholds(msr_val); ··· 669 669 CORE_LEVEL); 670 670 671 671 if (this_cpu_has(X86_FEATURE_PTS)) { 672 672 - rdmsrl(MSR_IA32_PACKAGE_THERM_STATUS, msr_val); 672 672 + rdmsrq(MSR_IA32_PACKAGE_THERM_STATUS, msr_val); 673 673 /* check violations of package thermal thresholds */ 674 674 notify_package_thresholds(msr_val); 675 675 therm_throt_process(msr_val & PACKAGE_THERM_STATUS_PROCHOT,

+1

drivers/thermal/intel/x86_pkg_temp_thermal.c

reviewed

··· 20 20 #include <linux/debugfs.h> 21 21 22 22 #include <asm/cpu_device_id.h> 23 23 + #include <asm/msr.h> 23 24 24 25 #include "thermal_interrupt.h" 25 26

+1

drivers/video/fbdev/geode/display_gx.c

reviewed

··· 13 13 #include <asm/io.h> 14 14 #include <asm/div64.h> 15 15 #include <asm/delay.h> 16 16 + #include <asm/msr.h> 16 17 #include <linux/cs5535.h> 17 18 18 19 #include "gxfb.h"

+2 -1

drivers/video/fbdev/geode/gxfb_core.c

reviewed

··· 29 29 #include <linux/pci.h> 30 30 #include <linux/cs5535.h> 31 31 32 32 + #include <asm/msr.h> 32 33 #include <asm/olpc.h> 33 34 34 35 #include "gxfb.h" ··· 378 377 379 378 /* Figure out if this is a TFT or CRT part */ 380 379 381 381 - rdmsrl(MSR_GX_GLD_MSR_CONFIG, val); 380 380 + rdmsrq(MSR_GX_GLD_MSR_CONFIG, val); 382 381 383 382 if ((val & MSR_GX_GLD_MSR_CONFIG_FP) == MSR_GX_GLD_MSR_CONFIG_FP) 384 383 par->enable_crt = 0;

+12 -11

drivers/video/fbdev/geode/lxfb_ops.c

reviewed

··· 11 11 #include <linux/delay.h> 12 12 #include <linux/cs5535.h> 13 13 14 14 + #include <asm/msr.h> 14 15 #include "lxfb.h" 15 16 16 17 /* TODO ··· 359 358 360 359 /* Set output mode */ 361 360 362 362 - rdmsrl(MSR_LX_GLD_MSR_CONFIG, msrval); 361 361 + rdmsrq(MSR_LX_GLD_MSR_CONFIG, msrval); 363 362 msrval &= ~MSR_LX_GLD_MSR_CONFIG_FMT; 364 363 365 364 if (par->output & OUTPUT_PANEL) { ··· 372 371 } else 373 372 msrval |= MSR_LX_GLD_MSR_CONFIG_FMT_CRT; 374 373 375 375 - wrmsrl(MSR_LX_GLD_MSR_CONFIG, msrval); 374 374 + wrmsrq(MSR_LX_GLD_MSR_CONFIG, msrval); 376 375 377 376 /* Clear the various buffers */ 378 377 /* FIXME: Adjust for panning here */ ··· 420 419 421 420 /* Set default watermark values */ 422 421 423 423 - rdmsrl(MSR_LX_SPARE_MSR, msrval); 422 422 + rdmsrq(MSR_LX_SPARE_MSR, msrval); 424 423 425 424 msrval &= ~(MSR_LX_SPARE_MSR_DIS_CFIFO_HGO 426 425 | MSR_LX_SPARE_MSR_VFIFO_ARB_SEL ··· 428 427 | MSR_LX_SPARE_MSR_WM_LPEN_OVRD); 429 428 msrval |= MSR_LX_SPARE_MSR_DIS_VIFO_WM | 430 429 MSR_LX_SPARE_MSR_DIS_INIT_V_PRI; 431 431 - wrmsrl(MSR_LX_SPARE_MSR, msrval); 430 430 + wrmsrq(MSR_LX_SPARE_MSR, msrval); 432 431 433 432 gcfg = DC_GENERAL_CFG_DFLE; /* Display fifo enable */ 434 433 gcfg |= (0x6 << DC_GENERAL_CFG_DFHPSL_SHIFT) | /* default priority */ ··· 592 591 } while ((i & GP_BLT_STATUS_PB) || !(i & GP_BLT_STATUS_CE)); 593 592 594 593 /* save MSRs */ 595 595 - rdmsrl(MSR_LX_MSR_PADSEL, par->msr.padsel); 596 596 - rdmsrl(MSR_GLCP_DOTPLL, par->msr.dotpll); 597 597 - rdmsrl(MSR_LX_GLD_MSR_CONFIG, par->msr.dfglcfg); 598 598 - rdmsrl(MSR_LX_SPARE_MSR, par->msr.dcspare); 594 594 + rdmsrq(MSR_LX_MSR_PADSEL, par->msr.padsel); 595 595 + rdmsrq(MSR_GLCP_DOTPLL, par->msr.dotpll); 596 596 + rdmsrq(MSR_LX_GLD_MSR_CONFIG, par->msr.dfglcfg); 597 597 + rdmsrq(MSR_LX_SPARE_MSR, par->msr.dcspare); 599 598 600 599 write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK); 601 600 ··· 665 664 uint32_t filt; 666 665 int i; 667 666 668 668 - wrmsrl(MSR_LX_SPARE_MSR, par->msr.dcspare); 667 667 + wrmsrq(MSR_LX_SPARE_MSR, par->msr.dcspare); 669 668 670 669 for (i = 0; i < ARRAY_SIZE(par->dc); i++) { 671 670 switch (i) { ··· 730 729 { 731 730 int i; 732 731 733 733 - wrmsrl(MSR_LX_GLD_MSR_CONFIG, par->msr.dfglcfg); 734 734 - wrmsrl(MSR_LX_MSR_PADSEL, par->msr.padsel); 732 732 + wrmsrq(MSR_LX_GLD_MSR_CONFIG, par->msr.dfglcfg); 733 733 + wrmsrq(MSR_LX_MSR_PADSEL, par->msr.padsel); 735 734 736 735 for (i = 0; i < ARRAY_SIZE(par->vp); i++) { 737 736 switch (i) {

+5 -5

drivers/video/fbdev/geode/suspend_gx.c

reviewed

··· 21 21 } while (i & (GP_BLT_STATUS_BLT_PENDING | GP_BLT_STATUS_BLT_BUSY)); 22 22 23 23 /* save MSRs */ 24 24 - rdmsrl(MSR_GX_MSR_PADSEL, par->msr.padsel); 25 25 - rdmsrl(MSR_GLCP_DOTPLL, par->msr.dotpll); 24 24 + rdmsrq(MSR_GX_MSR_PADSEL, par->msr.padsel); 25 25 + rdmsrq(MSR_GLCP_DOTPLL, par->msr.dotpll); 26 26 27 27 write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK); 28 28 ··· 43 43 uint32_t dotpll_lo; 44 44 int i; 45 45 46 46 - rdmsrl(MSR_GLCP_DOTPLL, dotpll_lo); 46 46 + rdmsrq(MSR_GLCP_DOTPLL, dotpll_lo); 47 47 dotpll_lo |= MSR_GLCP_DOTPLL_DOTRESET; 48 48 dotpll_lo &= ~MSR_GLCP_DOTPLL_BYPASS; 49 49 wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi); 50 50 51 51 /* wait for the PLL to lock */ 52 52 for (i = 0; i < 200; i++) { 53 53 - rdmsrl(MSR_GLCP_DOTPLL, dotpll_lo); 53 53 + rdmsrq(MSR_GLCP_DOTPLL, dotpll_lo); 54 54 if (dotpll_lo & MSR_GLCP_DOTPLL_LOCK) 55 55 break; 56 56 udelay(1); ··· 133 133 { 134 134 int i; 135 135 136 136 - wrmsrl(MSR_GX_MSR_PADSEL, par->msr.padsel); 136 136 + wrmsrq(MSR_GX_MSR_PADSEL, par->msr.padsel); 137 137 138 138 for (i = 0; i < ARRAY_SIZE(par->vp); i++) { 139 139 switch (i) {

+8 -8

drivers/video/fbdev/geode/video_gx.c

reviewed

··· 142 142 } 143 143 } 144 144 145 145 - rdmsrl(MSR_GLCP_SYS_RSTPLL, sys_rstpll); 146 146 - rdmsrl(MSR_GLCP_DOTPLL, dotpll); 145 145 + rdmsrq(MSR_GLCP_SYS_RSTPLL, sys_rstpll); 146 146 + rdmsrq(MSR_GLCP_DOTPLL, dotpll); 147 147 148 148 /* Program new M, N and P. */ 149 149 dotpll &= 0x00000000ffffffffull; ··· 151 151 dotpll |= MSR_GLCP_DOTPLL_DOTRESET; 152 152 dotpll &= ~MSR_GLCP_DOTPLL_BYPASS; 153 153 154 154 - wrmsrl(MSR_GLCP_DOTPLL, dotpll); 154 154 + wrmsrq(MSR_GLCP_DOTPLL, dotpll); 155 155 156 156 /* Program dividers. */ 157 157 sys_rstpll &= ~( MSR_GLCP_SYS_RSTPLL_DOTPREDIV2 ··· 159 159 | MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3 ); 160 160 sys_rstpll |= pll_table[best_i].sys_rstpll_bits; 161 161 162 162 - wrmsrl(MSR_GLCP_SYS_RSTPLL, sys_rstpll); 162 162 + wrmsrq(MSR_GLCP_SYS_RSTPLL, sys_rstpll); 163 163 164 164 /* Clear reset bit to start PLL. */ 165 165 dotpll &= ~(MSR_GLCP_DOTPLL_DOTRESET); 166 166 - wrmsrl(MSR_GLCP_DOTPLL, dotpll); 166 166 + wrmsrq(MSR_GLCP_DOTPLL, dotpll); 167 167 168 168 /* Wait for LOCK bit. */ 169 169 do { 170 170 - rdmsrl(MSR_GLCP_DOTPLL, dotpll); 170 170 + rdmsrq(MSR_GLCP_DOTPLL, dotpll); 171 171 } while (timeout-- && !(dotpll & MSR_GLCP_DOTPLL_LOCK)); 172 172 } 173 173 ··· 180 180 181 181 /* Set up the DF pad select MSR */ 182 182 183 183 - rdmsrl(MSR_GX_MSR_PADSEL, val); 183 183 + rdmsrq(MSR_GX_MSR_PADSEL, val); 184 184 val &= ~MSR_GX_MSR_PADSEL_MASK; 185 185 val |= MSR_GX_MSR_PADSEL_TFT; 186 186 - wrmsrl(MSR_GX_MSR_PADSEL, val); 186 186 + wrmsrq(MSR_GX_MSR_PADSEL, val); 187 187 188 188 /* Turn off the panel */ 189 189

+1 -1

include/hyperv/hvgdk_mini.h

reviewed

··· 1013 1013 1014 1014 /* 1015 1015 * To support arch-generic code calling hv_set/get_register: 1016 1016 - * - On x86, HV_MSR_ indicates an MSR accessed via rdmsrl/wrmsrl 1016 1016 + * - On x86, HV_MSR_ indicates an MSR accessed via rdmsrq/wrmsrq 1017 1017 * - On ARM, HV_MSR_ indicates a VP register accessed via hypercall 1018 1018 */ 1019 1019 #define HV_MSR_CRASH_P0 (HV_X64_MSR_CRASH_P0)