Merge tag 'amd-drm-next-6.13-2024-11-06' of https://gitlab.freedesktop.org/agd5f/linux into drm-next

+12

Documentation/gpu/amdgpu/thermal.rst

··· 100 100 .. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c 101 101 :doc: fan_minimum_pwm 102 102 103 + fan_zero_rpm_enable 104 + ---------------------- 105 + 106 + .. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c 107 + :doc: fan_zero_rpm_enable 108 + 109 + fan_zero_rpm_stop_temperature 110 + ----------------------------- 111 + 112 + .. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c 113 + :doc: fan_zero_rpm_stop_temperature 114 + 103 115 GFXOFF 104 116 ====== 105 117

+1 -3

drivers/gpu/drm/amd/amdgpu/amdgpu.h

··· 118 118 119 119 #define MAX_GPU_INSTANCE 64 120 120 121 - #define GFX_SLICE_PERIOD msecs_to_jiffies(250) 121 + #define GFX_SLICE_PERIOD_MS 250 122 122 123 123 struct amdgpu_gpu_instance { 124 124 struct amdgpu_device *adev; ··· 1111 1111 bool in_s3; 1112 1112 bool in_s4; 1113 1113 bool in_s0ix; 1114 - /* indicate amdgpu suspension status */ 1115 - bool suspend_complete; 1116 1114 1117 1115 enum pp_mp1_state mp1_state; 1118 1116 struct amdgpu_doorbell_index doorbell_index;

+2 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c

··· 172 172 &buffer); 173 173 obj = (union acpi_object *)buffer.pointer; 174 174 175 - /* Fail if calling the method fails and ATIF is supported */ 176 - if (ACPI_FAILURE(status) && status != AE_NOT_FOUND) { 175 + /* Fail if calling the method fails */ 176 + if (ACPI_FAILURE(status)) { 177 177 DRM_DEBUG_DRIVER("failed to evaluate ATIF got %s\n", 178 178 acpi_format_exception(status)); 179 179 kfree(obj);

+9

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

··· 890 890 return kgd2kfd_start_sched(adev->kfd.dev, node_id); 891 891 } 892 892 893 + /* check if there are KFD queues active */ 894 + bool amdgpu_amdkfd_compute_active(struct amdgpu_device *adev, uint32_t node_id) 895 + { 896 + if (!adev->kfd.init_complete) 897 + return false; 898 + 899 + return kgd2kfd_compute_active(adev->kfd.dev, node_id); 900 + } 901 + 893 902 /* Config CGTT_SQ_CLK_CTRL */ 894 903 int amdgpu_amdkfd_config_sq_perfmon(struct amdgpu_device *adev, uint32_t xcp_id, 895 904 bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable)

+7

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h

··· 268 268 int amdgpu_amdkfd_stop_sched(struct amdgpu_device *adev, uint32_t node_id); 269 269 int amdgpu_amdkfd_config_sq_perfmon(struct amdgpu_device *adev, uint32_t xcp_id, 270 270 bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable); 271 + bool amdgpu_amdkfd_compute_active(struct amdgpu_device *adev, uint32_t node_id); 271 272 272 273 273 274 /* Read user wptr from a specified user address space with page fault ··· 432 431 void kgd2kfd_unlock_kfd(void); 433 432 int kgd2kfd_start_sched(struct kfd_dev *kfd, uint32_t node_id); 434 433 int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id); 434 + bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id); 435 435 #else 436 436 static inline int kgd2kfd_init(void) 437 437 { ··· 512 510 static inline int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id) 513 511 { 514 512 return 0; 513 + } 514 + 515 + static inline bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id) 516 + { 517 + return false; 515 518 } 516 519 #endif 517 520 #endif /* AMDGPU_AMDKFD_H_INCLUDED */

+8 -5

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

··· 402 402 int r; 403 403 uint32_t *data, x; 404 404 405 - if (size & 0x3 || *pos & 0x3) 405 + if (size > 4096 || size & 0x3 || *pos & 0x3) 406 406 return -EINVAL; 407 407 408 408 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); ··· 1648 1648 1649 1649 for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { 1650 1650 ent = debugfs_create_file(debugfs_regs_names[i], 1651 - S_IFREG | 0444, root, 1651 + S_IFREG | 0400, root, 1652 1652 adev, debugfs_regs[i]); 1653 1653 if (!i && !IS_ERR_OR_NULL(ent)) 1654 1654 i_size_write(ent->d_inode, adev->rmmio_size); ··· 2096 2096 amdgpu_debugfs_umsch_fwlog_init(adev, &adev->umsch_mm); 2097 2097 2098 2098 amdgpu_debugfs_jpeg_sched_mask_init(adev); 2099 + amdgpu_debugfs_gfx_sched_mask_init(adev); 2100 + amdgpu_debugfs_compute_sched_mask_init(adev); 2101 + amdgpu_debugfs_sdma_sched_mask_init(adev); 2099 2102 2100 2103 amdgpu_ras_debugfs_create_all(adev); 2101 2104 amdgpu_rap_debugfs_init(adev); 2102 2105 amdgpu_securedisplay_debugfs_init(adev); 2103 2106 amdgpu_fw_attestation_debugfs_init(adev); 2104 2107 2105 - debugfs_create_file("amdgpu_evict_vram", 0444, root, adev, 2108 + debugfs_create_file("amdgpu_evict_vram", 0400, root, adev, 2106 2109 &amdgpu_evict_vram_fops); 2107 - debugfs_create_file("amdgpu_evict_gtt", 0444, root, adev, 2110 + debugfs_create_file("amdgpu_evict_gtt", 0400, root, adev, 2108 2111 &amdgpu_evict_gtt_fops); 2109 - debugfs_create_file("amdgpu_test_ib", 0444, root, adev, 2112 + debugfs_create_file("amdgpu_test_ib", 0400, root, adev, 2110 2113 &amdgpu_debugfs_test_ib_fops); 2111 2114 debugfs_create_file("amdgpu_vm_info", 0444, root, adev, 2112 2115 &amdgpu_debugfs_vm_info_fops);

+3

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

··· 6452 6452 struct amdgpu_device *adev = drm_to_adev(dev); 6453 6453 int r; 6454 6454 6455 + if (amdgpu_sriov_vf(adev)) 6456 + return false; 6457 + 6455 6458 r = pci_save_state(pdev); 6456 6459 if (!r) { 6457 6460 kfree(adev->pci_state);

+5 -3

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

··· 1795 1795 1796 1796 switch (le16_to_cpu(nps_info->v1.header.version_major)) { 1797 1797 case 1: 1798 + mem_ranges = kvcalloc(nps_info->v1.count, 1799 + sizeof(*mem_ranges), 1800 + GFP_KERNEL); 1801 + if (!mem_ranges) 1802 + return -ENOMEM; 1798 1803 *nps_type = nps_info->v1.nps_type; 1799 1804 *range_cnt = nps_info->v1.count; 1800 - mem_ranges = kvzalloc( 1801 - *range_cnt * sizeof(struct amdgpu_gmc_memrange), 1802 - GFP_KERNEL); 1803 1805 for (i = 0; i < *range_cnt; i++) { 1804 1806 mem_ranges[i].base_address = 1805 1807 nps_info->v1.instance_info[i].base_address;

+1 -3

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

··· 888 888 * the ABM algorithm, with 1 being the least reduction and 4 being the most 889 889 * reduction. 890 890 * 891 - * Defaults to -1, or disabled. Userspace can only override this level after 891 + * Defaults to -1, or auto. Userspace can only override this level after 892 892 * boot if it's set to auto. 893 893 */ 894 894 int amdgpu_dm_abm_level = -1; ··· 2505 2505 struct drm_device *drm_dev = dev_get_drvdata(dev); 2506 2506 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2507 2507 2508 - adev->suspend_complete = false; 2509 2508 if (amdgpu_acpi_is_s0ix_active(adev)) 2510 2509 adev->in_s0ix = true; 2511 2510 else if (amdgpu_acpi_is_s3_active(adev)) ··· 2519 2520 struct drm_device *drm_dev = dev_get_drvdata(dev); 2520 2521 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2521 2522 2522 - adev->suspend_complete = true; 2523 2523 if (amdgpu_acpi_should_gpu_reset(adev)) 2524 2524 return amdgpu_asic_reset(adev); 2525 2525

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c

··· 200 200 dev_err_ratelimited(&i2c_adap->dev, 201 201 "maddr:0x%04X size:0x%02X:quirk max_%s_len must be > %d", 202 202 eeprom_addr, buf_size, 203 - read ? "read" : "write", EEPROM_OFFSET_SIZE); 203 + str_read_write(read), EEPROM_OFFSET_SIZE); 204 204 return -EINVAL; 205 205 } 206 206

+13 -10

drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c

··· 33 33 #include <drm/amdgpu_drm.h> 34 34 #include <drm/drm_debugfs.h> 35 35 #include <drm/drm_drv.h> 36 + #include <drm/drm_file.h> 36 37 37 38 #include "amdgpu.h" 38 39 #include "amdgpu_vm.h" ··· 66 65 [TTM_PL_VRAM] = "vram", 67 66 [TTM_PL_TT] = "gtt", 68 67 [TTM_PL_SYSTEM] = "cpu", 68 + [AMDGPU_PL_GDS] = "gds", 69 + [AMDGPU_PL_GWS] = "gws", 70 + [AMDGPU_PL_OA] = "oa", 71 + [AMDGPU_PL_DOORBELL] = "doorbell", 69 72 }; 70 73 unsigned int hw_ip, i; 71 74 int ret; ··· 91 86 92 87 drm_printf(p, "pasid:\t%u\n", fpriv->vm.pasid); 93 88 94 - for (i = 0; i < TTM_PL_PRIV; i++) 89 + for (i = 0; i < ARRAY_SIZE(pl_name); i++) { 90 + if (!pl_name[i]) 91 + continue; 92 + 95 93 drm_print_memory_stats(p, 96 94 &stats[i].drm, 97 95 DRM_GEM_OBJECT_RESIDENT | 98 96 DRM_GEM_OBJECT_PURGEABLE, 99 97 pl_name[i]); 98 + } 100 99 101 100 /* Legacy amdgpu keys, alias to drm-resident-memory-: */ 102 101 drm_printf(p, "drm-memory-vram:\t%llu KiB\n", 103 - stats[TTM_PL_VRAM].total/1024UL); 102 + stats[TTM_PL_VRAM].drm.resident/1024UL); 104 103 drm_printf(p, "drm-memory-gtt: \t%llu KiB\n", 105 - stats[TTM_PL_TT].total/1024UL); 104 + stats[TTM_PL_TT].drm.resident/1024UL); 106 105 drm_printf(p, "drm-memory-cpu: \t%llu KiB\n", 107 - stats[TTM_PL_SYSTEM].total/1024UL); 106 + stats[TTM_PL_SYSTEM].drm.resident/1024UL); 108 107 109 108 /* Amdgpu specific memory accounting keys: */ 110 - drm_printf(p, "amd-memory-visible-vram:\t%llu KiB\n", 111 - stats[TTM_PL_VRAM].visible/1024UL); 112 109 drm_printf(p, "amd-evicted-vram:\t%llu KiB\n", 113 110 stats[TTM_PL_VRAM].evicted/1024UL); 114 - drm_printf(p, "amd-evicted-visible-vram:\t%llu KiB\n", 115 - stats[TTM_PL_VRAM].evicted_visible/1024UL); 116 111 drm_printf(p, "amd-requested-vram:\t%llu KiB\n", 117 112 stats[TTM_PL_VRAM].requested/1024UL); 118 - drm_printf(p, "amd-requested-visible-vram:\t%llu KiB\n", 119 - stats[TTM_PL_VRAM].requested_visible/1024UL); 120 113 drm_printf(p, "amd-requested-gtt:\t%llu KiB\n", 121 114 stats[TTM_PL_TT].requested/1024UL); 122 115

+6 -4

drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c

··· 78 78 79 79 if (adev->dummy_page_addr) 80 80 return 0; 81 - adev->dummy_page_addr = dma_map_page(&adev->pdev->dev, dummy_page, 0, 82 - PAGE_SIZE, DMA_BIDIRECTIONAL); 81 + adev->dummy_page_addr = dma_map_page_attrs(&adev->pdev->dev, dummy_page, 0, 82 + PAGE_SIZE, DMA_BIDIRECTIONAL, 83 + DMA_ATTR_SKIP_CPU_SYNC); 83 84 if (dma_mapping_error(&adev->pdev->dev, adev->dummy_page_addr)) { 84 85 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n"); 85 86 adev->dummy_page_addr = 0; ··· 100 99 { 101 100 if (!adev->dummy_page_addr) 102 101 return; 103 - dma_unmap_page(&adev->pdev->dev, adev->dummy_page_addr, PAGE_SIZE, 104 - DMA_BIDIRECTIONAL); 102 + dma_unmap_page_attrs(&adev->pdev->dev, adev->dummy_page_addr, PAGE_SIZE, 103 + DMA_BIDIRECTIONAL, 104 + DMA_ATTR_SKIP_CPU_SYNC); 105 105 adev->dummy_page_addr = 0; 106 106 } 107 107

+224 -12

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

··· 1602 1602 static DEVICE_ATTR(available_compute_partition, 0444, 1603 1603 amdgpu_gfx_get_available_compute_partition, NULL); 1604 1604 1605 - int amdgpu_gfx_sysfs_init(struct amdgpu_device *adev) 1605 + static int amdgpu_gfx_sysfs_xcp_init(struct amdgpu_device *adev) 1606 1606 { 1607 1607 struct amdgpu_xcp_mgr *xcp_mgr = adev->xcp_mgr; 1608 1608 bool xcp_switch_supported; ··· 1629 1629 return r; 1630 1630 } 1631 1631 1632 - void amdgpu_gfx_sysfs_fini(struct amdgpu_device *adev) 1632 + static void amdgpu_gfx_sysfs_xcp_fini(struct amdgpu_device *adev) 1633 1633 { 1634 1634 struct amdgpu_xcp_mgr *xcp_mgr = adev->xcp_mgr; 1635 1635 bool xcp_switch_supported; ··· 1646 1646 &dev_attr_available_compute_partition); 1647 1647 } 1648 1648 1649 - int amdgpu_gfx_sysfs_isolation_shader_init(struct amdgpu_device *adev) 1649 + static int amdgpu_gfx_sysfs_isolation_shader_init(struct amdgpu_device *adev) 1650 1650 { 1651 1651 int r; 1652 1652 1653 1653 r = device_create_file(adev->dev, &dev_attr_enforce_isolation); 1654 1654 if (r) 1655 1655 return r; 1656 + if (adev->gfx.enable_cleaner_shader) 1657 + r = device_create_file(adev->dev, &dev_attr_run_cleaner_shader); 1656 1658 1657 - r = device_create_file(adev->dev, &dev_attr_run_cleaner_shader); 1658 - if (r) 1659 - return r; 1660 - 1661 - return 0; 1659 + return r; 1662 1660 } 1663 1661 1664 - void amdgpu_gfx_sysfs_isolation_shader_fini(struct amdgpu_device *adev) 1662 + static void amdgpu_gfx_sysfs_isolation_shader_fini(struct amdgpu_device *adev) 1665 1663 { 1666 1664 device_remove_file(adev->dev, &dev_attr_enforce_isolation); 1667 - device_remove_file(adev->dev, &dev_attr_run_cleaner_shader); 1665 + if (adev->gfx.enable_cleaner_shader) 1666 + device_remove_file(adev->dev, &dev_attr_run_cleaner_shader); 1667 + } 1668 + 1669 + int amdgpu_gfx_sysfs_init(struct amdgpu_device *adev) 1670 + { 1671 + int r; 1672 + 1673 + r = amdgpu_gfx_sysfs_xcp_init(adev); 1674 + if (r) { 1675 + dev_err(adev->dev, "failed to create xcp sysfs files"); 1676 + return r; 1677 + } 1678 + 1679 + r = amdgpu_gfx_sysfs_isolation_shader_init(adev); 1680 + if (r) 1681 + dev_err(adev->dev, "failed to create isolation sysfs files"); 1682 + 1683 + return r; 1684 + } 1685 + 1686 + void amdgpu_gfx_sysfs_fini(struct amdgpu_device *adev) 1687 + { 1688 + amdgpu_gfx_sysfs_xcp_fini(adev); 1689 + amdgpu_gfx_sysfs_isolation_shader_fini(adev); 1668 1690 } 1669 1691 1670 1692 int amdgpu_gfx_cleaner_shader_sw_init(struct amdgpu_device *adev, ··· 1774 1752 if (adev->gfx.kfd_sch_req_count[idx] == 0 && 1775 1753 adev->gfx.kfd_sch_inactive[idx]) { 1776 1754 schedule_delayed_work(&adev->gfx.enforce_isolation[idx].work, 1777 - GFX_SLICE_PERIOD); 1755 + msecs_to_jiffies(adev->gfx.enforce_isolation_time[idx])); 1778 1756 } 1779 1757 } else { 1780 1758 if (adev->gfx.kfd_sch_req_count[idx] == 0) { ··· 1829 1807 fences += amdgpu_fence_count_emitted(&adev->gfx.compute_ring[i]); 1830 1808 } 1831 1809 if (fences) { 1810 + /* we've already had our timeslice, so let's wrap this up */ 1832 1811 schedule_delayed_work(&adev->gfx.enforce_isolation[idx].work, 1833 - GFX_SLICE_PERIOD); 1812 + msecs_to_jiffies(1)); 1834 1813 } else { 1835 1814 /* Tell KFD to resume the runqueue */ 1836 1815 if (adev->kfd.init_complete) { ··· 1842 1819 } 1843 1820 } 1844 1821 mutex_unlock(&adev->enforce_isolation_mutex); 1822 + } 1823 + 1824 + static void 1825 + amdgpu_gfx_enforce_isolation_wait_for_kfd(struct amdgpu_device *adev, 1826 + u32 idx) 1827 + { 1828 + unsigned long cjiffies; 1829 + bool wait = false; 1830 + 1831 + mutex_lock(&adev->enforce_isolation_mutex); 1832 + if (adev->enforce_isolation[idx]) { 1833 + /* set the initial values if nothing is set */ 1834 + if (!adev->gfx.enforce_isolation_jiffies[idx]) { 1835 + adev->gfx.enforce_isolation_jiffies[idx] = jiffies; 1836 + adev->gfx.enforce_isolation_time[idx] = GFX_SLICE_PERIOD_MS; 1837 + } 1838 + /* Make sure KFD gets a chance to run */ 1839 + if (amdgpu_amdkfd_compute_active(adev, idx)) { 1840 + cjiffies = jiffies; 1841 + if (time_after(cjiffies, adev->gfx.enforce_isolation_jiffies[idx])) { 1842 + cjiffies -= adev->gfx.enforce_isolation_jiffies[idx]; 1843 + if ((jiffies_to_msecs(cjiffies) >= GFX_SLICE_PERIOD_MS)) { 1844 + /* if our time is up, let KGD work drain before scheduling more */ 1845 + wait = true; 1846 + /* reset the timer period */ 1847 + adev->gfx.enforce_isolation_time[idx] = GFX_SLICE_PERIOD_MS; 1848 + } else { 1849 + /* set the timer period to what's left in our time slice */ 1850 + adev->gfx.enforce_isolation_time[idx] = 1851 + GFX_SLICE_PERIOD_MS - jiffies_to_msecs(cjiffies); 1852 + } 1853 + } else { 1854 + /* if jiffies wrap around we will just wait a little longer */ 1855 + adev->gfx.enforce_isolation_jiffies[idx] = jiffies; 1856 + } 1857 + } else { 1858 + /* if there is no KFD work, then set the full slice period */ 1859 + adev->gfx.enforce_isolation_jiffies[idx] = jiffies; 1860 + adev->gfx.enforce_isolation_time[idx] = GFX_SLICE_PERIOD_MS; 1861 + } 1862 + } 1863 + mutex_unlock(&adev->enforce_isolation_mutex); 1864 + 1865 + if (wait) 1866 + msleep(GFX_SLICE_PERIOD_MS); 1845 1867 } 1846 1868 1847 1869 void amdgpu_gfx_enforce_isolation_ring_begin_use(struct amdgpu_ring *ring) ··· 1904 1836 1905 1837 if (idx >= MAX_XCP) 1906 1838 return; 1839 + 1840 + /* Don't submit more work until KFD has had some time */ 1841 + amdgpu_gfx_enforce_isolation_wait_for_kfd(adev, idx); 1907 1842 1908 1843 mutex_lock(&adev->enforce_isolation_mutex); 1909 1844 if (adev->enforce_isolation[idx]) { ··· 1938 1867 amdgpu_gfx_kfd_sch_ctrl(adev, idx, true); 1939 1868 } 1940 1869 mutex_unlock(&adev->enforce_isolation_mutex); 1870 + } 1871 + 1872 + /* 1873 + * debugfs for to enable/disable gfx job submission to specific core. 1874 + */ 1875 + #if defined(CONFIG_DEBUG_FS) 1876 + static int amdgpu_debugfs_gfx_sched_mask_set(void *data, u64 val) 1877 + { 1878 + struct amdgpu_device *adev = (struct amdgpu_device *)data; 1879 + u32 i; 1880 + u64 mask = 0; 1881 + struct amdgpu_ring *ring; 1882 + 1883 + if (!adev) 1884 + return -ENODEV; 1885 + 1886 + mask = (1 << adev->gfx.num_gfx_rings) - 1; 1887 + if ((val & mask) == 0) 1888 + return -EINVAL; 1889 + 1890 + for (i = 0; i < adev->gfx.num_gfx_rings; ++i) { 1891 + ring = &adev->gfx.gfx_ring[i]; 1892 + if (val & (1 << i)) 1893 + ring->sched.ready = true; 1894 + else 1895 + ring->sched.ready = false; 1896 + } 1897 + /* publish sched.ready flag update effective immediately across smp */ 1898 + smp_rmb(); 1899 + return 0; 1900 + } 1901 + 1902 + static int amdgpu_debugfs_gfx_sched_mask_get(void *data, u64 *val) 1903 + { 1904 + struct amdgpu_device *adev = (struct amdgpu_device *)data; 1905 + u32 i; 1906 + u64 mask = 0; 1907 + struct amdgpu_ring *ring; 1908 + 1909 + if (!adev) 1910 + return -ENODEV; 1911 + for (i = 0; i < adev->gfx.num_gfx_rings; ++i) { 1912 + ring = &adev->gfx.gfx_ring[i]; 1913 + if (ring->sched.ready) 1914 + mask |= 1 << i; 1915 + } 1916 + 1917 + *val = mask; 1918 + return 0; 1919 + } 1920 + 1921 + DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_gfx_sched_mask_fops, 1922 + amdgpu_debugfs_gfx_sched_mask_get, 1923 + amdgpu_debugfs_gfx_sched_mask_set, "%llx\n"); 1924 + 1925 + #endif 1926 + 1927 + void amdgpu_debugfs_gfx_sched_mask_init(struct amdgpu_device *adev) 1928 + { 1929 + #if defined(CONFIG_DEBUG_FS) 1930 + struct drm_minor *minor = adev_to_drm(adev)->primary; 1931 + struct dentry *root = minor->debugfs_root; 1932 + char name[32]; 1933 + 1934 + if (!(adev->gfx.num_gfx_rings > 1)) 1935 + return; 1936 + sprintf(name, "amdgpu_gfx_sched_mask"); 1937 + debugfs_create_file(name, 0600, root, adev, 1938 + &amdgpu_debugfs_gfx_sched_mask_fops); 1939 + #endif 1940 + } 1941 + 1942 + /* 1943 + * debugfs for to enable/disable compute job submission to specific core. 1944 + */ 1945 + #if defined(CONFIG_DEBUG_FS) 1946 + static int amdgpu_debugfs_compute_sched_mask_set(void *data, u64 val) 1947 + { 1948 + struct amdgpu_device *adev = (struct amdgpu_device *)data; 1949 + u32 i; 1950 + u64 mask = 0; 1951 + struct amdgpu_ring *ring; 1952 + 1953 + if (!adev) 1954 + return -ENODEV; 1955 + 1956 + mask = (1 << adev->gfx.num_compute_rings) - 1; 1957 + if ((val & mask) == 0) 1958 + return -EINVAL; 1959 + 1960 + for (i = 0; i < adev->gfx.num_compute_rings; ++i) { 1961 + ring = &adev->gfx.compute_ring[i]; 1962 + if (val & (1 << i)) 1963 + ring->sched.ready = true; 1964 + else 1965 + ring->sched.ready = false; 1966 + } 1967 + 1968 + /* publish sched.ready flag update effective immediately across smp */ 1969 + smp_rmb(); 1970 + return 0; 1971 + } 1972 + 1973 + static int amdgpu_debugfs_compute_sched_mask_get(void *data, u64 *val) 1974 + { 1975 + struct amdgpu_device *adev = (struct amdgpu_device *)data; 1976 + u32 i; 1977 + u64 mask = 0; 1978 + struct amdgpu_ring *ring; 1979 + 1980 + if (!adev) 1981 + return -ENODEV; 1982 + for (i = 0; i < adev->gfx.num_compute_rings; ++i) { 1983 + ring = &adev->gfx.compute_ring[i]; 1984 + if (ring->sched.ready) 1985 + mask |= 1 << i; 1986 + } 1987 + 1988 + *val = mask; 1989 + return 0; 1990 + } 1991 + 1992 + DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_compute_sched_mask_fops, 1993 + amdgpu_debugfs_compute_sched_mask_get, 1994 + amdgpu_debugfs_compute_sched_mask_set, "%llx\n"); 1995 + 1996 + #endif 1997 + 1998 + void amdgpu_debugfs_compute_sched_mask_init(struct amdgpu_device *adev) 1999 + { 2000 + #if defined(CONFIG_DEBUG_FS) 2001 + struct drm_minor *minor = adev_to_drm(adev)->primary; 2002 + struct dentry *root = minor->debugfs_root; 2003 + char name[32]; 2004 + 2005 + if (!(adev->gfx.num_compute_rings > 1)) 2006 + return; 2007 + sprintf(name, "amdgpu_compute_sched_mask"); 2008 + debugfs_create_file(name, 0600, root, adev, 2009 + &amdgpu_debugfs_compute_sched_mask_fops); 2010 + #endif 1941 2011 }

+4 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

··· 472 472 struct mutex kfd_sch_mutex; 473 473 u64 kfd_sch_req_count[MAX_XCP]; 474 474 bool kfd_sch_inactive[MAX_XCP]; 475 + unsigned long enforce_isolation_jiffies[MAX_XCP]; 476 + unsigned long enforce_isolation_time[MAX_XCP]; 475 477 }; 476 478 477 479 struct amdgpu_gfx_ras_reg_entry { ··· 579 577 void amdgpu_gfx_cleaner_shader_init(struct amdgpu_device *adev, 580 578 unsigned int cleaner_shader_size, 581 579 const void *cleaner_shader_ptr); 582 - int amdgpu_gfx_sysfs_isolation_shader_init(struct amdgpu_device *adev); 583 - void amdgpu_gfx_sysfs_isolation_shader_fini(struct amdgpu_device *adev); 584 580 void amdgpu_gfx_enforce_isolation_handler(struct work_struct *work); 585 581 void amdgpu_gfx_enforce_isolation_ring_begin_use(struct amdgpu_ring *ring); 586 582 void amdgpu_gfx_enforce_isolation_ring_end_use(struct amdgpu_ring *ring); 583 + void amdgpu_debugfs_gfx_sched_mask_init(struct amdgpu_device *adev); 584 + void amdgpu_debugfs_compute_sched_mask_init(struct amdgpu_device *adev); 587 585 588 586 static inline const char *amdgpu_gfx_compute_mode_desc(int mode) 589 587 {

+2

drivers/gpu/drm/amd/amdgpu/amdgpu_job.c

··· 137 137 /* attempt a per ring reset */ 138 138 if (amdgpu_gpu_recovery && 139 139 ring->funcs->reset) { 140 + dev_err(adev->dev, "Starting %s ring reset\n", s_job->sched->name); 140 141 /* stop the scheduler, but don't mess with the 141 142 * bad job yet because if ring reset fails 142 143 * we'll fall back to full GPU reset. ··· 153 152 drm_sched_start(&ring->sched, 0); 154 153 goto exit; 155 154 } 155 + dev_err(adev->dev, "Ring %s reset failure\n", ring->sched.name); 156 156 } 157 157 158 158 if (amdgpu_device_should_recover_gpu(ring->adev)) {

+20 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c

··· 348 348 return ret; 349 349 } 350 350 351 + static bool amdgpu_mca_bank_should_dump(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, 352 + struct mca_bank_entry *entry) 353 + { 354 + bool ret; 355 + 356 + switch (type) { 357 + case AMDGPU_MCA_ERROR_TYPE_CE: 358 + ret = amdgpu_mca_is_deferred_error(adev, entry->regs[MCA_REG_IDX_STATUS]); 359 + break; 360 + case AMDGPU_MCA_ERROR_TYPE_UE: 361 + default: 362 + ret = true; 363 + break; 364 + } 365 + 366 + return ret; 367 + } 368 + 351 369 static int amdgpu_mca_smu_get_mca_set(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, struct mca_bank_set *mca_set, 352 370 struct ras_query_context *qctx) 353 371 { ··· 391 373 392 374 amdgpu_mca_bank_set_add_entry(mca_set, &entry); 393 375 394 - amdgpu_mca_smu_mca_bank_dump(adev, i, &entry, qctx); 376 + if (amdgpu_mca_bank_should_dump(adev, type, &entry)) 377 + amdgpu_mca_smu_mca_bank_dump(adev, i, &entry, qctx); 395 378 } 396 379 397 380 return 0;

+5

drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c

··· 1594 1594 char ucode_prefix[30]; 1595 1595 char fw_name[50]; 1596 1596 bool need_retry = false; 1597 + u32 *ucode_ptr; 1597 1598 int r; 1598 1599 1599 1600 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, ··· 1632 1631 adev->mes.data_start_addr[pipe] = 1633 1632 le32_to_cpu(mes_hdr->mes_data_start_addr_lo) | 1634 1633 ((uint64_t)(le32_to_cpu(mes_hdr->mes_data_start_addr_hi)) << 32); 1634 + ucode_ptr = (u32 *)(adev->mes.fw[pipe]->data + 1635 + sizeof(union amdgpu_firmware_header)); 1636 + adev->mes.fw_version[pipe] = 1637 + le32_to_cpu(ucode_ptr[24]) & AMDGPU_MES_VERSION_MASK; 1635 1638 1636 1639 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1637 1640 int ucode, ucode_data;

+1

drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h

··· 75 75 76 76 uint32_t sched_version; 77 77 uint32_t kiq_version; 78 + uint32_t fw_version[AMDGPU_MAX_MES_PIPES]; 78 79 bool enable_legacy_queue_map; 79 80 80 81 uint32_t total_max_queue;

+2 -22

drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

··· 40 40 #include "amdgpu_trace.h" 41 41 #include "amdgpu_amdkfd.h" 42 42 #include "amdgpu_vram_mgr.h" 43 + #include "amdgpu_vm.h" 43 44 44 45 /** 45 46 * DOC: amdgpu_object ··· 1209 1208 type = res->mem_type; 1210 1209 } 1211 1210 1212 - /* Squash some into 'cpu' to keep the legacy userspace view. */ 1213 - switch (type) { 1214 - case TTM_PL_VRAM: 1215 - case TTM_PL_TT: 1216 - case TTM_PL_SYSTEM: 1217 - break; 1218 - default: 1219 - type = TTM_PL_SYSTEM; 1220 - break; 1221 - } 1222 - 1223 1211 if (drm_WARN_ON_ONCE(&adev->ddev, type >= sz)) 1224 1212 return; 1225 1213 1226 1214 /* DRM stats common fields: */ 1227 1215 1228 - stats[type].total += size; 1229 1216 if (drm_gem_object_is_shared_for_memory_stats(obj)) 1230 1217 stats[type].drm.shared += size; 1231 1218 else ··· 1226 1237 stats[type].drm.active += size; 1227 1238 else if (bo->flags & AMDGPU_GEM_CREATE_DISCARDABLE) 1228 1239 stats[type].drm.purgeable += size; 1229 - 1230 - if (type == TTM_PL_VRAM && amdgpu_res_cpu_visible(adev, res)) 1231 - stats[type].visible += size; 1232 1240 } 1233 1241 1234 1242 /* amdgpu specific stats: */ 1235 1243 1236 1244 if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) { 1237 1245 stats[TTM_PL_VRAM].requested += size; 1238 - if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 1239 - stats[TTM_PL_VRAM].requested_visible += size; 1240 - 1241 - if (type != TTM_PL_VRAM) { 1246 + if (type != TTM_PL_VRAM) 1242 1247 stats[TTM_PL_VRAM].evicted += size; 1243 - if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 1244 - stats[TTM_PL_VRAM].evicted_visible += size; 1245 - } 1246 1248 } else if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_GTT) { 1247 1249 stats[TTM_PL_TT].requested += size; 1248 1250 }

-11

drivers/gpu/drm/amd/amdgpu/amdgpu_object.h

··· 139 139 struct amdgpu_vm_bo_base entries[]; 140 140 }; 141 141 142 - struct amdgpu_mem_stats { 143 - struct drm_memory_stats drm; 144 - 145 - uint64_t total; 146 - uint64_t visible; 147 - uint64_t evicted; 148 - uint64_t evicted_visible; 149 - uint64_t requested; 150 - uint64_t requested_visible; 151 - }; 152 - 153 142 static inline struct amdgpu_bo *ttm_to_amdgpu_bo(struct ttm_buffer_object *tbo) 154 143 { 155 144 return container_of(tbo, struct amdgpu_bo, tbo);

+37

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

··· 1834 1834 ras_cmd->ras_in_message.init_flags.xcc_mask = 1835 1835 adev->gfx.xcc_mask; 1836 1836 ras_cmd->ras_in_message.init_flags.channel_dis_num = hweight32(adev->gmc.m_half_use) * 2; 1837 + if (adev->gmc.gmc_funcs->query_mem_partition_mode) 1838 + ras_cmd->ras_in_message.init_flags.nps_mode = 1839 + adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 1837 1840 1838 1841 ret = psp_ta_load(psp, &psp->ras_context.context); 1839 1842 ··· 3566 3563 return err; 3567 3564 } 3568 3565 3566 + static bool is_ta_fw_applicable(struct psp_context *psp, 3567 + const struct psp_fw_bin_desc *desc) 3568 + { 3569 + struct amdgpu_device *adev = psp->adev; 3570 + uint32_t fw_version; 3571 + 3572 + switch (desc->fw_type) { 3573 + case TA_FW_TYPE_PSP_XGMI: 3574 + case TA_FW_TYPE_PSP_XGMI_AUX: 3575 + /* for now, AUX TA only exists on 13.0.6 ta bin, 3576 + * from v20.00.0x.14 3577 + */ 3578 + if (amdgpu_ip_version(adev, MP0_HWIP, 0) == 3579 + IP_VERSION(13, 0, 6)) { 3580 + fw_version = le32_to_cpu(desc->fw_version); 3581 + 3582 + if (adev->flags & AMD_IS_APU && 3583 + (fw_version & 0xff) >= 0x14) 3584 + return desc->fw_type == TA_FW_TYPE_PSP_XGMI_AUX; 3585 + else 3586 + return desc->fw_type == TA_FW_TYPE_PSP_XGMI; 3587 + } 3588 + break; 3589 + default: 3590 + break; 3591 + } 3592 + 3593 + return true; 3594 + } 3595 + 3569 3596 static int parse_ta_bin_descriptor(struct psp_context *psp, 3570 3597 const struct psp_fw_bin_desc *desc, 3571 3598 const struct ta_firmware_header_v2_0 *ta_hdr) ··· 3604 3571 3605 3572 if (!psp || !desc || !ta_hdr) 3606 3573 return -EINVAL; 3574 + 3575 + if (!is_ta_fw_applicable(psp, desc)) 3576 + return 0; 3607 3577 3608 3578 ucode_start_addr = (uint8_t *)ta_hdr + 3609 3579 le32_to_cpu(desc->offset_bytes) + ··· 3620 3584 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 3621 3585 break; 3622 3586 case TA_FW_TYPE_PSP_XGMI: 3587 + case TA_FW_TYPE_PSP_XGMI_AUX: 3623 3588 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3624 3589 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3625 3590 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr;

+1

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

··· 2605 2605 reset_context.method = AMD_RESET_METHOD_NONE; 2606 2606 reset_context.reset_req_dev = adev; 2607 2607 reset_context.src = AMDGPU_RESET_SRC_RAS; 2608 + set_bit(AMDGPU_SKIP_COREDUMP, &reset_context.flags); 2608 2609 2609 2610 /* Perform full reset in fatal error mode */ 2610 2611 if (!amdgpu_ras_is_poison_mode_supported(ras->adev))

+3 -7

drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c

··· 109 109 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 110 110 { 111 111 uint32_t occupied, chunk1, chunk2; 112 - uint32_t *dst; 113 112 114 113 occupied = ring->wptr & ring->buf_mask; 115 - dst = (void *)&ring->ring[occupied]; 116 114 chunk1 = ring->buf_mask + 1 - occupied; 117 115 chunk1 = (chunk1 >= count) ? count : chunk1; 118 116 chunk2 = count - chunk1; 119 117 120 118 if (chunk1) 121 - memset32(dst, ring->funcs->nop, chunk1); 119 + memset32(&ring->ring[occupied], ring->funcs->nop, chunk1); 122 120 123 - if (chunk2) { 124 - dst = (void *)ring->ring; 125 - memset32(dst, ring->funcs->nop, chunk2); 126 - } 121 + if (chunk2) 122 + memset32(ring->ring, ring->funcs->nop, chunk2); 127 123 128 124 ring->wptr += count; 129 125 ring->wptr &= ring->ptr_mask;

+4 -7

drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h

··· 246 246 struct drm_gpu_scheduler sched; 247 247 248 248 struct amdgpu_bo *ring_obj; 249 - volatile uint32_t *ring; 249 + uint32_t *ring; 250 250 unsigned rptr_offs; 251 251 u64 rptr_gpu_addr; 252 252 volatile u32 *rptr_cpu_addr; ··· 288 288 u64 cond_exe_gpu_addr; 289 289 volatile u32 *cond_exe_cpu_addr; 290 290 unsigned int set_q_mode_offs; 291 - volatile u32 *set_q_mode_ptr; 291 + u32 *set_q_mode_ptr; 292 292 u64 set_q_mode_token; 293 293 unsigned vm_hub; 294 294 unsigned vm_inv_eng; ··· 386 386 void *src, int count_dw) 387 387 { 388 388 unsigned occupied, chunk1, chunk2; 389 - void *dst; 390 389 391 390 occupied = ring->wptr & ring->buf_mask; 392 - dst = (void *)&ring->ring[occupied]; 393 391 chunk1 = ring->buf_mask + 1 - occupied; 394 392 chunk1 = (chunk1 >= count_dw) ? count_dw : chunk1; 395 393 chunk2 = count_dw - chunk1; ··· 395 397 chunk2 <<= 2; 396 398 397 399 if (chunk1) 398 - memcpy(dst, src, chunk1); 400 + memcpy(&ring->ring[occupied], src, chunk1); 399 401 400 402 if (chunk2) { 401 403 src += chunk1; 402 - dst = (void *)ring->ring; 403 - memcpy(dst, src, chunk2); 404 + memcpy(ring->ring, src, chunk2); 404 405 } 405 406 406 407 ring->wptr += count_dw;

+70

drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c

··· 343 343 344 344 return 0; 345 345 } 346 + 347 + /* 348 + * debugfs for to enable/disable sdma job submission to specific core. 349 + */ 350 + #if defined(CONFIG_DEBUG_FS) 351 + static int amdgpu_debugfs_sdma_sched_mask_set(void *data, u64 val) 352 + { 353 + struct amdgpu_device *adev = (struct amdgpu_device *)data; 354 + u32 i; 355 + u64 mask = 0; 356 + struct amdgpu_ring *ring; 357 + 358 + if (!adev) 359 + return -ENODEV; 360 + 361 + mask = (1 << adev->sdma.num_instances) - 1; 362 + if ((val & mask) == 0) 363 + return -EINVAL; 364 + 365 + for (i = 0; i < adev->sdma.num_instances; ++i) { 366 + ring = &adev->sdma.instance[i].ring; 367 + if (val & (1 << i)) 368 + ring->sched.ready = true; 369 + else 370 + ring->sched.ready = false; 371 + } 372 + /* publish sched.ready flag update effective immediately across smp */ 373 + smp_rmb(); 374 + return 0; 375 + } 376 + 377 + static int amdgpu_debugfs_sdma_sched_mask_get(void *data, u64 *val) 378 + { 379 + struct amdgpu_device *adev = (struct amdgpu_device *)data; 380 + u32 i; 381 + u64 mask = 0; 382 + struct amdgpu_ring *ring; 383 + 384 + if (!adev) 385 + return -ENODEV; 386 + for (i = 0; i < adev->sdma.num_instances; ++i) { 387 + ring = &adev->sdma.instance[i].ring; 388 + if (ring->sched.ready) 389 + mask |= 1 << i; 390 + } 391 + 392 + *val = mask; 393 + return 0; 394 + } 395 + 396 + DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_sdma_sched_mask_fops, 397 + amdgpu_debugfs_sdma_sched_mask_get, 398 + amdgpu_debugfs_sdma_sched_mask_set, "%llx\n"); 399 + 400 + #endif 401 + 402 + void amdgpu_debugfs_sdma_sched_mask_init(struct amdgpu_device *adev) 403 + { 404 + #if defined(CONFIG_DEBUG_FS) 405 + struct drm_minor *minor = adev_to_drm(adev)->primary; 406 + struct dentry *root = minor->debugfs_root; 407 + char name[32]; 408 + 409 + if (!(adev->sdma.num_instances > 1)) 410 + return; 411 + sprintf(name, "amdgpu_sdma_sched_mask"); 412 + debugfs_create_file(name, 0600, root, adev, 413 + &amdgpu_debugfs_sdma_sched_mask_fops); 414 + #endif 415 + }

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h

··· 175 175 void amdgpu_sdma_destroy_inst_ctx(struct amdgpu_device *adev, 176 176 bool duplicate); 177 177 int amdgpu_sdma_ras_sw_init(struct amdgpu_device *adev); 178 - 178 + void amdgpu_debugfs_sdma_sched_mask_init(struct amdgpu_device *adev); 179 179 #endif

+1

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

··· 1851 1851 1852 1852 mutex_init(&adev->mman.gtt_window_lock); 1853 1853 1854 + dma_set_max_seg_size(adev->dev, UINT_MAX); 1854 1855 /* No others user of address space so set it to 0 */ 1855 1856 r = ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev, 1856 1857 adev_to_drm(adev)->anon_inode->i_mapping,

+1

drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h

··· 163 163 TA_FW_TYPE_PSP_DTM, 164 164 TA_FW_TYPE_PSP_RAP, 165 165 TA_FW_TYPE_PSP_SECUREDISPLAY, 166 + TA_FW_TYPE_PSP_XGMI_AUX, 166 167 TA_FW_TYPE_MAX_INDEX, 167 168 }; 168 169

+5 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

··· 1161 1161 int r; 1162 1162 1163 1163 amdgpu_sync_create(&sync); 1164 - if (clear || !bo) { 1164 + if (clear) { 1165 1165 mem = NULL; 1166 1166 1167 1167 /* Implicitly sync to command submissions in the same VM before ··· 1176 1176 if (r) 1177 1177 goto error_free; 1178 1178 } 1179 + } else if (!bo) { 1180 + mem = NULL; 1181 + 1182 + /* PRT map operations don't need to sync to anything. */ 1179 1183 1180 1184 } else { 1181 1185 struct drm_gem_object *obj = &bo->tbo.base;

+10 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h

··· 42 42 struct amdgpu_job; 43 43 struct amdgpu_bo_list_entry; 44 44 struct amdgpu_bo_vm; 45 - struct amdgpu_mem_stats; 46 45 47 46 /* 48 47 * GPUVM handling ··· 319 320 uint32_t status; 320 321 /* which vmhub? gfxhub, mmhub, etc. */ 321 322 unsigned int vmhub; 323 + }; 324 + 325 + struct amdgpu_mem_stats { 326 + struct drm_memory_stats drm; 327 + 328 + /* buffers that requested this placement */ 329 + uint64_t requested; 330 + /* buffers that requested this placement 331 + * but are currently evicted */ 332 + uint64_t evicted; 322 333 }; 323 334 324 335 struct amdgpu_vm {

+1

drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h

··· 77 77 u8 num_res; 78 78 struct amdgpu_xcp_mgr *xcp_mgr; 79 79 struct kobject kobj; 80 + u16 compatible_nps_modes; 80 81 }; 81 82 82 83 struct amdgpu_xcp_ip_funcs {

+12 -1

drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c

··· 455 455 int max_res[AMDGPU_XCP_RES_MAX] = {}; 456 456 bool res_lt_xcp; 457 457 int num_xcp, i; 458 + u16 nps_modes; 458 459 459 460 if (!(xcp_mgr->supp_xcp_modes & BIT(mode))) 460 461 return -EINVAL; ··· 468 467 switch (mode) { 469 468 case AMDGPU_SPX_PARTITION_MODE: 470 469 num_xcp = 1; 470 + nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE); 471 471 break; 472 472 case AMDGPU_DPX_PARTITION_MODE: 473 473 num_xcp = 2; 474 + nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE); 474 475 break; 475 476 case AMDGPU_TPX_PARTITION_MODE: 476 477 num_xcp = 3; 478 + nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) | 479 + BIT(AMDGPU_NPS4_PARTITION_MODE); 477 480 break; 478 481 case AMDGPU_QPX_PARTITION_MODE: 479 482 num_xcp = 4; 483 + nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) | 484 + BIT(AMDGPU_NPS4_PARTITION_MODE); 480 485 break; 481 486 case AMDGPU_CPX_PARTITION_MODE: 482 487 num_xcp = NUM_XCC(adev->gfx.xcc_mask); 488 + nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) | 489 + BIT(AMDGPU_NPS4_PARTITION_MODE); 483 490 break; 484 491 default: 485 492 return -EINVAL; 486 493 } 487 494 495 + xcp_cfg->compatible_nps_modes = 496 + (adev->gmc.supported_nps_modes & nps_modes); 488 497 xcp_cfg->num_res = ARRAY_SIZE(max_res); 489 498 490 499 for (i = 0; i < xcp_cfg->num_res; i++) { ··· 548 537 case AMDGPU_SPX_PARTITION_MODE: 549 538 return adev->gmc.num_mem_partitions == 1 && num_xcc > 0; 550 539 case AMDGPU_DPX_PARTITION_MODE: 551 - return adev->gmc.num_mem_partitions != 8 && (num_xcc % 4) == 0; 540 + return adev->gmc.num_mem_partitions <= 2 && (num_xcc % 4) == 0; 552 541 case AMDGPU_TPX_PARTITION_MODE: 553 542 return (adev->gmc.num_mem_partitions == 1 || 554 543 adev->gmc.num_mem_partitions == 3) &&

+3 -2

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

··· 4853 4853 4854 4854 gfx_v10_0_alloc_ip_dump(adev); 4855 4855 4856 - r = amdgpu_gfx_sysfs_isolation_shader_init(adev); 4856 + r = amdgpu_gfx_sysfs_init(adev); 4857 4857 if (r) 4858 4858 return r; 4859 + 4859 4860 return 0; 4860 4861 } 4861 4862 ··· 4908 4907 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev); 4909 4908 4910 4909 gfx_v10_0_free_microcode(adev); 4911 - amdgpu_gfx_sysfs_isolation_shader_fini(adev); 4910 + amdgpu_gfx_sysfs_fini(adev); 4912 4911 4913 4912 kfree(adev->gfx.ip_dump_core); 4914 4913 kfree(adev->gfx.ip_dump_compute_queues);

+19 -2

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

··· 46 46 #include "clearstate_gfx11.h" 47 47 #include "v11_structs.h" 48 48 #include "gfx_v11_0.h" 49 + #include "gfx_v11_0_cleaner_shader.h" 49 50 #include "gfx_v11_0_3.h" 50 51 #include "nbio_v4_3.h" 51 52 #include "mes_v11_0.h" ··· 1580 1579 } 1581 1580 1582 1581 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1582 + case IP_VERSION(11, 0, 3): 1583 + adev->gfx.cleaner_shader_ptr = gfx_11_0_3_cleaner_shader_hex; 1584 + adev->gfx.cleaner_shader_size = sizeof(gfx_11_0_3_cleaner_shader_hex); 1585 + if (adev->gfx.me_fw_version >= 2280 && 1586 + adev->gfx.pfp_fw_version >= 2370 && 1587 + adev->gfx.mec_fw_version >= 2450 && 1588 + adev->mes.fw_version[0] >= 99) { 1589 + adev->gfx.enable_cleaner_shader = true; 1590 + r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 1591 + if (r) { 1592 + adev->gfx.enable_cleaner_shader = false; 1593 + dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 1594 + } 1595 + } 1596 + break; 1583 1597 default: 1584 1598 adev->gfx.enable_cleaner_shader = false; 1599 + break; 1585 1600 } 1586 1601 1587 1602 /* Enable CG flag in one VF mode for enabling RLC safe mode enter/exit */ ··· 1725 1708 1726 1709 gfx_v11_0_alloc_ip_dump(adev); 1727 1710 1728 - r = amdgpu_gfx_sysfs_isolation_shader_init(adev); 1711 + r = amdgpu_gfx_sysfs_init(adev); 1729 1712 if (r) 1730 1713 return r; 1731 1714 ··· 1790 1773 1791 1774 gfx_v11_0_free_microcode(adev); 1792 1775 1793 - amdgpu_gfx_sysfs_isolation_shader_fini(adev); 1776 + amdgpu_gfx_sysfs_fini(adev); 1794 1777 1795 1778 kfree(adev->gfx.ip_dump_core); 1796 1779 kfree(adev->gfx.ip_dump_compute_queues);

+118

drivers/gpu/drm/amd/amdgpu/gfx_v11_0_3_cleaner_shader.asm

··· 1 + /* SPDX-License-Identifier: MIT */ 2 + /* 3 + * Copyright 2024 Advanced Micro Devices, Inc. 4 + * 5 + * Permission is hereby granted, free of charge, to any person obtaining a 6 + * copy of this software and associated documentation files (the "Software"), 7 + * to deal in the Software without restriction, including without limitation 8 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 + * and/or sell copies of the Software, and to permit persons to whom the 10 + * Software is furnished to do so, subject to the following conditions: 11 + * 12 + * The above copyright notice and this permission notice shall be included in 13 + * all copies or substantial portions of the Software. 14 + * 15 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 + * OTHER DEALINGS IN THE SOFTWARE. 22 + */ 23 + 24 + // This shader is to clean LDS, SGPRs and VGPRs. It is first 64 Dwords or 256 bytes of 192 Dwords cleaner shader. 25 + //To turn this shader program on for complitaion change this to main and lower shader main to main_1 26 + 27 + // Navi3 : Clear SGPRs, VGPRs and LDS 28 + // Launch 32 waves per CU (16 per SIMD) as a workgroup (threadgroup) to fill every wave slot 29 + // Waves are "wave32" and have 64 VGPRs each, which uses all 1024 VGPRs per SIMD 30 + // Waves are launched in "CU" mode, and the workgroup shares 64KB of LDS (half of the WGP's LDS) 31 + // It takes 2 workgroups to use all of LDS: one on each CU of the WGP 32 + // Each wave clears SGPRs 0 - 107 33 + // Each wave clears VGPRs 0 - 63 34 + // The first wave of the workgroup clears its 64KB of LDS 35 + // The shader starts with "S_BARRIER" to ensure SPI has launched all waves of the workgroup 36 + // before any wave in the workgroup could end. Without this, it is possible not all SGPRs get cleared. 37 + 38 + shader main 39 + asic(GFX11) 40 + type(CS) 41 + wave_size(32) 42 + // Note: original source code from SQ team 43 + 44 + // Takes about 2500 clocks to run. 45 + // (theorhetical fastest = 1024clks vgpr + 640lds = 1660 clks) 46 + // 47 + S_BARRIER 48 + 49 + // 50 + // CLEAR VGPRs 51 + // 52 + s_mov_b32 m0, 0x00000058 // Loop 96/8=12 times (loop unrolled for performance) 53 + 54 + label_0005: 55 + v_movreld_b32 v0, 0 56 + v_movreld_b32 v1, 0 57 + v_movreld_b32 v2, 0 58 + v_movreld_b32 v3, 0 59 + v_movreld_b32 v4, 0 60 + v_movreld_b32 v5, 0 61 + v_movreld_b32 v6, 0 62 + v_movreld_b32 v7, 0 63 + s_sub_u32 m0, m0, 8 64 + s_cbranch_scc0 label_0005 65 + // 66 + // 67 + 68 + s_mov_b32 s2, 0x80000000 // Bit31 is first_wave 69 + s_and_b32 s2, s2, s0 // sgpr0 has tg_size (first_wave) term as in ucode only COMPUTE_PGM_RSRC2.tg_size_en is set 70 + s_cbranch_scc0 label_0023 // Clean LDS if its first wave of ThreadGroup/WorkGroup 71 + // CLEAR LDS 72 + // 73 + s_mov_b32 exec_lo, 0xffffffff 74 + s_mov_b32 exec_hi, 0xffffffff 75 + v_mbcnt_lo_u32_b32 v1, exec_hi, 0 // Set V1 to thread-ID (0..63) 76 + v_mbcnt_hi_u32_b32 v1, exec_lo, v1 // Set V1 to thread-ID (0..63) 77 + v_mul_u32_u24 v1, 0x00000008, v1 // * 8, so each thread is a double-dword address (8byte) 78 + s_mov_b32 s2, 0x00000003f // 64 loop iterations 79 + s_mov_b32 m0, 0xffffffff 80 + // Clear all of LDS space 81 + // Each FirstWave of WorkGroup clears 64kbyte block 82 + 83 + label_001F: 84 + ds_write2_b64 v1, v[2:3], v[2:3] offset1:32 85 + ds_write2_b64 v1, v[4:5], v[4:5] offset0:64 offset1:96 86 + v_add_co_u32 v1, vcc, 0x00000400, v1 87 + s_sub_u32 s2, s2, 1 88 + s_cbranch_scc0 label_001F 89 + // 90 + // CLEAR SGPRs 91 + // 92 + label_0023: 93 + s_mov_b32 m0, 0x00000068 // Loop 108/4=27 times (loop unrolled for performance) 94 + label_sgpr_loop: 95 + s_movreld_b32 s0, 0 96 + s_movreld_b32 s1, 0 97 + s_movreld_b32 s2, 0 98 + s_movreld_b32 s3, 0 99 + s_sub_u32 m0, m0, 4 100 + s_cbranch_scc0 label_sgpr_loop 101 + 102 + //clear vcc 103 + s_mov_b64 vcc, 0 //clear vcc 104 + s_mov_b32 flat_scratch_lo, 0 //clear flat scratch lo SGPR 105 + s_mov_b32 flat_scratch_hi, 0 //clear flat scratch hi SGPR 106 + s_mov_b64 ttmp0, 0 //Clear ttmp0 and ttmp1 107 + s_mov_b64 ttmp2, 0 //Clear ttmp2 and ttmp3 108 + s_mov_b64 ttmp4, 0 //Clear ttmp4 and ttmp5 109 + s_mov_b64 ttmp6, 0 //Clear ttmp6 and ttmp7 110 + s_mov_b64 ttmp8, 0 //Clear ttmp8 and ttmp9 111 + s_mov_b64 ttmp10, 0 //Clear ttmp10 and ttmp11 112 + s_mov_b64 ttmp12, 0 //Clear ttmp12 and ttmp13 113 + s_mov_b64 ttmp14, 0 //Clear ttmp14 and ttmp15 114 + 115 + s_endpgm 116 + 117 + end 118 +

+56

drivers/gpu/drm/amd/amdgpu/gfx_v11_0_cleaner_shader.h

··· 1 + /* SPDX-License-Identifier: MIT */ 2 + /* 3 + * Copyright 2024 Advanced Micro Devices, Inc. 4 + * 5 + * Permission is hereby granted, free of charge, to any person obtaining a 6 + * copy of this software and associated documentation files (the "Software"), 7 + * to deal in the Software without restriction, including without limitation 8 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 + * and/or sell copies of the Software, and to permit persons to whom the 10 + * Software is furnished to do so, subject to the following conditions: 11 + * 12 + * The above copyright notice and this permission notice shall be included in 13 + * all copies or substantial portions of the Software. 14 + * 15 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 + * OTHER DEALINGS IN THE SOFTWARE. 22 + */ 23 + 24 + /* Define the cleaner shader gfx_11_0_3 */ 25 + static const u32 gfx_11_0_3_cleaner_shader_hex[] = { 26 + 0xb0804006, 0xbe8200ff, 27 + 0x00000058, 0xbefd0080, 28 + 0x7e008480, 0x7e028480, 29 + 0x7e048480, 0x7e068480, 30 + 0x7e088480, 0x7e0a8480, 31 + 0x7e0c8480, 0x7e0e8480, 32 + 0xbefd0002, 0x80828802, 33 + 0xbfa1fff5, 0xbe8200ff, 34 + 0x80000000, 0x8b020002, 35 + 0xbfa10012, 0xbefe00c1, 36 + 0xbeff00c1, 0xd71f0001, 37 + 0x0001007f, 0xd7200001, 38 + 0x0002027e, 0x16020288, 39 + 0xbe8200bf, 0xbefd00c1, 40 + 0xd9382000, 0x00020201, 41 + 0xd9386040, 0x00040401, 42 + 0xd7006a01, 0x000202ff, 43 + 0x00000400, 0x80828102, 44 + 0xbfa1fff7, 0xbefd00ff, 45 + 0x00000068, 0xbe804280, 46 + 0xbe814280, 0xbe824280, 47 + 0xbe834280, 0x80fd847d, 48 + 0xbfa1fffa, 0xbeea0180, 49 + 0xbeec0180, 0xbeee0180, 50 + 0xbef00180, 0xbef20180, 51 + 0xbef40180, 0xbef60180, 52 + 0xbef80180, 0xbefa0180, 53 + 0xbfb00000, 0xbf9f0000, 54 + 0xbf9f0000, 0xbf9f0000, 55 + 0xbf9f0000, 0xbf9f0000, 56 + };

+2 -2

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

··· 1466 1466 1467 1467 gfx_v12_0_alloc_ip_dump(adev); 1468 1468 1469 - r = amdgpu_gfx_sysfs_isolation_shader_init(adev); 1469 + r = amdgpu_gfx_sysfs_init(adev); 1470 1470 if (r) 1471 1471 return r; 1472 1472 ··· 1529 1529 1530 1530 gfx_v12_0_free_microcode(adev); 1531 1531 1532 - amdgpu_gfx_sysfs_isolation_shader_fini(adev); 1532 + amdgpu_gfx_sysfs_fini(adev); 1533 1533 1534 1534 kfree(adev->gfx.ip_dump_core); 1535 1535 kfree(adev->gfx.ip_dump_compute_queues);

+4 -4

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

··· 2402 2402 2403 2403 gfx_v9_0_alloc_ip_dump(adev); 2404 2404 2405 - r = amdgpu_gfx_sysfs_isolation_shader_init(adev); 2405 + r = amdgpu_gfx_sysfs_init(adev); 2406 2406 if (r) 2407 2407 return r; 2408 2408 ··· 2443 2443 } 2444 2444 gfx_v9_0_free_microcode(adev); 2445 2445 2446 - amdgpu_gfx_sysfs_isolation_shader_fini(adev); 2446 + amdgpu_gfx_sysfs_fini(adev); 2447 2447 2448 2448 kfree(adev->gfx.ip_dump_core); 2449 2449 kfree(adev->gfx.ip_dump_compute_queues); ··· 3288 3288 * confirmed that the APU gfx10/gfx11 needn't such update. 3289 3289 */ 3290 3290 if (adev->flags & AMD_IS_APU && 3291 - adev->in_s3 && !adev->suspend_complete) { 3292 - DRM_INFO(" Will skip the CSB packet resubmit\n"); 3291 + adev->in_s3 && !pm_resume_via_firmware()) { 3292 + DRM_INFO("Will skip the CSB packet resubmit\n"); 3293 3293 return 0; 3294 3294 } 3295 3295 r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3);

-5

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

··· 1171 1171 1172 1172 gfx_v9_4_3_alloc_ip_dump(adev); 1173 1173 1174 - r = amdgpu_gfx_sysfs_isolation_shader_init(adev); 1175 - if (r) 1176 - return r; 1177 - 1178 1174 return 0; 1179 1175 } 1180 1176 ··· 1195 1199 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); 1196 1200 gfx_v9_4_3_free_microcode(adev); 1197 1201 amdgpu_gfx_sysfs_fini(adev); 1198 - amdgpu_gfx_sysfs_isolation_shader_fini(adev); 1199 1202 1200 1203 kfree(adev->gfx.ip_dump_core); 1201 1204 kfree(adev->gfx.ip_dump_compute_queues);

+14 -14

drivers/gpu/drm/amd/amdgpu/soc15.c

··· 578 578 579 579 static bool soc15_need_reset_on_resume(struct amdgpu_device *adev) 580 580 { 581 - u32 sol_reg; 582 - 583 - sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 584 - 585 581 /* Will reset for the following suspend abort cases. 586 - * 1) Only reset limit on APU side, dGPU hasn't checked yet. 587 - * 2) S3 suspend abort and TOS already launched. 582 + * 1) Only reset on APU side, dGPU hasn't checked yet. 583 + * 2) S3 suspend aborted in the normal S3 suspend or 584 + * performing pm core test. 588 585 */ 589 586 if (adev->flags & AMD_IS_APU && adev->in_s3 && 590 - sol_reg) { 591 - adev->suspend_complete = false; 587 + !pm_resume_via_firmware()) 592 588 return true; 593 - } else { 594 - adev->suspend_complete = true; 589 + else 595 590 return false; 596 - } 597 591 } 598 592 599 593 static int soc15_asic_reset(struct amdgpu_device *adev) ··· 597 603 * successfully. So now, temporarily enable it for the 598 604 * S3 suspend abort case. 599 605 */ 600 - if (((adev->apu_flags & AMD_APU_IS_RAVEN) || 601 - (adev->apu_flags & AMD_APU_IS_RAVEN2)) && 602 - !soc15_need_reset_on_resume(adev)) 606 + 607 + if ((adev->apu_flags & AMD_APU_IS_PICASSO || 608 + !(adev->apu_flags & AMD_APU_IS_RAVEN)) && 609 + soc15_need_reset_on_resume(adev)) 610 + goto asic_reset; 611 + 612 + if ((adev->apu_flags & AMD_APU_IS_RAVEN) || 613 + (adev->apu_flags & AMD_APU_IS_RAVEN2)) 603 614 return 0; 604 615 616 + asic_reset: 605 617 switch (soc15_asic_reset_method(adev)) { 606 618 case AMD_RESET_METHOD_PCI: 607 619 dev_info(adev->dev, "PCI reset\n");

+3 -2

drivers/gpu/drm/amd/amdgpu/soc21.c

··· 897 897 /* Will reset for the following suspend abort cases. 898 898 * 1) Only reset dGPU side. 899 899 * 2) S3 suspend got aborted and TOS is active. 900 + * As for dGPU suspend abort cases the SOL value 901 + * will be kept as zero at this resume point. 900 902 */ 901 - if (!(adev->flags & AMD_IS_APU) && adev->in_s3 && 902 - !adev->suspend_complete) { 903 + if (!(adev->flags & AMD_IS_APU) && adev->in_s3) { 903 904 sol_reg1 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 904 905 msleep(100); 905 906 sol_reg2 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);

+9

drivers/gpu/drm/amd/amdgpu/ta_ras_if.h

··· 113 113 TA_RAS_PA_TO_MCA, 114 114 }; 115 115 116 + enum ta_ras_nps_mode { 117 + TA_RAS_UNKNOWN_MODE = 0, 118 + TA_RAS_NPS1_MODE = 1, 119 + TA_RAS_NPS2_MODE = 2, 120 + TA_RAS_NPS4_MODE = 4, 121 + TA_RAS_NPS8_MODE = 8, 122 + }; 123 + 116 124 /* Input/output structures for RAS commands */ 117 125 /**********************************************************/ 118 126 ··· 147 139 uint8_t dgpu_mode; 148 140 uint16_t xcc_mask; 149 141 uint8_t channel_dis_num; 142 + uint8_t nps_mode; 150 143 }; 151 144 152 145 struct ta_ras_mca_addr {

+25

drivers/gpu/drm/amd/amdkfd/kfd_device.c

··· 1392 1392 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1393 1393 } 1394 1394 1395 + static bool kfd_compute_active(struct kfd_node *node) 1396 + { 1397 + if (atomic_read(&node->kfd->compute_profile)) 1398 + return true; 1399 + return false; 1400 + } 1401 + 1395 1402 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 1396 1403 { 1397 1404 /* ··· 1490 1483 1491 1484 node = kfd->nodes[node_id]; 1492 1485 return node->dqm->ops.halt(node->dqm); 1486 + } 1487 + 1488 + bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id) 1489 + { 1490 + struct kfd_node *node; 1491 + 1492 + if (!kfd->init_complete) 1493 + return false; 1494 + 1495 + if (node_id >= kfd->num_nodes) { 1496 + dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n", 1497 + node_id, kfd->num_nodes - 1); 1498 + return false; 1499 + } 1500 + 1501 + node = kfd->nodes[node_id]; 1502 + 1503 + return kfd_compute_active(node); 1493 1504 } 1494 1505 1495 1506 #if defined(CONFIG_DEBUG_FS)

+6 -3

drivers/gpu/drm/amd/amdkfd/kfd_process.c

··· 271 271 struct kfd_process *proc = NULL; 272 272 struct kfd_process_device *pdd = NULL; 273 273 int i; 274 - struct kfd_cu_occupancy cu_occupancy[AMDGPU_MAX_QUEUES]; 274 + struct kfd_cu_occupancy *cu_occupancy; 275 275 u32 queue_format; 276 - 277 - memset(cu_occupancy, 0x0, sizeof(cu_occupancy)); 278 276 279 277 pdd = container_of(attr, struct kfd_process_device, attr_cu_occupancy); 280 278 dev = pdd->dev; ··· 290 292 /* Collect wave count from device if it supports */ 291 293 wave_cnt = 0; 292 294 max_waves_per_cu = 0; 295 + 296 + cu_occupancy = kcalloc(AMDGPU_MAX_QUEUES, sizeof(*cu_occupancy), GFP_KERNEL); 297 + if (!cu_occupancy) 298 + return -ENOMEM; 293 299 294 300 /* 295 301 * For GFX 9.4.3, fetch the CU occupancy from the first XCC in the partition. ··· 320 318 321 319 /* Translate wave count to number of compute units */ 322 320 cu_cnt = (wave_cnt + (max_waves_per_cu - 1)) / max_waves_per_cu; 321 + kfree(cu_occupancy); 323 322 return snprintf(buffer, PAGE_SIZE, "%d\n", cu_cnt); 324 323 } 325 324

+2

drivers/gpu/drm/amd/amdkfd/kfd_topology.c

··· 1998 1998 if (KFD_GC_VERSION(dev->gpu) >= IP_VERSION(9, 4, 2)) 1999 1999 dev->node_props.capability |= 2000 2000 HSA_CAP_TRAP_DEBUG_PRECISE_MEMORY_OPERATIONS_SUPPORTED; 2001 + 2002 + dev->node_props.capability |= HSA_CAP_PER_QUEUE_RESET_SUPPORTED; 2001 2003 } else { 2002 2004 dev->node_props.debug_prop |= HSA_DBG_WATCH_ADDR_MASK_LO_BIT_GFX10 | 2003 2005 HSA_DBG_WATCH_ADDR_MASK_HI_BIT;

+39 -18

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

··· 3170 3170 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state); 3171 3171 enum dc_connection_type new_connection_type = dc_connection_none; 3172 3172 struct dc_state *dc_state; 3173 - int i, r, j, ret; 3174 - bool need_hotplug = false; 3173 + int i, r, j; 3175 3174 struct dc_commit_streams_params commit_params = {}; 3176 3175 3177 3176 if (dm->dc->caps.ips_support) { ··· 3359 3360 aconnector->mst_root) 3360 3361 continue; 3361 3362 3362 - ret = drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr, true); 3363 - 3364 - if (ret < 0) { 3365 - dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx, 3366 - aconnector->dc_link); 3367 - need_hotplug = true; 3368 - } 3363 + drm_dp_mst_topology_queue_probe(&aconnector->mst_mgr); 3369 3364 } 3370 3365 drm_connector_list_iter_end(&iter); 3371 - 3372 - if (need_hotplug) 3373 - drm_kms_helper_hotplug_event(ddev); 3374 3366 3375 3367 amdgpu_dm_irq_resume_late(adev); 3376 3368 3377 3369 amdgpu_dm_smu_write_watermarks_table(adev); 3370 + 3371 + drm_kms_helper_hotplug_event(ddev); 3378 3372 3379 3373 return 0; 3380 3374 } ··· 4640 4648 if (!rc) 4641 4649 DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx); 4642 4650 } else { 4643 - rc = dc_link_set_backlight_level(link, brightness, 0); 4651 + struct set_backlight_level_params backlight_level_params = { 0 }; 4652 + 4653 + backlight_level_params.backlight_pwm_u16_16 = brightness; 4654 + backlight_level_params.transition_time_in_ms = 0; 4655 + 4656 + rc = dc_link_set_backlight_level(link, &backlight_level_params); 4644 4657 if (!rc) 4645 4658 DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx); 4646 4659 } ··· 7323 7326 const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL; 7324 7327 int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8; 7325 7328 enum dc_status dc_result = DC_OK; 7329 + uint8_t bpc_limit = 6; 7326 7330 7327 7331 if (!dm_state) 7328 7332 return NULL; 7333 + 7334 + if (aconnector->dc_link->connector_signal == SIGNAL_TYPE_HDMI_TYPE_A || 7335 + aconnector->dc_link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) 7336 + bpc_limit = 8; 7329 7337 7330 7338 do { 7331 7339 stream = create_stream_for_sink(connector, drm_mode, ··· 7352 7350 dc_result = dm_validate_stream_and_context(adev->dm.dc, stream); 7353 7351 7354 7352 if (dc_result != DC_OK) { 7355 - DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n", 7353 + DRM_DEBUG_KMS("Mode %dx%d (clk %d) pixel_encoding:%s color_depth:%s failed validation -- %s\n", 7356 7354 drm_mode->hdisplay, 7357 7355 drm_mode->vdisplay, 7358 7356 drm_mode->clock, 7359 - dc_result, 7357 + dc_pixel_encoding_to_str(stream->timing.pixel_encoding), 7358 + dc_color_depth_to_str(stream->timing.display_color_depth), 7360 7359 dc_status_to_str(dc_result)); 7361 7360 7362 7361 dc_stream_release(stream); ··· 7365 7362 requested_bpc -= 2; /* lower bpc to retry validation */ 7366 7363 } 7367 7364 7368 - } while (stream == NULL && requested_bpc >= 6); 7365 + } while (stream == NULL && requested_bpc >= bpc_limit); 7369 7366 7370 - if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) { 7371 - DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n"); 7367 + if ((dc_result == DC_FAIL_ENC_VALIDATE || 7368 + dc_result == DC_EXCEED_DONGLE_CAP) && 7369 + !aconnector->force_yuv420_output) { 7370 + DRM_DEBUG_KMS("%s:%d Retry forcing yuv420 encoding\n", 7371 + __func__, __LINE__); 7372 7372 7373 7373 aconnector->force_yuv420_output = true; 7374 7374 stream = create_validate_stream_for_sink(aconnector, drm_mode, ··· 9448 9442 bool mode_set_reset_required = false; 9449 9443 u32 i; 9450 9444 struct dc_commit_streams_params params = {dc_state->streams, dc_state->stream_count}; 9445 + bool set_backlight_level = false; 9451 9446 9452 9447 /* Disable writeback */ 9453 9448 for_each_old_connector_in_state(state, connector, old_con_state, i) { ··· 9568 9561 acrtc->hw_mode = new_crtc_state->mode; 9569 9562 crtc->hwmode = new_crtc_state->mode; 9570 9563 mode_set_reset_required = true; 9564 + set_backlight_level = true; 9571 9565 } else if (modereset_required(new_crtc_state)) { 9572 9566 drm_dbg_atomic(dev, 9573 9567 "Atomic commit: RESET. crtc id %d:[%p]\n", ··· 9618 9610 dm_new_crtc_state->stream, acrtc); 9619 9611 else 9620 9612 acrtc->otg_inst = status->primary_otg_inst; 9613 + } 9614 + } 9615 + 9616 + /* During boot up and resume the DC layer will reset the panel brightness 9617 + * to fix a flicker issue. 9618 + * It will cause the dm->actual_brightness is not the current panel brightness 9619 + * level. (the dm->brightness is the correct panel level) 9620 + * So we set the backlight level with dm->brightness value after set mode 9621 + */ 9622 + if (set_backlight_level) { 9623 + for (i = 0; i < dm->num_of_edps; i++) { 9624 + if (dm->backlight_dev[i]) 9625 + amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); 9621 9626 } 9622 9627 } 9623 9628 }

+3 -7

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

··· 35 35 #include "amdgpu_dm_trace.h" 36 36 #include "amdgpu_dm_debugfs.h" 37 37 38 - #define HPD_DETECTION_PERIOD_uS 5000000 38 + #define HPD_DETECTION_PERIOD_uS 2000000 39 39 #define HPD_DETECTION_TIME_uS 100000 40 40 41 41 void amdgpu_dm_crtc_handle_vblank(struct amdgpu_crtc *acrtc) ··· 252 252 else if (dm->active_vblank_irq_count) 253 253 dm->active_vblank_irq_count--; 254 254 255 - if (dm->active_vblank_irq_count > 0) { 256 - DRM_DEBUG_KMS("Allow idle optimizations (MALL): false\n"); 255 + if (dm->active_vblank_irq_count > 0) 257 256 dc_allow_idle_optimizations(dm->dc, false); 258 - } 259 257 260 258 /* 261 259 * Control PSR based on vblank requirements from OS ··· 272 274 vblank_work->stream->link->replay_settings.replay_feature_enabled); 273 275 } 274 276 275 - if (dm->active_vblank_irq_count == 0) { 276 - DRM_DEBUG_KMS("Allow idle optimizations (MALL): true\n"); 277 + if (dm->active_vblank_irq_count == 0) 277 278 dc_allow_idle_optimizations(dm->dc, true); 278 - } 279 279 280 280 mutex_unlock(&dm->dc_lock); 281 281

+3 -1

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

··· 3127 3127 struct atom_data_revision revision; 3128 3128 3129 3129 // vram info moved to umc_info for DCN4x 3130 - if (info && DATA_TABLES(umc_info)) { 3130 + if (dcb->ctx->dce_version >= DCN_VERSION_4_01 && 3131 + dcb->ctx->dce_version < DCN_VERSION_MAX && 3132 + info && DATA_TABLES(umc_info)) { 3131 3133 header = GET_IMAGE(struct atom_common_table_header, 3132 3134 DATA_TABLES(umc_info)); 3133 3135

+3 -2

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

··· 50 50 #include "link.h" 51 51 52 52 #include "logger_types.h" 53 + 54 + 55 + #include "yellow_carp_offset.h" 53 56 #undef DC_LOGGER 54 57 #define DC_LOGGER \ 55 58 clk_mgr->base.base.ctx->logger 56 - 57 - #include "yellow_carp_offset.h" 58 59 59 60 #define regCLK1_CLK_PLL_REQ 0x0237 60 61 #define regCLK1_CLK_PLL_REQ_BASE_IDX 0

+3 -3

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

··· 53 53 54 54 55 55 #include "logger_types.h" 56 - #undef DC_LOGGER 57 - #define DC_LOGGER \ 58 - clk_mgr->base.base.ctx->logger 59 56 60 57 61 58 #define MAX_INSTANCE 7 ··· 74 77 { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0, 0, 0 } }, 75 78 { { 0x0001B400, 0x0242E000, 0, 0, 0, 0, 0, 0 } } } }; 76 79 80 + #undef DC_LOGGER 81 + #define DC_LOGGER \ 82 + clk_mgr->base.base.ctx->logger 77 83 #define regCLK1_CLK_PLL_REQ 0x0237 78 84 #define regCLK1_CLK_PLL_REQ_BASE_IDX 0 79 85

+19 -6

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

··· 55 55 #define DC_LOGGER \ 56 56 clk_mgr->base.base.ctx->logger 57 57 58 + 58 59 #define regCLK1_CLK_PLL_REQ 0x0237 59 60 #define regCLK1_CLK_PLL_REQ_BASE_IDX 0 60 61 ··· 133 132 for (i = 0; i < dc->res_pool->pipe_count; ++i) { 134 133 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 135 134 struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i]; 135 + struct clk_mgr_internal *clk_mgr_internal = TO_CLK_MGR_INTERNAL(clk_mgr_base); 136 + struct dccg *dccg = clk_mgr_internal->dccg; 136 137 struct pipe_ctx *pipe = safe_to_lower 137 138 ? &context->res_ctx.pipe_ctx[i] 138 139 : &dc->current_state->res_ctx.pipe_ctx[i]; ··· 151 148 new_pipe->stream_res.stream_enc && 152 149 new_pipe->stream_res.stream_enc->funcs->is_fifo_enabled && 153 150 new_pipe->stream_res.stream_enc->funcs->is_fifo_enabled(new_pipe->stream_res.stream_enc); 154 - if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal) || 155 - !pipe->stream->link_enc) && !stream_changed_otg_dig_on) { 151 + 152 + bool has_active_hpo = false; 153 + 154 + if (old_pipe->stream && new_pipe->stream && old_pipe->stream == new_pipe->stream) { 155 + has_active_hpo = dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(old_pipe) && 156 + dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(new_pipe); 157 + 158 + } 159 + 160 + 161 + if (!has_active_hpo && !dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe) && 162 + (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal) || 163 + !pipe->stream->link_enc) && !stream_changed_otg_dig_on)) { 164 + 165 + 156 166 /* This w/a should not trigger when we have a dig active */ 157 167 if (disable) { 158 168 if (pipe->stream_res.tg && pipe->stream_res.tg->funcs->immediate_disable_crtc) ··· 993 977 static bool dcn35_is_ips_supported(struct clk_mgr *clk_mgr_base) 994 978 { 995 979 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 996 - bool ips_supported = true; 997 980 998 - ips_supported = dcn35_smu_get_ips_supported(clk_mgr) ? true : false; 999 - 1000 - return ips_supported; 981 + return dcn35_smu_get_ips_supported(clk_mgr) ? true : false; 1001 982 } 1002 983 1003 984 static void dcn35_init_clocks_fpga(struct clk_mgr *clk_mgr)

+10 -3

drivers/gpu/drm/amd/display/dc/core/dc.c

··· 3835 3835 dc_exit_ips_for_hw_access(dc); 3836 3836 3837 3837 dc_z10_restore(dc); 3838 - if (update_type == UPDATE_TYPE_FULL) 3838 + if (update_type == UPDATE_TYPE_FULL && dc->optimized_required) 3839 3839 hwss_process_outstanding_hw_updates(dc, dc->current_state); 3840 3840 3841 3841 for (i = 0; i < dc->res_pool->pipe_count; i++) { ··· 3861 3861 3862 3862 context_clock_trace(dc, context); 3863 3863 } 3864 + 3865 + if (update_type == UPDATE_TYPE_FULL) 3866 + hwss_wait_for_outstanding_hw_updates(dc, dc->current_state); 3864 3867 3865 3868 top_pipe_to_program = resource_get_otg_master_for_stream( 3866 3869 &context->res_ctx, ··· 5432 5429 5433 5430 void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, char const *caller_name) 5434 5431 { 5435 - if (dc->debug.disable_idle_power_optimizations) 5432 + if (dc->debug.disable_idle_power_optimizations) { 5433 + DC_LOG_DEBUG("%s: disabled\n", __func__); 5436 5434 return; 5435 + } 5437 5436 5438 5437 if (allow != dc->idle_optimizations_allowed) 5439 5438 DC_LOG_IPS("%s: allow_idle old=%d new=%d (caller=%s)\n", __func__, ··· 5452 5447 return; 5453 5448 5454 5449 if (dc->hwss.apply_idle_power_optimizations && dc->clk_mgr != NULL && 5455 - dc->hwss.apply_idle_power_optimizations(dc, allow)) 5450 + dc->hwss.apply_idle_power_optimizations(dc, allow)) { 5456 5451 dc->idle_optimizations_allowed = allow; 5452 + DC_LOG_DEBUG("%s: %s\n", __func__, allow ? "enabled" : "disabled"); 5453 + } 5457 5454 } 5458 5455 5459 5456 void dc_exit_ips_for_hw_access_internal(struct dc *dc, const char *caller_name)

+40 -42

drivers/gpu/drm/amd/display/dc/core/dc_debug.c

··· 46 46 DC_LOG_IF_TRACE(__VA_ARGS__); \ 47 47 } while (0) 48 48 49 - #define TIMING_TRACE(...) do {\ 50 - if (dc->debug.timing_trace) \ 51 - DC_LOG_SYNC(__VA_ARGS__); \ 52 - } while (0) 53 - 54 49 #define CLOCK_TRACE(...) do {\ 55 50 if (dc->debug.clock_trace) \ 56 51 DC_LOG_BANDWIDTH_CALCS(__VA_ARGS__); \ ··· 301 306 302 307 } 303 308 304 - void context_timing_trace( 305 - struct dc *dc, 306 - struct resource_context *res_ctx) 307 - { 308 - int i; 309 - int h_pos[MAX_PIPES] = {0}, v_pos[MAX_PIPES] = {0}; 310 - struct crtc_position position; 311 - unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 312 - DC_LOGGER_INIT(dc->ctx->logger); 313 - 314 - 315 - for (i = 0; i < dc->res_pool->pipe_count; i++) { 316 - struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 317 - /* get_position() returns CRTC vertical/horizontal counter 318 - * hence not applicable for underlay pipe 319 - */ 320 - if (pipe_ctx->stream == NULL || pipe_ctx->pipe_idx == underlay_idx) 321 - continue; 322 - 323 - pipe_ctx->stream_res.tg->funcs->get_position(pipe_ctx->stream_res.tg, &position); 324 - h_pos[i] = position.horizontal_count; 325 - v_pos[i] = position.vertical_count; 326 - } 327 - for (i = 0; i < dc->res_pool->pipe_count; i++) { 328 - struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 329 - 330 - if (pipe_ctx->stream == NULL || pipe_ctx->pipe_idx == underlay_idx) 331 - continue; 332 - 333 - TIMING_TRACE("OTG_%d H_tot:%d V_tot:%d H_pos:%d V_pos:%d\n", 334 - pipe_ctx->stream_res.tg->inst, 335 - pipe_ctx->stream->timing.h_total, 336 - pipe_ctx->stream->timing.v_total, 337 - h_pos[i], v_pos[i]); 338 - } 339 - } 340 - 341 309 void context_clock_trace( 342 310 struct dc *dc, 343 311 struct dc_state *context) ··· 391 433 } 392 434 393 435 return "Unexpected status error"; 436 + } 437 + 438 + char *dc_pixel_encoding_to_str(enum dc_pixel_encoding pixel_encoding) 439 + { 440 + switch (pixel_encoding) { 441 + case PIXEL_ENCODING_RGB: 442 + return "RGB"; 443 + case PIXEL_ENCODING_YCBCR422: 444 + return "YUV422"; 445 + case PIXEL_ENCODING_YCBCR444: 446 + return "YUV444"; 447 + case PIXEL_ENCODING_YCBCR420: 448 + return "YUV420"; 449 + default: 450 + return "Unknown"; 451 + } 452 + } 453 + 454 + char *dc_color_depth_to_str(enum dc_color_depth color_depth) 455 + { 456 + switch (color_depth) { 457 + case COLOR_DEPTH_666: 458 + return "6-bpc"; 459 + case COLOR_DEPTH_888: 460 + return "8-bpc"; 461 + case COLOR_DEPTH_101010: 462 + return "10-bpc"; 463 + case COLOR_DEPTH_121212: 464 + return "12-bpc"; 465 + case COLOR_DEPTH_141414: 466 + return "14-bpc"; 467 + case COLOR_DEPTH_161616: 468 + return "16-bpc"; 469 + case COLOR_DEPTH_999: 470 + return "9-bpc"; 471 + case COLOR_DEPTH_111111: 472 + return "11-bpc"; 473 + default: 474 + return "Unknown"; 475 + } 394 476 }

+2 -2

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

··· 312 312 { 313 313 const struct tg_color pipe_colors[6] = { 314 314 {MAX_TG_COLOR_VALUE, 0, 0}, /* red */ 315 - {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE / 4, 0}, /* orange */ 316 315 {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE, 0}, /* yellow */ 317 316 {0, MAX_TG_COLOR_VALUE, 0}, /* green */ 317 + {0, MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE}, /* cyan */ 318 318 {0, 0, MAX_TG_COLOR_VALUE}, /* blue */ 319 - {MAX_TG_COLOR_VALUE / 2, 0, MAX_TG_COLOR_VALUE / 2}, /* purple */ 319 + {MAX_TG_COLOR_VALUE, 0, MAX_TG_COLOR_VALUE}, /* magenta */ 320 320 }; 321 321 322 322 struct pipe_ctx *top_pipe = pipe_ctx;

+2 -3

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

··· 430 430 } 431 431 432 432 bool dc_link_set_backlight_level(const struct dc_link *link, 433 - uint32_t backlight_pwm_u16_16, 434 - uint32_t frame_ramp) 433 + struct set_backlight_level_params *backlight_level_params) 435 434 { 436 435 return link->dc->link_srv->edp_set_backlight_level(link, 437 - backlight_pwm_u16_16, frame_ramp); 436 + backlight_level_params); 438 437 } 439 438 440 439 bool dc_link_set_backlight_level_nits(struct dc_link *link,

+6 -4

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

··· 292 292 * 2. If not subvp high refresh, for single display cases, if resolution is >= 5K and refresh rate < 120hz 293 293 * 3. If not subvp high refresh, for multi display cases, if resolution is >= 4K and refresh rate < 120hz 294 294 */ 295 - if (dc->debug.allow_sw_cursor_fallback && attributes->height * attributes->width * 4 > 16384) { 295 + if (dc->debug.allow_sw_cursor_fallback && 296 + attributes->height * attributes->width * 4 > 16384 && 297 + !stream->hw_cursor_req) { 296 298 if (check_subvp_sw_cursor_fallback_req(dc, stream)) 297 299 return false; 298 300 } ··· 812 810 stream->dst.height, 813 811 stream->output_color_space); 814 812 DC_LOG_DC( 815 - "\tpix_clk_khz: %d, h_total: %d, v_total: %d, pixelencoder:%d, displaycolorDepth:%d\n", 813 + "\tpix_clk_khz: %d, h_total: %d, v_total: %d, pixel_encoding:%s, color_depth:%s\n", 816 814 stream->timing.pix_clk_100hz / 10, 817 815 stream->timing.h_total, 818 816 stream->timing.v_total, 819 - stream->timing.pixel_encoding, 820 - stream->timing.display_color_depth); 817 + dc_pixel_encoding_to_str(stream->timing.pixel_encoding), 818 + dc_color_depth_to_str(stream->timing.display_color_depth)); 821 819 DC_LOG_DC( 822 820 "\tlink: %d\n", 823 821 stream->link->link_index);

+4 -4

drivers/gpu/drm/amd/display/dc/dc.h

··· 55 55 struct set_config_cmd_payload; 56 56 struct dmub_notification; 57 57 58 - #define DC_VER "3.2.306" 58 + #define DC_VER "3.2.308" 59 59 60 60 #define MAX_SURFACES 3 61 61 #define MAX_PLANES 6 ··· 225 225 bool subvp_psr; 226 226 bool gecc_enable; 227 227 uint8_t fams_ver; 228 + bool aux_backlight_support; 228 229 }; 229 230 230 231 struct dc_scl_caps { ··· 869 868 bool sanity_checks; 870 869 bool max_disp_clk; 871 870 bool surface_trace; 872 - bool timing_trace; 873 871 bool clock_trace; 874 872 bool validation_trace; 875 873 bool bandwidth_calcs_trace; ··· 1067 1067 unsigned int sharpen_policy; 1068 1068 unsigned int scale_to_sharpness_policy; 1069 1069 bool skip_full_updated_if_possible; 1070 + unsigned int enable_oled_edp_power_up_opt; 1070 1071 }; 1071 1072 1072 1073 ··· 2211 2210 * and 16 bit fractional, where 1.0 is max backlight value. 2212 2211 */ 2213 2212 bool dc_link_set_backlight_level(const struct dc_link *dc_link, 2214 - uint32_t backlight_pwm_u16_16, 2215 - uint32_t frame_ramp); 2213 + struct set_backlight_level_params *backlight_level_params); 2216 2214 2217 2215 /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */ 2218 2216 bool dc_link_set_backlight_level_nits(struct dc_link *link,

-1

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

··· 1013 1013 r2 = test_pipe->plane_res.scl_data.recout; 1014 1014 r2_r = r2.x + r2.width; 1015 1015 r2_b = r2.y + r2.height; 1016 - split_pipe = test_pipe; 1017 1016 1018 1017 /** 1019 1018 * There is another half plane on same layer because of

+7 -7

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

··· 8 8 #include "dcn32/dcn32_dpp.h" 9 9 #include "dcn401/dcn401_dpp.h" 10 10 11 - static struct spl_funcs dcn2_spl_funcs = { 11 + static struct spl_callbacks dcn2_spl_callbacks = { 12 12 .spl_calc_lb_num_partitions = dscl2_spl_calc_lb_num_partitions, 13 13 }; 14 - static struct spl_funcs dcn32_spl_funcs = { 14 + static struct spl_callbacks dcn32_spl_callbacks = { 15 15 .spl_calc_lb_num_partitions = dscl32_spl_calc_lb_num_partitions, 16 16 }; 17 - static struct spl_funcs dcn401_spl_funcs = { 17 + static struct spl_callbacks dcn401_spl_callbacks = { 18 18 .spl_calc_lb_num_partitions = dscl401_spl_calc_lb_num_partitions, 19 19 }; 20 20 static void populate_splrect_from_rect(struct spl_rect *spl_rect, const struct rect *rect) ··· 77 77 // This is used to determine the vtap support 78 78 switch (plane_state->ctx->dce_version) { 79 79 case DCN_VERSION_2_0: 80 - spl_in->funcs = &dcn2_spl_funcs; 80 + spl_in->callbacks = dcn2_spl_callbacks; 81 81 break; 82 82 case DCN_VERSION_3_2: 83 - spl_in->funcs = &dcn32_spl_funcs; 83 + spl_in->callbacks = dcn32_spl_callbacks; 84 84 break; 85 85 case DCN_VERSION_4_01: 86 - spl_in->funcs = &dcn401_spl_funcs; 86 + spl_in->callbacks = dcn401_spl_callbacks; 87 87 break; 88 88 default: 89 - spl_in->funcs = &dcn2_spl_funcs; 89 + spl_in->callbacks = dcn2_spl_callbacks; 90 90 } 91 91 // Make format field from spl_in point to plane_res scl_data format 92 92 spl_in->basic_in.format = (enum spl_pixel_format)pipe_ctx->plane_res.scl_data.format;

+28

drivers/gpu/drm/amd/display/dc/dc_types.h

··· 180 180 unsigned int remove_sink_ext_caps; 181 181 unsigned int disable_colorimetry; 182 182 uint8_t blankstream_before_otg_off; 183 + bool oled_optimize_display_on; 183 184 }; 184 185 185 186 struct dc_edid_caps { ··· 1301 1300 struct dc_stream_state **streams; 1302 1301 uint8_t stream_count; 1303 1302 enum dc_power_source_type power_source; 1303 + }; 1304 + 1305 + struct set_backlight_level_params { 1306 + /* backlight in pwm */ 1307 + uint32_t backlight_pwm_u16_16; 1308 + /* brightness ramping */ 1309 + uint32_t frame_ramp; 1310 + /* backlight control type 1311 + * 0: PWM backlight control 1312 + * 1: VESA AUX backlight control 1313 + * 2: AMD AUX backlight control 1314 + */ 1315 + enum backlight_control_type control_type; 1316 + /* backlight in millinits */ 1317 + uint32_t backlight_millinits; 1318 + /* transition time in ms */ 1319 + uint32_t transition_time_in_ms; 1320 + /* minimum luminance in nits */ 1321 + uint32_t min_luminance; 1322 + /* maximum luminance in nits */ 1323 + uint32_t max_luminance; 1324 + /* minimum backlight in pwm */ 1325 + uint32_t min_backlight_pwm; 1326 + /* maximum backlight in pwm */ 1327 + uint32_t max_backlight_pwm; 1328 + /* AUX HW instance */ 1329 + uint8_t aux_inst; 1304 1330 }; 1305 1331 1306 1332 #endif /* DC_TYPES_H_ */

-2

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

··· 277 277 uint32_t misc1 = 0; 278 278 uint32_t h_blank; 279 279 uint32_t h_back_porch; 280 - uint8_t synchronous_clock = 0; /* asynchronous mode */ 281 280 uint8_t colorimetry_bpc; 282 281 uint8_t dynamic_range_rgb = 0; /*full range*/ 283 282 uint8_t dynamic_range_ycbcr = 1; /*bt709*/ ··· 379 380 break; 380 381 } 381 382 382 - misc0 = misc0 | synchronous_clock; 383 383 misc0 = colorimetry_bpc << 5; 384 384 385 385 if (REG(DP_MSA_TIMING_PARAM1)) {

-2

drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c

··· 76 76 mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C, 77 77 value); 78 78 79 - temp = 0; 80 79 value = 0; 81 80 temp = address.low_part >> 82 81 UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C__SHIFT; ··· 111 112 mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L, 112 113 value); 113 114 114 - temp = 0; 115 115 value = 0; 116 116 temp = address.low_part >> 117 117 UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L__SHIFT;

-151

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c

··· 280 280 return true; 281 281 } 282 282 283 - #define NUM_DEGAMMA_REGIONS 12 284 - 285 - 286 - bool cm3_helper_translate_curve_to_degamma_hw_format( 287 - const struct dc_transfer_func *output_tf, 288 - struct pwl_params *lut_params) 289 - { 290 - struct curve_points3 *corner_points; 291 - struct pwl_result_data *rgb_resulted; 292 - struct pwl_result_data *rgb; 293 - struct pwl_result_data *rgb_plus_1; 294 - 295 - int32_t region_start, region_end; 296 - int32_t i; 297 - uint32_t j, k, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points; 298 - 299 - if (output_tf == NULL || lut_params == NULL || output_tf->type == TF_TYPE_BYPASS) 300 - return false; 301 - 302 - corner_points = lut_params->corner_points; 303 - rgb_resulted = lut_params->rgb_resulted; 304 - hw_points = 0; 305 - 306 - memset(lut_params, 0, sizeof(struct pwl_params)); 307 - memset(seg_distr, 0, sizeof(seg_distr)); 308 - 309 - region_start = -NUM_DEGAMMA_REGIONS; 310 - region_end = 0; 311 - 312 - 313 - for (i = region_end - region_start; i < MAX_REGIONS_NUMBER ; i++) 314 - seg_distr[i] = -1; 315 - /* 12 segments 316 - * segments are from 2^-12 to 0 317 - */ 318 - for (i = 0; i < NUM_DEGAMMA_REGIONS ; i++) 319 - seg_distr[i] = 4; 320 - 321 - for (k = 0; k < MAX_REGIONS_NUMBER; k++) { 322 - if (seg_distr[k] != -1) 323 - hw_points += (1 << seg_distr[k]); 324 - } 325 - 326 - j = 0; 327 - for (k = 0; k < (region_end - region_start); k++) { 328 - increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]); 329 - start_index = (region_start + k + MAX_LOW_POINT) * 330 - NUMBER_SW_SEGMENTS; 331 - for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS; 332 - i += increment) { 333 - if (j == hw_points - 1) 334 - break; 335 - if (i >= TRANSFER_FUNC_POINTS) 336 - return false; 337 - rgb_resulted[j].red = output_tf->tf_pts.red[i]; 338 - rgb_resulted[j].green = output_tf->tf_pts.green[i]; 339 - rgb_resulted[j].blue = output_tf->tf_pts.blue[i]; 340 - j++; 341 - } 342 - } 343 - 344 - /* last point */ 345 - start_index = (region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS; 346 - rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index]; 347 - rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index]; 348 - rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index]; 349 - 350 - corner_points[0].red.x = dc_fixpt_pow(dc_fixpt_from_int(2), 351 - dc_fixpt_from_int(region_start)); 352 - corner_points[0].green.x = corner_points[0].red.x; 353 - corner_points[0].blue.x = corner_points[0].red.x; 354 - corner_points[1].red.x = dc_fixpt_pow(dc_fixpt_from_int(2), 355 - dc_fixpt_from_int(region_end)); 356 - corner_points[1].green.x = corner_points[1].red.x; 357 - corner_points[1].blue.x = corner_points[1].red.x; 358 - 359 - corner_points[0].red.y = rgb_resulted[0].red; 360 - corner_points[0].green.y = rgb_resulted[0].green; 361 - corner_points[0].blue.y = rgb_resulted[0].blue; 362 - 363 - /* see comment above, m_arrPoints[1].y should be the Y value for the 364 - * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1) 365 - */ 366 - corner_points[1].red.y = rgb_resulted[hw_points - 1].red; 367 - corner_points[1].green.y = rgb_resulted[hw_points - 1].green; 368 - corner_points[1].blue.y = rgb_resulted[hw_points - 1].blue; 369 - corner_points[1].red.slope = dc_fixpt_zero; 370 - corner_points[1].green.slope = dc_fixpt_zero; 371 - corner_points[1].blue.slope = dc_fixpt_zero; 372 - 373 - if (output_tf->tf == TRANSFER_FUNCTION_PQ) { 374 - /* for PQ, we want to have a straight line from last HW X point, 375 - * and the slope to be such that we hit 1.0 at 10000 nits. 376 - */ 377 - const struct fixed31_32 end_value = 378 - dc_fixpt_from_int(125); 379 - 380 - corner_points[1].red.slope = dc_fixpt_div( 381 - dc_fixpt_sub(dc_fixpt_one, corner_points[1].red.y), 382 - dc_fixpt_sub(end_value, corner_points[1].red.x)); 383 - corner_points[1].green.slope = dc_fixpt_div( 384 - dc_fixpt_sub(dc_fixpt_one, corner_points[1].green.y), 385 - dc_fixpt_sub(end_value, corner_points[1].green.x)); 386 - corner_points[1].blue.slope = dc_fixpt_div( 387 - dc_fixpt_sub(dc_fixpt_one, corner_points[1].blue.y), 388 - dc_fixpt_sub(end_value, corner_points[1].blue.x)); 389 - } 390 - 391 - lut_params->hw_points_num = hw_points; 392 - 393 - k = 0; 394 - for (i = 1; i < MAX_REGIONS_NUMBER; i++) { 395 - if (seg_distr[k] != -1) { 396 - lut_params->arr_curve_points[k].segments_num = 397 - seg_distr[k]; 398 - lut_params->arr_curve_points[i].offset = 399 - lut_params->arr_curve_points[k].offset + (1 << seg_distr[k]); 400 - } 401 - k++; 402 - } 403 - 404 - if (seg_distr[k] != -1) 405 - lut_params->arr_curve_points[k].segments_num = seg_distr[k]; 406 - 407 - rgb = rgb_resulted; 408 - rgb_plus_1 = rgb_resulted + 1; 409 - 410 - i = 1; 411 - while (i != hw_points + 1) { 412 - if (dc_fixpt_lt(rgb_plus_1->red, rgb->red)) 413 - rgb_plus_1->red = rgb->red; 414 - if (dc_fixpt_lt(rgb_plus_1->green, rgb->green)) 415 - rgb_plus_1->green = rgb->green; 416 - if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue)) 417 - rgb_plus_1->blue = rgb->blue; 418 - 419 - rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red); 420 - rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green); 421 - rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue); 422 - 423 - ++rgb_plus_1; 424 - ++rgb; 425 - ++i; 426 - } 427 - cm3_helper_convert_to_custom_float(rgb_resulted, 428 - lut_params->corner_points, 429 - hw_points, false); 430 - 431 - return true; 432 - } 433 - 434 283 bool cm3_helper_convert_to_custom_float( 435 284 struct pwl_result_data *rgb_resulted, 436 285 struct curve_points3 *corner_points,

-2

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

··· 255 255 uint32_t misc1 = 0; 256 256 uint32_t h_blank; 257 257 uint32_t h_back_porch; 258 - uint8_t synchronous_clock = 0; /* asynchronous mode */ 259 258 uint8_t colorimetry_bpc; 260 259 uint8_t dp_pixel_encoding = 0; 261 260 uint8_t dp_component_depth = 0; ··· 361 362 break; 362 363 } 363 364 364 - misc0 = misc0 | synchronous_clock; 365 365 misc0 = colorimetry_bpc << 5; 366 366 367 367 switch (output_color_space) {

-2

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

··· 447 447 uint32_t misc1 = 0; 448 448 uint32_t h_blank; 449 449 uint32_t h_back_porch; 450 - uint8_t synchronous_clock = 0; /* asynchronous mode */ 451 450 uint8_t colorimetry_bpc; 452 451 uint8_t dp_pixel_encoding = 0; 453 452 uint8_t dp_component_depth = 0; ··· 602 603 break; 603 604 } 604 605 605 - misc0 = misc0 | synchronous_clock; 606 606 misc0 = colorimetry_bpc << 5; 607 607 608 608 switch (output_color_space) {

+1 -1

drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

··· 859 859 plane->immediate_flip = plane_state->flip_immediate; 860 860 861 861 plane->composition.rect_out_height_spans_vactive = 862 - plane_state->dst_rect.height >= stream->timing.v_addressable && 862 + plane_state->dst_rect.height >= stream->src.height && 863 863 stream->dst.height >= stream->timing.v_addressable; 864 864 } 865 865

+1

drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

··· 88 88 uint32_t sdpif_request_rate_limit; 89 89 uint32_t allow_sdpif_rate_limit_when_cstate_req; 90 90 uint32_t dcfclk_deep_sleep_hysteresis; 91 + uint32_t pstate_stall_threshold; 91 92 }; 92 93 93 94 struct dml2_cursor_dlg_regs{

+3

drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

··· 12236 12236 12237 12237 static void rq_dlg_get_arb_params(const struct dml2_display_cfg *display_cfg, const struct dml2_core_internal_display_mode_lib *mode_lib, struct dml2_display_arb_regs *arb_param) 12238 12238 { 12239 + double refclk_freq_in_mhz = (display_cfg->overrides.hw.dlg_ref_clk_mhz > 0) ? (double)display_cfg->overrides.hw.dlg_ref_clk_mhz : mode_lib->soc.dchub_refclk_mhz; 12240 + 12239 12241 arb_param->max_req_outstanding = mode_lib->soc.max_outstanding_reqs; 12240 12242 arb_param->min_req_outstanding = mode_lib->soc.max_outstanding_reqs; // turn off the sat level feature if this set to max 12241 12243 arb_param->sdpif_request_rate_limit = (3 * mode_lib->ip.words_per_channel * mode_lib->soc.clk_table.dram_config.channel_count) / 4; ··· 12249 12247 arb_param->compbuf_size = mode_lib->mp.CompressedBufferSizeInkByte / mode_lib->ip.compressed_buffer_segment_size_in_kbytes; 12250 12248 arb_param->allow_sdpif_rate_limit_when_cstate_req = dml_get_hw_debug5(mode_lib); 12251 12249 arb_param->dcfclk_deep_sleep_hysteresis = dml_get_dcfclk_deep_sleep_hysteresis(mode_lib); 12250 + arb_param->pstate_stall_threshold = (unsigned int)(mode_lib->ip_caps.fams2.max_allow_delay_us * refclk_freq_in_mhz); 12252 12251 12253 12252 #ifdef __DML_VBA_DEBUG__ 12254 12253 dml2_printf("DML::%s: max_req_outstanding = %d\n", __func__, arb_param->max_req_outstanding);

+2 -1

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

··· 1091 1091 /* ISHARP_DELTA_LUT */ 1092 1092 dpp401_dscl_set_isharp_filter(dpp, scl_data->dscl_prog_data.isharp_delta); 1093 1093 dpp->scl_data.dscl_prog_data.sharpness_level = scl_data->dscl_prog_data.sharpness_level; 1094 - dpp->scl_data.dscl_prog_data.isharp_delta = scl_data->dscl_prog_data.isharp_delta; 1094 + memcpy(dpp->scl_data.dscl_prog_data.isharp_delta, scl_data->dscl_prog_data.isharp_delta, 1095 + sizeof(uint32_t) * ISHARP_LUT_TABLE_SIZE); 1095 1096 1096 1097 if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data)) == 0) 1097 1098 return;

-4

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_cm_common.h

··· 63 63 const struct dc_transfer_func *output_tf, 64 64 struct pwl_params *lut_params, bool fixpoint); 65 65 66 - bool cm3_helper_translate_curve_to_degamma_hw_format( 67 - const struct dc_transfer_func *output_tf, 68 - struct pwl_params *lut_params); 69 - 70 66 bool cm3_helper_convert_to_custom_float( 71 67 struct pwl_result_data *rgb_resulted, 72 68 struct curve_points3 *corner_points,

+8 -1

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h

··· 198 198 uint32_t DCHUBBUB_ARB_REFCYC_PER_META_TRIP_B; 199 199 uint32_t DCHUBBUB_ARB_FRAC_URG_BW_MALL_A; 200 200 uint32_t DCHUBBUB_ARB_FRAC_URG_BW_MALL_B; 201 + uint32_t DCHUBBUB_TIMEOUT_DETECTION_CTRL1; 202 + uint32_t DCHUBBUB_TIMEOUT_DETECTION_CTRL2; 201 203 }; 202 204 203 205 #define HUBBUB_REG_FIELD_LIST_DCN32(type) \ ··· 315 313 type DCN_VM_ERROR_VMID;\ 316 314 type DCN_VM_ERROR_TABLE_LEVEL;\ 317 315 type DCN_VM_ERROR_PIPE;\ 318 - type DCN_VM_ERROR_INTERRUPT_STATUS 316 + type DCN_VM_ERROR_INTERRUPT_STATUS;\ 317 + type DCHUBBUB_TIMEOUT_ERROR_STATUS;\ 318 + type DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD;\ 319 + type DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD;\ 320 + type DCHUBBUB_TIMEOUT_DETECTION_EN;\ 321 + type DCHUBBUB_TIMEOUT_TIMER_RESET 319 322 320 323 #define HUBBUB_STUTTER_REG_FIELD_LIST(type) \ 321 324 type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A;\

+12

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

··· 1192 1192 } 1193 1193 } 1194 1194 1195 + static void dcn401_program_timeout_thresholds(struct hubbub *hubbub, struct dml2_display_arb_regs *arb_regs) 1196 + { 1197 + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); 1198 + 1199 + /* request backpressure and outstanding return threshold (unused)*/ 1200 + //REG_UPDATE(DCHUBBUB_TIMEOUT_DETECTION_CTRL1, DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD, arb_regs->req_stall_threshold); 1201 + 1202 + /* P-State stall threshold */ 1203 + REG_UPDATE(DCHUBBUB_TIMEOUT_DETECTION_CTRL2, DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD, arb_regs->pstate_stall_threshold); 1204 + } 1205 + 1195 1206 static const struct hubbub_funcs hubbub4_01_funcs = { 1196 1207 .update_dchub = hubbub2_update_dchub, 1197 1208 .init_dchub_sys_ctx = hubbub3_init_dchub_sys_ctx, ··· 1226 1215 .program_det_segments = dcn401_program_det_segments, 1227 1216 .program_compbuf_segments = dcn401_program_compbuf_segments, 1228 1217 .wait_for_det_update = dcn401_wait_for_det_update, 1218 + .program_timeout_thresholds = dcn401_program_timeout_thresholds, 1229 1219 }; 1230 1220 1231 1221 void hubbub401_construct(struct dcn20_hubbub *hubbub2,

+6 -2

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h

··· 123 123 HUBBUB_SF(DCHUBBUB_CLOCK_CNTL, DCFCLK_R_DCHUBBUB_GATE_DIS, mask_sh),\ 124 124 HUBBUB_SF(DCHUBBUB_SDPIF_CFG0, SDPIF_PORT_CONTROL, mask_sh),\ 125 125 HUBBUB_SF(DCHUBBUB_SDPIF_CFG1, SDPIF_MAX_NUM_OUTSTANDING, mask_sh),\ 126 - HUBBUB_SF(DCHUBBUB_MEM_PWR_MODE_CTRL, DET_MEM_PWR_LS_MODE, mask_sh) 127 - 126 + HUBBUB_SF(DCHUBBUB_MEM_PWR_MODE_CTRL, DET_MEM_PWR_LS_MODE, mask_sh),\ 127 + HUBBUB_SF(DCHUBBUB_TIMEOUT_DETECTION_CTRL1, DCHUBBUB_TIMEOUT_ERROR_STATUS, mask_sh),\ 128 + HUBBUB_SF(DCHUBBUB_TIMEOUT_DETECTION_CTRL1, DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD, mask_sh),\ 129 + HUBBUB_SF(DCHUBBUB_TIMEOUT_DETECTION_CTRL2, DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD, mask_sh),\ 130 + HUBBUB_SF(DCHUBBUB_TIMEOUT_DETECTION_CTRL2, DCHUBBUB_TIMEOUT_DETECTION_EN, mask_sh),\ 131 + HUBBUB_SF(DCHUBBUB_TIMEOUT_DETECTION_CTRL2, DCHUBBUB_TIMEOUT_TIMER_RESET, mask_sh) 128 132 129 133 bool hubbub401_program_urgent_watermarks( 130 134 struct hubbub *hubbub,

+5 -4

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

··· 1039 1039 link_transmitter_control(ctx->dc_bios, &cntl); 1040 1040 1041 1041 if (enable && link->dpcd_sink_ext_caps.bits.oled && 1042 - !link->dc->config.edp_no_power_sequencing) { 1042 + !link->dc->config.edp_no_power_sequencing && 1043 + !link->local_sink->edid_caps.panel_patch.oled_optimize_display_on) { 1043 1044 post_T7_delay += link->panel_config.pps.extra_post_t7_ms; 1044 1045 msleep(post_T7_delay); 1045 1046 } ··· 3143 3142 } 3144 3143 3145 3144 bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx, 3146 - struct set_backlight_level_params *params) 3145 + struct set_backlight_level_params *backlight_level_params) 3147 3146 { 3148 - uint32_t backlight_pwm_u16_16 = params->backlight_pwm_u16_16; 3149 - uint32_t frame_ramp = params->frame_ramp; 3147 + uint32_t backlight_pwm_u16_16 = backlight_level_params->backlight_pwm_u16_16; 3148 + uint32_t frame_ramp = backlight_level_params->frame_ramp; 3150 3149 struct dc_link *link = pipe_ctx->stream->link; 3151 3150 struct dc *dc = link->ctx->dc; 3152 3151 struct abm *abm = pipe_ctx->stream_res.abm;

+8 -8

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

··· 137 137 pipe_ctx->stream->dpms_off = true; 138 138 } 139 139 140 - static bool dmub_abm_set_pipe(struct abm *abm, uint32_t otg_inst, 140 + bool dcn21_dmub_abm_set_pipe(struct abm *abm, uint32_t otg_inst, 141 141 uint32_t option, uint32_t panel_inst, uint32_t pwrseq_inst) 142 142 { 143 143 union dmub_rb_cmd cmd; ··· 199 199 abm->funcs->set_pipe_ex(abm, otg_inst, SET_ABM_PIPE_IMMEDIATELY_DISABLE, 200 200 panel_cntl->inst, panel_cntl->pwrseq_inst); 201 201 } else { 202 - dmub_abm_set_pipe(abm, 202 + dcn21_dmub_abm_set_pipe(abm, 203 203 otg_inst, 204 204 SET_ABM_PIPE_IMMEDIATELY_DISABLE, 205 205 panel_cntl->inst, ··· 234 234 panel_cntl->inst, 235 235 panel_cntl->pwrseq_inst); 236 236 } else { 237 - dmub_abm_set_pipe(abm, otg_inst, 237 + dcn21_dmub_abm_set_pipe(abm, otg_inst, 238 238 SET_ABM_PIPE_NORMAL, 239 239 panel_cntl->inst, 240 240 panel_cntl->pwrseq_inst); ··· 242 242 } 243 243 244 244 bool dcn21_set_backlight_level(struct pipe_ctx *pipe_ctx, 245 - struct set_backlight_level_params *params) 245 + struct set_backlight_level_params *backlight_level_params) 246 246 { 247 247 struct dc_context *dc = pipe_ctx->stream->ctx; 248 248 struct abm *abm = pipe_ctx->stream_res.abm; 249 249 struct timing_generator *tg = pipe_ctx->stream_res.tg; 250 250 struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl; 251 251 uint32_t otg_inst; 252 - uint32_t backlight_pwm_u16_16 = params->backlight_pwm_u16_16; 253 - uint32_t frame_ramp = params->frame_ramp; 252 + uint32_t backlight_pwm_u16_16 = backlight_level_params->backlight_pwm_u16_16; 253 + uint32_t frame_ramp = backlight_level_params->frame_ramp; 254 254 255 255 if (!abm || !tg || !panel_cntl) 256 256 return false; ··· 258 258 otg_inst = tg->inst; 259 259 260 260 if (dc->dc->res_pool->dmcu) { 261 - dce110_set_backlight_level(pipe_ctx, params); 261 + dce110_set_backlight_level(pipe_ctx, backlight_level_params); 262 262 return true; 263 263 } 264 264 ··· 269 269 panel_cntl->inst, 270 270 panel_cntl->pwrseq_inst); 271 271 } else { 272 - dmub_abm_set_pipe(abm, 272 + dcn21_dmub_abm_set_pipe(abm, 273 273 otg_inst, 274 274 SET_ABM_PIPE_NORMAL, 275 275 panel_cntl->inst,

+2

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h

··· 47 47 void dcn21_PLAT_58856_wa(struct dc_state *context, 48 48 struct pipe_ctx *pipe_ctx); 49 49 50 + bool dcn21_dmub_abm_set_pipe(struct abm *abm, uint32_t otg_inst, 51 + uint32_t option, uint32_t panel_inst, uint32_t pwrseq_inst); 50 52 void dcn21_set_pipe(struct pipe_ctx *pipe_ctx); 51 53 void dcn21_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx); 52 54 bool dcn21_set_backlight_level(struct pipe_ctx *pipe_ctx,

+49

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

··· 47 47 #include "dce/dmub_outbox.h" 48 48 #include "link.h" 49 49 #include "dcn10/dcn10_hwseq.h" 50 + #include "dcn21/dcn21_hwseq.h" 50 51 #include "inc/link_enc_cfg.h" 51 52 #include "dcn30/dcn30_vpg.h" 52 53 #include "dce/dce_i2c_hw.h" 54 + #include "dce/dmub_abm_lcd.h" 53 55 54 56 #define DC_LOGGER_INIT(logger) 55 57 ··· 639 637 for (i = 0; i < num_pipes; i++) 640 638 pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(pipe_ctx[i]->stream_res.tg, 641 639 triggers, params->num_frames); 640 + } 641 + 642 + static void dmub_abm_set_backlight(struct dc_context *dc, 643 + struct set_backlight_level_params *backlight_level_params, uint32_t panel_inst) 644 + { 645 + union dmub_rb_cmd cmd; 646 + 647 + memset(&cmd, 0, sizeof(cmd)); 648 + cmd.abm_set_backlight.header.type = DMUB_CMD__ABM; 649 + cmd.abm_set_backlight.header.sub_type = DMUB_CMD__ABM_SET_BACKLIGHT; 650 + cmd.abm_set_backlight.abm_set_backlight_data.frame_ramp = backlight_level_params->frame_ramp; 651 + cmd.abm_set_backlight.abm_set_backlight_data.backlight_user_level = backlight_level_params->backlight_pwm_u16_16; 652 + cmd.abm_set_backlight.abm_set_backlight_data.backlight_control_type = backlight_level_params->control_type; 653 + cmd.abm_set_backlight.abm_set_backlight_data.min_luminance = backlight_level_params->min_luminance; 654 + cmd.abm_set_backlight.abm_set_backlight_data.max_luminance = backlight_level_params->max_luminance; 655 + cmd.abm_set_backlight.abm_set_backlight_data.min_backlight_pwm = backlight_level_params->min_backlight_pwm; 656 + cmd.abm_set_backlight.abm_set_backlight_data.max_backlight_pwm = backlight_level_params->max_backlight_pwm; 657 + cmd.abm_set_backlight.abm_set_backlight_data.version = DMUB_CMD_ABM_CONTROL_VERSION_1; 658 + cmd.abm_set_backlight.abm_set_backlight_data.panel_mask = (0x01 << panel_inst); 659 + cmd.abm_set_backlight.header.payload_bytes = sizeof(struct dmub_cmd_abm_set_backlight_data); 660 + 661 + dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 662 + } 663 + 664 + bool dcn31_set_backlight_level(struct pipe_ctx *pipe_ctx, 665 + struct set_backlight_level_params *backlight_level_params) 666 + { 667 + struct dc_context *dc = pipe_ctx->stream->ctx; 668 + struct abm *abm = pipe_ctx->stream_res.abm; 669 + struct timing_generator *tg = pipe_ctx->stream_res.tg; 670 + struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl; 671 + uint32_t otg_inst; 672 + 673 + if (!abm || !tg || !panel_cntl) 674 + return false; 675 + 676 + otg_inst = tg->inst; 677 + 678 + dcn21_dmub_abm_set_pipe(abm, 679 + otg_inst, 680 + SET_ABM_PIPE_NORMAL, 681 + panel_cntl->inst, 682 + panel_cntl->pwrseq_inst); 683 + 684 + dmub_abm_set_backlight(dc, backlight_level_params, panel_cntl->inst); 685 + 686 + return true; 642 687 }

+2 -1

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

··· 51 51 void dcn31_reset_hw_ctx_wrap( 52 52 struct dc *dc, 53 53 struct dc_state *context); 54 + bool dcn31_set_backlight_level(struct pipe_ctx *pipe_ctx, 55 + struct set_backlight_level_params *params); 54 56 bool dcn31_is_abm_supported(struct dc *dc, 55 57 struct dc_state *context, struct dc_stream_state *stream); 56 58 void dcn31_init_pipes(struct dc *dc, struct dc_state *context); ··· 60 58 61 59 void dcn31_set_static_screen_control(struct pipe_ctx **pipe_ctx, 62 60 int num_pipes, const struct dc_static_screen_params *params); 63 - 64 61 65 62 #endif /* __DC_HWSS_DCN31_H__ */

+1 -1

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c

··· 98 98 .set_flip_control_gsl = dcn20_set_flip_control_gsl, 99 99 .get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync, 100 100 .calc_vupdate_position = dcn10_calc_vupdate_position, 101 - .set_backlight_level = dcn21_set_backlight_level, 101 + .set_backlight_level = dcn31_set_backlight_level, 102 102 .set_abm_immediate_disable = dcn21_set_abm_immediate_disable, 103 103 .set_pipe = dcn21_set_pipe, 104 104 .enable_lvds_link_output = dce110_enable_lvds_link_output,

+1 -1

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c

··· 100 100 .set_flip_control_gsl = dcn20_set_flip_control_gsl, 101 101 .get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync, 102 102 .calc_vupdate_position = dcn10_calc_vupdate_position, 103 - .set_backlight_level = dcn21_set_backlight_level, 103 + .set_backlight_level = dcn31_set_backlight_level, 104 104 .set_abm_immediate_disable = dcn21_set_abm_immediate_disable, 105 105 .set_pipe = dcn21_set_pipe, 106 106 .enable_lvds_link_output = dce110_enable_lvds_link_output,

+1 -1

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c

··· 98 98 .calc_vupdate_position = dcn10_calc_vupdate_position, 99 99 .apply_idle_power_optimizations = dcn32_apply_idle_power_optimizations, 100 100 .does_plane_fit_in_mall = NULL, 101 - .set_backlight_level = dcn21_set_backlight_level, 101 + .set_backlight_level = dcn31_set_backlight_level, 102 102 .set_abm_immediate_disable = dcn21_set_abm_immediate_disable, 103 103 .hardware_release = dcn30_hardware_release, 104 104 .set_pipe = dcn21_set_pipe,

+10 -6

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

··· 309 309 dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv); 310 310 dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr; 311 311 dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver; 312 + dc->caps.dmub_caps.aux_backlight_support = dc->ctx->dmub_srv->dmub->feature_caps.abm_aux_backlight_support; 312 313 } 313 314 314 315 if (dc->res_pool->pg_cntl) { ··· 842 841 uint32_t num_opps = 0; 843 842 uint32_t opp_id_src0 = OPP_ID_INVALID; 844 843 uint32_t opp_id_src1 = OPP_ID_INVALID; 844 + uint32_t optc_dsc_state = 0; 845 845 846 846 // Step 1: To find out which OPTC is running & OPTC DSC is ON 847 847 // We can't use res_pool->res_cap->num_timing_generator to check ··· 851 849 // Some ASICs would be fused display pipes less than the default setting. 852 850 // In dcnxx_resource_construct function, driver would obatin real information. 853 851 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 854 - uint32_t optc_dsc_state = 0; 855 852 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 856 853 857 854 if (tg->funcs->is_tg_enabled(tg)) { ··· 865 864 } 866 865 } 867 866 868 - // Step 2: To power down DSC but skip DSC of running OPTC 867 + // Step 2: To power down DSC but skip DSC of running OPTC 869 868 for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) { 870 869 struct dcn_dsc_state s = {0}; 871 870 872 - dc->res_pool->dscs[i]->funcs->dsc_read_state(dc->res_pool->dscs[i], &s); 871 + /* avoid reading DSC state when it is not in use as it may be power gated */ 872 + if (optc_dsc_state) { 873 + dc->res_pool->dscs[i]->funcs->dsc_read_state(dc->res_pool->dscs[i], &s); 873 874 874 - if ((s.dsc_opp_source == opp_id_src0 || s.dsc_opp_source == opp_id_src1) && 875 - s.dsc_clock_en && s.dsc_fw_en) 876 - continue; 875 + if ((s.dsc_opp_source == opp_id_src0 || s.dsc_opp_source == opp_id_src1) && 876 + s.dsc_clock_en && s.dsc_fw_en) 877 + continue; 878 + } 877 879 878 880 pg_cntl->funcs->dsc_pg_control(pg_cntl, dc->res_pool->dscs[i]->inst, false); 879 881 }

+1 -1

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c

··· 101 101 .set_flip_control_gsl = dcn20_set_flip_control_gsl, 102 102 .get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync, 103 103 .calc_vupdate_position = dcn10_calc_vupdate_position, 104 - .set_backlight_level = dcn21_set_backlight_level, 104 + .set_backlight_level = dcn31_set_backlight_level, 105 105 .set_abm_immediate_disable = dcn21_set_abm_immediate_disable, 106 106 .set_pipe = dcn21_set_pipe, 107 107 .enable_lvds_link_output = dce110_enable_lvds_link_output,

+1 -1

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c

··· 100 100 .set_flip_control_gsl = dcn20_set_flip_control_gsl, 101 101 .get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync, 102 102 .calc_vupdate_position = dcn10_calc_vupdate_position, 103 - .set_backlight_level = dcn21_set_backlight_level, 103 + .set_backlight_level = dcn31_set_backlight_level, 104 104 .set_abm_immediate_disable = dcn21_set_abm_immediate_disable, 105 105 .set_pipe = dcn21_set_pipe, 106 106 .enable_lvds_link_output = dce110_enable_lvds_link_output,

+5

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

··· 1554 1554 pipe_ctx->dlg_regs.min_dst_y_next_start); 1555 1555 } 1556 1556 } 1557 + 1558 + /* update timeout thresholds */ 1559 + if (hubbub->funcs->program_timeout_thresholds) { 1560 + hubbub->funcs->program_timeout_thresholds(hubbub, &context->bw_ctx.bw.dcn.arb_regs); 1561 + } 1557 1562 } 1558 1563 1559 1564 void dcn401_fams2_global_control_lock(struct dc *dc,

+1 -1

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c

··· 77 77 .calc_vupdate_position = dcn10_calc_vupdate_position, 78 78 .apply_idle_power_optimizations = dcn401_apply_idle_power_optimizations, 79 79 .does_plane_fit_in_mall = NULL, 80 - .set_backlight_level = dcn21_set_backlight_level, 80 + .set_backlight_level = dcn31_set_backlight_level, 81 81 .set_abm_immediate_disable = dcn21_set_abm_immediate_disable, 82 82 .hardware_release = dcn401_hardware_release, 83 83 .set_pipe = dcn21_set_pipe,

-5

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

··· 174 174 struct fams2_global_control_lock_fast_params fams2_global_control_lock_fast_params; 175 175 }; 176 176 177 - struct set_backlight_level_params { 178 - uint32_t backlight_pwm_u16_16; 179 - uint32_t frame_ramp; 180 - }; 181 - 182 177 enum block_sequence_func { 183 178 DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST = 0, 184 179 OPTC_PIPE_CONTROL_LOCK,

+2

drivers/gpu/drm/amd/display/dc/inc/core_status.h

··· 60 60 }; 61 61 62 62 char *dc_status_to_str(enum dc_status status); 63 + char *dc_pixel_encoding_to_str(enum dc_pixel_encoding pixel_encoding); 64 + char *dc_color_depth_to_str(enum dc_color_depth color_depth); 63 65 64 66 #endif /* _CORE_STATUS_H_ */

+1

drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h

··· 228 228 void (*program_det_segments)(struct hubbub *hubbub, int hubp_inst, unsigned det_buffer_size_seg); 229 229 void (*program_compbuf_segments)(struct hubbub *hubbub, unsigned compbuf_size_seg, bool safe_to_increase); 230 230 void (*wait_for_det_update)(struct hubbub *hubbub, int hubp_inst); 231 + void (*program_timeout_thresholds)(struct hubbub *hubbub, struct dml2_display_arb_regs *arb_regs); 231 232 }; 232 233 233 234 struct hubbub {

+1 -2

drivers/gpu/drm/amd/display/dc/inc/link.h

··· 248 248 uint32_t *backlight_millinits_avg, 249 249 uint32_t *backlight_millinits_peak); 250 250 bool (*edp_set_backlight_level)(const struct dc_link *link, 251 - uint32_t backlight_pwm_u16_16, 252 - uint32_t frame_ramp); 251 + struct set_backlight_level_params *backlight_level_params); 253 252 bool (*edp_set_backlight_level_nits)(struct dc_link *link, 254 253 bool isHDR, 255 254 uint32_t backlight_millinits,

+11 -4

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

··· 2082 2082 if (link_settings->link_rate == LINK_RATE_LOW) 2083 2083 skip_video_pattern = false; 2084 2084 2085 + if (stream->sink_patches.oled_optimize_display_on) 2086 + set_default_brightness_aux(link); 2087 + 2085 2088 if (perform_link_training_with_retries(link_settings, 2086 2089 skip_video_pattern, 2087 2090 lt_attempts, ··· 2108 2105 if (link->dpcd_sink_ext_caps.bits.oled == 1 || 2109 2106 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 || 2110 2107 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) { 2111 - set_default_brightness_aux(link); 2112 - if (link->dpcd_sink_ext_caps.bits.oled == 1) 2113 - msleep(bl_oled_enable_delay); 2114 - edp_backlight_enable_aux(link, true); 2108 + if (!stream->sink_patches.oled_optimize_display_on) { 2109 + set_default_brightness_aux(link); 2110 + if (link->dpcd_sink_ext_caps.bits.oled == 1) 2111 + msleep(bl_oled_enable_delay); 2112 + edp_backlight_enable_aux(link, true); 2113 + } else { 2114 + edp_backlight_enable_aux(link, true); 2115 + } 2115 2116 } 2116 2117 2117 2118 return status;

+8 -17

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

··· 51 51 #include "dc_dmub_srv.h" 52 52 #include "gpio_service_interface.h" 53 53 54 + #define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */ 55 + 54 56 #define DC_LOGGER \ 55 57 link->ctx->logger 56 - #define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */ 57 58 58 59 #ifndef MAX 59 60 #define MAX(X, Y) ((X) > (Y) ? (X) : (Y)) ··· 1417 1416 1418 1417 if (!link->ctx->dmub_srv || 1419 1418 link->ep_type != DISPLAY_ENDPOINT_PHY || 1420 - link->link_enc->features.flags.bits.DP_IS_USB_C == 0 || 1421 - link->link_enc->features.flags.bits.IS_DP2_CAPABLE == 0) 1419 + link->link_enc->features.flags.bits.DP_IS_USB_C == 0) 1422 1420 return false; 1423 1421 1424 1422 memset(&cmd, 0, sizeof(cmd)); ··· 1430 1430 cable_id->raw = cmd.cable_id.data.output_raw; 1431 1431 DC_LOG_DC("usbc_cable_id = %d.\n", cable_id->raw); 1432 1432 } 1433 - 1434 - ASSERT(cmd.cable_id.header.ret_status); 1435 - return true; 1433 + return cmd.cable_id.header.ret_status == 1; 1436 1434 } 1437 1435 1438 1436 static void retrieve_cable_id(struct dc_link *link) ··· 2127 2129 /* get max link encoder capability */ 2128 2130 if (link_enc) 2129 2131 link_enc->funcs->get_max_link_cap(link_enc, &max_link_cap); 2130 - else 2131 - return max_link_cap; 2132 2132 2133 2133 /* Lower link settings based on sink's link cap */ 2134 2134 if (link->reported_link_cap.lane_count < max_link_cap.lane_count) ··· 2160 2164 */ 2161 2165 cable_max_link_rate = get_cable_max_link_rate(link); 2162 2166 2163 - if (!link->dc->debug.ignore_cable_id) { 2164 - if (cable_max_link_rate != LINK_RATE_UNKNOWN) 2165 - // cable max link rate known 2166 - max_link_cap.link_rate = MIN(max_link_cap.link_rate, cable_max_link_rate); 2167 - else if (link_enc->funcs->is_in_alt_mode && link_enc->funcs->is_in_alt_mode(link_enc)) 2168 - // cable max link rate ambiguous, DP alt mode, limit to HBR3 2169 - max_link_cap.link_rate = MIN(max_link_cap.link_rate, LINK_RATE_HIGH3); 2170 - //else {} 2171 - // cable max link rate ambiguous, DP, do nothing 2167 + if (!link->dc->debug.ignore_cable_id && 2168 + cable_max_link_rate != LINK_RATE_UNKNOWN) { 2169 + if (cable_max_link_rate < max_link_cap.link_rate) 2170 + max_link_cap.link_rate = cable_max_link_rate; 2172 2171 2173 2172 if (!link->dpcd_caps.cable_id.bits.UHBR13_5_CAPABILITY && 2174 2173 link->dpcd_caps.cable_id.bits.CABLE_TYPE >= 2)

+9 -8

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

··· 161 161 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT)) 162 162 return false; 163 163 164 - if (link->backlight_control_type == BACKLIGHT_CONTROL_VESA_AUX) { 164 + // use internal backlight control if dmub capabilities are not present 165 + if (link->backlight_control_type == BACKLIGHT_CONTROL_VESA_AUX && 166 + !link->dc->caps.dmub_caps.aux_backlight_support) { 165 167 uint8_t backlight_enable = 0; 166 168 struct target_luminance_value *target_luminance = NULL; 167 169 ··· 187 185 (uint8_t *)(target_luminance), 188 186 sizeof(struct target_luminance_value)) != DC_OK) 189 187 return false; 190 - } else { 188 + } else if (link->backlight_control_type == BACKLIGHT_CONTROL_AMD_AUX) { 191 189 struct dpcd_source_backlight_set dpcd_backlight_set; 192 190 *(uint32_t *)&dpcd_backlight_set.backlight_level_millinits = backlight_millinits; 193 191 *(uint16_t *)&dpcd_backlight_set.backlight_transition_time_ms = (uint16_t)transition_time_in_ms; ··· 519 517 } 520 518 521 519 bool edp_set_backlight_level(const struct dc_link *link, 522 - uint32_t backlight_pwm_u16_16, 523 - uint32_t frame_ramp) 520 + struct set_backlight_level_params *backlight_level_params) 524 521 { 525 522 struct dc *dc = link->ctx->dc; 523 + uint32_t backlight_pwm_u16_16 = backlight_level_params->backlight_pwm_u16_16; 524 + uint32_t frame_ramp = backlight_level_params->frame_ramp; 526 525 DC_LOGGER_INIT(link->ctx->logger); 527 526 DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n", 528 527 backlight_pwm_u16_16, backlight_pwm_u16_16); 529 528 530 529 if (dc_is_embedded_signal(link->connector_signal)) { 531 530 struct pipe_ctx *pipe_ctx = get_pipe_from_link(link); 532 - struct set_backlight_level_params backlight_level_param = { 0 }; 533 531 534 532 if (link->panel_cntl) 535 533 link->panel_cntl->stored_backlight_registers.USER_LEVEL = backlight_pwm_u16_16; ··· 544 542 return false; 545 543 } 546 544 547 - backlight_level_param.backlight_pwm_u16_16 = backlight_pwm_u16_16; 548 - backlight_level_param.frame_ramp = frame_ramp; 545 + backlight_level_params->frame_ramp = frame_ramp; 549 546 550 547 dc->hwss.set_backlight_level( 551 548 pipe_ctx, 552 - &backlight_level_param); 549 + backlight_level_params); 553 550 } 554 551 return true; 555 552 }

+1 -2

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h

··· 36 36 uint32_t *backlight_millinits_avg, 37 37 uint32_t *backlight_millinits_peak); 38 38 bool edp_set_backlight_level(const struct dc_link *link, 39 - uint32_t backlight_pwm_u16_16, 40 - uint32_t frame_ramp); 39 + struct set_backlight_level_params *backlight_level_params); 41 40 bool edp_set_backlight_level_nits(struct dc_link *link, 42 41 bool isHDR, 43 42 uint32_t backlight_millinits,

-2

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

··· 533 533 .sanity_checks = true, 534 534 .disable_dmcu = false, 535 535 .force_abm_enable = false, 536 - .timing_trace = false, 537 536 .clock_trace = true, 538 537 539 538 /* raven smu dones't allow 0 disp clk, ··· 562 563 static const struct dc_debug_options debug_defaults_diags = { 563 564 .disable_dmcu = false, 564 565 .force_abm_enable = false, 565 - .timing_trace = true, 566 566 .clock_trace = true, 567 567 .disable_stutter = true, 568 568 .disable_pplib_clock_request = true,

-1

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

··· 706 706 static const struct dc_debug_options debug_defaults_drv = { 707 707 .disable_dmcu = false, 708 708 .force_abm_enable = false, 709 - .timing_trace = false, 710 709 .clock_trace = true, 711 710 .disable_pplib_clock_request = true, 712 711 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,

-1

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

··· 600 600 static const struct dc_debug_options debug_defaults_drv = { 601 601 .disable_dmcu = true, 602 602 .force_abm_enable = false, 603 - .timing_trace = false, 604 603 .clock_trace = true, 605 604 .disable_pplib_clock_request = true, 606 605 .pipe_split_policy = MPC_SPLIT_DYNAMIC,

-1

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

··· 610 610 static const struct dc_debug_options debug_defaults_drv = { 611 611 .disable_dmcu = false, 612 612 .force_abm_enable = false, 613 - .timing_trace = false, 614 613 .clock_trace = true, 615 614 .disable_pplib_clock_request = true, 616 615 .min_disp_clk_khz = 100000,

-1

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

··· 711 711 static const struct dc_debug_options debug_defaults_drv = { 712 712 .disable_dmcu = true, //No DMCU on DCN30 713 713 .force_abm_enable = false, 714 - .timing_trace = false, 715 714 .clock_trace = true, 716 715 .disable_pplib_clock_request = true, 717 716 .pipe_split_policy = MPC_SPLIT_DYNAMIC,

-1

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

··· 682 682 static const struct dc_debug_options debug_defaults_drv = { 683 683 .disable_dmcu = true, 684 684 .force_abm_enable = false, 685 - .timing_trace = false, 686 685 .clock_trace = true, 687 686 .disable_dpp_power_gate = false, 688 687 .disable_hubp_power_gate = false,

-1

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

··· 81 81 static const struct dc_debug_options debug_defaults_drv = { 82 82 .disable_dmcu = true, 83 83 .force_abm_enable = false, 84 - .timing_trace = false, 85 84 .clock_trace = true, 86 85 .disable_pplib_clock_request = true, 87 86 .pipe_split_policy = MPC_SPLIT_DYNAMIC,

-1

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

··· 82 82 static const struct dc_debug_options debug_defaults_drv = { 83 83 .disable_dmcu = true, 84 84 .force_abm_enable = false, 85 - .timing_trace = false, 86 85 .clock_trace = true, 87 86 .disable_pplib_clock_request = true, 88 87 .pipe_split_policy = MPC_SPLIT_AVOID,

-1

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

··· 858 858 static const struct dc_debug_options debug_defaults_drv = { 859 859 .disable_dmcu = true, 860 860 .force_abm_enable = false, 861 - .timing_trace = false, 862 861 .clock_trace = true, 863 862 .disable_pplib_clock_request = false, 864 863 .pipe_split_policy = MPC_SPLIT_DYNAMIC,

-1

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

··· 876 876 .replay_skip_crtc_disabled = true, 877 877 .disable_dmcu = true, 878 878 .force_abm_enable = false, 879 - .timing_trace = false, 880 879 .clock_trace = true, 881 880 .disable_dpp_power_gate = false, 882 881 .disable_hubp_power_gate = false,

-1

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

··· 858 858 .disable_z10 = true, /*hw not support it*/ 859 859 .disable_dmcu = true, 860 860 .force_abm_enable = false, 861 - .timing_trace = false, 862 861 .clock_trace = true, 863 862 .disable_pplib_clock_request = false, 864 863 .pipe_split_policy = MPC_SPLIT_DYNAMIC,

-1

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

··· 853 853 .disable_z10 = true, /*hw not support it*/ 854 854 .disable_dmcu = true, 855 855 .force_abm_enable = false, 856 - .timing_trace = false, 857 856 .clock_trace = true, 858 857 .disable_pplib_clock_request = false, 859 858 .pipe_split_policy = MPC_SPLIT_DYNAMIC,

-1

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

··· 689 689 static const struct dc_debug_options debug_defaults_drv = { 690 690 .disable_dmcu = true, 691 691 .force_abm_enable = false, 692 - .timing_trace = false, 693 692 .clock_trace = true, 694 693 .disable_pplib_clock_request = false, 695 694 .pipe_split_policy = MPC_SPLIT_AVOID, // Due to CRB, no need to MPC split anymore

-1

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

··· 686 686 static const struct dc_debug_options debug_defaults_drv = { 687 687 .disable_dmcu = true, 688 688 .force_abm_enable = false, 689 - .timing_trace = false, 690 689 .clock_trace = true, 691 690 .disable_pplib_clock_request = false, 692 691 .pipe_split_policy = MPC_SPLIT_AVOID,

-1

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

··· 712 712 static const struct dc_debug_options debug_defaults_drv = { 713 713 .disable_dmcu = true, 714 714 .force_abm_enable = false, 715 - .timing_trace = false, 716 715 .clock_trace = true, 717 716 .disable_pplib_clock_request = false, 718 717 .pipe_split_policy = MPC_SPLIT_AVOID,

-1

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

··· 692 692 static const struct dc_debug_options debug_defaults_drv = { 693 693 .disable_dmcu = true, 694 694 .force_abm_enable = false, 695 - .timing_trace = false, 696 695 .clock_trace = true, 697 696 .disable_pplib_clock_request = false, 698 697 .pipe_split_policy = MPC_SPLIT_AVOID,

-1

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

··· 685 685 static const struct dc_debug_options debug_defaults_drv = { 686 686 .disable_dmcu = true, 687 687 .force_abm_enable = false, 688 - .timing_trace = false, 689 688 .clock_trace = true, 690 689 .disable_pplib_clock_request = false, 691 690 .pipe_split_policy = MPC_SPLIT_AVOID,

+3 -1

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h

··· 610 610 SR(DCHUBBUB_CLOCK_CNTL), \ 611 611 SR(DCHUBBUB_SDPIF_CFG0), \ 612 612 SR(DCHUBBUB_SDPIF_CFG1), \ 613 - SR(DCHUBBUB_MEM_PWR_MODE_CTRL) 613 + SR(DCHUBBUB_MEM_PWR_MODE_CTRL), \ 614 + SR(DCHUBBUB_TIMEOUT_DETECTION_CTRL1), \ 615 + SR(DCHUBBUB_TIMEOUT_DETECTION_CTRL2) 614 616 615 617 /* DCCG */ 616 618

+59 -43

drivers/gpu/drm/amd/display/dc/spl/dc_spl.c

··· 868 868 return enable_isharp; 869 869 } 870 870 871 + /* Calculate number of tap with adaptive scaling off */ 872 + static void spl_get_taps_non_adaptive_scaler( 873 + struct spl_scratch *spl_scratch, const struct spl_taps *in_taps) 874 + { 875 + if (in_taps->h_taps == 0) { 876 + if (spl_fixpt_ceil(spl_scratch->scl_data.ratios.horz) > 1) 877 + spl_scratch->scl_data.taps.h_taps = spl_min(2 * spl_fixpt_ceil( 878 + spl_scratch->scl_data.ratios.horz), 8); 879 + else 880 + spl_scratch->scl_data.taps.h_taps = 4; 881 + } else 882 + spl_scratch->scl_data.taps.h_taps = in_taps->h_taps; 883 + 884 + if (in_taps->v_taps == 0) { 885 + if (spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert) > 1) 886 + spl_scratch->scl_data.taps.v_taps = spl_min(spl_fixpt_ceil(spl_fixpt_mul_int( 887 + spl_scratch->scl_data.ratios.vert, 2)), 8); 888 + else 889 + spl_scratch->scl_data.taps.v_taps = 4; 890 + } else 891 + spl_scratch->scl_data.taps.v_taps = in_taps->v_taps; 892 + 893 + if (in_taps->v_taps_c == 0) { 894 + if (spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert_c) > 1) 895 + spl_scratch->scl_data.taps.v_taps_c = spl_min(spl_fixpt_ceil(spl_fixpt_mul_int( 896 + spl_scratch->scl_data.ratios.vert_c, 2)), 8); 897 + else 898 + spl_scratch->scl_data.taps.v_taps_c = 4; 899 + } else 900 + spl_scratch->scl_data.taps.v_taps_c = in_taps->v_taps_c; 901 + 902 + if (in_taps->h_taps_c == 0) { 903 + if (spl_fixpt_ceil(spl_scratch->scl_data.ratios.horz_c) > 1) 904 + spl_scratch->scl_data.taps.h_taps_c = spl_min(2 * spl_fixpt_ceil( 905 + spl_scratch->scl_data.ratios.horz_c), 8); 906 + else 907 + spl_scratch->scl_data.taps.h_taps_c = 4; 908 + } else if ((in_taps->h_taps_c % 2) != 0 && in_taps->h_taps_c != 1) 909 + /* Only 1 and even h_taps_c are supported by hw */ 910 + spl_scratch->scl_data.taps.h_taps_c = in_taps->h_taps_c - 1; 911 + else 912 + spl_scratch->scl_data.taps.h_taps_c = in_taps->h_taps_c; 913 + } 914 + 871 915 /* Calculate optimal number of taps */ 872 916 static bool spl_get_optimal_number_of_taps( 873 917 int max_downscale_src_width, struct spl_in *spl_in, struct spl_scratch *spl_scratch, ··· 926 882 927 883 if (spl_scratch->scl_data.viewport.width > spl_scratch->scl_data.h_active && 928 884 max_downscale_src_width != 0 && 929 - spl_scratch->scl_data.viewport.width > max_downscale_src_width) 885 + spl_scratch->scl_data.viewport.width > max_downscale_src_width) { 886 + spl_get_taps_non_adaptive_scaler(spl_scratch, in_taps); 887 + *enable_easf_v = false; 888 + *enable_easf_h = false; 889 + *enable_isharp = false; 930 890 return false; 891 + } 931 892 932 893 /* Disable adaptive scaler and sharpener when integer scaling is enabled */ 933 894 if (spl_in->scaling_quality.integer_scaling) { ··· 954 905 * From programming guide: taps = min{ ceil(2*H_RATIO,1), 8} for downscaling 955 906 * taps = 4 for upscaling 956 907 */ 957 - if (skip_easf) { 958 - if (in_taps->h_taps == 0) { 959 - if (spl_fixpt_ceil(spl_scratch->scl_data.ratios.horz) > 1) 960 - spl_scratch->scl_data.taps.h_taps = spl_min(2 * spl_fixpt_ceil( 961 - spl_scratch->scl_data.ratios.horz), 8); 962 - else 963 - spl_scratch->scl_data.taps.h_taps = 4; 964 - } else 965 - spl_scratch->scl_data.taps.h_taps = in_taps->h_taps; 966 - if (in_taps->v_taps == 0) { 967 - if (spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert) > 1) 968 - spl_scratch->scl_data.taps.v_taps = spl_min(spl_fixpt_ceil(spl_fixpt_mul_int( 969 - spl_scratch->scl_data.ratios.vert, 2)), 8); 970 - else 971 - spl_scratch->scl_data.taps.v_taps = 4; 972 - } else 973 - spl_scratch->scl_data.taps.v_taps = in_taps->v_taps; 974 - if (in_taps->v_taps_c == 0) { 975 - if (spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert_c) > 1) 976 - spl_scratch->scl_data.taps.v_taps_c = spl_min(spl_fixpt_ceil(spl_fixpt_mul_int( 977 - spl_scratch->scl_data.ratios.vert_c, 2)), 8); 978 - else 979 - spl_scratch->scl_data.taps.v_taps_c = 4; 980 - } else 981 - spl_scratch->scl_data.taps.v_taps_c = in_taps->v_taps_c; 982 - if (in_taps->h_taps_c == 0) { 983 - if (spl_fixpt_ceil(spl_scratch->scl_data.ratios.horz_c) > 1) 984 - spl_scratch->scl_data.taps.h_taps_c = spl_min(2 * spl_fixpt_ceil( 985 - spl_scratch->scl_data.ratios.horz_c), 8); 986 - else 987 - spl_scratch->scl_data.taps.h_taps_c = 4; 988 - } else if ((in_taps->h_taps_c % 2) != 0 && in_taps->h_taps_c != 1) 989 - /* Only 1 and even h_taps_c are supported by hw */ 990 - spl_scratch->scl_data.taps.h_taps_c = in_taps->h_taps_c - 1; 991 - else 992 - spl_scratch->scl_data.taps.h_taps_c = in_taps->h_taps_c; 993 - } else { 908 + if (skip_easf) 909 + spl_get_taps_non_adaptive_scaler(spl_scratch, in_taps); 910 + else { 994 911 if (spl_is_yuv420(spl_in->basic_in.format)) { 995 912 spl_scratch->scl_data.taps.h_taps = 6; 996 913 spl_scratch->scl_data.taps.v_taps = 6; ··· 981 966 else 982 967 lb_config = LB_MEMORY_CONFIG_0; 983 968 // Determine max vtap support by calculating how much line buffer can fit 984 - spl_in->funcs->spl_calc_lb_num_partitions(spl_in->basic_out.alpha_en, &spl_scratch->scl_data, 969 + spl_in->callbacks.spl_calc_lb_num_partitions(spl_in->basic_out.alpha_en, &spl_scratch->scl_data, 985 970 lb_config, &num_part_y, &num_part_c); 986 971 /* MAX_V_TAPS = MIN (NUM_LINES - MAX(CEILING(V_RATIO,1)-2, 0), 8) */ 987 972 if (spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert) > 2) ··· 1617 1602 1618 1603 spl_build_isharp_1dlut_from_reference_curve(ratio, setup, adp_sharpness, 1619 1604 scale_to_sharpness_policy); 1620 - dscl_prog_data->isharp_delta = spl_get_pregen_filter_isharp_1D_lut(setup); 1605 + memcpy(dscl_prog_data->isharp_delta, spl_get_pregen_filter_isharp_1D_lut(setup), 1606 + sizeof(uint32_t) * ISHARP_LUT_TABLE_SIZE); 1621 1607 dscl_prog_data->sharpness_level = adp_sharpness.sharpness_level; 1622 1608 1623 1609 dscl_prog_data->isharp_en = 1; // ISHARP_EN ··· 1781 1765 // Clamp 1782 1766 spl_clamp_viewport(&spl_scratch.scl_data.viewport); 1783 1767 1784 - if (!res) 1785 - return res; 1786 - 1787 1768 // Save all calculated parameters in dscl_prog_data structure to program hw registers 1788 1769 spl_set_dscl_prog_data(spl_in, &spl_scratch, spl_out, enable_easf_v, enable_easf_h, enable_isharp); 1770 + 1771 + if (!res) 1772 + return res; 1789 1773 1790 1774 if (spl_in->lls_pref == LLS_PREF_YES) { 1791 1775 if (spl_in->is_hdr_on)

-1

drivers/gpu/drm/amd/display/dc/spl/dc_spl_isharp_filters.h

··· 7 7 8 8 #include "dc_spl_types.h" 9 9 10 - #define ISHARP_LUT_TABLE_SIZE 32 11 10 const uint32_t *spl_get_filter_isharp_1D_lut_0(void); 12 11 const uint32_t *spl_get_filter_isharp_1D_lut_0p5x(void); 13 12 const uint32_t *spl_get_filter_isharp_1D_lut_1p0x(void);

+4 -3

drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h

··· 250 250 ISHARP_DISABLE, 251 251 ISHARP_ENABLE 252 252 }; 253 + #define ISHARP_LUT_TABLE_SIZE 32 253 254 // Below struct holds values that can be directly used to program 254 255 // hardware registers. No conversion/clamping is required 255 256 struct dscl_prog_data { ··· 401 400 uint32_t isharp_nl_en; // ISHARP_NL_EN ? TODO:check this 402 401 struct isharp_lba isharp_lba; // ISHARP_LBA 403 402 struct isharp_fmt isharp_fmt; // ISHARP_FMT 404 - const uint32_t *isharp_delta; 403 + uint32_t isharp_delta[ISHARP_LUT_TABLE_SIZE]; 405 404 struct isharp_nldelta_sclip isharp_nldelta_sclip; // ISHARP_NLDELTA_SCLIP 406 405 /* blur and scale filter */ 407 406 const uint16_t *filter_blur_scale_v; ··· 497 496 SCALE_TO_SHARPNESS_ADJ_YUV = 1, 498 497 SCALE_TO_SHARPNESS_ADJ_ALL = 2 499 498 }; 500 - struct spl_funcs { 499 + struct spl_callbacks { 501 500 void (*spl_calc_lb_num_partitions) 502 501 (bool alpha_en, 503 502 const struct spl_scaler_data *scl_data, ··· 518 517 // Basic slice information 519 518 int odm_slice_index; // ODM Slice Index using get_odm_split_index 520 519 struct spl_taps scaling_quality; // Explicit Scaling Quality 521 - struct spl_funcs *funcs; 520 + struct spl_callbacks callbacks; 522 521 // Inputs for isharp and EASF 523 522 struct adaptive_sharpness adaptive_sharpness; // Adaptive Sharpness 524 523 enum linear_light_scaling lls_pref; // Linear Light Scaling

+17 -17

drivers/gpu/drm/amd/display/dc/spl/spl_fixpt31_32.c

··· 22 22 * result = dividend / divisor 23 23 * *remainder = dividend % divisor 24 24 */ 25 - static inline unsigned long long complete_integer_division_u64( 25 + static inline unsigned long long spl_complete_integer_division_u64( 26 26 unsigned long long dividend, 27 27 unsigned long long divisor, 28 28 unsigned long long *remainder) ··· 60 60 61 61 /* determine integer part */ 62 62 63 - unsigned long long res_value = complete_integer_division_u64( 63 + unsigned long long res_value = spl_complete_integer_division_u64( 64 64 arg1_value, arg2_value, &remainder); 65 65 66 66 SPL_ASSERT(res_value <= (unsigned long long)LONG_MAX); ··· 286 286 * 287 287 * Calculated as Taylor series. 288 288 */ 289 - static struct spl_fixed31_32 fixed31_32_exp_from_taylor_series(struct spl_fixed31_32 arg) 289 + static struct spl_fixed31_32 spl_fixed31_32_exp_from_taylor_series(struct spl_fixed31_32 arg) 290 290 { 291 291 unsigned int n = 9; 292 292 ··· 345 345 346 346 if (m > 0) 347 347 return spl_fixpt_shl( 348 - fixed31_32_exp_from_taylor_series(r), 348 + spl_fixed31_32_exp_from_taylor_series(r), 349 349 (unsigned char)m); 350 350 else 351 351 return spl_fixpt_div_int( 352 - fixed31_32_exp_from_taylor_series(r), 352 + spl_fixed31_32_exp_from_taylor_series(r), 353 353 1LL << -m); 354 354 } else if (arg.value != 0) 355 - return fixed31_32_exp_from_taylor_series(arg); 355 + return spl_fixed31_32_exp_from_taylor_series(arg); 356 356 else 357 357 return spl_fixpt_one; 358 358 } ··· 396 396 * part in 32 bits. It is used in hw programming (scaler) 397 397 */ 398 398 399 - static inline unsigned int ux_dy( 399 + static inline unsigned int spl_ux_dy( 400 400 long long value, 401 401 unsigned int integer_bits, 402 402 unsigned int fractional_bits) ··· 415 415 return result | fractional_part; 416 416 } 417 417 418 - static inline unsigned int clamp_ux_dy( 418 + static inline unsigned int spl_clamp_ux_dy( 419 419 long long value, 420 420 unsigned int integer_bits, 421 421 unsigned int fractional_bits, 422 422 unsigned int min_clamp) 423 423 { 424 - unsigned int truncated_val = ux_dy(value, integer_bits, fractional_bits); 424 + unsigned int truncated_val = spl_ux_dy(value, integer_bits, fractional_bits); 425 425 426 426 if (value >= (1LL << (integer_bits + FIXED31_32_BITS_PER_FRACTIONAL_PART))) 427 427 return (1 << (integer_bits + fractional_bits)) - 1; ··· 433 433 434 434 unsigned int spl_fixpt_u4d19(struct spl_fixed31_32 arg) 435 435 { 436 - return ux_dy(arg.value, 4, 19); 436 + return spl_ux_dy(arg.value, 4, 19); 437 437 } 438 438 439 439 unsigned int spl_fixpt_u3d19(struct spl_fixed31_32 arg) 440 440 { 441 - return ux_dy(arg.value, 3, 19); 441 + return spl_ux_dy(arg.value, 3, 19); 442 442 } 443 443 444 444 unsigned int spl_fixpt_u2d19(struct spl_fixed31_32 arg) 445 445 { 446 - return ux_dy(arg.value, 2, 19); 446 + return spl_ux_dy(arg.value, 2, 19); 447 447 } 448 448 449 449 unsigned int spl_fixpt_u0d19(struct spl_fixed31_32 arg) 450 450 { 451 - return ux_dy(arg.value, 0, 19); 451 + return spl_ux_dy(arg.value, 0, 19); 452 452 } 453 453 454 454 unsigned int spl_fixpt_clamp_u0d14(struct spl_fixed31_32 arg) 455 455 { 456 - return clamp_ux_dy(arg.value, 0, 14, 1); 456 + return spl_clamp_ux_dy(arg.value, 0, 14, 1); 457 457 } 458 458 459 459 unsigned int spl_fixpt_clamp_u0d10(struct spl_fixed31_32 arg) 460 460 { 461 - return clamp_ux_dy(arg.value, 0, 10, 1); 461 + return spl_clamp_ux_dy(arg.value, 0, 10, 1); 462 462 } 463 463 464 464 int spl_fixpt_s4d19(struct spl_fixed31_32 arg) 465 465 { 466 466 if (arg.value < 0) 467 - return -(int)ux_dy(spl_fixpt_abs(arg).value, 4, 19); 467 + return -(int)spl_ux_dy(spl_fixpt_abs(arg).value, 4, 19); 468 468 else 469 - return ux_dy(arg.value, 4, 19); 469 + return spl_ux_dy(arg.value, 4, 19); 470 470 } 471 471 472 472 struct spl_fixed31_32 spl_fixpt_from_ux_dy(unsigned int value,

+1

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

··· 301 301 bool disallow_phy_access; 302 302 bool disable_sldo_opt; 303 303 bool enable_non_transparent_setconfig; 304 + bool lower_hbr3_phy_ssc; 304 305 }; 305 306 306 307 /**

+50 -13

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

··· 495 495 uint8_t gecc_enable; 496 496 uint8_t replay_supported; 497 497 uint8_t replay_reserved[3]; 498 + uint8_t abm_aux_backlight_support; 498 499 }; 499 500 500 501 struct dmub_visual_confirm_color { ··· 695 694 uint32_t ips_disable: 3; /* options to disable ips support*/ 696 695 uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */ 697 696 uint32_t disable_sldo_opt: 1; /**< 1 to disable SLDO optimizations */ 698 - uint32_t reserved : 7; /**< reserved */ 697 + uint32_t lower_hbr3_phy_ssc: 1; /**< 1 to lower hbr3 phy ssc to 0.125 percent */ 698 + uint32_t reserved : 6; /**< reserved */ 699 699 } bits; /**< boot bits */ 700 700 uint32_t all; /**< 32-bit access to bits */ 701 701 }; ··· 728 726 DMUB_SHARED_SHARE_FEATURE__INVALID = 0, 729 727 DMUB_SHARED_SHARE_FEATURE__IPS_FW = 1, 730 728 DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER = 2, 729 + DMUB_SHARED_SHARE_FEATURE__DEBUG_SETUP = 3, 731 730 DMUB_SHARED_STATE_FEATURE__LAST, /* Total number of features. */ 732 731 }; 733 732 ··· 755 752 uint32_t allow_ips1 : 1; /**< 1 is IPS1 is allowed */ 756 753 uint32_t allow_ips2 : 1; /**< 1 is IPS1 is allowed */ 757 754 uint32_t allow_z10 : 1; /**< 1 if Z10 is allowed */ 758 - uint32_t allow_idle : 1; /**< 1 if driver is allowing idle */ 755 + uint32_t allow_idle: 1; /**< 1 if driver is allowing idle */ 759 756 uint32_t reserved_bits : 27; /**< Reversed bits */ 760 757 } bits; 761 758 uint32_t all; ··· 765 762 * IPS FW Version 766 763 */ 767 764 #define DMUB_SHARED_STATE__IPS_FW_VERSION 1 765 + 766 + struct dmub_shared_state_debug_setup { 767 + union { 768 + struct { 769 + uint32_t exclude_points[62]; 770 + } profile_mode; 771 + }; 772 + }; 768 773 769 774 /** 770 775 * struct dmub_shared_state_ips_fw - Firmware state for IPS. ··· 826 815 struct dmub_shared_state_feature_common common; /**< Generic data */ 827 816 struct dmub_shared_state_ips_fw ips_fw; /**< IPS firmware state */ 828 817 struct dmub_shared_state_ips_driver ips_driver; /**< IPS driver state */ 818 + struct dmub_shared_state_debug_setup debug_setup; /**< Debug setup */ 829 819 } data; /**< Shared state data. */ 830 820 }; /* 256-bytes, fixed */ 831 821 ··· 1169 1157 * RETURN: Total residency in microseconds - upper 32 bits 1170 1158 */ 1171 1159 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_HI = 133, 1160 + /** 1161 + * DESC: Setup debug configs. 1162 + */ 1163 + DMUB_GPINT__SETUP_DEBUG_MODE = 136, 1172 1164 }; 1173 1165 1174 1166 /** ··· 4461 4445 uint8_t backlight_control_type; 4462 4446 4463 4447 /** 4464 - * Explicit padding to 4 byte boundary. 4448 + * AUX HW instance. 4465 4449 */ 4466 - uint8_t pad[1]; 4450 + uint8_t aux_inst; 4467 4451 4468 4452 /** 4469 4453 * Minimum luminance in nits. ··· 5187 5171 enum dmub_cmd_secure_display_type { 5188 5172 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 5189 5173 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 5190 - DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY 5174 + DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY, 5175 + DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_STOP_UPDATE, 5176 + DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_WIN_NOTIFY 5177 + }; 5178 + 5179 + #define MAX_ROI_NUM 2 5180 + 5181 + struct dmub_cmd_roi_info { 5182 + uint16_t x_start; 5183 + uint16_t x_end; 5184 + uint16_t y_start; 5185 + uint16_t y_end; 5186 + uint8_t otg_id; 5187 + uint8_t phy_id; 5188 + }; 5189 + 5190 + struct dmub_cmd_roi_window_ctl { 5191 + uint16_t x_start; 5192 + uint16_t x_end; 5193 + uint16_t y_start; 5194 + uint16_t y_end; 5195 + bool enable; 5196 + }; 5197 + 5198 + struct dmub_cmd_roi_ctl_info { 5199 + uint8_t otg_id; 5200 + uint8_t phy_id; 5201 + struct dmub_cmd_roi_window_ctl roi_ctl[MAX_ROI_NUM]; 5191 5202 }; 5192 5203 5193 5204 /** ··· 5225 5182 /** 5226 5183 * Data passed from driver to dmub firmware. 5227 5184 */ 5228 - struct dmub_cmd_roi_info { 5229 - uint16_t x_start; 5230 - uint16_t x_end; 5231 - uint16_t y_start; 5232 - uint16_t y_end; 5233 - uint8_t otg_id; 5234 - uint8_t phy_id; 5235 - } roi_info; 5185 + struct dmub_cmd_roi_info roi_info; 5186 + struct dmub_cmd_roi_ctl_info mul_roi_ctl; 5236 5187 }; 5237 5188 5238 5189 /**

+2 -4

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

··· 426 426 boot_options.bits.ips_sequential_ono = params->ips_sequential_ono; 427 427 boot_options.bits.disable_sldo_opt = params->disable_sldo_opt; 428 428 boot_options.bits.enable_non_transparent_setconfig = params->enable_non_transparent_setconfig; 429 + boot_options.bits.lower_hbr3_phy_ssc = params->lower_hbr3_phy_ssc; 429 430 430 431 REG_WRITE(DMCUB_SCRATCH14, boot_options.all); 431 432 } ··· 464 463 465 464 void dmub_dcn35_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data) 466 465 { 467 - uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset; 466 + uint32_t is_dmub_enabled, is_soft_reset; 468 467 uint32_t is_traceport_enabled, is_cw6_enabled; 469 468 470 469 if (!dmub || !diag_data) ··· 513 512 514 513 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset); 515 514 diag_data->is_dmcub_soft_reset = is_soft_reset; 516 - 517 - REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset); 518 - diag_data->is_dmcub_secure_reset = is_sec_reset; 519 515 520 516 REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled); 521 517 diag_data->is_traceport_en = is_traceport_enabled;

-4

drivers/gpu/drm/amd/display/include/logger_interface.h

··· 52 52 53 53 void post_surface_trace(struct dc *dc); 54 54 55 - void context_timing_trace( 56 - struct dc *dc, 57 - struct resource_context *res_ctx); 58 - 59 55 void context_clock_trace( 60 56 struct dc *dc, 61 57 struct dc_state *context);

-307

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

··· 1399 1399 pwl_rgb[i-1].b, 2), pwl_rgb[i-2].b); 1400 1400 } 1401 1401 1402 - /* todo: all these scale_gamma functions are inherently the same but 1403 - * take different structures as params or different format for ramp 1404 - * values. We could probably implement it in a more generic fashion 1405 - */ 1406 - static void scale_user_regamma_ramp(struct pwl_float_data *pwl_rgb, 1407 - const struct regamma_ramp *ramp, 1408 - struct dividers dividers) 1409 - { 1410 - unsigned short max_driver = 0xFFFF; 1411 - unsigned short max_os = 0xFF00; 1412 - unsigned short scaler = max_os; 1413 - uint32_t i; 1414 - struct pwl_float_data *rgb = pwl_rgb; 1415 - struct pwl_float_data *rgb_last = rgb + GAMMA_RGB_256_ENTRIES - 1; 1416 - 1417 - i = 0; 1418 - do { 1419 - if (ramp->gamma[i] > max_os || 1420 - ramp->gamma[i + 256] > max_os || 1421 - ramp->gamma[i + 512] > max_os) { 1422 - scaler = max_driver; 1423 - break; 1424 - } 1425 - i++; 1426 - } while (i != GAMMA_RGB_256_ENTRIES); 1427 - 1428 - i = 0; 1429 - do { 1430 - rgb->r = dc_fixpt_from_fraction( 1431 - ramp->gamma[i], scaler); 1432 - rgb->g = dc_fixpt_from_fraction( 1433 - ramp->gamma[i + 256], scaler); 1434 - rgb->b = dc_fixpt_from_fraction( 1435 - ramp->gamma[i + 512], scaler); 1436 - 1437 - ++rgb; 1438 - ++i; 1439 - } while (i != GAMMA_RGB_256_ENTRIES); 1440 - 1441 - rgb->r = dc_fixpt_mul(rgb_last->r, 1442 - dividers.divider1); 1443 - rgb->g = dc_fixpt_mul(rgb_last->g, 1444 - dividers.divider1); 1445 - rgb->b = dc_fixpt_mul(rgb_last->b, 1446 - dividers.divider1); 1447 - 1448 - ++rgb; 1449 - 1450 - rgb->r = dc_fixpt_mul(rgb_last->r, 1451 - dividers.divider2); 1452 - rgb->g = dc_fixpt_mul(rgb_last->g, 1453 - dividers.divider2); 1454 - rgb->b = dc_fixpt_mul(rgb_last->b, 1455 - dividers.divider2); 1456 - 1457 - ++rgb; 1458 - 1459 - rgb->r = dc_fixpt_mul(rgb_last->r, 1460 - dividers.divider3); 1461 - rgb->g = dc_fixpt_mul(rgb_last->g, 1462 - dividers.divider3); 1463 - rgb->b = dc_fixpt_mul(rgb_last->b, 1464 - dividers.divider3); 1465 - } 1466 - 1467 1402 /* 1468 1403 * RS3+ color transform DDI - 1D LUT adjustment is composed with regamma here 1469 1404 * Input is evenly distributed in the output color space as specified in ··· 1598 1663 return true; 1599 1664 } 1600 1665 1601 - /* The "old" interpolation uses a complicated scheme to build an array of 1602 - * coefficients while also using an array of 0-255 normalized to 0-1 1603 - * Then there's another loop using both of the above + new scaled user ramp 1604 - * and we concatenate them. It also searches for points of interpolation and 1605 - * uses enums for positions. 1606 - * 1607 - * This function uses a different approach: 1608 - * user ramp is always applied on X with 0/255, 1/255, 2/255, ..., 255/255 1609 - * To find index for hwX , we notice the following: 1610 - * i/255 <= hwX < (i+1)/255 <=> i <= 255*hwX < i+1 1611 - * See apply_lut_1d which is the same principle, but on 4K entry 1D LUT 1612 - * 1613 - * Once the index is known, combined Y is simply: 1614 - * user_ramp(index) + (hwX-index/255)*(user_ramp(index+1) - user_ramp(index) 1615 - * 1616 - * We should switch to this method in all cases, it's simpler and faster 1617 - * ToDo one day - for now this only applies to ADL regamma to avoid regression 1618 - * for regular use cases (sRGB and PQ) 1619 - */ 1620 - static void interpolate_user_regamma(uint32_t hw_points_num, 1621 - struct pwl_float_data *rgb_user, 1622 - bool apply_degamma, 1623 - struct dc_transfer_func_distributed_points *tf_pts) 1624 - { 1625 - uint32_t i; 1626 - uint32_t color = 0; 1627 - int32_t index; 1628 - int32_t index_next; 1629 - struct fixed31_32 *tf_point; 1630 - struct fixed31_32 hw_x; 1631 - struct fixed31_32 norm_factor = 1632 - dc_fixpt_from_int(255); 1633 - struct fixed31_32 norm_x; 1634 - struct fixed31_32 index_f; 1635 - struct fixed31_32 lut1; 1636 - struct fixed31_32 lut2; 1637 - struct fixed31_32 delta_lut; 1638 - struct fixed31_32 delta_index; 1639 - const struct fixed31_32 one = dc_fixpt_from_int(1); 1640 - 1641 - i = 0; 1642 - /* fixed_pt library has problems handling too small values */ 1643 - while (i != 32) { 1644 - tf_pts->red[i] = dc_fixpt_zero; 1645 - tf_pts->green[i] = dc_fixpt_zero; 1646 - tf_pts->blue[i] = dc_fixpt_zero; 1647 - ++i; 1648 - } 1649 - while (i <= hw_points_num + 1) { 1650 - for (color = 0; color < 3; color++) { 1651 - if (color == 0) 1652 - tf_point = &tf_pts->red[i]; 1653 - else if (color == 1) 1654 - tf_point = &tf_pts->green[i]; 1655 - else 1656 - tf_point = &tf_pts->blue[i]; 1657 - 1658 - if (apply_degamma) { 1659 - if (color == 0) 1660 - hw_x = coordinates_x[i].regamma_y_red; 1661 - else if (color == 1) 1662 - hw_x = coordinates_x[i].regamma_y_green; 1663 - else 1664 - hw_x = coordinates_x[i].regamma_y_blue; 1665 - } else 1666 - hw_x = coordinates_x[i].x; 1667 - 1668 - if (dc_fixpt_le(one, hw_x)) 1669 - hw_x = one; 1670 - 1671 - norm_x = dc_fixpt_mul(norm_factor, hw_x); 1672 - index = dc_fixpt_floor(norm_x); 1673 - if (index < 0 || index > 255) 1674 - continue; 1675 - 1676 - index_f = dc_fixpt_from_int(index); 1677 - index_next = (index == 255) ? index : index + 1; 1678 - 1679 - if (color == 0) { 1680 - lut1 = rgb_user[index].r; 1681 - lut2 = rgb_user[index_next].r; 1682 - } else if (color == 1) { 1683 - lut1 = rgb_user[index].g; 1684 - lut2 = rgb_user[index_next].g; 1685 - } else { 1686 - lut1 = rgb_user[index].b; 1687 - lut2 = rgb_user[index_next].b; 1688 - } 1689 - 1690 - // we have everything now, so interpolate 1691 - delta_lut = dc_fixpt_sub(lut2, lut1); 1692 - delta_index = dc_fixpt_sub(norm_x, index_f); 1693 - 1694 - *tf_point = dc_fixpt_add(lut1, 1695 - dc_fixpt_mul(delta_index, delta_lut)); 1696 - } 1697 - ++i; 1698 - } 1699 - } 1700 - 1701 1666 static void build_new_custom_resulted_curve( 1702 1667 uint32_t hw_points_num, 1703 1668 struct dc_transfer_func_distributed_points *tf_pts) ··· 1615 1780 tf_pts->blue[i], dc_fixpt_zero, 1616 1781 dc_fixpt_one); 1617 1782 1618 - ++i; 1619 - } 1620 - } 1621 - 1622 - static void apply_degamma_for_user_regamma(struct pwl_float_data_ex *rgb_regamma, 1623 - uint32_t hw_points_num, struct calculate_buffer *cal_buffer) 1624 - { 1625 - uint32_t i; 1626 - 1627 - struct gamma_coefficients coeff; 1628 - struct pwl_float_data_ex *rgb = rgb_regamma; 1629 - const struct hw_x_point *coord_x = coordinates_x; 1630 - 1631 - build_coefficients(&coeff, TRANSFER_FUNCTION_SRGB); 1632 - 1633 - i = 0; 1634 - while (i != hw_points_num + 1) { 1635 - rgb->r = translate_from_linear_space_ex( 1636 - coord_x->x, &coeff, 0, cal_buffer); 1637 - rgb->g = rgb->r; 1638 - rgb->b = rgb->r; 1639 - ++coord_x; 1640 - ++rgb; 1641 1783 ++i; 1642 1784 } 1643 1785 } ··· 1666 1854 } 1667 1855 1668 1856 #define _EXTRA_POINTS 3 1669 - 1670 - bool calculate_user_regamma_coeff(struct dc_transfer_func *output_tf, 1671 - const struct regamma_lut *regamma, 1672 - struct calculate_buffer *cal_buffer, 1673 - const struct dc_gamma *ramp) 1674 - { 1675 - struct gamma_coefficients coeff; 1676 - const struct hw_x_point *coord_x = coordinates_x; 1677 - uint32_t i = 0; 1678 - 1679 - do { 1680 - coeff.a0[i] = dc_fixpt_from_fraction( 1681 - regamma->coeff.A0[i], 10000000); 1682 - coeff.a1[i] = dc_fixpt_from_fraction( 1683 - regamma->coeff.A1[i], 1000); 1684 - coeff.a2[i] = dc_fixpt_from_fraction( 1685 - regamma->coeff.A2[i], 1000); 1686 - coeff.a3[i] = dc_fixpt_from_fraction( 1687 - regamma->coeff.A3[i], 1000); 1688 - coeff.user_gamma[i] = dc_fixpt_from_fraction( 1689 - regamma->coeff.gamma[i], 1000); 1690 - 1691 - ++i; 1692 - } while (i != 3); 1693 - 1694 - i = 0; 1695 - /* fixed_pt library has problems handling too small values */ 1696 - while (i != 32) { 1697 - output_tf->tf_pts.red[i] = dc_fixpt_zero; 1698 - output_tf->tf_pts.green[i] = dc_fixpt_zero; 1699 - output_tf->tf_pts.blue[i] = dc_fixpt_zero; 1700 - ++coord_x; 1701 - ++i; 1702 - } 1703 - while (i != MAX_HW_POINTS + 1) { 1704 - output_tf->tf_pts.red[i] = translate_from_linear_space_ex( 1705 - coord_x->x, &coeff, 0, cal_buffer); 1706 - output_tf->tf_pts.green[i] = translate_from_linear_space_ex( 1707 - coord_x->x, &coeff, 1, cal_buffer); 1708 - output_tf->tf_pts.blue[i] = translate_from_linear_space_ex( 1709 - coord_x->x, &coeff, 2, cal_buffer); 1710 - ++coord_x; 1711 - ++i; 1712 - } 1713 - 1714 - if (ramp && ramp->type == GAMMA_CS_TFM_1D) 1715 - apply_lut_1d(ramp, MAX_HW_POINTS, &output_tf->tf_pts); 1716 - 1717 - // this function just clamps output to 0-1 1718 - build_new_custom_resulted_curve(MAX_HW_POINTS, &output_tf->tf_pts); 1719 - output_tf->type = TF_TYPE_DISTRIBUTED_POINTS; 1720 - 1721 - return true; 1722 - } 1723 - 1724 - bool calculate_user_regamma_ramp(struct dc_transfer_func *output_tf, 1725 - const struct regamma_lut *regamma, 1726 - struct calculate_buffer *cal_buffer, 1727 - const struct dc_gamma *ramp) 1728 - { 1729 - struct dc_transfer_func_distributed_points *tf_pts = &output_tf->tf_pts; 1730 - struct dividers dividers; 1731 - 1732 - struct pwl_float_data *rgb_user = NULL; 1733 - struct pwl_float_data_ex *rgb_regamma = NULL; 1734 - bool ret = false; 1735 - 1736 - if (regamma == NULL) 1737 - return false; 1738 - 1739 - output_tf->type = TF_TYPE_DISTRIBUTED_POINTS; 1740 - 1741 - rgb_user = kcalloc(GAMMA_RGB_256_ENTRIES + _EXTRA_POINTS, 1742 - sizeof(*rgb_user), 1743 - GFP_KERNEL); 1744 - if (!rgb_user) 1745 - goto rgb_user_alloc_fail; 1746 - 1747 - rgb_regamma = kcalloc(MAX_HW_POINTS + _EXTRA_POINTS, 1748 - sizeof(*rgb_regamma), 1749 - GFP_KERNEL); 1750 - if (!rgb_regamma) 1751 - goto rgb_regamma_alloc_fail; 1752 - 1753 - dividers.divider1 = dc_fixpt_from_fraction(3, 2); 1754 - dividers.divider2 = dc_fixpt_from_int(2); 1755 - dividers.divider3 = dc_fixpt_from_fraction(5, 2); 1756 - 1757 - scale_user_regamma_ramp(rgb_user, &regamma->ramp, dividers); 1758 - 1759 - if (regamma->flags.bits.applyDegamma == 1) { 1760 - apply_degamma_for_user_regamma(rgb_regamma, MAX_HW_POINTS, cal_buffer); 1761 - copy_rgb_regamma_to_coordinates_x(coordinates_x, 1762 - MAX_HW_POINTS, rgb_regamma); 1763 - } 1764 - 1765 - interpolate_user_regamma(MAX_HW_POINTS, rgb_user, 1766 - regamma->flags.bits.applyDegamma, tf_pts); 1767 - 1768 - // no custom HDR curves! 1769 - tf_pts->end_exponent = 0; 1770 - tf_pts->x_point_at_y1_red = 1; 1771 - tf_pts->x_point_at_y1_green = 1; 1772 - tf_pts->x_point_at_y1_blue = 1; 1773 - 1774 - if (ramp && ramp->type == GAMMA_CS_TFM_1D) 1775 - apply_lut_1d(ramp, MAX_HW_POINTS, &output_tf->tf_pts); 1776 - 1777 - // this function just clamps output to 0-1 1778 - build_new_custom_resulted_curve(MAX_HW_POINTS, tf_pts); 1779 - 1780 - ret = true; 1781 - 1782 - kfree(rgb_regamma); 1783 - rgb_regamma_alloc_fail: 1784 - kfree(rgb_user); 1785 - rgb_user_alloc_fail: 1786 - return ret; 1787 - } 1788 1857 1789 1858 bool mod_color_calculate_degamma_params(struct dc_color_caps *dc_caps, 1790 1859 struct dc_transfer_func *input_tf,

-11

drivers/gpu/drm/amd/display/modules/color/color_gamma.h

··· 115 115 struct dc_transfer_func *output_tf, 116 116 const struct dc_gamma *ramp, bool mapUserRamp); 117 117 118 - bool calculate_user_regamma_coeff(struct dc_transfer_func *output_tf, 119 - const struct regamma_lut *regamma, 120 - struct calculate_buffer *cal_buffer, 121 - const struct dc_gamma *ramp); 122 - 123 - bool calculate_user_regamma_ramp(struct dc_transfer_func *output_tf, 124 - const struct regamma_lut *regamma, 125 - struct calculate_buffer *cal_buffer, 126 - const struct dc_gamma *ramp); 127 - 128 - 129 118 #endif /* COLOR_MOD_COLOR_GAMMA_H_ */

+3

drivers/gpu/drm/amd/display/modules/freesync/freesync.c

··· 129 129 unsigned int v_total; 130 130 unsigned int frame_duration_in_ns; 131 131 132 + if (refresh_in_uhz == 0) 133 + return stream->timing.v_total; 134 + 132 135 frame_duration_in_ns = 133 136 ((unsigned int)(div64_u64((1000000000ULL * 1000000), 134 137 refresh_in_uhz)));

+12 -19

drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c

··· 27 27 28 28 #include "hdcp.h" 29 29 30 + static inline uint16_t get_hdmi_rxstatus_msg_size(const uint8_t rxstatus[2]) 31 + { 32 + return HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rxstatus[1]) << 8 | rxstatus[0]; 33 + } 34 + 30 35 static inline enum mod_hdcp_status check_receiver_id_list_ready(struct mod_hdcp *hdcp) 31 36 { 32 37 uint8_t is_ready = 0; ··· 40 35 is_ready = HDCP_2_2_DP_RXSTATUS_READY(hdcp->auth.msg.hdcp2.rxstatus_dp) ? 1 : 0; 41 36 else 42 37 is_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(hdcp->auth.msg.hdcp2.rxstatus[1]) && 43 - (HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(hdcp->auth.msg.hdcp2.rxstatus[1]) << 8 | 44 - hdcp->auth.msg.hdcp2.rxstatus[0])) ? 1 : 0; 38 + get_hdmi_rxstatus_msg_size(hdcp->auth.msg.hdcp2.rxstatus) != 0) ? 1 : 0; 45 39 return is_ready ? MOD_HDCP_STATUS_SUCCESS : 46 40 MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_NOT_READY; 47 41 } ··· 88 84 static enum mod_hdcp_status check_ake_cert_available(struct mod_hdcp *hdcp) 89 85 { 90 86 enum mod_hdcp_status status; 91 - uint16_t size; 92 87 93 88 if (is_dp_hdcp(hdcp)) { 94 89 status = MOD_HDCP_STATUS_SUCCESS; 95 90 } else { 96 91 status = mod_hdcp_read_rxstatus(hdcp); 97 92 if (status == MOD_HDCP_STATUS_SUCCESS) { 98 - size = HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(hdcp->auth.msg.hdcp2.rxstatus[1]) << 8 | 99 - hdcp->auth.msg.hdcp2.rxstatus[0]; 93 + const uint16_t size = get_hdmi_rxstatus_msg_size(hdcp->auth.msg.hdcp2.rxstatus); 100 94 status = (size == sizeof(hdcp->auth.msg.hdcp2.ake_cert)) ? 101 95 MOD_HDCP_STATUS_SUCCESS : 102 96 MOD_HDCP_STATUS_HDCP2_AKE_CERT_PENDING; ··· 106 104 static enum mod_hdcp_status check_h_prime_available(struct mod_hdcp *hdcp) 107 105 { 108 106 enum mod_hdcp_status status; 109 - uint8_t size; 110 107 111 108 status = mod_hdcp_read_rxstatus(hdcp); 112 109 if (status != MOD_HDCP_STATUS_SUCCESS) ··· 116 115 MOD_HDCP_STATUS_SUCCESS : 117 116 MOD_HDCP_STATUS_HDCP2_H_PRIME_PENDING; 118 117 } else { 119 - size = HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(hdcp->auth.msg.hdcp2.rxstatus[1]) << 8 | 120 - hdcp->auth.msg.hdcp2.rxstatus[0]; 118 + const uint16_t size = get_hdmi_rxstatus_msg_size(hdcp->auth.msg.hdcp2.rxstatus); 121 119 status = (size == sizeof(hdcp->auth.msg.hdcp2.ake_h_prime)) ? 122 120 MOD_HDCP_STATUS_SUCCESS : 123 121 MOD_HDCP_STATUS_HDCP2_H_PRIME_PENDING; ··· 128 128 static enum mod_hdcp_status check_pairing_info_available(struct mod_hdcp *hdcp) 129 129 { 130 130 enum mod_hdcp_status status; 131 - uint8_t size; 132 131 133 132 status = mod_hdcp_read_rxstatus(hdcp); 134 133 if (status != MOD_HDCP_STATUS_SUCCESS) ··· 138 139 MOD_HDCP_STATUS_SUCCESS : 139 140 MOD_HDCP_STATUS_HDCP2_PAIRING_INFO_PENDING; 140 141 } else { 141 - size = HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(hdcp->auth.msg.hdcp2.rxstatus[1]) << 8 | 142 - hdcp->auth.msg.hdcp2.rxstatus[0]; 142 + const uint16_t size = get_hdmi_rxstatus_msg_size(hdcp->auth.msg.hdcp2.rxstatus); 143 143 status = (size == sizeof(hdcp->auth.msg.hdcp2.ake_pairing_info)) ? 144 144 MOD_HDCP_STATUS_SUCCESS : 145 145 MOD_HDCP_STATUS_HDCP2_PAIRING_INFO_PENDING; ··· 150 152 static enum mod_hdcp_status poll_l_prime_available(struct mod_hdcp *hdcp) 151 153 { 152 154 enum mod_hdcp_status status = MOD_HDCP_STATUS_FAILURE; 153 - uint8_t size; 154 155 uint16_t max_wait = 20; // units of ms 155 156 uint16_t num_polls = 5; 156 157 uint16_t wait_time = max_wait / num_polls; ··· 164 167 if (status != MOD_HDCP_STATUS_SUCCESS) 165 168 break; 166 169 167 - size = HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(hdcp->auth.msg.hdcp2.rxstatus[1]) << 8 | 168 - hdcp->auth.msg.hdcp2.rxstatus[0]; 170 + const uint16_t size = get_hdmi_rxstatus_msg_size(hdcp->auth.msg.hdcp2.rxstatus); 169 171 status = (size == sizeof(hdcp->auth.msg.hdcp2.lc_l_prime)) ? 170 172 MOD_HDCP_STATUS_SUCCESS : 171 173 MOD_HDCP_STATUS_HDCP2_L_PRIME_PENDING; ··· 177 181 static enum mod_hdcp_status check_stream_ready_available(struct mod_hdcp *hdcp) 178 182 { 179 183 enum mod_hdcp_status status; 180 - uint8_t size; 181 184 182 185 if (is_dp_hdcp(hdcp)) { 183 186 status = MOD_HDCP_STATUS_INVALID_OPERATION; ··· 184 189 status = mod_hdcp_read_rxstatus(hdcp); 185 190 if (status != MOD_HDCP_STATUS_SUCCESS) 186 191 goto out; 187 - size = HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(hdcp->auth.msg.hdcp2.rxstatus[1]) << 8 | 188 - hdcp->auth.msg.hdcp2.rxstatus[0]; 192 + const uint16_t size = get_hdmi_rxstatus_msg_size(hdcp->auth.msg.hdcp2.rxstatus); 189 193 status = (size == sizeof(hdcp->auth.msg.hdcp2.repeater_auth_stream_ready)) ? 190 194 MOD_HDCP_STATUS_SUCCESS : 191 195 MOD_HDCP_STATUS_HDCP2_STREAM_READY_PENDING; ··· 243 249 sizeof(hdcp->auth.msg.hdcp2.rx_id_list); 244 250 else 245 251 hdcp->auth.msg.hdcp2.rx_id_list_size = 246 - HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(hdcp->auth.msg.hdcp2.rxstatus[1]) << 8 | 247 - hdcp->auth.msg.hdcp2.rxstatus[0]; 252 + get_hdmi_rxstatus_msg_size(hdcp->auth.msg.hdcp2.rxstatus); 248 253 } 249 254 out: 250 255 return (*status == MOD_HDCP_STATUS_SUCCESS);

+2

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_sh_mask.h

··· 6199 6199 #define DCHUBBUB_CTRL_STATUS__ROB_UNDERFLOW_STATUS__SHIFT 0x1 6200 6200 #define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_STATUS__SHIFT 0x2 6201 6201 #define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_CLEAR__SHIFT 0x3 6202 + #define DCHUBBUB_CTRL_STATUS__DCHUBBUB_HW_DEBUG__SHIFT 0x4 6202 6203 #define DCHUBBUB_CTRL_STATUS__CSTATE_SWATH_CHK_GOOD_MODE__SHIFT 0x1f 6203 6204 #define DCHUBBUB_CTRL_STATUS__ROB_UNDERFLOW_STATUS_MASK 0x00000002L 6204 6205 #define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_STATUS_MASK 0x00000004L 6205 6206 #define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_CLEAR_MASK 0x00000008L 6207 + #define DCHUBBUB_CTRL_STATUS__DCHUBBUB_HW_DEBUG_MASK 0x3FFFFFF0L 6206 6208 #define DCHUBBUB_CTRL_STATUS__CSTATE_SWATH_CHK_GOOD_MODE_MASK 0x80000000L 6207 6209 //DCHUBBUB_TIMEOUT_DETECTION_CTRL1 6208 6210 #define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS__SHIFT 0x0

+4

drivers/gpu/drm/amd/include/kgd_pp_interface.h

··· 119 119 OD_ACOUSTIC_TARGET, 120 120 OD_FAN_TARGET_TEMPERATURE, 121 121 OD_FAN_MINIMUM_PWM, 122 + OD_FAN_ZERO_RPM_ENABLE, 123 + OD_FAN_ZERO_RPM_STOP_TEMP, 122 124 }; 123 125 124 126 enum amd_pp_sensors { ··· 201 199 PP_OD_EDIT_ACOUSTIC_TARGET, 202 200 PP_OD_EDIT_FAN_TARGET_TEMPERATURE, 203 201 PP_OD_EDIT_FAN_MINIMUM_PWM, 202 + PP_OD_EDIT_FAN_ZERO_RPM_ENABLE, 203 + PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP, 204 204 }; 205 205 206 206 struct pp_states_info {

+127

drivers/gpu/drm/amd/pm/amdgpu_pm.c

··· 4109 4109 return umode; 4110 4110 } 4111 4111 4112 + /** 4113 + * DOC: fan_zero_rpm_enable 4114 + * 4115 + * The amdgpu driver provides a sysfs API for checking and adjusting the 4116 + * zero RPM feature. 4117 + * 4118 + * Reading back the file shows you the current setting and the permitted 4119 + * ranges if changable. 4120 + * 4121 + * Writing an integer to the file, change the setting accordingly. 4122 + * 4123 + * When you have finished the editing, write "c" (commit) to the file to commit 4124 + * your changes. 4125 + * 4126 + * If you want to reset to the default value, write "r" (reset) to the file to 4127 + * reset them. 4128 + */ 4129 + static ssize_t fan_zero_rpm_enable_show(struct kobject *kobj, 4130 + struct kobj_attribute *attr, 4131 + char *buf) 4132 + { 4133 + struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 4134 + struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 4135 + 4136 + return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_FAN_ZERO_RPM_ENABLE, buf); 4137 + } 4138 + 4139 + static ssize_t fan_zero_rpm_enable_store(struct kobject *kobj, 4140 + struct kobj_attribute *attr, 4141 + const char *buf, 4142 + size_t count) 4143 + { 4144 + struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 4145 + struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 4146 + 4147 + return (ssize_t)amdgpu_distribute_custom_od_settings(adev, 4148 + PP_OD_EDIT_FAN_ZERO_RPM_ENABLE, 4149 + buf, 4150 + count); 4151 + } 4152 + 4153 + static umode_t fan_zero_rpm_enable_visible(struct amdgpu_device *adev) 4154 + { 4155 + umode_t umode = 0000; 4156 + 4157 + if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_RETRIEVE) 4158 + umode |= S_IRUSR | S_IRGRP | S_IROTH; 4159 + 4160 + if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_SET) 4161 + umode |= S_IWUSR; 4162 + 4163 + return umode; 4164 + } 4165 + 4166 + /** 4167 + * DOC: fan_zero_rpm_stop_temperature 4168 + * 4169 + * The amdgpu driver provides a sysfs API for checking and adjusting the 4170 + * zero RPM stop temperature feature. 4171 + * 4172 + * Reading back the file shows you the current setting and the permitted 4173 + * ranges if changable. 4174 + * 4175 + * Writing an integer to the file, change the setting accordingly. 4176 + * 4177 + * When you have finished the editing, write "c" (commit) to the file to commit 4178 + * your changes. 4179 + * 4180 + * If you want to reset to the default value, write "r" (reset) to the file to 4181 + * reset them. 4182 + * 4183 + * This setting works only if the Zero RPM setting is enabled. It adjusts the 4184 + * temperature below which the fan can stop. 4185 + */ 4186 + static ssize_t fan_zero_rpm_stop_temp_show(struct kobject *kobj, 4187 + struct kobj_attribute *attr, 4188 + char *buf) 4189 + { 4190 + struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 4191 + struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 4192 + 4193 + return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_FAN_ZERO_RPM_STOP_TEMP, buf); 4194 + } 4195 + 4196 + static ssize_t fan_zero_rpm_stop_temp_store(struct kobject *kobj, 4197 + struct kobj_attribute *attr, 4198 + const char *buf, 4199 + size_t count) 4200 + { 4201 + struct od_kobj *container = container_of(kobj, struct od_kobj, kobj); 4202 + struct amdgpu_device *adev = (struct amdgpu_device *)container->priv; 4203 + 4204 + return (ssize_t)amdgpu_distribute_custom_od_settings(adev, 4205 + PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP, 4206 + buf, 4207 + count); 4208 + } 4209 + 4210 + static umode_t fan_zero_rpm_stop_temp_visible(struct amdgpu_device *adev) 4211 + { 4212 + umode_t umode = 0000; 4213 + 4214 + if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_ZERO_RPM_STOP_TEMP_RETRIEVE) 4215 + umode |= S_IRUSR | S_IRGRP | S_IROTH; 4216 + 4217 + if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_ZERO_RPM_STOP_TEMP_SET) 4218 + umode |= S_IWUSR; 4219 + 4220 + return umode; 4221 + } 4222 + 4112 4223 static struct od_feature_set amdgpu_od_set = { 4113 4224 .containers = { 4114 4225 [0] = { ··· 4263 4152 .is_visible = fan_minimum_pwm_visible, 4264 4153 .show = fan_minimum_pwm_show, 4265 4154 .store = fan_minimum_pwm_store, 4155 + }, 4156 + }, 4157 + [5] = { 4158 + .name = "fan_zero_rpm_enable", 4159 + .ops = { 4160 + .is_visible = fan_zero_rpm_enable_visible, 4161 + .show = fan_zero_rpm_enable_show, 4162 + .store = fan_zero_rpm_enable_store, 4163 + }, 4164 + }, 4165 + [6] = { 4166 + .name = "fan_zero_rpm_stop_temperature", 4167 + .ops = { 4168 + .is_visible = fan_zero_rpm_stop_temp_visible, 4169 + .show = fan_zero_rpm_stop_temp_show, 4170 + .store = fan_zero_rpm_stop_temp_store, 4266 4171 }, 4267 4172 }, 4268 4173 },

+4

drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h

··· 328 328 #define OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_SET BIT(7) 329 329 #define OD_OPS_SUPPORT_FAN_MINIMUM_PWM_RETRIEVE BIT(8) 330 330 #define OD_OPS_SUPPORT_FAN_MINIMUM_PWM_SET BIT(9) 331 + #define OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_RETRIEVE BIT(10) 332 + #define OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_SET BIT(11) 333 + #define OD_OPS_SUPPORT_FAN_ZERO_RPM_STOP_TEMP_RETRIEVE BIT(12) 334 + #define OD_OPS_SUPPORT_FAN_ZERO_RPM_STOP_TEMP_SET BIT(13) 331 335 332 336 struct amdgpu_pm { 333 337 struct mutex mutex;

+40 -15

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

··· 252 252 if (atomic_read(&power_gate->vcn_gated) ^ enable) 253 253 return 0; 254 254 255 - ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 255 + ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable, 0xff); 256 256 if (!ret) 257 257 atomic_set(&power_gate->vcn_gated, !enable); 258 258 ··· 1261 1261 smu->watermarks_bitmap = 0; 1262 1262 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1263 1263 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1264 + smu->user_dpm_profile.user_workload_mask = 0; 1264 1265 1265 1266 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 1266 1267 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1267 1268 atomic_set(&smu->smu_power.power_gate.vpe_gated, 1); 1268 1269 atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1); 1269 1270 1270 - smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 1271 - smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 1272 - smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 1273 - smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 1274 - smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 1275 - smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 1276 - smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 1271 + smu->workload_priority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 1272 + smu->workload_priority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 1273 + smu->workload_priority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 1274 + smu->workload_priority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 1275 + smu->workload_priority[PP_SMC_POWER_PROFILE_VR] = 4; 1276 + smu->workload_priority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 1277 + smu->workload_priority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 1277 1278 1278 1279 if (smu->is_apu || 1279 - !smu_is_workload_profile_available(smu, PP_SMC_POWER_PROFILE_FULLSCREEN3D)) 1280 - smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 1281 - else 1282 - smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D]; 1280 + !smu_is_workload_profile_available(smu, PP_SMC_POWER_PROFILE_FULLSCREEN3D)) { 1281 + smu->driver_workload_mask = 1282 + 1 << smu->workload_priority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 1283 + } else { 1284 + smu->driver_workload_mask = 1285 + 1 << smu->workload_priority[PP_SMC_POWER_PROFILE_FULLSCREEN3D]; 1286 + smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1287 + } 1283 1288 1289 + smu->workload_mask = smu->driver_workload_mask | 1290 + smu->user_dpm_profile.user_workload_mask; 1284 1291 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1285 1292 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1286 1293 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; ··· 2362 2355 return -EINVAL; 2363 2356 2364 2357 if (!en) { 2365 - smu->workload_mask &= ~(1 << smu->workload_prority[type]); 2358 + smu->driver_workload_mask &= ~(1 << smu->workload_priority[type]); 2366 2359 index = fls(smu->workload_mask); 2367 2360 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2368 2361 workload[0] = smu->workload_setting[index]; 2369 2362 } else { 2370 - smu->workload_mask |= (1 << smu->workload_prority[type]); 2363 + smu->driver_workload_mask |= (1 << smu->workload_priority[type]); 2371 2364 index = fls(smu->workload_mask); 2372 2365 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 2373 2366 workload[0] = smu->workload_setting[index]; 2374 2367 } 2368 + 2369 + smu->workload_mask = smu->driver_workload_mask | 2370 + smu->user_dpm_profile.user_workload_mask; 2375 2371 2376 2372 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2377 2373 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) ··· 2895 2885 clk_type = SMU_OD_FAN_TARGET_TEMPERATURE; break; 2896 2886 case OD_FAN_MINIMUM_PWM: 2897 2887 clk_type = SMU_OD_FAN_MINIMUM_PWM; break; 2888 + case OD_FAN_ZERO_RPM_ENABLE: 2889 + clk_type = SMU_OD_FAN_ZERO_RPM_ENABLE; break; 2890 + case OD_FAN_ZERO_RPM_STOP_TEMP: 2891 + clk_type = SMU_OD_FAN_ZERO_RPM_STOP_TEMP; break; 2898 2892 default: 2899 2893 clk_type = SMU_CLK_COUNT; break; 2900 2894 } ··· 3070 3056 uint32_t param_size) 3071 3057 { 3072 3058 struct smu_context *smu = handle; 3059 + int ret; 3073 3060 3074 3061 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3075 3062 !smu->ppt_funcs->set_power_profile_mode) 3076 3063 return -EOPNOTSUPP; 3077 3064 3078 - return smu_bump_power_profile_mode(smu, param, param_size); 3065 + if (smu->user_dpm_profile.user_workload_mask & 3066 + (1 << smu->workload_priority[param[param_size]])) 3067 + return 0; 3068 + 3069 + smu->user_dpm_profile.user_workload_mask = 3070 + (1 << smu->workload_priority[param[param_size]]); 3071 + smu->workload_mask = smu->user_dpm_profile.user_workload_mask | 3072 + smu->driver_workload_mask; 3073 + ret = smu_bump_power_profile_mode(smu, param, param_size); 3074 + 3075 + return ret; 3079 3076 } 3080 3077 3081 3078 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode)

+4 -2

drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h

··· 240 240 /* user clock state information */ 241 241 uint32_t clk_mask[SMU_CLK_COUNT]; 242 242 uint32_t clk_dependency; 243 + uint32_t user_workload_mask; 243 244 }; 244 245 245 246 #define SMU_TABLE_INIT(tables, table_id, s, a, d) \ ··· 558 557 bool disable_uclk_switch; 559 558 560 559 uint32_t workload_mask; 561 - uint32_t workload_prority[WORKLOAD_POLICY_MAX]; 560 + uint32_t driver_workload_mask; 561 + uint32_t workload_priority[WORKLOAD_POLICY_MAX]; 562 562 uint32_t workload_setting[WORKLOAD_POLICY_MAX]; 563 563 uint32_t power_profile_mode; 564 564 uint32_t default_power_profile_mode; ··· 741 739 * @dpm_set_vcn_enable: Enable/disable VCN engine dynamic power 742 740 * management. 743 741 */ 744 - int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable); 742 + int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable, int inst); 745 743 746 744 /** 747 745 * @dpm_set_jpeg_enable: Enable/disable JPEG engine dynamic power

+2

drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h

··· 313 313 SMU_OD_ACOUSTIC_TARGET, 314 314 SMU_OD_FAN_TARGET_TEMPERATURE, 315 315 SMU_OD_FAN_MINIMUM_PWM, 316 + SMU_OD_FAN_ZERO_RPM_ENABLE, 317 + SMU_OD_FAN_ZERO_RPM_STOP_TEMP, 316 318 SMU_CLK_COUNT, 317 319 }; 318 320

+2 -1

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h

··· 255 255 uint64_t event_arg); 256 256 257 257 int smu_v13_0_set_vcn_enable(struct smu_context *smu, 258 - bool enable); 258 + bool enable, 259 + int inst); 259 260 260 261 int smu_v13_0_set_jpeg_enable(struct smu_context *smu, 261 262 bool enable);

+2 -1

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h

··· 210 210 uint64_t event_arg); 211 211 212 212 int smu_v14_0_set_vcn_enable(struct smu_context *smu, 213 - bool enable); 213 + bool enable, 214 + int inst); 214 215 215 216 int smu_v14_0_set_jpeg_enable(struct smu_context *smu, 216 217 bool enable);

+5 -4

drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

··· 1455 1455 return -EINVAL; 1456 1456 } 1457 1457 1458 - 1459 1458 if ((profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) && 1460 1459 (smu->smc_fw_version >= 0x360d00)) { 1461 1460 if (size != 10) ··· 1522 1523 1523 1524 ret = smu_cmn_send_smc_msg_with_param(smu, 1524 1525 SMU_MSG_SetWorkloadMask, 1525 - 1 << workload_type, 1526 + smu->workload_mask, 1526 1527 NULL); 1527 1528 if (ret) { 1528 1529 dev_err(smu->adev->dev, "Fail to set workload type %d\n", workload_type); 1529 1530 return ret; 1530 1531 } 1531 1532 1532 - smu->power_profile_mode = profile_mode; 1533 + smu_cmn_assign_power_profile(smu); 1533 1534 1534 1535 return 0; 1535 1536 } ··· 1570 1571 return !!(feature_enabled & SMC_DPM_FEATURE); 1571 1572 } 1572 1573 1573 - static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 1574 + static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, 1575 + bool enable, 1576 + int inst) 1574 1577 { 1575 1578 int ret = 0; 1576 1579

+7 -2

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

··· 1135 1135 return 0; 1136 1136 } 1137 1137 1138 - static int navi10_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 1138 + static int navi10_dpm_set_vcn_enable(struct smu_context *smu, 1139 + bool enable, 1140 + int inst) 1139 1141 { 1140 1142 int ret = 0; 1141 1143 ··· 2083 2081 smu->power_profile_mode); 2084 2082 if (workload_type < 0) 2085 2083 return -EINVAL; 2084 + 2086 2085 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask, 2087 - 1 << workload_type, NULL); 2086 + smu->workload_mask, NULL); 2088 2087 if (ret) 2089 2088 dev_err(smu->adev->dev, "[%s] Failed to set work load mask!", __func__); 2089 + else 2090 + smu_cmn_assign_power_profile(smu); 2090 2091 2091 2092 return ret; 2092 2093 }

+7 -2

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

··· 1152 1152 return 0; 1153 1153 } 1154 1154 1155 - static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 1155 + static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, 1156 + bool enable, 1157 + int inst) 1156 1158 { 1157 1159 struct amdgpu_device *adev = smu->adev; 1158 1160 int i, ret = 0; ··· 1788 1786 smu->power_profile_mode); 1789 1787 if (workload_type < 0) 1790 1788 return -EINVAL; 1789 + 1791 1790 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask, 1792 - 1 << workload_type, NULL); 1791 + smu->workload_mask, NULL); 1793 1792 if (ret) 1794 1793 dev_err(smu->adev->dev, "[%s] Failed to set work load mask!", __func__); 1794 + else 1795 + smu_cmn_assign_power_profile(smu); 1795 1796 1796 1797 return ret; 1797 1798 }

+5 -3

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

··· 461 461 return smu_v11_0_init_smc_tables(smu); 462 462 } 463 463 464 - static int vangogh_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 464 + static int vangogh_dpm_set_vcn_enable(struct smu_context *smu, 465 + bool enable, 466 + int inst) 465 467 { 466 468 int ret = 0; 467 469 ··· 1081 1079 } 1082 1080 1083 1081 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify, 1084 - 1 << workload_type, 1082 + smu->workload_mask, 1085 1083 NULL); 1086 1084 if (ret) { 1087 1085 dev_err_once(smu->adev->dev, "Fail to set workload type %d\n", ··· 1089 1087 return ret; 1090 1088 } 1091 1089 1092 - smu->power_profile_mode = profile_mode; 1090 + smu_cmn_assign_power_profile(smu); 1093 1091 1094 1092 return 0; 1095 1093 }

+5 -3

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

··· 645 645 return pm_type; 646 646 } 647 647 648 - static int renoir_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 648 + static int renoir_dpm_set_vcn_enable(struct smu_context *smu, 649 + bool enable, 650 + int inst) 649 651 { 650 652 int ret = 0; 651 653 ··· 892 890 } 893 891 894 892 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify, 895 - 1 << workload_type, 893 + smu->workload_mask, 896 894 NULL); 897 895 if (ret) { 898 896 dev_err_once(smu->adev->dev, "Fail to set workload type %d\n", workload_type); 899 897 return ret; 900 898 } 901 899 902 - smu->power_profile_mode = profile_mode; 900 + smu_cmn_assign_power_profile(smu); 903 901 904 902 return 0; 905 903 }

+2 -1

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

··· 2104 2104 } 2105 2105 2106 2106 int smu_v13_0_set_vcn_enable(struct smu_context *smu, 2107 - bool enable) 2107 + bool enable, 2108 + int inst) 2108 2109 { 2109 2110 struct amdgpu_device *adev = smu->adev; 2110 2111 int i, ret = 0;

+122 -6

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

··· 107 107 #define PP_OD_FEATURE_FAN_ACOUSTIC_TARGET 8 108 108 #define PP_OD_FEATURE_FAN_TARGET_TEMPERATURE 9 109 109 #define PP_OD_FEATURE_FAN_MINIMUM_PWM 10 110 + #define PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE 11 111 + #define PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP 12 110 112 111 113 #define LINK_SPEED_MAX 3 112 114 ··· 1132 1130 od_min_setting = overdrive_lowerlimits->FanMinimumPwm; 1133 1131 od_max_setting = overdrive_upperlimits->FanMinimumPwm; 1134 1132 break; 1133 + case PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE: 1134 + od_min_setting = overdrive_lowerlimits->FanZeroRpmEnable; 1135 + od_max_setting = overdrive_upperlimits->FanZeroRpmEnable; 1136 + break; 1137 + case PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP: 1138 + od_min_setting = overdrive_lowerlimits->FanZeroRpmStopTemp; 1139 + od_max_setting = overdrive_upperlimits->FanZeroRpmStopTemp; 1140 + break; 1135 1141 default: 1136 1142 od_min_setting = od_max_setting = INT_MAX; 1137 1143 break; ··· 1460 1450 min_value, max_value); 1461 1451 break; 1462 1452 1453 + case SMU_OD_FAN_ZERO_RPM_ENABLE: 1454 + if (!smu_v13_0_0_is_od_feature_supported(smu, 1455 + PP_OD_FEATURE_ZERO_FAN_BIT)) 1456 + break; 1457 + 1458 + size += sysfs_emit_at(buf, size, "FAN_ZERO_RPM_ENABLE:\n"); 1459 + size += sysfs_emit_at(buf, size, "%d\n", 1460 + (int)od_table->OverDriveTable.FanZeroRpmEnable); 1461 + 1462 + size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 1463 + smu_v13_0_0_get_od_setting_limits(smu, 1464 + PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE, 1465 + &min_value, 1466 + &max_value); 1467 + size += sysfs_emit_at(buf, size, "ZERO_RPM_ENABLE: %u %u\n", 1468 + min_value, max_value); 1469 + break; 1470 + 1471 + case SMU_OD_FAN_ZERO_RPM_STOP_TEMP: 1472 + if (!smu_v13_0_0_is_od_feature_supported(smu, 1473 + PP_OD_FEATURE_ZERO_FAN_BIT)) 1474 + break; 1475 + 1476 + size += sysfs_emit_at(buf, size, "FAN_ZERO_RPM_STOP_TEMPERATURE:\n"); 1477 + size += sysfs_emit_at(buf, size, "%d\n", 1478 + (int)od_table->OverDriveTable.FanZeroRpmStopTemp); 1479 + 1480 + size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 1481 + smu_v13_0_0_get_od_setting_limits(smu, 1482 + PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP, 1483 + &min_value, 1484 + &max_value); 1485 + size += sysfs_emit_at(buf, size, "ZERO_RPM_STOP_TEMPERATURE: %u %u\n", 1486 + min_value, max_value); 1487 + break; 1488 + 1463 1489 case SMU_OD_RANGE: 1464 1490 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT) && 1465 1491 !smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT) && ··· 1592 1546 boot_overdrive_table->OverDriveTable.FanMinimumPwm; 1593 1547 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO; 1594 1548 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT); 1549 + break; 1550 + case PP_OD_EDIT_FAN_ZERO_RPM_ENABLE: 1551 + od_table->OverDriveTable.FanZeroRpmEnable = 1552 + boot_overdrive_table->OverDriveTable.FanZeroRpmEnable; 1553 + od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT); 1554 + break; 1555 + case PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP: 1556 + od_table->OverDriveTable.FanZeroRpmStopTemp = 1557 + boot_overdrive_table->OverDriveTable.FanZeroRpmStopTemp; 1558 + od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT); 1595 1559 break; 1596 1560 default: 1597 1561 dev_info(adev->dev, "Invalid table index: %ld\n", input); ··· 1896 1840 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT); 1897 1841 break; 1898 1842 1843 + case PP_OD_EDIT_FAN_ZERO_RPM_ENABLE: 1844 + if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_ZERO_FAN_BIT)) { 1845 + dev_warn(adev->dev, "Zero RPM setting not supported!\n"); 1846 + return -ENOTSUPP; 1847 + } 1848 + 1849 + smu_v13_0_0_get_od_setting_limits(smu, 1850 + PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE, 1851 + &minimum, 1852 + &maximum); 1853 + if (input[0] < minimum || 1854 + input[0] > maximum) { 1855 + dev_info(adev->dev, "zero RPM enable setting(%ld) must be within [%d, %d]!\n", 1856 + input[0], minimum, maximum); 1857 + return -EINVAL; 1858 + } 1859 + 1860 + od_table->OverDriveTable.FanZeroRpmEnable = input[0]; 1861 + od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT); 1862 + break; 1863 + 1864 + case PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP: 1865 + if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_ZERO_FAN_BIT)) { 1866 + dev_warn(adev->dev, "Zero RPM setting not supported!\n"); 1867 + return -ENOTSUPP; 1868 + } 1869 + 1870 + smu_v13_0_0_get_od_setting_limits(smu, 1871 + PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP, 1872 + &minimum, 1873 + &maximum); 1874 + if (input[0] < minimum || 1875 + input[0] > maximum) { 1876 + dev_info(adev->dev, "zero RPM stop temperature setting(%ld) must be within [%d, %d]!\n", 1877 + input[0], minimum, maximum); 1878 + return -EINVAL; 1879 + } 1880 + 1881 + od_table->OverDriveTable.FanZeroRpmStopTemp = input[0]; 1882 + od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT); 1883 + break; 1884 + 1899 1885 case PP_OD_RESTORE_DEFAULT_TABLE: 1900 1886 if (size == 1) { 1901 1887 ret = smu_v13_0_0_od_restore_table_single(smu, input[0]); ··· 2208 2110 OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_RETRIEVE | 2209 2111 OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_SET | 2210 2112 OD_OPS_SUPPORT_FAN_MINIMUM_PWM_RETRIEVE | 2211 - OD_OPS_SUPPORT_FAN_MINIMUM_PWM_SET; 2113 + OD_OPS_SUPPORT_FAN_MINIMUM_PWM_SET | 2114 + OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_RETRIEVE | 2115 + OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_SET | 2116 + OD_OPS_SUPPORT_FAN_ZERO_RPM_STOP_TEMP_RETRIEVE | 2117 + OD_OPS_SUPPORT_FAN_ZERO_RPM_STOP_TEMP_SET; 2212 2118 } 2213 2119 2214 2120 static int smu_v13_0_0_set_default_od_settings(struct smu_context *smu) ··· 2278 2176 user_od_table_bak.OverDriveTable.FanTargetTemperature; 2279 2177 user_od_table->OverDriveTable.FanMinimumPwm = 2280 2178 user_od_table_bak.OverDriveTable.FanMinimumPwm; 2179 + user_od_table->OverDriveTable.FanZeroRpmEnable = 2180 + user_od_table_bak.OverDriveTable.FanZeroRpmEnable; 2181 + user_od_table->OverDriveTable.FanZeroRpmStopTemp = 2182 + user_od_table_bak.OverDriveTable.FanZeroRpmStopTemp; 2281 2183 } 2282 2184 2283 2185 smu_v13_0_0_set_supported_od_feature_mask(smu); ··· 2579 2473 DpmActivityMonitorCoeffInt_t *activity_monitor = 2580 2474 &(activity_monitor_external.DpmActivityMonitorCoeffInt); 2581 2475 int workload_type, ret = 0; 2582 - u32 workload_mask, selected_workload_mask; 2476 + u32 workload_mask; 2583 2477 2584 2478 smu->power_profile_mode = input[size]; 2585 2479 ··· 2646 2540 if (workload_type < 0) 2647 2541 return -EINVAL; 2648 2542 2649 - selected_workload_mask = workload_mask = 1 << workload_type; 2543 + workload_mask = 1 << workload_type; 2650 2544 2651 2545 /* Add optimizations for SMU13.0.0/10. Reuse the power saving profile */ 2652 2546 if ((amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 0) && ··· 2661 2555 workload_mask |= 1 << workload_type; 2662 2556 } 2663 2557 2558 + smu->workload_mask |= workload_mask; 2664 2559 ret = smu_cmn_send_smc_msg_with_param(smu, 2665 2560 SMU_MSG_SetWorkloadMask, 2666 - workload_mask, 2561 + smu->workload_mask, 2667 2562 NULL); 2668 - if (!ret) 2669 - smu->workload_mask = selected_workload_mask; 2563 + if (!ret) { 2564 + smu_cmn_assign_power_profile(smu); 2565 + if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING) { 2566 + workload_type = smu_cmn_to_asic_specific_index(smu, 2567 + CMN2ASIC_MAPPING_WORKLOAD, 2568 + PP_SMC_POWER_PROFILE_FULLSCREEN3D); 2569 + smu->power_profile_mode = smu->workload_mask & (1 << workload_type) 2570 + ? PP_SMC_POWER_PROFILE_FULLSCREEN3D 2571 + : PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 2572 + } 2573 + } 2670 2574 2671 2575 return ret; 2672 2576 }

+3 -1

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

··· 193 193 return ret; 194 194 } 195 195 196 - static int smu_v13_0_5_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 196 + static int smu_v13_0_5_dpm_set_vcn_enable(struct smu_context *smu, 197 + bool enable, 198 + int inst) 197 199 { 198 200 int ret = 0; 199 201

+110 -3

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

··· 83 83 #define PP_OD_FEATURE_FAN_ACOUSTIC_TARGET 8 84 84 #define PP_OD_FEATURE_FAN_TARGET_TEMPERATURE 9 85 85 #define PP_OD_FEATURE_FAN_MINIMUM_PWM 10 86 + #define PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE 11 87 + #define PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP 12 86 88 87 89 #define LINK_SPEED_MAX 3 88 90 ··· 1121 1119 od_min_setting = overdrive_lowerlimits->FanMinimumPwm; 1122 1120 od_max_setting = overdrive_upperlimits->FanMinimumPwm; 1123 1121 break; 1122 + case PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE: 1123 + od_min_setting = overdrive_lowerlimits->FanZeroRpmEnable; 1124 + od_max_setting = overdrive_upperlimits->FanZeroRpmEnable; 1125 + break; 1126 + case PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP: 1127 + od_min_setting = overdrive_lowerlimits->FanZeroRpmStopTemp; 1128 + od_max_setting = overdrive_upperlimits->FanZeroRpmStopTemp; 1129 + break; 1124 1130 default: 1125 1131 od_min_setting = od_max_setting = INT_MAX; 1126 1132 break; ··· 1449 1439 min_value, max_value); 1450 1440 break; 1451 1441 1442 + case SMU_OD_FAN_ZERO_RPM_ENABLE: 1443 + if (!smu_v13_0_7_is_od_feature_supported(smu, 1444 + PP_OD_FEATURE_ZERO_FAN_BIT)) 1445 + break; 1446 + 1447 + size += sysfs_emit_at(buf, size, "FAN_ZERO_RPM_ENABLE:\n"); 1448 + size += sysfs_emit_at(buf, size, "%d\n", 1449 + (int)od_table->OverDriveTable.FanZeroRpmEnable); 1450 + 1451 + size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 1452 + smu_v13_0_7_get_od_setting_limits(smu, 1453 + PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE, 1454 + &min_value, 1455 + &max_value); 1456 + size += sysfs_emit_at(buf, size, "ZERO_RPM_ENABLE: %u %u\n", 1457 + min_value, max_value); 1458 + break; 1459 + 1460 + case SMU_OD_FAN_ZERO_RPM_STOP_TEMP: 1461 + if (!smu_v13_0_7_is_od_feature_supported(smu, 1462 + PP_OD_FEATURE_ZERO_FAN_BIT)) 1463 + break; 1464 + 1465 + size += sysfs_emit_at(buf, size, "FAN_ZERO_RPM_STOP_TEMPERATURE:\n"); 1466 + size += sysfs_emit_at(buf, size, "%d\n", 1467 + (int)od_table->OverDriveTable.FanZeroRpmStopTemp); 1468 + 1469 + size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 1470 + smu_v13_0_7_get_od_setting_limits(smu, 1471 + PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP, 1472 + &min_value, 1473 + &max_value); 1474 + size += sysfs_emit_at(buf, size, "ZERO_RPM_STOP_TEMPERATURE: %u %u\n", 1475 + min_value, max_value); 1476 + break; 1477 + 1452 1478 case SMU_OD_RANGE: 1453 1479 if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT) && 1454 1480 !smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT) && ··· 1580 1534 boot_overdrive_table->OverDriveTable.FanMinimumPwm; 1581 1535 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO; 1582 1536 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT); 1537 + break; 1538 + case PP_OD_EDIT_FAN_ZERO_RPM_ENABLE: 1539 + od_table->OverDriveTable.FanZeroRpmEnable = 1540 + boot_overdrive_table->OverDriveTable.FanZeroRpmEnable; 1541 + od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT); 1542 + break; 1543 + case PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP: 1544 + od_table->OverDriveTable.FanZeroRpmStopTemp = 1545 + boot_overdrive_table->OverDriveTable.FanZeroRpmStopTemp; 1546 + od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT); 1583 1547 break; 1584 1548 default: 1585 1549 dev_info(adev->dev, "Invalid table index: %ld\n", input); ··· 1884 1828 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT); 1885 1829 break; 1886 1830 1831 + case PP_OD_EDIT_FAN_ZERO_RPM_ENABLE: 1832 + if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_ZERO_FAN_BIT)) { 1833 + dev_warn(adev->dev, "Zero RPM setting not supported!\n"); 1834 + return -ENOTSUPP; 1835 + } 1836 + 1837 + smu_v13_0_7_get_od_setting_limits(smu, 1838 + PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE, 1839 + &minimum, 1840 + &maximum); 1841 + if (input[0] < minimum || 1842 + input[0] > maximum) { 1843 + dev_info(adev->dev, "zero RPM enable setting(%ld) must be within [%d, %d]!\n", 1844 + input[0], minimum, maximum); 1845 + return -EINVAL; 1846 + } 1847 + 1848 + od_table->OverDriveTable.FanZeroRpmEnable = input[0]; 1849 + od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT); 1850 + break; 1851 + 1852 + case PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP: 1853 + if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_ZERO_FAN_BIT)) { 1854 + dev_warn(adev->dev, "Zero RPM setting not supported!\n"); 1855 + return -ENOTSUPP; 1856 + } 1857 + 1858 + smu_v13_0_7_get_od_setting_limits(smu, 1859 + PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP, 1860 + &minimum, 1861 + &maximum); 1862 + if (input[0] < minimum || 1863 + input[0] > maximum) { 1864 + dev_info(adev->dev, "zero RPM stop temperature setting(%ld) must be within [%d, %d]!\n", 1865 + input[0], minimum, maximum); 1866 + return -EINVAL; 1867 + } 1868 + 1869 + od_table->OverDriveTable.FanZeroRpmStopTemp = input[0]; 1870 + od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT); 1871 + break; 1872 + 1887 1873 case PP_OD_RESTORE_DEFAULT_TABLE: 1888 1874 if (size == 1) { 1889 1875 ret = smu_v13_0_7_od_restore_table_single(smu, input[0]); ··· 2192 2094 OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_RETRIEVE | 2193 2095 OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_SET | 2194 2096 OD_OPS_SUPPORT_FAN_MINIMUM_PWM_RETRIEVE | 2195 - OD_OPS_SUPPORT_FAN_MINIMUM_PWM_SET; 2097 + OD_OPS_SUPPORT_FAN_MINIMUM_PWM_SET | 2098 + OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_RETRIEVE | 2099 + OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_SET | 2100 + OD_OPS_SUPPORT_FAN_ZERO_RPM_STOP_TEMP_RETRIEVE | 2101 + OD_OPS_SUPPORT_FAN_ZERO_RPM_STOP_TEMP_SET; 2196 2102 } 2197 2103 2198 2104 static int smu_v13_0_7_set_default_od_settings(struct smu_context *smu) ··· 2262 2160 user_od_table_bak.OverDriveTable.FanTargetTemperature; 2263 2161 user_od_table->OverDriveTable.FanMinimumPwm = 2264 2162 user_od_table_bak.OverDriveTable.FanMinimumPwm; 2163 + user_od_table->OverDriveTable.FanZeroRpmEnable = 2164 + user_od_table_bak.OverDriveTable.FanZeroRpmEnable; 2165 + user_od_table->OverDriveTable.FanZeroRpmStopTemp = 2166 + user_od_table_bak.OverDriveTable.FanZeroRpmStopTemp; 2265 2167 } 2266 2168 2267 2169 smu_v13_0_7_set_supported_od_feature_mask(smu); ··· 2593 2487 smu->power_profile_mode); 2594 2488 if (workload_type < 0) 2595 2489 return -EINVAL; 2490 + 2596 2491 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask, 2597 - 1 << workload_type, NULL); 2492 + smu->workload_mask, NULL); 2598 2493 2599 2494 if (ret) 2600 2495 dev_err(smu->adev->dev, "[%s] Failed to set work load mask!", __func__); 2601 2496 else 2602 - smu->workload_mask = (1 << workload_type); 2497 + smu_cmn_assign_power_profile(smu); 2603 2498 2604 2499 return ret; 2605 2500 }

+3 -1

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

··· 220 220 return ret; 221 221 } 222 222 223 - static int yellow_carp_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 223 + static int yellow_carp_dpm_set_vcn_enable(struct smu_context *smu, 224 + bool enable, 225 + int inst) 224 226 { 225 227 int ret = 0; 226 228

+2 -1

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

··· 1507 1507 } 1508 1508 1509 1509 int smu_v14_0_set_vcn_enable(struct smu_context *smu, 1510 - bool enable) 1510 + bool enable, 1511 + int inst) 1511 1512 { 1512 1513 struct amdgpu_device *adev = smu->adev; 1513 1514 int i, ret = 0;

+5 -69

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

··· 367 367 return 0; 368 368 } 369 369 370 - #ifndef atom_smc_dpm_info_table_14_0_0 371 - struct atom_smc_dpm_info_table_14_0_0 { 372 - struct atom_common_table_header table_header; 373 - BoardTable_t BoardTable; 374 - }; 375 - #endif 376 - 377 - static int smu_v14_0_2_append_powerplay_table(struct smu_context *smu) 378 - { 379 - struct smu_table_context *table_context = &smu->smu_table; 380 - PPTable_t *smc_pptable = table_context->driver_pptable; 381 - struct atom_smc_dpm_info_table_14_0_0 *smc_dpm_table; 382 - BoardTable_t *BoardTable = &smc_pptable->BoardTable; 383 - int index, ret; 384 - 385 - index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 386 - smc_dpm_info); 387 - 388 - ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL, 389 - (uint8_t **)&smc_dpm_table); 390 - if (ret) 391 - return ret; 392 - 393 - memcpy(BoardTable, &smc_dpm_table->BoardTable, sizeof(BoardTable_t)); 394 - 395 - return 0; 396 - } 397 - 398 - #if 0 399 - static int smu_v14_0_2_get_pptable_from_pmfw(struct smu_context *smu, 400 - void **table, 401 - uint32_t *size) 402 - { 403 - struct smu_table_context *smu_table = &smu->smu_table; 404 - void *combo_pptable = smu_table->combo_pptable; 405 - int ret = 0; 406 - 407 - ret = smu_cmn_get_combo_pptable(smu); 408 - if (ret) 409 - return ret; 410 - 411 - *table = combo_pptable; 412 - *size = sizeof(struct smu_14_0_powerplay_table); 413 - 414 - return 0; 415 - } 416 - #endif 417 - 418 370 static int smu_v14_0_2_get_pptable_from_pmfw(struct smu_context *smu, 419 371 void **table, 420 372 uint32_t *size) ··· 388 436 static int smu_v14_0_2_setup_pptable(struct smu_context *smu) 389 437 { 390 438 struct smu_table_context *smu_table = &smu->smu_table; 391 - struct amdgpu_device *adev = smu->adev; 392 439 int ret = 0; 393 440 394 441 if (amdgpu_sriov_vf(smu->adev)) 395 442 return 0; 396 443 397 - if (!adev->scpm_enabled) 398 - ret = smu_v14_0_setup_pptable(smu); 399 - else 400 - ret = smu_v14_0_2_get_pptable_from_pmfw(smu, 444 + ret = smu_v14_0_2_get_pptable_from_pmfw(smu, 401 445 &smu_table->power_play_table, 402 446 &smu_table->power_play_table_size); 403 447 if (ret) ··· 402 454 ret = smu_v14_0_2_store_powerplay_table(smu); 403 455 if (ret) 404 456 return ret; 405 - 406 - /* 407 - * With SCPM enabled, the operation below will be handled 408 - * by PSP. Driver involvment is unnecessary and useless. 409 - */ 410 - if (!adev->scpm_enabled) { 411 - ret = smu_v14_0_2_append_powerplay_table(smu); 412 - if (ret) 413 - return ret; 414 - } 415 457 416 458 ret = smu_v14_0_2_check_powerplay_table(smu); 417 459 if (ret) ··· 1795 1857 if (workload_type < 0) 1796 1858 return -EINVAL; 1797 1859 1798 - ret = smu_cmn_send_smc_msg_with_param(smu, 1799 - SMU_MSG_SetWorkloadMask, 1800 - 1 << workload_type, 1801 - NULL); 1860 + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask, 1861 + smu->workload_mask, NULL); 1862 + 1802 1863 if (!ret) 1803 - smu->workload_mask = 1 << workload_type; 1864 + smu_cmn_assign_power_profile(smu); 1804 1865 1805 1866 return ret; 1806 1867 } ··· 2723 2786 .check_fw_status = smu_v14_0_check_fw_status, 2724 2787 .setup_pptable = smu_v14_0_2_setup_pptable, 2725 2788 .check_fw_version = smu_v14_0_check_fw_version, 2726 - .write_pptable = smu_cmn_write_pptable, 2727 2789 .set_driver_table_location = smu_v14_0_set_driver_table_location, 2728 2790 .system_features_control = smu_v14_0_system_features_control, 2729 2791 .set_allowed_mask = smu_v14_0_set_allowed_mask,

+8

drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c

··· 1141 1141 return ret; 1142 1142 } 1143 1143 1144 + void smu_cmn_assign_power_profile(struct smu_context *smu) 1145 + { 1146 + uint32_t index; 1147 + index = fls(smu->workload_mask); 1148 + index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1149 + smu->power_profile_mode = smu->workload_setting[index]; 1150 + } 1151 + 1144 1152 bool smu_cmn_is_audio_func_enabled(struct amdgpu_device *adev) 1145 1153 { 1146 1154 struct pci_dev *p = NULL;

+2

drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h

··· 130 130 int smu_cmn_set_mp1_state(struct smu_context *smu, 131 131 enum pp_mp1_state mp1_state); 132 132 133 + void smu_cmn_assign_power_profile(struct smu_context *smu); 134 + 133 135 /* 134 136 * Helper function to make sysfs_emit_at() happy. Align buf to 135 137 * the current page boundary and record the offset.

+2 -1

include/uapi/linux/kfd_sysfs.h

··· 60 60 #define HSA_CAP_FLAGS_COHERENTHOSTACCESS 0x10000000 61 61 #define HSA_CAP_TRAP_DEBUG_FIRMWARE_SUPPORTED 0x20000000 62 62 #define HSA_CAP_TRAP_DEBUG_PRECISE_ALU_OPERATIONS_SUPPORTED 0x40000000 63 - #define HSA_CAP_RESERVED 0x800f8000 63 + #define HSA_CAP_PER_QUEUE_RESET_SUPPORTED 0x80000000 64 + #define HSA_CAP_RESERVED 0x000f8000 64 65 65 66 /* debug_prop bits in node properties */ 66 67 #define HSA_DBG_WATCH_ADDR_MASK_LO_BIT_MASK 0x0000000f

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