tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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dt-bindings: clock: eswin: Documentation for eic7700 SoC

Add device tree binding documentation for the ESWIN eic7700
clock controller module.

Signed-off-by: Yifeng Huang <huangyifeng@eswincomputing.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Troy Mitchell <troy.mitchell@linux.dev>
Tested-by: Marcel Ziswiler <marcel@ziswiler.com> # ebc77
Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

authored by

Xuyang Dong and committed by
Stephen Boyd 1fb83132 c3692998

+331
+46
Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/clock/eswin,eic7700-clock.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Eswin EIC7700 SoC clock controller 8 + 9 + maintainers: 10 + - Yifeng Huang <huangyifeng@eswincomputing.com> 11 + - Xuyang Dong <dongxuyang@eswincomputing.com> 12 + 13 + description: 14 + The clock controller generates and supplies clock to all the modules 15 + for eic7700 SoC. 16 + 17 + properties: 18 + compatible: 19 + const: eswin,eic7700-clock 20 + 21 + reg: 22 + maxItems: 1 23 + 24 + clocks: 25 + items: 26 + - description: External 24MHz oscillator clock 27 + 28 + '#clock-cells': 29 + const: 1 30 + 31 + required: 32 + - compatible 33 + - reg 34 + - clocks 35 + - '#clock-cells' 36 + 37 + additionalProperties: false 38 + 39 + examples: 40 + - | 41 + clock-controller@51828000 { 42 + compatible = "eswin,eic7700-clock"; 43 + reg = <0x51828000 0x300>; 44 + clocks = <&xtal24m>; 45 + #clock-cells = <1>; 46 + };
+285
include/dt-bindings/clock/eswin,eic7700-clock.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd.. 4 + * All rights reserved. 5 + * 6 + * Device Tree binding constants for EIC7700 clock controller. 7 + * 8 + * Authors: 9 + * Yifeng Huang <huangyifeng@eswincomputing.com> 10 + * Xuyang Dong <dongxuyang@eswincomputing.com> 11 + */ 12 + 13 + #ifndef _DT_BINDINGS_ESWIN_EIC7700_CLOCK_H_ 14 + #define _DT_BINDINGS_ESWIN_EIC7700_CLOCK_H_ 15 + 16 + #define EIC7700_CLK_XTAL_32K 0 17 + #define EIC7700_CLK_PLL_CPU 1 18 + #define EIC7700_CLK_SPLL0_FOUT1 2 19 + #define EIC7700_CLK_SPLL0_FOUT2 3 20 + #define EIC7700_CLK_SPLL0_FOUT3 4 21 + #define EIC7700_CLK_SPLL1_FOUT1 5 22 + #define EIC7700_CLK_SPLL1_FOUT2 6 23 + #define EIC7700_CLK_SPLL1_FOUT3 7 24 + #define EIC7700_CLK_SPLL2_FOUT1 8 25 + #define EIC7700_CLK_SPLL2_FOUT2 9 26 + #define EIC7700_CLK_SPLL2_FOUT3 10 27 + #define EIC7700_CLK_VPLL_FOUT1 11 28 + #define EIC7700_CLK_VPLL_FOUT2 12 29 + #define EIC7700_CLK_VPLL_FOUT3 13 30 + #define EIC7700_CLK_APLL_FOUT1 14 31 + #define EIC7700_CLK_APLL_FOUT2 15 32 + #define EIC7700_CLK_APLL_FOUT3 16 33 + #define EIC7700_CLK_EXT_MCLK 17 34 + #define EIC7700_CLK_LPDDR_REF_BAK 18 35 + #define EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE 19 36 + #define EIC7700_CLK_MUX_CPU_ACLK_2MUX1_GFREE 20 37 + #define EIC7700_CLK_MUX_DSP_ACLK_ROOT_2MUX1_GFREE 21 38 + #define EIC7700_CLK_MUX_D2D_ACLK_ROOT_2MUX1_GFREE 22 39 + #define EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_0 23 40 + #define EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_1 24 41 + #define EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_2 25 42 + #define EIC7700_CLK_MUX_NPU_LLCLK_3MUX1_GFREE 26 43 + #define EIC7700_CLK_MUX_NPU_CORE_3MUX1_GFREE 27 44 + #define EIC7700_CLK_MUX_VI_ACLK_ROOT_2MUX1_GFREE 28 45 + #define EIC7700_CLK_MUX_VI_DVP_ROOT_2MUX1_GFREE 29 46 + #define EIC7700_CLK_MUX_VI_DIG_ISP_ROOT_2MUX1_GFREE 30 47 + #define EIC7700_CLK_MUX_VO_ACLK_ROOT_2MUX1_GFREE 31 48 + #define EIC7700_CLK_MUX_VO_PIXEL_ROOT_2MUX1 32 49 + #define EIC7700_CLK_MUX_VCDEC_ROOT_2MUX1_GFREE 33 50 + #define EIC7700_CLK_MUX_VCACLK_ROOT_2MUX1_GFREE 34 51 + #define EIC7700_CLK_MUX_SATA_PHY_2MUX1 35 52 + #define EIC7700_CLK_MUX_BOOTSPI_CLK_2MUX1_GFREE 36 53 + #define EIC7700_CLK_MUX_SCPU_CORE_CLK_2MUX1_GFREE 37 54 + #define EIC7700_CLK_MUX_LPCPU_CORE_CLK_2MUX1_GFREE 38 55 + #define EIC7700_CLK_MUX_VO_MCLK_2MUX_EXT_MCLK 39 56 + #define EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE 40 57 + #define EIC7700_CLK_MUX_AONDMA_AXI2MUX1_GFREE 41 58 + #define EIC7700_CLK_MUX_RMII_REF_2MUX 42 59 + #define EIC7700_CLK_MUX_ETH_CORE_2MUX1 43 60 + #define EIC7700_CLK_MUX_VI_DW_ROOT_2MUX1 44 61 + #define EIC7700_CLK_MUX_NPU_E31_3MUX1_GFREE 45 62 + #define EIC7700_CLK_MUX_DDR_ACLK_ROOT_2MUX1_GFREE 46 63 + #define EIC7700_CLK_DIV_SYS_CFG_DYNM 47 64 + #define EIC7700_CLK_DIV_NOC_NSP_DYNM 48 65 + #define EIC7700_CLK_DIV_BOOTSPI_DYNM 49 66 + #define EIC7700_CLK_DIV_SCPU_CORE_DYNM 50 67 + #define EIC7700_CLK_DIV_LPCPU_CORE_DYNM 51 68 + #define EIC7700_CLK_DIV_GPU_ACLK_DYNM 52 69 + #define EIC7700_CLK_DIV_DSP_ACLK_DYNM 53 70 + #define EIC7700_CLK_DIV_D2D_ACLK_DYNM 54 71 + #define EIC7700_CLK_DIV_HSP_ACLK_DYNM 55 72 + #define EIC7700_CLK_DIV_ETH_TXCLK_DYNM_0 56 73 + #define EIC7700_CLK_DIV_ETH_TXCLK_DYNM_1 57 74 + #define EIC7700_CLK_DIV_MSHC_CORE_DYNM_0 58 75 + #define EIC7700_CLK_DIV_MSHC_CORE_DYNM_1 59 76 + #define EIC7700_CLK_DIV_MSHC_CORE_DYNM_2 60 77 + #define EIC7700_CLK_DIV_PCIE_ACLK_DYNM 61 78 + #define EIC7700_CLK_DIV_NPU_ACLK_DYNM 62 79 + #define EIC7700_CLK_DIV_NPU_LLC_SRC0_DYNM 63 80 + #define EIC7700_CLK_DIV_NPU_LLC_SRC1_DYNM 64 81 + #define EIC7700_CLK_DIV_NPU_CORECLK_DYNM 65 82 + #define EIC7700_CLK_DIV_VI_ACLK_DYNM 66 83 + #define EIC7700_CLK_DIV_VI_DVP_DYNM 67 84 + #define EIC7700_CLK_DIV_VI_DIG_ISP_DYNM 68 85 + #define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_0 69 86 + #define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_1 70 87 + #define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_2 71 88 + #define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_3 72 89 + #define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_4 73 90 + #define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_5 74 91 + #define EIC7700_CLK_DIV_VO_ACLK_DYNM 75 92 + #define EIC7700_CLK_DIV_IESMCLK_DYNM 76 93 + #define EIC7700_CLK_DIV_VO_PIXEL_DYNM 77 94 + #define EIC7700_CLK_DIV_VO_MCLK_DYNM 78 95 + #define EIC7700_CLK_DIV_VC_ACLK_DYNM 79 96 + #define EIC7700_CLK_DIV_JD_DYNM 80 97 + #define EIC7700_CLK_DIV_JE_DYNM 81 98 + #define EIC7700_CLK_DIV_VE_DYNM 82 99 + #define EIC7700_CLK_DIV_VD_DYNM 83 100 + #define EIC7700_CLK_DIV_G2D_DYNM 84 101 + #define EIC7700_CLK_DIV_AONDMA_AXI_DYNM 85 102 + #define EIC7700_CLK_DIV_CRYPTO_DYNM 86 103 + #define EIC7700_CLK_DIV_VI_DW_DYNM 87 104 + #define EIC7700_CLK_DIV_NPU_E31_DYNM 88 105 + #define EIC7700_CLK_DIV_SATA_PHY_REF_DYNM 89 106 + #define EIC7700_CLK_DIV_DSP_0_ACLK_DYNM 90 107 + #define EIC7700_CLK_DIV_DSP_1_ACLK_DYNM 91 108 + #define EIC7700_CLK_DIV_DSP_2_ACLK_DYNM 92 109 + #define EIC7700_CLK_DIV_DSP_3_ACLK_DYNM 93 110 + #define EIC7700_CLK_DIV_DDR_ACLK_DYNM 94 111 + #define EIC7700_CLK_DIV_AON_RTC_DYNM 95 112 + #define EIC7700_CLK_DIV_U84_RTC_TOGGLE_DYNM 96 113 + #define EIC7700_CLK_DIV_VO_CEC_DYNM 97 114 + #define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_0 98 115 + #define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_1 99 116 + #define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_2 100 117 + #define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_3 101 118 + #define EIC7700_CLK_GATE_CPU_TRACE_CLK_0 102 119 + #define EIC7700_CLK_GATE_CPU_TRACE_CLK_1 103 120 + #define EIC7700_CLK_GATE_CPU_TRACE_CLK_2 104 121 + #define EIC7700_CLK_GATE_CPU_TRACE_CLK_3 105 122 + #define EIC7700_CLK_GATE_CPU_TRACE_COM_CLK 106 123 + #define EIC7700_CLK_GATE_SPLL0_FOUT2 107 124 + #define EIC7700_CLK_GATE_NOC_NSP_CLK 108 125 + #define EIC7700_CLK_GATE_BOOTSPI 109 126 + #define EIC7700_CLK_GATE_BOOTSPI_CFG 110 127 + #define EIC7700_CLK_GATE_SCPU_CORE 111 128 + #define EIC7700_CLK_GATE_SCPU_BUS 112 129 + #define EIC7700_CLK_GATE_LPCPU_CORE 113 130 + #define EIC7700_CLK_GATE_LPCPU_BUS 114 131 + #define EIC7700_CLK_GATE_GPU_ACLK 115 132 + #define EIC7700_CLK_GATE_GPU_GRAY_CLK 116 133 + #define EIC7700_CLK_GATE_GPU_CFG_CLK 117 134 + #define EIC7700_CLK_GATE_DSPT_ACLK 118 135 + #define EIC7700_CLK_GATE_DSPT_CFG_CLK 119 136 + #define EIC7700_CLK_GATE_D2D_ACLK 120 137 + #define EIC7700_CLK_GATE_D2D_CFG_CLK 121 138 + #define EIC7700_CLK_GATE_TCU_ACLK 122 139 + #define EIC7700_CLK_GATE_TCU_CFG_CLK 123 140 + #define EIC7700_CLK_GATE_DDRT_CFG_CLK 124 141 + #define EIC7700_CLK_GATE_DDRT0_P0_ACLK 125 142 + #define EIC7700_CLK_GATE_DDRT0_P1_ACLK 126 143 + #define EIC7700_CLK_GATE_DDRT0_P2_ACLK 127 144 + #define EIC7700_CLK_GATE_DDRT0_P3_ACLK 128 145 + #define EIC7700_CLK_GATE_DDRT0_P4_ACLK 129 146 + #define EIC7700_CLK_GATE_DDRT1_P0_ACLK 130 147 + #define EIC7700_CLK_GATE_DDRT1_P1_ACLK 131 148 + #define EIC7700_CLK_GATE_DDRT1_P2_ACLK 132 149 + #define EIC7700_CLK_GATE_DDRT1_P3_ACLK 133 150 + #define EIC7700_CLK_GATE_DDRT1_P4_ACLK 134 151 + #define EIC7700_CLK_GATE_TIMER_CLK_0 135 152 + #define EIC7700_CLK_GATE_TIMER_CLK_1 136 153 + #define EIC7700_CLK_GATE_TIMER_CLK_2 137 154 + #define EIC7700_CLK_GATE_TIMER_CLK_3 138 155 + #define EIC7700_CLK_GATE_TIMER_PCLK_0 139 156 + #define EIC7700_CLK_GATE_TIMER_PCLK_1 140 157 + #define EIC7700_CLK_GATE_TIMER_PCLK_2 141 158 + #define EIC7700_CLK_GATE_TIMER_PCLK_3 142 159 + #define EIC7700_CLK_GATE_TIMER3_CLK8 143 160 + #define EIC7700_CLK_GATE_PCIET_ACLK 144 161 + #define EIC7700_CLK_GATE_PCIET_CFG_CLK 145 162 + #define EIC7700_CLK_GATE_PCIET_CR_CLK 146 163 + #define EIC7700_CLK_GATE_PCIET_AUX_CLK 147 164 + #define EIC7700_CLK_GATE_NPU_ACLK 148 165 + #define EIC7700_CLK_GATE_NPU_CFG_CLK 149 166 + #define EIC7700_CLK_GATE_NPU_LLC_ACLK 150 167 + #define EIC7700_CLK_GATE_NPU_CLK 151 168 + #define EIC7700_CLK_GATE_NPU_E31_CLK 152 169 + #define EIC7700_CLK_GATE_VI_ACLK 153 170 + #define EIC7700_CLK_GATE_VI_DVP_CLK 154 171 + #define EIC7700_CLK_GATE_VI_CFG_CLK 155 172 + #define EIC7700_CLK_GATE_VI_DIG_DW_CLK 156 173 + #define EIC7700_CLK_GATE_VI_DIG_ISP_CLK 157 174 + #define EIC7700_CLK_GATE_VI_SHUTTER_0 158 175 + #define EIC7700_CLK_GATE_VI_SHUTTER_1 159 176 + #define EIC7700_CLK_GATE_VI_SHUTTER_2 160 177 + #define EIC7700_CLK_GATE_VI_SHUTTER_3 161 178 + #define EIC7700_CLK_GATE_VI_SHUTTER_4 162 179 + #define EIC7700_CLK_GATE_VI_SHUTTER_5 163 180 + #define EIC7700_CLK_GATE_VI_PHY_TXCLKESC 164 181 + #define EIC7700_CLK_GATE_VI_PHY_CFG 165 182 + #define EIC7700_CLK_GATE_VO_ACLK 166 183 + #define EIC7700_CLK_GATE_VO_CFG_CLK 167 184 + #define EIC7700_CLK_GATE_VO_HDMI_IESMCLK 168 185 + #define EIC7700_CLK_GATE_VO_PIXEL_CLK 169 186 + #define EIC7700_CLK_GATE_VO_I2S_MCLK 170 187 + #define EIC7700_CLK_GATE_HSP_CFG_CLK 171 188 + #define EIC7700_CLK_GATE_VC_ACLK 172 189 + #define EIC7700_CLK_GATE_VC_CFG_CLK 173 190 + #define EIC7700_CLK_GATE_VC_JE_CLK 174 191 + #define EIC7700_CLK_GATE_VC_JD_CLK 175 192 + #define EIC7700_CLK_GATE_VC_VE_CLK 176 193 + #define EIC7700_CLK_GATE_VC_VD_CLK 177 194 + #define EIC7700_CLK_GATE_G2D_CFG_CLK 178 195 + #define EIC7700_CLK_GATE_G2D_CLK 179 196 + #define EIC7700_CLK_GATE_G2D_ACLK 180 197 + #define EIC7700_CLK_GATE_AONDMA_CFG 181 198 + #define EIC7700_CLK_GATE_AONDMA_ACLK 182 199 + #define EIC7700_CLK_GATE_AON_ACLK 183 200 + #define EIC7700_CLK_GATE_HSP_SATA_RBC_CLK 184 201 + #define EIC7700_CLK_GATE_VO_CR_CLK 185 202 + #define EIC7700_CLK_GATE_HSP_ACLK 186 203 + #define EIC7700_CLK_GATE_HSP_SATA_OOB_CLK 187 204 + #define EIC7700_CLK_GATE_RTC_CFG 188 205 + #define EIC7700_CLK_GATE_RTC 189 206 + #define EIC7700_CLK_GATE_HSP_MSHC0_CORE_CLK 190 207 + #define EIC7700_CLK_GATE_HSP_MSHC1_CORE_CLK 191 208 + #define EIC7700_CLK_GATE_HSP_MSHC2_CORE_CLK 192 209 + #define EIC7700_CLK_GATE_HSP_ETH0_CORE_CLK 193 210 + #define EIC7700_CLK_GATE_HSP_ETH1_CORE_CLK 194 211 + #define EIC7700_CLK_GATE_HSP_RMII_REF_0 195 212 + #define EIC7700_CLK_GATE_HSP_RMII_REF_1 196 213 + #define EIC7700_CLK_GATE_PKA_CFG 197 214 + #define EIC7700_CLK_GATE_SPACC_CFG 198 215 + #define EIC7700_CLK_GATE_CRYPTO 199 216 + #define EIC7700_CLK_GATE_TRNG_CFG 200 217 + #define EIC7700_CLK_GATE_OTP_CFG 201 218 + #define EIC7700_CLK_GATE_MAILBOX_0 202 219 + #define EIC7700_CLK_GATE_MAILBOX_1 203 220 + #define EIC7700_CLK_GATE_MAILBOX_2 204 221 + #define EIC7700_CLK_GATE_MAILBOX_3 205 222 + #define EIC7700_CLK_GATE_MAILBOX_4 206 223 + #define EIC7700_CLK_GATE_MAILBOX_5 207 224 + #define EIC7700_CLK_GATE_MAILBOX_6 208 225 + #define EIC7700_CLK_GATE_MAILBOX_7 209 226 + #define EIC7700_CLK_GATE_MAILBOX_8 210 227 + #define EIC7700_CLK_GATE_MAILBOX_9 211 228 + #define EIC7700_CLK_GATE_MAILBOX_10 212 229 + #define EIC7700_CLK_GATE_MAILBOX_11 213 230 + #define EIC7700_CLK_GATE_MAILBOX_12 214 231 + #define EIC7700_CLK_GATE_MAILBOX_13 215 232 + #define EIC7700_CLK_GATE_MAILBOX_14 216 233 + #define EIC7700_CLK_GATE_MAILBOX_15 217 234 + #define EIC7700_CLK_GATE_LSP_I2C0_PCLK 218 235 + #define EIC7700_CLK_GATE_LSP_I2C1_PCLK 219 236 + #define EIC7700_CLK_GATE_LSP_I2C2_PCLK 220 237 + #define EIC7700_CLK_GATE_LSP_I2C3_PCLK 221 238 + #define EIC7700_CLK_GATE_LSP_I2C4_PCLK 222 239 + #define EIC7700_CLK_GATE_LSP_I2C5_PCLK 223 240 + #define EIC7700_CLK_GATE_LSP_I2C6_PCLK 224 241 + #define EIC7700_CLK_GATE_LSP_I2C7_PCLK 225 242 + #define EIC7700_CLK_GATE_LSP_I2C8_PCLK 226 243 + #define EIC7700_CLK_GATE_LSP_I2C9_PCLK 227 244 + #define EIC7700_CLK_GATE_LSP_WDT0_PCLK 228 245 + #define EIC7700_CLK_GATE_LSP_WDT1_PCLK 229 246 + #define EIC7700_CLK_GATE_LSP_WDT2_PCLK 230 247 + #define EIC7700_CLK_GATE_LSP_WDT3_PCLK 231 248 + #define EIC7700_CLK_GATE_LSP_SSI0_PCLK 232 249 + #define EIC7700_CLK_GATE_LSP_SSI1_PCLK 233 250 + #define EIC7700_CLK_GATE_LSP_PVT_PCLK 234 251 + #define EIC7700_CLK_GATE_AON_I2C0_PCLK 235 252 + #define EIC7700_CLK_GATE_AON_I2C1_PCLK 236 253 + #define EIC7700_CLK_GATE_LSP_UART0_PCLK 237 254 + #define EIC7700_CLK_GATE_LSP_UART1_PCLK 238 255 + #define EIC7700_CLK_GATE_LSP_UART2_PCLK 239 256 + #define EIC7700_CLK_GATE_LSP_UART3_PCLK 240 257 + #define EIC7700_CLK_GATE_LSP_UART4_PCLK 241 258 + #define EIC7700_CLK_GATE_LSP_TIMER_PCLK 242 259 + #define EIC7700_CLK_GATE_LSP_FAN_PCLK 243 260 + #define EIC7700_CLK_GATE_LSP_PVT0_CLK 244 261 + #define EIC7700_CLK_GATE_LSP_PVT1_CLK 245 262 + #define EIC7700_CLK_GATE_VC_JE_PCLK 246 263 + #define EIC7700_CLK_GATE_VC_JD_PCLK 247 264 + #define EIC7700_CLK_GATE_VC_VE_PCLK 248 265 + #define EIC7700_CLK_GATE_VC_VD_PCLK 249 266 + #define EIC7700_CLK_GATE_VC_MON_PCLK 250 267 + #define EIC7700_CLK_GATE_HSP_DMA0_CLK 251 268 + #define EIC7700_CLK_GATE_HSP_DMA0_CLK_TEST 252 269 + #define EIC7700_CLK_FIXED_FACTOR_CPU_DIV2 253 270 + #define EIC7700_CLK_FIXED_FACTOR_CLK_1M_DIV24 254 271 + #define EIC7700_CLK_FIXED_FACTOR_MIPI_TXESC_DIV10 255 272 + #define EIC7700_CLK_FIXED_FACTOR_U84_CORE_LP_DIV2 256 273 + #define EIC7700_CLK_FIXED_FACTOR_SCPU_BUS_DIV2 257 274 + #define EIC7700_CLK_FIXED_FACTOR_LPCPU_BUS_DIV2 258 275 + #define EIC7700_CLK_FIXED_FACTOR_PCIE_CR_DIV2 259 276 + #define EIC7700_CLK_FIXED_FACTOR_PCIE_AUX_DIV4 260 277 + #define EIC7700_CLK_FIXED_FACTOR_PVT_DIV20 261 278 + #define EIC7700_CLK_FIXED_FACTOR_HSP_RMII_REF_DIV6 262 279 + #define EIC7700_CLK_DIV_NOC_WDREF_DYNM 263 280 + #define EIC7700_CLK_GATE_DDR0_TRACE 264 281 + #define EIC7700_CLK_GATE_DDR1_TRACE 265 282 + #define EIC7700_CLK_GATE_RNOC_NSP 266 283 + #define EIC7700_CLK_GATE_NOC_WDREF 267 284 + 285 + #endif /* _DT_BINDINGS_ESWIN_EIC7700_CLOCK_H_ */