tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

clk: qcom: gcc-sc8180x: Register QUPv3 RCGs for DFS on sc8180x

QUPv3 clocks support DFS on sc8180x platform but currently the code
changes for it are missing from the driver, this results in not
populating all the DFS supported frequencies and returns incorrect
frequency when the clients request for them. Hence add the DFS
registration for QUPv3 RCGs.

Fixes: 4433594bbe5d ("clk: qcom: gcc: Add global clock controller driver for SC8180x")
Cc: stable@vger.kernel.org
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Link: https://lore.kernel.org/r/20240812-gcc-sc8180x-fixes-v2-1-8b3eaa5fb856@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Satya Priya Kakitapalli and committed by
Bjorn Andersson 1fc8c02e a4e5af27

+210 -140
+210 -140
drivers/clk/qcom/gcc-sc8180x.c
··· 609 609 { } 610 610 }; 611 611 612 + static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { 613 + .name = "gcc_qupv3_wrap0_s0_clk_src", 614 + .parent_data = gcc_parents_0, 615 + .num_parents = ARRAY_SIZE(gcc_parents_0), 616 + .flags = CLK_SET_RATE_PARENT, 617 + .ops = &clk_rcg2_ops, 618 + }; 619 + 612 620 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { 613 621 .cmd_rcgr = 0x17148, 614 622 .mnd_width = 16, 615 623 .hid_width = 5, 616 624 .parent_map = gcc_parent_map_0, 617 625 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 618 - .clkr.hw.init = &(struct clk_init_data){ 619 - .name = "gcc_qupv3_wrap0_s0_clk_src", 620 - .parent_data = gcc_parents_0, 621 - .num_parents = ARRAY_SIZE(gcc_parents_0), 622 - .flags = CLK_SET_RATE_PARENT, 623 - .ops = &clk_rcg2_ops, 624 - }, 626 + .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, 627 + }; 628 + 629 + static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { 630 + .name = "gcc_qupv3_wrap0_s1_clk_src", 631 + .parent_data = gcc_parents_0, 632 + .num_parents = ARRAY_SIZE(gcc_parents_0), 633 + .flags = CLK_SET_RATE_PARENT, 634 + .ops = &clk_rcg2_ops, 625 635 }; 626 636 627 637 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { ··· 640 630 .hid_width = 5, 641 631 .parent_map = gcc_parent_map_0, 642 632 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 643 - .clkr.hw.init = &(struct clk_init_data){ 644 - .name = "gcc_qupv3_wrap0_s1_clk_src", 645 - .parent_data = gcc_parents_0, 646 - .num_parents = ARRAY_SIZE(gcc_parents_0), 647 - .flags = CLK_SET_RATE_PARENT, 648 - .ops = &clk_rcg2_ops, 649 - }, 633 + .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, 634 + }; 635 + 636 + static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { 637 + .name = "gcc_qupv3_wrap0_s2_clk_src", 638 + .parent_data = gcc_parents_0, 639 + .num_parents = ARRAY_SIZE(gcc_parents_0), 640 + .flags = CLK_SET_RATE_PARENT, 641 + .ops = &clk_rcg2_ops, 650 642 }; 651 643 652 644 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { ··· 657 645 .hid_width = 5, 658 646 .parent_map = gcc_parent_map_0, 659 647 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 660 - .clkr.hw.init = &(struct clk_init_data){ 661 - .name = "gcc_qupv3_wrap0_s2_clk_src", 662 - .parent_data = gcc_parents_0, 663 - .num_parents = ARRAY_SIZE(gcc_parents_0), 664 - .flags = CLK_SET_RATE_PARENT, 665 - .ops = &clk_rcg2_ops, 666 - }, 648 + .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, 649 + }; 650 + 651 + static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { 652 + .name = "gcc_qupv3_wrap0_s3_clk_src", 653 + .parent_data = gcc_parents_0, 654 + .num_parents = ARRAY_SIZE(gcc_parents_0), 655 + .flags = CLK_SET_RATE_PARENT, 656 + .ops = &clk_rcg2_ops, 667 657 }; 668 658 669 659 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { ··· 674 660 .hid_width = 5, 675 661 .parent_map = gcc_parent_map_0, 676 662 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 677 - .clkr.hw.init = &(struct clk_init_data){ 678 - .name = "gcc_qupv3_wrap0_s3_clk_src", 679 - .parent_data = gcc_parents_0, 680 - .num_parents = ARRAY_SIZE(gcc_parents_0), 681 - .flags = CLK_SET_RATE_PARENT, 682 - .ops = &clk_rcg2_ops, 683 - }, 663 + .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, 664 + }; 665 + 666 + static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { 667 + .name = "gcc_qupv3_wrap0_s4_clk_src", 668 + .parent_data = gcc_parents_0, 669 + .num_parents = ARRAY_SIZE(gcc_parents_0), 670 + .flags = CLK_SET_RATE_PARENT, 671 + .ops = &clk_rcg2_ops, 684 672 }; 685 673 686 674 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { ··· 691 675 .hid_width = 5, 692 676 .parent_map = gcc_parent_map_0, 693 677 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 694 - .clkr.hw.init = &(struct clk_init_data){ 695 - .name = "gcc_qupv3_wrap0_s4_clk_src", 696 - .parent_data = gcc_parents_0, 697 - .num_parents = ARRAY_SIZE(gcc_parents_0), 698 - .flags = CLK_SET_RATE_PARENT, 699 - .ops = &clk_rcg2_ops, 700 - }, 678 + .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, 679 + }; 680 + 681 + static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { 682 + .name = "gcc_qupv3_wrap0_s5_clk_src", 683 + .parent_data = gcc_parents_0, 684 + .num_parents = ARRAY_SIZE(gcc_parents_0), 685 + .flags = CLK_SET_RATE_PARENT, 686 + .ops = &clk_rcg2_ops, 701 687 }; 702 688 703 689 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { ··· 708 690 .hid_width = 5, 709 691 .parent_map = gcc_parent_map_0, 710 692 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 711 - .clkr.hw.init = &(struct clk_init_data){ 712 - .name = "gcc_qupv3_wrap0_s5_clk_src", 713 - .parent_data = gcc_parents_0, 714 - .num_parents = ARRAY_SIZE(gcc_parents_0), 715 - .flags = CLK_SET_RATE_PARENT, 716 - .ops = &clk_rcg2_ops, 717 - }, 693 + .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, 694 + }; 695 + 696 + static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { 697 + .name = "gcc_qupv3_wrap0_s6_clk_src", 698 + .parent_data = gcc_parents_0, 699 + .num_parents = ARRAY_SIZE(gcc_parents_0), 700 + .flags = CLK_SET_RATE_PARENT, 701 + .ops = &clk_rcg2_ops, 718 702 }; 719 703 720 704 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { ··· 725 705 .hid_width = 5, 726 706 .parent_map = gcc_parent_map_0, 727 707 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 728 - .clkr.hw.init = &(struct clk_init_data){ 729 - .name = "gcc_qupv3_wrap0_s6_clk_src", 730 - .parent_data = gcc_parents_0, 731 - .num_parents = ARRAY_SIZE(gcc_parents_0), 732 - .flags = CLK_SET_RATE_PARENT, 733 - .ops = &clk_rcg2_ops, 734 - }, 708 + .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init, 709 + }; 710 + 711 + static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { 712 + .name = "gcc_qupv3_wrap0_s7_clk_src", 713 + .parent_data = gcc_parents_0, 714 + .num_parents = ARRAY_SIZE(gcc_parents_0), 715 + .flags = CLK_SET_RATE_PARENT, 716 + .ops = &clk_rcg2_ops, 735 717 }; 736 718 737 719 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { ··· 742 720 .hid_width = 5, 743 721 .parent_map = gcc_parent_map_0, 744 722 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 745 - .clkr.hw.init = &(struct clk_init_data){ 746 - .name = "gcc_qupv3_wrap0_s7_clk_src", 747 - .parent_data = gcc_parents_0, 748 - .num_parents = ARRAY_SIZE(gcc_parents_0), 749 - .flags = CLK_SET_RATE_PARENT, 750 - .ops = &clk_rcg2_ops, 751 - }, 723 + .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init, 724 + }; 725 + 726 + static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 727 + .name = "gcc_qupv3_wrap1_s0_clk_src", 728 + .parent_data = gcc_parents_0, 729 + .num_parents = ARRAY_SIZE(gcc_parents_0), 730 + .flags = CLK_SET_RATE_PARENT, 731 + .ops = &clk_rcg2_ops, 752 732 }; 753 733 754 734 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { ··· 759 735 .hid_width = 5, 760 736 .parent_map = gcc_parent_map_0, 761 737 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 762 - .clkr.hw.init = &(struct clk_init_data){ 763 - .name = "gcc_qupv3_wrap1_s0_clk_src", 764 - .parent_data = gcc_parents_0, 765 - .num_parents = ARRAY_SIZE(gcc_parents_0), 766 - .flags = CLK_SET_RATE_PARENT, 767 - .ops = &clk_rcg2_ops, 768 - }, 738 + .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 739 + }; 740 + 741 + static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 742 + .name = "gcc_qupv3_wrap1_s1_clk_src", 743 + .parent_data = gcc_parents_0, 744 + .num_parents = ARRAY_SIZE(gcc_parents_0), 745 + .flags = CLK_SET_RATE_PARENT, 746 + .ops = &clk_rcg2_ops, 769 747 }; 770 748 771 749 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { ··· 776 750 .hid_width = 5, 777 751 .parent_map = gcc_parent_map_0, 778 752 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 779 - .clkr.hw.init = &(struct clk_init_data){ 780 - .name = "gcc_qupv3_wrap1_s1_clk_src", 781 - .parent_data = gcc_parents_0, 782 - .num_parents = ARRAY_SIZE(gcc_parents_0), 783 - .flags = CLK_SET_RATE_PARENT, 784 - .ops = &clk_rcg2_ops, 785 - }, 753 + .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 754 + }; 755 + 756 + static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { 757 + .name = "gcc_qupv3_wrap1_s2_clk_src", 758 + .parent_data = gcc_parents_0, 759 + .num_parents = ARRAY_SIZE(gcc_parents_0), 760 + .flags = CLK_SET_RATE_PARENT, 761 + .ops = &clk_rcg2_ops, 786 762 }; 787 763 788 764 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { ··· 793 765 .hid_width = 5, 794 766 .parent_map = gcc_parent_map_0, 795 767 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 796 - .clkr.hw.init = &(struct clk_init_data){ 797 - .name = "gcc_qupv3_wrap1_s2_clk_src", 798 - .parent_data = gcc_parents_0, 799 - .num_parents = ARRAY_SIZE(gcc_parents_0), 800 - .flags = CLK_SET_RATE_PARENT, 801 - .ops = &clk_rcg2_ops, 802 - }, 768 + .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, 769 + }; 770 + 771 + static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 772 + .name = "gcc_qupv3_wrap1_s3_clk_src", 773 + .parent_data = gcc_parents_0, 774 + .num_parents = ARRAY_SIZE(gcc_parents_0), 775 + .flags = CLK_SET_RATE_PARENT, 776 + .ops = &clk_rcg2_ops, 803 777 }; 804 778 805 779 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { ··· 810 780 .hid_width = 5, 811 781 .parent_map = gcc_parent_map_0, 812 782 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 813 - .clkr.hw.init = &(struct clk_init_data){ 814 - .name = "gcc_qupv3_wrap1_s3_clk_src", 815 - .parent_data = gcc_parents_0, 816 - .num_parents = ARRAY_SIZE(gcc_parents_0), 817 - .flags = CLK_SET_RATE_PARENT, 818 - .ops = &clk_rcg2_ops, 819 - }, 783 + .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 784 + }; 785 + 786 + static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 787 + .name = "gcc_qupv3_wrap1_s4_clk_src", 788 + .parent_data = gcc_parents_0, 789 + .num_parents = ARRAY_SIZE(gcc_parents_0), 790 + .flags = CLK_SET_RATE_PARENT, 791 + .ops = &clk_rcg2_ops, 820 792 }; 821 793 822 794 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { ··· 827 795 .hid_width = 5, 828 796 .parent_map = gcc_parent_map_0, 829 797 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 830 - .clkr.hw.init = &(struct clk_init_data){ 831 - .name = "gcc_qupv3_wrap1_s4_clk_src", 832 - .parent_data = gcc_parents_0, 833 - .num_parents = ARRAY_SIZE(gcc_parents_0), 834 - .flags = CLK_SET_RATE_PARENT, 835 - .ops = &clk_rcg2_ops, 836 - }, 798 + .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 799 + }; 800 + 801 + static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 802 + .name = "gcc_qupv3_wrap1_s5_clk_src", 803 + .parent_data = gcc_parents_0, 804 + .num_parents = ARRAY_SIZE(gcc_parents_0), 805 + .flags = CLK_SET_RATE_PARENT, 806 + .ops = &clk_rcg2_ops, 837 807 }; 838 808 839 809 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { ··· 844 810 .hid_width = 5, 845 811 .parent_map = gcc_parent_map_0, 846 812 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 847 - .clkr.hw.init = &(struct clk_init_data){ 848 - .name = "gcc_qupv3_wrap1_s5_clk_src", 849 - .parent_data = gcc_parents_0, 850 - .num_parents = ARRAY_SIZE(gcc_parents_0), 851 - .flags = CLK_SET_RATE_PARENT, 852 - .ops = &clk_rcg2_ops, 853 - }, 813 + .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 814 + }; 815 + 816 + static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = { 817 + .name = "gcc_qupv3_wrap2_s0_clk_src", 818 + .parent_data = gcc_parents_0, 819 + .num_parents = ARRAY_SIZE(gcc_parents_0), 820 + .flags = CLK_SET_RATE_PARENT, 821 + .ops = &clk_rcg2_ops, 854 822 }; 855 823 856 824 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { ··· 861 825 .hid_width = 5, 862 826 .parent_map = gcc_parent_map_0, 863 827 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 864 - .clkr.hw.init = &(struct clk_init_data){ 865 - .name = "gcc_qupv3_wrap2_s0_clk_src", 866 - .parent_data = gcc_parents_0, 867 - .num_parents = ARRAY_SIZE(gcc_parents_0), 868 - .flags = CLK_SET_RATE_PARENT, 869 - .ops = &clk_rcg2_ops, 870 - }, 828 + .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init, 829 + }; 830 + 831 + static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = { 832 + .name = "gcc_qupv3_wrap2_s1_clk_src", 833 + .parent_data = gcc_parents_0, 834 + .num_parents = ARRAY_SIZE(gcc_parents_0), 835 + .flags = CLK_SET_RATE_PARENT, 836 + .ops = &clk_rcg2_ops, 871 837 }; 872 838 873 839 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { ··· 878 840 .hid_width = 5, 879 841 .parent_map = gcc_parent_map_0, 880 842 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 881 - .clkr.hw.init = &(struct clk_init_data){ 882 - .name = "gcc_qupv3_wrap2_s1_clk_src", 883 - .parent_data = gcc_parents_0, 884 - .num_parents = ARRAY_SIZE(gcc_parents_0), 885 - .flags = CLK_SET_RATE_PARENT, 886 - .ops = &clk_rcg2_ops, 887 - }, 843 + .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init, 888 844 }; 845 + 846 + static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = { 847 + .name = "gcc_qupv3_wrap2_s2_clk_src", 848 + .parent_data = gcc_parents_0, 849 + .num_parents = ARRAY_SIZE(gcc_parents_0), 850 + .flags = CLK_SET_RATE_PARENT, 851 + .ops = &clk_rcg2_ops, 852 + }; 853 + 889 854 890 855 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { 891 856 .cmd_rcgr = 0x1e3a8, ··· 896 855 .hid_width = 5, 897 856 .parent_map = gcc_parent_map_0, 898 857 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 899 - .clkr.hw.init = &(struct clk_init_data){ 900 - .name = "gcc_qupv3_wrap2_s2_clk_src", 901 - .parent_data = gcc_parents_0, 902 - .num_parents = ARRAY_SIZE(gcc_parents_0), 903 - .flags = CLK_SET_RATE_PARENT, 904 - .ops = &clk_rcg2_ops, 905 - }, 858 + .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init, 859 + }; 860 + 861 + static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = { 862 + .name = "gcc_qupv3_wrap2_s3_clk_src", 863 + .parent_data = gcc_parents_0, 864 + .num_parents = ARRAY_SIZE(gcc_parents_0), 865 + .flags = CLK_SET_RATE_PARENT, 866 + .ops = &clk_rcg2_ops, 906 867 }; 907 868 908 869 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { ··· 913 870 .hid_width = 5, 914 871 .parent_map = gcc_parent_map_0, 915 872 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 916 - .clkr.hw.init = &(struct clk_init_data){ 917 - .name = "gcc_qupv3_wrap2_s3_clk_src", 918 - .parent_data = gcc_parents_0, 919 - .num_parents = ARRAY_SIZE(gcc_parents_0), 920 - .flags = CLK_SET_RATE_PARENT, 921 - .ops = &clk_rcg2_ops, 922 - }, 873 + .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init, 874 + }; 875 + 876 + static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = { 877 + .name = "gcc_qupv3_wrap2_s4_clk_src", 878 + .parent_data = gcc_parents_0, 879 + .num_parents = ARRAY_SIZE(gcc_parents_0), 880 + .flags = CLK_SET_RATE_PARENT, 881 + .ops = &clk_rcg2_ops, 923 882 }; 924 883 925 884 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { ··· 930 885 .hid_width = 5, 931 886 .parent_map = gcc_parent_map_0, 932 887 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 933 - .clkr.hw.init = &(struct clk_init_data){ 934 - .name = "gcc_qupv3_wrap2_s4_clk_src", 935 - .parent_data = gcc_parents_0, 936 - .num_parents = ARRAY_SIZE(gcc_parents_0), 937 - .flags = CLK_SET_RATE_PARENT, 938 - .ops = &clk_rcg2_ops, 939 - }, 888 + .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init, 889 + }; 890 + 891 + static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = { 892 + .name = "gcc_qupv3_wrap2_s5_clk_src", 893 + .parent_data = gcc_parents_0, 894 + .num_parents = ARRAY_SIZE(gcc_parents_0), 895 + .flags = CLK_SET_RATE_PARENT, 896 + .ops = &clk_rcg2_ops, 940 897 }; 941 898 942 899 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { ··· 947 900 .hid_width = 5, 948 901 .parent_map = gcc_parent_map_0, 949 902 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, 950 - .clkr.hw.init = &(struct clk_init_data){ 951 - .name = "gcc_qupv3_wrap2_s5_clk_src", 952 - .parent_data = gcc_parents_0, 953 - .num_parents = ARRAY_SIZE(gcc_parents_0), 954 - .flags = CLK_SET_RATE_PARENT, 955 - .ops = &clk_rcg2_ops, 956 - }, 903 + .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init, 957 904 }; 958 905 959 906 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { ··· 4606 4565 [GCC_VIDEO_AXI1_CLK_BCR] = { .reg = 0xb028, .bit = 2, .udelay = 150 }, 4607 4566 }; 4608 4567 4568 + static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 4569 + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), 4570 + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), 4571 + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), 4572 + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), 4573 + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), 4574 + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), 4575 + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src), 4576 + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src), 4577 + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 4578 + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 4579 + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), 4580 + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 4581 + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 4582 + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 4583 + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src), 4584 + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src), 4585 + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src), 4586 + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src), 4587 + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src), 4588 + DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src), 4589 + }; 4590 + 4609 4591 static struct gdsc *gcc_sc8180x_gdscs[] = { 4610 4592 [EMAC_GDSC] = &emac_gdsc, 4611 4593 [PCIE_0_GDSC] = &pcie_0_gdsc, ··· 4670 4606 static int gcc_sc8180x_probe(struct platform_device *pdev) 4671 4607 { 4672 4608 struct regmap *regmap; 4609 + int ret; 4673 4610 4674 4611 regmap = qcom_cc_map(pdev, &gcc_sc8180x_desc); 4675 4612 if (IS_ERR(regmap)) ··· 4691 4626 /* Disable the GPLL0 active input to NPU and GPU via MISC registers */ 4692 4627 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); 4693 4628 regmap_update_bits(regmap, 0x71028, 0x3, 0x3); 4629 + 4630 + ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 4631 + ARRAY_SIZE(gcc_dfs_clocks)); 4632 + if (ret) 4633 + return ret; 4694 4634 4695 4635 return qcom_cc_really_probe(&pdev->dev, &gcc_sc8180x_desc, regmap); 4696 4636 }