tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
drm/radeon/kms: fix channel_remap setup (v2)
drm/radeon: Set cursor x/y to 0 when x/yorigin > 0.
drm/radeon: Update AVIVO cursor coordinate origin before x/yorigin calculation.
drm/radeon: Simplify cursor x/yorigin calculation.
drm/radeon/kms: fix cursor image off-by-one error
drm/radeon/kms: Fix logic error in DP HPD handler
drm/radeon/kms: add retry limits for native DP aux defer
drm/radeon/kms: fix regression in DP aux defer handling

Linus Torvalds 1fd2a850 f8451c3f

+33 -158
+10 -6
drivers/gpu/drm/radeon/atombios_dp.c
··· 115 115 u8 msg[20]; 116 116 int msg_bytes = send_bytes + 4; 117 117 u8 ack; 118 + unsigned retry; 118 119 119 120 if (send_bytes > 16) 120 121 return -1; ··· 126 125 msg[3] = (msg_bytes << 4) | (send_bytes - 1); 127 126 memcpy(&msg[4], send, send_bytes); 128 127 129 - while (1) { 128 + for (retry = 0; retry < 4; retry++) { 130 129 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, 131 130 msg, msg_bytes, NULL, 0, delay, &ack); 132 131 if (ret < 0) 133 132 return ret; 134 133 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) 135 - break; 134 + return send_bytes; 136 135 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 137 136 udelay(400); 138 137 else 139 138 return -EIO; 140 139 } 141 140 142 - return send_bytes; 141 + return -EIO; 143 142 } 144 143 145 144 static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector, ··· 150 149 int msg_bytes = 4; 151 150 u8 ack; 152 151 int ret; 152 + unsigned retry; 153 153 154 154 msg[0] = address; 155 155 msg[1] = address >> 8; 156 156 msg[2] = AUX_NATIVE_READ << 4; 157 157 msg[3] = (msg_bytes << 4) | (recv_bytes - 1); 158 158 159 - while (1) { 159 + for (retry = 0; retry < 4; retry++) { 160 160 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, 161 161 msg, msg_bytes, recv, recv_bytes, delay, &ack); 162 - if (ret == 0) 163 - return -EPROTO; 164 162 if (ret < 0) 165 163 return ret; 166 164 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) 167 165 return ret; 168 166 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 169 167 udelay(400); 168 + else if (ret == 0) 169 + return -EPROTO; 170 170 else 171 171 return -EIO; 172 172 } 173 + 174 + return -EIO; 173 175 } 174 176 175 177 static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector,
-44
drivers/gpu/drm/radeon/evergreen.c
··· 1590 1590 return backend_map; 1591 1591 } 1592 1592 1593 - static void evergreen_program_channel_remap(struct radeon_device *rdev) 1594 - { 1595 - u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp; 1596 - 1597 - tmp = RREG32(MC_SHARED_CHMAP); 1598 - switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 1599 - case 0: 1600 - case 1: 1601 - case 2: 1602 - case 3: 1603 - default: 1604 - /* default mapping */ 1605 - mc_shared_chremap = 0x00fac688; 1606 - break; 1607 - } 1608 - 1609 - switch (rdev->family) { 1610 - case CHIP_HEMLOCK: 1611 - case CHIP_CYPRESS: 1612 - case CHIP_BARTS: 1613 - tcp_chan_steer_lo = 0x54763210; 1614 - tcp_chan_steer_hi = 0x0000ba98; 1615 - break; 1616 - case CHIP_JUNIPER: 1617 - case CHIP_REDWOOD: 1618 - case CHIP_CEDAR: 1619 - case CHIP_PALM: 1620 - case CHIP_SUMO: 1621 - case CHIP_SUMO2: 1622 - case CHIP_TURKS: 1623 - case CHIP_CAICOS: 1624 - default: 1625 - tcp_chan_steer_lo = 0x76543210; 1626 - tcp_chan_steer_hi = 0x0000ba98; 1627 - break; 1628 - } 1629 - 1630 - WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo); 1631 - WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi); 1632 - WREG32(MC_SHARED_CHREMAP, mc_shared_chremap); 1633 - } 1634 - 1635 1593 static void evergreen_gpu_init(struct radeon_device *rdev) 1636 1594 { 1637 1595 u32 cc_rb_backend_disable = 0; ··· 2035 2077 WREG32(GB_ADDR_CONFIG, gb_addr_config); 2036 2078 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); 2037 2079 WREG32(HDP_ADDR_CONFIG, gb_addr_config); 2038 - 2039 - evergreen_program_channel_remap(rdev); 2040 2080 2041 2081 num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1; 2042 2082 grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
-32
drivers/gpu/drm/radeon/ni.c
··· 569 569 return backend_map; 570 570 } 571 571 572 - static void cayman_program_channel_remap(struct radeon_device *rdev) 573 - { 574 - u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp; 575 - 576 - tmp = RREG32(MC_SHARED_CHMAP); 577 - switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 578 - case 0: 579 - case 1: 580 - case 2: 581 - case 3: 582 - default: 583 - /* default mapping */ 584 - mc_shared_chremap = 0x00fac688; 585 - break; 586 - } 587 - 588 - switch (rdev->family) { 589 - case CHIP_CAYMAN: 590 - default: 591 - //tcp_chan_steer_lo = 0x54763210 592 - tcp_chan_steer_lo = 0x76543210; 593 - tcp_chan_steer_hi = 0x0000ba98; 594 - break; 595 - } 596 - 597 - WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo); 598 - WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi); 599 - WREG32(MC_SHARED_CHREMAP, mc_shared_chremap); 600 - } 601 - 602 572 static u32 cayman_get_disable_mask_per_asic(struct radeon_device *rdev, 603 573 u32 disable_mask_per_se, 604 574 u32 max_disable_mask_per_se, ··· 811 841 WREG32(GB_ADDR_CONFIG, gb_addr_config); 812 842 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); 813 843 WREG32(HDP_ADDR_CONFIG, gb_addr_config); 814 - 815 - cayman_program_channel_remap(rdev); 816 844 817 845 /* primary versions */ 818 846 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
+4 -4
drivers/gpu/drm/radeon/radeon_connectors.c
··· 68 68 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 69 69 int saved_dpms = connector->dpms; 70 70 71 - if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd) && 72 - radeon_dp_needs_link_train(radeon_connector)) 73 - drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 74 - else 71 + /* Only turn off the display it it's physically disconnected */ 72 + if (!radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) 75 73 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 74 + else if (radeon_dp_needs_link_train(radeon_connector)) 75 + drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 76 76 connector->dpms = saved_dpms; 77 77 } 78 78 }
+19 -21
drivers/gpu/drm/radeon/radeon_cursor.c
··· 208 208 int xorigin = 0, yorigin = 0; 209 209 int w = radeon_crtc->cursor_width; 210 210 211 - if (x < 0) 212 - xorigin = -x + 1; 213 - if (y < 0) 214 - yorigin = -y + 1; 215 - if (xorigin >= CURSOR_WIDTH) 216 - xorigin = CURSOR_WIDTH - 1; 217 - if (yorigin >= CURSOR_HEIGHT) 218 - yorigin = CURSOR_HEIGHT - 1; 211 + if (ASIC_IS_AVIVO(rdev)) { 212 + /* avivo cursor are offset into the total surface */ 213 + x += crtc->x; 214 + y += crtc->y; 215 + } 216 + DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); 217 + 218 + if (x < 0) { 219 + xorigin = min(-x, CURSOR_WIDTH - 1); 220 + x = 0; 221 + } 222 + if (y < 0) { 223 + yorigin = min(-y, CURSOR_HEIGHT - 1); 224 + y = 0; 225 + } 219 226 220 227 if (ASIC_IS_AVIVO(rdev)) { 221 228 int i = 0; 222 229 struct drm_crtc *crtc_p; 223 - 224 - /* avivo cursor are offset into the total surface */ 225 - x += crtc->x; 226 - y += crtc->y; 227 - DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); 228 230 229 231 /* avivo cursor image can't end on 128 pixel boundary or 230 232 * go past the end of the frame if both crtcs are enabled ··· 255 253 256 254 radeon_lock_cursor(crtc, true); 257 255 if (ASIC_IS_DCE4(rdev)) { 258 - WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, 259 - ((xorigin ? 0 : x) << 16) | 260 - (yorigin ? 0 : y)); 256 + WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y); 261 257 WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin); 262 258 WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset, 263 259 ((w - 1) << 16) | (radeon_crtc->cursor_height - 1)); 264 260 } else if (ASIC_IS_AVIVO(rdev)) { 265 - WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, 266 - ((xorigin ? 0 : x) << 16) | 267 - (yorigin ? 0 : y)); 261 + WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y); 268 262 WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin); 269 263 WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset, 270 264 ((w - 1) << 16) | (radeon_crtc->cursor_height - 1)); ··· 274 276 | yorigin)); 275 277 WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset, 276 278 (RADEON_CUR_LOCK 277 - | ((xorigin ? 0 : x) << 16) 278 - | (yorigin ? 0 : y))); 279 + | (x << 16) 280 + | y)); 279 281 /* offset is from DISP(2)_BASE_ADDRESS */ 280 282 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, (radeon_crtc->legacy_cursor_offset + 281 283 (yorigin * 256)));
-51
drivers/gpu/drm/radeon/rv770.c
··· 536 536 return backend_map; 537 537 } 538 538 539 - static void rv770_program_channel_remap(struct radeon_device *rdev) 540 - { 541 - u32 tcp_chan_steer, mc_shared_chremap, tmp; 542 - bool force_no_swizzle; 543 - 544 - switch (rdev->family) { 545 - case CHIP_RV770: 546 - case CHIP_RV730: 547 - force_no_swizzle = false; 548 - break; 549 - case CHIP_RV710: 550 - case CHIP_RV740: 551 - default: 552 - force_no_swizzle = true; 553 - break; 554 - } 555 - 556 - tmp = RREG32(MC_SHARED_CHMAP); 557 - switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 558 - case 0: 559 - case 1: 560 - default: 561 - /* default mapping */ 562 - mc_shared_chremap = 0x00fac688; 563 - break; 564 - case 2: 565 - case 3: 566 - if (force_no_swizzle) 567 - mc_shared_chremap = 0x00fac688; 568 - else 569 - mc_shared_chremap = 0x00bbc298; 570 - break; 571 - } 572 - 573 - if (rdev->family == CHIP_RV740) 574 - tcp_chan_steer = 0x00ef2a60; 575 - else 576 - tcp_chan_steer = 0x00fac688; 577 - 578 - /* RV770 CE has special chremap setup */ 579 - if (rdev->pdev->device == 0x944e) { 580 - tcp_chan_steer = 0x00b08b08; 581 - mc_shared_chremap = 0x00b08b08; 582 - } 583 - 584 - WREG32(TCP_CHAN_STEER, tcp_chan_steer); 585 - WREG32(MC_SHARED_CHREMAP, mc_shared_chremap); 586 - } 587 - 588 539 static void rv770_gpu_init(struct radeon_device *rdev) 589 540 { 590 541 int i, j, num_qd_pipes; ··· 735 784 WREG32(GB_TILING_CONFIG, gb_tiling_config); 736 785 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 737 786 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 738 - 739 - rv770_program_channel_remap(rdev); 740 787 741 788 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); 742 789 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);