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Merge branch 'pm-cpufreq'

Merge cpufreq updates for 6.19-rc1:

- Add OPP and bandwidth support for Tegra186 (Aaron Kling)

- Optimizations for parameter array handling in the amd-pstate cpufreq
driver (Mario Limonciello)

- Fix for mode changes with offline CPUs in the amd-pstate cpufreq
driver (Gautham Shenoy)

- Preserve freq_table_sorted across suspend/hibernate in the cpufreq
core (Zihuan Zhang)

- Adjust energy model rules for Intel hybrid platforms in the
intel_pstate cpufreq driver and improve printing of debug messages
in it (Rafael Wysocki)

- Replace deprecated strcpy() in cpufreq_unregister_governor()
(Thorsten Blum)

- Fix duplicate hyperlink target errors in the intel_pstate cpufreq
driver documentation and use :ref: directive for internal linking in
it (Swaraj Gaikwad, Bagas Sanjaya)

- Add Diamond Rapids OOB mode support to the intel_pstate cpufreq
driver (Kuppuswamy Sathyanarayanan)

- Use mutex guard for driver locking in the intel_pstate driver and
eliminate some code duplication from it (Rafael Wysocki)

- Replace udelay() with usleep_range() in ACPI cpufreq (Kaushlendra
Kumar)

- Minor improvements to various cpufreq drivers (Christian Marangi, Hal
Feng, Jie Zhan, Marco Crivellari, Miaoqian Lin, and Shuhao Fu)

* pm-cpufreq: (27 commits)
cpufreq: qcom-nvmem: fix compilation warning for qcom_cpufreq_ipq806x_match_list
cpufreq: ACPI: Replace udelay() with usleep_range()
cpufreq: intel_pstate: Eliminate some code duplication
cpufreq: intel_pstate: Use mutex guard for driver locking
cpufreq/amd-pstate: Call cppc_set_auto_sel() only for online CPUs
cpufreq/amd-pstate: Add static asserts for EPP indices
cpufreq/amd-pstate: Fix some whitespace issues
cpufreq/amd-pstate: Adjust return values in amd_pstate_update_status()
cpufreq/amd-pstate: Make amd_pstate_get_mode_string() never return NULL
cpufreq/amd-pstate: Drop NULL value from amd_pstate_mode_string
cpufreq/amd-pstate: Use sysfs_match_string() for epp
cpufreq: tegra194: add WQ_PERCPU to alloc_workqueue users
cpufreq: qcom-nvmem: add compatible fallback for ipq806x for no SMEM
Documentation: intel-pstate: Use :ref: directive for internal linking
cpufreq: intel_pstate: Add Diamond Rapids OOB mode support
Documentation: intel_pstate: fix duplicate hyperlink target errors
cpufreq: CPPC: Don't warn if FIE init fails to read counters
cpufreq: nforce2: fix reference count leak in nforce2
cpufreq: tegra186: add OPP support and set bandwidth
cpufreq: dt-platdev: Add JH7110S SOC to the allowlist
...

Rafael J. Wysocki 1fe25237 f086594a

+390 -235
+74 -59
Documentation/admin-guide/pm/intel_pstate.rst
··· 48 48 command line. However, its configuration can be adjusted via ``sysfs`` to a 49 49 great extent. In some configurations it even is possible to unregister it via 50 50 ``sysfs`` which allows another ``CPUFreq`` scaling driver to be loaded and 51 - registered (see `below <status_attr_>`_). 51 + registered (see :ref:`below <status_attr>`). 52 52 53 + .. _operation_modes: 53 54 54 55 Operation Modes 55 56 =============== ··· 62 61 a certain performance scaling algorithm. Which of them will be in effect 63 62 depends on what kernel command line options are used and on the capabilities of 64 63 the processor. 64 + 65 + .. _active_mode: 65 66 66 67 Active Mode 67 68 ----------- ··· 97 94 Namely, if that option is set, the ``performance`` algorithm will be used by 98 95 default, and the other one will be used by default if it is not set. 99 96 97 + .. _active_mode_hwp: 98 + 100 99 Active Mode With HWP 101 100 ~~~~~~~~~~~~~~~~~~~~ 102 101 ··· 128 123 internal P-state selection logic is expected to focus entirely on performance. 129 124 130 125 This will override the EPP/EPB setting coming from the ``sysfs`` interface 131 - (see `Energy vs Performance Hints`_ below). Moreover, any attempts to change 126 + (see :ref:`energy_performance_hints` below). Moreover, any attempts to change 132 127 the EPP/EPB to a value different from 0 ("performance") via ``sysfs`` in this 133 128 configuration will be rejected. 134 129 ··· 196 191 This is the default P-state selection algorithm if the 197 192 :c:macro:`CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE` kernel configuration option 198 193 is not set. 194 + 195 + .. _passive_mode: 199 196 200 197 Passive Mode 201 198 ------------ ··· 296 289 the entire range of available P-states, including the whole turbo range, to the 297 290 ``CPUFreq`` core and (in the passive mode) to generic scaling governors. This 298 291 generally causes turbo P-states to be set more often when ``intel_pstate`` is 299 - used relative to ACPI-based CPU performance scaling (see `below <acpi-cpufreq_>`_ 300 - for more information). 292 + used relative to ACPI-based CPU performance scaling (see 293 + :ref:`below <acpi-cpufreq>` for more information). 301 294 302 295 Moreover, since ``intel_pstate`` always knows what the real turbo threshold is 303 296 (even if the Configurable TDP feature is enabled in the processor), its 304 - ``no_turbo`` attribute in ``sysfs`` (described `below <no_turbo_attr_>`_) should 297 + ``no_turbo`` attribute in ``sysfs`` (described :ref:`below <no_turbo_attr>`) should 305 298 work as expected in all cases (that is, if set to disable turbo P-states, it 306 299 always should prevent ``intel_pstate`` from using them). 307 300 ··· 314 307 315 308 * The minimum supported P-state. 316 309 317 - * The maximum supported `non-turbo P-state <turbo_>`_. 310 + * The maximum supported :ref:`non-turbo P-state <turbo>`. 318 311 319 312 * Whether or not turbo P-states are supported at all. 320 313 321 - * The maximum supported `one-core turbo P-state <turbo_>`_ (if turbo P-states 322 - are supported). 314 + * The maximum supported :ref:`one-core turbo P-state <turbo>` (if turbo 315 + P-states are supported). 323 316 324 317 * The scaling formula to translate the driver's internal representation 325 318 of P-states into frequencies and the other way around. ··· 407 400 408 401 If ``CONFIG_ENERGY_MODEL`` has been set during kernel configuration and 409 402 ``intel_pstate`` runs on a hybrid processor without SMT, in addition to enabling 410 - `CAS <CAS_>`_ it registers an Energy Model for the processor. This allows the 403 + :ref:`CAS` it registers an Energy Model for the processor. This allows the 411 404 Energy-Aware Scheduling (EAS) support to be enabled in the CPU scheduler if 412 405 ``schedutil`` is used as the ``CPUFreq`` governor which requires ``intel_pstate`` 413 - to operate in the `passive mode <Passive Mode_>`_. 406 + to operate in the :ref:`passive mode <passive_mode>`. 414 407 415 408 The Energy Model registered by ``intel_pstate`` is artificial (that is, it is 416 409 based on abstract cost values and it does not include any real power numbers) ··· 439 432 User Space Interface in ``sysfs`` 440 433 ================================= 441 434 435 + .. _global_attributes: 436 + 442 437 Global Attributes 443 438 ----------------- 444 439 ··· 453 444 454 445 ``max_perf_pct`` 455 446 Maximum P-state the driver is allowed to set in percent of the 456 - maximum supported performance level (the highest supported `turbo 457 - P-state <turbo_>`_). 447 + maximum supported performance level (the highest supported :ref:`turbo 448 + P-state <turbo>`). 458 449 459 450 This attribute will not be exposed if the 460 451 ``intel_pstate=per_cpu_perf_limits`` argument is present in the kernel ··· 462 453 463 454 ``min_perf_pct`` 464 455 Minimum P-state the driver is allowed to set in percent of the 465 - maximum supported performance level (the highest supported `turbo 466 - P-state <turbo_>`_). 456 + maximum supported performance level (the highest supported :ref:`turbo 457 + P-state <turbo>`). 467 458 468 459 This attribute will not be exposed if the 469 460 ``intel_pstate=per_cpu_perf_limits`` argument is present in the kernel ··· 472 463 ``num_pstates`` 473 464 Number of P-states supported by the processor (between 0 and 255 474 465 inclusive) including both turbo and non-turbo P-states (see 475 - `Turbo P-states Support`_). 466 + :ref:`turbo`). 476 467 477 468 This attribute is present only if the value exposed by it is the same 478 469 for all of the CPUs in the system. 479 470 480 471 The value of this attribute is not affected by the ``no_turbo`` 481 - setting described `below <no_turbo_attr_>`_. 472 + setting described :ref:`below <no_turbo_attr>`. 482 473 483 474 This attribute is read-only. 484 475 485 476 ``turbo_pct`` 486 - Ratio of the `turbo range <turbo_>`_ size to the size of the entire 477 + Ratio of the :ref:`turbo range <turbo>` size to the size of the entire 487 478 range of supported P-states, in percent. 488 479 489 480 This attribute is present only if the value exposed by it is the same ··· 495 486 496 487 ``no_turbo`` 497 488 If set (equal to 1), the driver is not allowed to set any turbo P-states 498 - (see `Turbo P-states Support`_). If unset (equal to 0, which is the 489 + (see :ref:`turbo`). If unset (equal to 0, which is the 499 490 default), turbo P-states can be set by the driver. 500 491 [Note that ``intel_pstate`` does not support the general ``boost`` 501 492 attribute (supported by some other scaling drivers) which is replaced ··· 504 495 This attribute does not affect the maximum supported frequency value 505 496 supplied to the ``CPUFreq`` core and exposed via the policy interface, 506 497 but it affects the maximum possible value of per-policy P-state limits 507 - (see `Interpretation of Policy Attributes`_ below for details). 498 + (see :ref:`policy_attributes_interpretation` below for details). 508 499 509 500 ``hwp_dynamic_boost`` 510 501 This attribute is only present if ``intel_pstate`` works in the 511 - `active mode with the HWP feature enabled <Active Mode With HWP_>`_ in 502 + :ref:`active mode with the HWP feature enabled <active_mode_hwp>` in 512 503 the processor. If set (equal to 1), it causes the minimum P-state limit 513 504 to be increased dynamically for a short time whenever a task previously 514 505 waiting on I/O is selected to run on a given logical CPU (the purpose ··· 523 514 Operation mode of the driver: "active", "passive" or "off". 524 515 525 516 "active" 526 - The driver is functional and in the `active mode 527 - <Active Mode_>`_. 517 + The driver is functional and in the :ref:`active mode 518 + <active_mode>`. 528 519 529 520 "passive" 530 - The driver is functional and in the `passive mode 531 - <Passive Mode_>`_. 521 + The driver is functional and in the :ref:`passive mode 522 + <passive_mode>`. 532 523 533 524 "off" 534 525 The driver is not functional (it is not registered as a scaling ··· 556 547 attribute to "1" enables the energy-efficiency optimizations and setting 557 548 to "0" disables them. 558 549 550 + .. _policy_attributes_interpretation: 551 + 559 552 Interpretation of Policy Attributes 560 553 ----------------------------------- 561 554 562 555 The interpretation of some ``CPUFreq`` policy attributes described in 563 556 Documentation/admin-guide/pm/cpufreq.rst is special with ``intel_pstate`` 564 557 as the current scaling driver and it generally depends on the driver's 565 - `operation mode <Operation Modes_>`_. 558 + :ref:`operation mode <operation_modes>`. 566 559 567 560 First of all, the values of the ``cpuinfo_max_freq``, ``cpuinfo_min_freq`` and 568 561 ``scaling_cur_freq`` attributes are produced by applying a processor-specific ··· 573 562 attributes are capped by the frequency corresponding to the maximum P-state that 574 563 the driver is allowed to set. 575 564 576 - If the ``no_turbo`` `global attribute <no_turbo_attr_>`_ is set, the driver is 577 - not allowed to use turbo P-states, so the maximum value of ``scaling_max_freq`` 578 - and ``scaling_min_freq`` is limited to the maximum non-turbo P-state frequency. 565 + If the ``no_turbo`` :ref:`global attribute <no_turbo_attr>` is set, the driver 566 + is not allowed to use turbo P-states, so the maximum value of 567 + ``scaling_max_freq`` and ``scaling_min_freq`` is limited to the maximum 568 + non-turbo P-state frequency. 579 569 Accordingly, setting ``no_turbo`` causes ``scaling_max_freq`` and 580 570 ``scaling_min_freq`` to go down to that value if they were above it before. 581 571 However, the old values of ``scaling_max_freq`` and ``scaling_min_freq`` will be ··· 588 576 which also is the value of ``cpuinfo_max_freq`` in either case. 589 577 590 578 Next, the following policy attributes have special meaning if 591 - ``intel_pstate`` works in the `active mode <Active Mode_>`_: 579 + ``intel_pstate`` works in the :ref:`active mode <active_mode>`: 592 580 593 581 ``scaling_available_governors`` 594 582 List of P-state selection algorithms provided by ``intel_pstate``. ··· 609 597 Shows the base frequency of the CPU. Any frequency above this will be 610 598 in the turbo frequency range. 611 599 612 - The meaning of these attributes in the `passive mode <Passive Mode_>`_ is the 600 + The meaning of these attributes in the :ref:`passive mode <passive_mode>` is the 613 601 same as for other scaling drivers. 614 602 615 603 Additionally, the value of the ``scaling_driver`` attribute for ``intel_pstate`` 616 604 depends on the operation mode of the driver. Namely, it is either 617 - "intel_pstate" (in the `active mode <Active Mode_>`_) or "intel_cpufreq" (in the 618 - `passive mode <Passive Mode_>`_). 605 + "intel_pstate" (in the :ref:`active mode <active_mode>`) or "intel_cpufreq" 606 + (in the :ref:`passive mode <passive_mode>`). 607 + 608 + .. _pstate_limits_coordination: 619 609 620 610 Coordination of P-State Limits 621 611 ------------------------------ 622 612 623 613 ``intel_pstate`` allows P-state limits to be set in two ways: with the help of 624 - the ``max_perf_pct`` and ``min_perf_pct`` `global attributes 625 - <Global Attributes_>`_ or via the ``scaling_max_freq`` and ``scaling_min_freq`` 614 + the ``max_perf_pct`` and ``min_perf_pct`` :ref:`global attributes 615 + <global_attributes>` or via the ``scaling_max_freq`` and ``scaling_min_freq`` 626 616 ``CPUFreq`` policy attributes. The coordination between those limits is based 627 617 on the following rules, regardless of the current operation mode of the driver: 628 618 ··· 646 632 647 633 3. The global and per-policy limits can be set independently. 648 634 649 - In the `active mode with the HWP feature enabled <Active Mode With HWP_>`_, the 635 + In the :ref:`active mode with the HWP feature enabled <active_mode_hwp>`, the 650 636 resulting effective values are written into hardware registers whenever the 651 637 limits change in order to request its internal P-state selection logic to always 652 638 set P-states within these limits. Otherwise, the limits are taken into account 653 - by scaling governors (in the `passive mode <Passive Mode_>`_) and by the driver 654 - every time before setting a new P-state for a CPU. 639 + by scaling governors (in the :ref:`passive mode <passive_mode>`) and by the 640 + driver every time before setting a new P-state for a CPU. 655 641 656 642 Additionally, if the ``intel_pstate=per_cpu_perf_limits`` command line argument 657 643 is passed to the kernel, ``max_perf_pct`` and ``min_perf_pct`` are not exposed 658 644 at all and the only way to set the limits is by using the policy attributes. 659 645 646 + .. _energy_performance_hints: 660 647 661 648 Energy vs Performance Hints 662 649 --------------------------- ··· 717 702 On those systems each ``_PSS`` object returns a list of P-states supported by 718 703 the corresponding CPU which basically is a subset of the P-states range that can 719 704 be used by ``intel_pstate`` on the same system, with one exception: the whole 720 - `turbo range <turbo_>`_ is represented by one item in it (the topmost one). By 721 - convention, the frequency returned by ``_PSS`` for that item is greater by 1 MHz 722 - than the frequency of the highest non-turbo P-state listed by it, but the 705 + :ref:`turbo range <turbo>` is represented by one item in it (the topmost one). 706 + By convention, the frequency returned by ``_PSS`` for that item is greater by 707 + 1 MHz than the frequency of the highest non-turbo P-state listed by it, but the 723 708 corresponding P-state representation (following the hardware specification) 724 709 returned for it matches the maximum supported turbo P-state (or is the 725 710 special value 255 meaning essentially "go as high as you can get"). ··· 745 730 instead. 746 731 747 732 One more issue related to that may appear on systems supporting the 748 - `Configurable TDP feature <turbo_>`_ allowing the platform firmware to set the 749 - turbo threshold. Namely, if that is not coordinated with the lists of P-states 750 - returned by ``_PSS`` properly, there may be more than one item corresponding to 751 - a turbo P-state in those lists and there may be a problem with avoiding the 752 - turbo range (if desirable or necessary). Usually, to avoid using turbo 753 - P-states overall, ``acpi-cpufreq`` simply avoids using the topmost state listed 754 - by ``_PSS``, but that is not sufficient when there are other turbo P-states in 755 - the list returned by it. 733 + :ref:`Configurable TDP feature <turbo>` allowing the platform firmware to set 734 + the turbo threshold. Namely, if that is not coordinated with the lists of 735 + P-states returned by ``_PSS`` properly, there may be more than one item 736 + corresponding to a turbo P-state in those lists and there may be a problem with 737 + avoiding the turbo range (if desirable or necessary). Usually, to avoid using 738 + turbo P-states overall, ``acpi-cpufreq`` simply avoids using the topmost state 739 + listed by ``_PSS``, but that is not sufficient when there are other turbo 740 + P-states in the list returned by it. 756 741 757 742 Apart from the above, ``acpi-cpufreq`` works like ``intel_pstate`` in the 758 - `passive mode <Passive Mode_>`_, except that the number of P-states it can set 759 - is limited to the ones listed by the ACPI ``_PSS`` objects. 743 + :ref:`passive mode <passive_mode>`, except that the number of P-states it can 744 + set is limited to the ones listed by the ACPI ``_PSS`` objects. 760 745 761 746 762 747 Kernel Command Line Options for ``intel_pstate`` ··· 771 756 processor is supported by it. 772 757 773 758 ``active`` 774 - Register ``intel_pstate`` in the `active mode <Active Mode_>`_ to start 775 - with. 759 + Register ``intel_pstate`` in the :ref:`active mode <active_mode>` to 760 + start with. 776 761 777 762 ``passive`` 778 - Register ``intel_pstate`` in the `passive mode <Passive Mode_>`_ to 763 + Register ``intel_pstate`` in the :ref:`passive mode <passive_mode>` to 779 764 start with. 780 765 781 766 ``force`` ··· 808 793 and this option has no effect. 809 794 810 795 ``per_cpu_perf_limits`` 811 - Use per-logical-CPU P-State limits (see `Coordination of P-state 812 - Limits`_ for details). 796 + Use per-logical-CPU P-State limits (see 797 + :ref:`pstate_limits_coordination` for details). 813 798 814 799 ``no_cas`` 815 - Do not enable `capacity-aware scheduling <CAS_>`_ which is enabled by 816 - default on hybrid systems without SMT. 800 + Do not enable :ref:`capacity-aware scheduling <CAS>` which is enabled 801 + by default on hybrid systems without SMT. 817 802 818 803 Diagnostics and Tuning 819 804 ====================== ··· 825 810 diagnostics. One of them is the ``cpu_frequency`` trace event generally used 826 811 by ``CPUFreq``, and the other one is the ``pstate_sample`` trace event specific 827 812 to ``intel_pstate``. Both of them are triggered by ``intel_pstate`` only if 828 - it works in the `active mode <Active Mode_>`_. 813 + it works in the :ref:`active mode <active_mode>`. 829 814 830 815 The following sequence of shell commands can be used to enable them and see 831 816 their output (if the kernel is generally configured to support event tracing):: ··· 837 822 gnome-terminal--4510 [001] ..s. 1177.680733: pstate_sample: core_busy=107 scaled=94 from=26 to=26 mperf=1143818 aperf=1230607 tsc=29838618 freq=2474476 838 823 cat-5235 [002] ..s. 1177.681723: cpu_frequency: state=2900000 cpu_id=2 839 824 840 - If ``intel_pstate`` works in the `passive mode <Passive Mode_>`_, the 825 + If ``intel_pstate`` works in the :ref:`passive mode <passive_mode>`, the 841 826 ``cpu_frequency`` trace event will be triggered either by the ``schedutil`` 842 827 scaling governor (for the policies it is attached to), or by the ``CPUFreq`` 843 828 core (for the policies with other scaling governors).
+1 -1
drivers/cpufreq/acpi-cpufreq.c
··· 395 395 cur_freq = extract_freq(policy, get_cur_val(mask, data)); 396 396 if (cur_freq == freq) 397 397 return 1; 398 - udelay(10); 398 + usleep_range(10, 15); 399 399 } 400 400 return 0; 401 401 }
+15 -20
drivers/cpufreq/amd-pstate.c
··· 65 65 [AMD_PSTATE_PASSIVE] = "passive", 66 66 [AMD_PSTATE_ACTIVE] = "active", 67 67 [AMD_PSTATE_GUIDED] = "guided", 68 - NULL, 69 68 }; 69 + static_assert(ARRAY_SIZE(amd_pstate_mode_string) == AMD_PSTATE_MAX); 70 70 71 71 const char *amd_pstate_get_mode_string(enum amd_pstate_mode mode) 72 72 { 73 - if (mode < 0 || mode >= AMD_PSTATE_MAX) 74 - return NULL; 73 + if (mode < AMD_PSTATE_UNDEFINED || mode >= AMD_PSTATE_MAX) 74 + mode = AMD_PSTATE_UNDEFINED; 75 75 return amd_pstate_mode_string[mode]; 76 76 } 77 77 EXPORT_SYMBOL_GPL(amd_pstate_get_mode_string); ··· 110 110 EPP_INDEX_BALANCE_PERFORMANCE, 111 111 EPP_INDEX_BALANCE_POWERSAVE, 112 112 EPP_INDEX_POWERSAVE, 113 + EPP_INDEX_MAX, 113 114 }; 114 115 115 116 static const char * const energy_perf_strings[] = { ··· 119 118 [EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance", 120 119 [EPP_INDEX_BALANCE_POWERSAVE] = "balance_power", 121 120 [EPP_INDEX_POWERSAVE] = "power", 122 - NULL 123 121 }; 122 + static_assert(ARRAY_SIZE(energy_perf_strings) == EPP_INDEX_MAX); 124 123 125 124 static unsigned int epp_values[] = { 126 125 [EPP_INDEX_DEFAULT] = 0, ··· 128 127 [EPP_INDEX_BALANCE_PERFORMANCE] = AMD_CPPC_EPP_BALANCE_PERFORMANCE, 129 128 [EPP_INDEX_BALANCE_POWERSAVE] = AMD_CPPC_EPP_BALANCE_POWERSAVE, 130 129 [EPP_INDEX_POWERSAVE] = AMD_CPPC_EPP_POWERSAVE, 131 - }; 130 + }; 131 + static_assert(ARRAY_SIZE(epp_values) == EPP_INDEX_MAX); 132 132 133 133 typedef int (*cppc_mode_transition_fn)(int); 134 134 ··· 185 183 { 186 184 int i; 187 185 188 - for (i=0; i < AMD_PSTATE_MAX; i++) { 186 + for (i = 0; i < AMD_PSTATE_MAX; i++) { 189 187 if (!strncmp(str, amd_pstate_mode_string[i], size)) 190 188 return i; 191 189 } ··· 1139 1137 static ssize_t show_energy_performance_available_preferences( 1140 1138 struct cpufreq_policy *policy, char *buf) 1141 1139 { 1142 - int i = 0; 1143 - int offset = 0; 1140 + int offset = 0, i; 1144 1141 struct amd_cpudata *cpudata = policy->driver_data; 1145 1142 1146 1143 if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) 1147 1144 return sysfs_emit_at(buf, offset, "%s\n", 1148 1145 energy_perf_strings[EPP_INDEX_PERFORMANCE]); 1149 1146 1150 - while (energy_perf_strings[i] != NULL) 1151 - offset += sysfs_emit_at(buf, offset, "%s ", energy_perf_strings[i++]); 1147 + for (i = 0; i < ARRAY_SIZE(energy_perf_strings); i++) 1148 + offset += sysfs_emit_at(buf, offset, "%s ", energy_perf_strings[i]); 1152 1149 1153 1150 offset += sysfs_emit_at(buf, offset, "\n"); 1154 1151 ··· 1158 1157 struct cpufreq_policy *policy, const char *buf, size_t count) 1159 1158 { 1160 1159 struct amd_cpudata *cpudata = policy->driver_data; 1161 - char str_preference[21]; 1162 1160 ssize_t ret; 1163 1161 u8 epp; 1164 1162 1165 - ret = sscanf(buf, "%20s", str_preference); 1166 - if (ret != 1) 1167 - return -EINVAL; 1168 - 1169 - ret = match_string(energy_perf_strings, -1, str_preference); 1163 + ret = sysfs_match_string(energy_perf_strings, buf); 1170 1164 if (ret < 0) 1171 1165 return -EINVAL; 1172 1166 ··· 1278 1282 if (cpu_feature_enabled(X86_FEATURE_CPPC) || cppc_state == AMD_PSTATE_ACTIVE) 1279 1283 return 0; 1280 1284 1281 - for_each_present_cpu(cpu) { 1285 + for_each_online_cpu(cpu) { 1282 1286 cppc_set_auto_sel(cpu, (cppc_state == AMD_PSTATE_PASSIVE) ? 0 : 1); 1283 1287 } 1284 1288 ··· 1349 1353 return -EINVAL; 1350 1354 1351 1355 mode_idx = get_mode_idx_from_str(buf, size); 1352 - 1353 - if (mode_idx < 0 || mode_idx >= AMD_PSTATE_MAX) 1354 - return -EINVAL; 1356 + if (mode_idx < 0) 1357 + return mode_idx; 1355 1358 1356 1359 if (mode_state_machine[cppc_state][mode_idx]) { 1357 1360 guard(mutex)(&amd_pstate_driver_lock);
+8 -9
drivers/cpufreq/cppc_cpufreq.c
··· 142 142 init_irq_work(&cppc_fi->irq_work, cppc_irq_work); 143 143 144 144 ret = cppc_get_perf_ctrs(cpu, &cppc_fi->prev_perf_fb_ctrs); 145 - if (ret) { 146 - pr_warn("%s: failed to read perf counters for cpu:%d: %d\n", 147 - __func__, cpu, ret); 148 145 149 - /* 150 - * Don't abort if the CPU was offline while the driver 151 - * was getting registered. 152 - */ 153 - if (cpu_online(cpu)) 154 - return; 146 + /* 147 + * Don't abort as the CPU was offline while the driver was 148 + * getting registered. 149 + */ 150 + if (ret && cpu_online(cpu)) { 151 + pr_debug("%s: failed to read perf counters for cpu:%d: %d\n", 152 + __func__, cpu, ret); 153 + return; 155 154 } 156 155 } 157 156
+1
drivers/cpufreq/cpufreq-dt-platdev.c
··· 87 87 { .compatible = "st-ericsson,u9540", }, 88 88 89 89 { .compatible = "starfive,jh7110", }, 90 + { .compatible = "starfive,jh7110s", }, 90 91 91 92 { .compatible = "ti,omap2", }, 92 93 { .compatible = "ti,omap4", },
+3
drivers/cpufreq/cpufreq-nforce2.c
··· 145 145 pci_read_config_dword(nforce2_sub5, NFORCE2_BOOTFSB, &fsb); 146 146 fsb /= 1000000; 147 147 148 + pci_dev_put(nforce2_sub5); 149 + 148 150 /* Check if PLL register is already set */ 149 151 pci_read_config_byte(nforce2_dev, NFORCE2_PLLENABLE, (u8 *)&temp); 150 152 ··· 428 426 static void __exit nforce2_exit(void) 429 427 { 430 428 cpufreq_unregister_driver(&nforce2_driver); 429 + pci_dev_put(nforce2_dev); 431 430 } 432 431 433 432 module_init(nforce2_init);
+7 -4
drivers/cpufreq/cpufreq.c
··· 1421 1421 * If there is a problem with its frequency table, take it 1422 1422 * offline and drop it. 1423 1423 */ 1424 - ret = cpufreq_table_validate_and_sort(policy); 1425 - if (ret) 1426 - goto out_offline_policy; 1424 + if (policy->freq_table_sorted != CPUFREQ_TABLE_SORTED_ASCENDING && 1425 + policy->freq_table_sorted != CPUFREQ_TABLE_SORTED_DESCENDING) { 1426 + ret = cpufreq_table_validate_and_sort(policy); 1427 + if (ret) 1428 + goto out_offline_policy; 1429 + } 1427 1430 1428 1431 /* related_cpus should at least include policy->cpus. */ 1429 1432 cpumask_copy(policy->related_cpus, policy->cpus); ··· 2553 2550 for_each_inactive_policy(policy) { 2554 2551 if (!strcmp(policy->last_governor, governor->name)) { 2555 2552 policy->governor = NULL; 2556 - strcpy(policy->last_governor, "\0"); 2553 + policy->last_governor[0] = '\0'; 2557 2554 } 2558 2555 } 2559 2556 read_unlock_irqrestore(&cpufreq_driver_lock, flags);
+99 -130
drivers/cpufreq/intel_pstate.c
··· 575 575 int scaling = cpu->pstate.scaling; 576 576 int freq; 577 577 578 - pr_debug("CPU%d: perf_ctl_max_phys = %d\n", cpu->cpu, perf_ctl_max_phys); 579 - pr_debug("CPU%d: perf_ctl_turbo = %d\n", cpu->cpu, perf_ctl_turbo); 580 - pr_debug("CPU%d: perf_ctl_scaling = %d\n", cpu->cpu, perf_ctl_scaling); 578 + pr_debug("CPU%d: PERF_CTL max_phys = %d\n", cpu->cpu, perf_ctl_max_phys); 579 + pr_debug("CPU%d: PERF_CTL turbo = %d\n", cpu->cpu, perf_ctl_turbo); 580 + pr_debug("CPU%d: PERF_CTL scaling = %d\n", cpu->cpu, perf_ctl_scaling); 581 581 pr_debug("CPU%d: HWP_CAP guaranteed = %d\n", cpu->cpu, cpu->pstate.max_pstate); 582 582 pr_debug("CPU%d: HWP_CAP highest = %d\n", cpu->cpu, cpu->pstate.turbo_pstate); 583 583 pr_debug("CPU%d: HWP-to-frequency scaling factor: %d\n", cpu->cpu, scaling); 584 + 585 + if (scaling == perf_ctl_scaling) 586 + return; 587 + 588 + hwp_is_hybrid = true; 584 589 585 590 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_pstate * scaling, 586 591 perf_ctl_scaling); ··· 914 909 [HWP_CPUFREQ_ATTR_COUNT] = NULL, 915 910 }; 916 911 912 + static u8 hybrid_get_cpu_type(unsigned int cpu) 913 + { 914 + return cpu_data(cpu).topo.intel_type; 915 + } 916 + 917 917 static bool no_cas __ro_after_init; 918 918 919 919 static struct cpudata *hybrid_max_perf_cpu __read_mostly; ··· 935 925 unsigned long *freq) 936 926 { 937 927 /* 938 - * Create "utilization bins" of 0-40%, 40%-60%, 60%-80%, and 80%-100% 939 - * of the maximum capacity such that two CPUs of the same type will be 940 - * regarded as equally attractive if the utilization of each of them 941 - * falls into the same bin, which should prevent tasks from being 942 - * migrated between them too often. 928 + * Create four "states" corresponding to 40%, 60%, 80%, and 100% of the 929 + * full capacity. 943 930 * 944 931 * For this purpose, return the "frequency" of 2 for the first 945 932 * performance level and otherwise leave the value set by the caller. ··· 950 943 return 0; 951 944 } 952 945 946 + static bool hybrid_has_l3(unsigned int cpu) 947 + { 948 + struct cpu_cacheinfo *cacheinfo = get_cpu_cacheinfo(cpu); 949 + unsigned int i; 950 + 951 + if (!cacheinfo) 952 + return false; 953 + 954 + for (i = 0; i < cacheinfo->num_leaves; i++) { 955 + if (cacheinfo->info_list[i].level == 3) 956 + return true; 957 + } 958 + 959 + return false; 960 + } 961 + 953 962 static int hybrid_get_cost(struct device *dev, unsigned long freq, 954 963 unsigned long *cost) 955 964 { 956 - struct pstate_data *pstate = &all_cpu_data[dev->id]->pstate; 957 - struct cpu_cacheinfo *cacheinfo = get_cpu_cacheinfo(dev->id); 958 - 965 + /* Facilitate load balancing between CPUs of the same type. */ 966 + *cost = freq; 959 967 /* 960 - * The smaller the perf-to-frequency scaling factor, the larger the IPC 961 - * ratio between the given CPU and the least capable CPU in the system. 962 - * Regard that IPC ratio as the primary cost component and assume that 963 - * the scaling factors for different CPU types will differ by at least 964 - * 5% and they will not be above INTEL_PSTATE_CORE_SCALING. 968 + * Adjust the cost depending on CPU type. 965 969 * 966 - * Add the freq value to the cost, so that the cost of running on CPUs 967 - * of the same type in different "utilization bins" is different. 970 + * The idea is to start loading up LPE-cores before E-cores and start 971 + * to populate E-cores when LPE-cores are utilized above 60% of the 972 + * capacity. Similarly, P-cores start to be populated when E-cores are 973 + * utilized above 60% of the capacity. 968 974 */ 969 - *cost = div_u64(100ULL * INTEL_PSTATE_CORE_SCALING, pstate->scaling) + freq; 970 - /* 971 - * Increase the cost slightly for CPUs able to access L3 to avoid 972 - * touching it in case some other CPUs of the same type can do the work 973 - * without it. 974 - */ 975 - if (cacheinfo) { 976 - unsigned int i; 977 - 978 - /* Check if L3 cache is there. */ 979 - for (i = 0; i < cacheinfo->num_leaves; i++) { 980 - if (cacheinfo->info_list[i].level == 3) { 981 - *cost += 2; 982 - break; 983 - } 984 - } 975 + if (hybrid_get_cpu_type(dev->id) == INTEL_CPU_TYPE_ATOM) { 976 + if (hybrid_has_l3(dev->id)) /* E-core */ 977 + *cost += 1; 978 + } else { /* P-core */ 979 + *cost += 2; 985 980 } 986 981 987 982 return 0; ··· 1046 1037 1047 1038 topology_set_cpu_scale(cpu->cpu, arch_scale_cpu_capacity(cpu->cpu)); 1048 1039 1049 - pr_debug("CPU%d: perf = %u, max. perf = %u, base perf = %d\n", cpu->cpu, 1050 - cpu->capacity_perf, hybrid_max_perf_cpu->capacity_perf, 1051 - cpu->pstate.max_pstate_physical); 1040 + pr_debug("CPU%d: capacity perf = %u, base perf = %u, sys max perf = %u\n", 1041 + cpu->cpu, cpu->capacity_perf, cpu->pstate.max_pstate_physical, 1042 + hybrid_max_perf_cpu->capacity_perf); 1052 1043 } 1053 1044 1054 1045 static void hybrid_clear_cpu_capacity(unsigned int cpunum) ··· 1393 1384 { 1394 1385 u64 power_ctl; 1395 1386 1396 - mutex_lock(&intel_pstate_driver_lock); 1387 + guard(mutex)(&intel_pstate_driver_lock); 1388 + 1397 1389 rdmsrq(MSR_IA32_POWER_CTL, power_ctl); 1398 1390 if (input) { 1399 1391 power_ctl &= ~BIT(MSR_IA32_POWER_CTL_BIT_EE); ··· 1404 1394 power_ctl_ee_state = POWER_CTL_EE_DISABLE; 1405 1395 } 1406 1396 wrmsrq(MSR_IA32_POWER_CTL, power_ctl); 1407 - mutex_unlock(&intel_pstate_driver_lock); 1408 1397 } 1409 1398 1410 1399 static void intel_pstate_hwp_enable(struct cpudata *cpudata); ··· 1525 1516 static ssize_t show_status(struct kobject *kobj, 1526 1517 struct kobj_attribute *attr, char *buf) 1527 1518 { 1528 - ssize_t ret; 1519 + guard(mutex)(&intel_pstate_driver_lock); 1529 1520 1530 - mutex_lock(&intel_pstate_driver_lock); 1531 - ret = intel_pstate_show_status(buf); 1532 - mutex_unlock(&intel_pstate_driver_lock); 1533 - 1534 - return ret; 1521 + return intel_pstate_show_status(buf); 1535 1522 } 1536 1523 1537 1524 static ssize_t store_status(struct kobject *a, struct kobj_attribute *b, ··· 1536 1531 char *p = memchr(buf, '\n', count); 1537 1532 int ret; 1538 1533 1539 - mutex_lock(&intel_pstate_driver_lock); 1540 - ret = intel_pstate_update_status(buf, p ? p - buf : count); 1541 - mutex_unlock(&intel_pstate_driver_lock); 1534 + guard(mutex)(&intel_pstate_driver_lock); 1542 1535 1543 - return ret < 0 ? ret : count; 1536 + ret = intel_pstate_update_status(buf, p ? p - buf : count); 1537 + if (ret < 0) 1538 + return ret; 1539 + 1540 + return count; 1544 1541 } 1545 1542 1546 1543 static ssize_t show_turbo_pct(struct kobject *kobj, ··· 1552 1545 int total, no_turbo, turbo_pct; 1553 1546 uint32_t turbo_fp; 1554 1547 1555 - mutex_lock(&intel_pstate_driver_lock); 1548 + guard(mutex)(&intel_pstate_driver_lock); 1556 1549 1557 - if (!intel_pstate_driver) { 1558 - mutex_unlock(&intel_pstate_driver_lock); 1550 + if (!intel_pstate_driver) 1559 1551 return -EAGAIN; 1560 - } 1561 1552 1562 1553 cpu = all_cpu_data[0]; 1563 1554 ··· 1563 1558 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1; 1564 1559 turbo_fp = div_fp(no_turbo, total); 1565 1560 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100))); 1566 - 1567 - mutex_unlock(&intel_pstate_driver_lock); 1568 1561 1569 1562 return sprintf(buf, "%u\n", turbo_pct); 1570 1563 } ··· 1573 1570 struct cpudata *cpu; 1574 1571 int total; 1575 1572 1576 - mutex_lock(&intel_pstate_driver_lock); 1573 + guard(mutex)(&intel_pstate_driver_lock); 1577 1574 1578 - if (!intel_pstate_driver) { 1579 - mutex_unlock(&intel_pstate_driver_lock); 1575 + if (!intel_pstate_driver) 1580 1576 return -EAGAIN; 1581 - } 1582 1577 1583 1578 cpu = all_cpu_data[0]; 1584 1579 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; 1585 - 1586 - mutex_unlock(&intel_pstate_driver_lock); 1587 1580 1588 1581 return sprintf(buf, "%u\n", total); 1589 1582 } ··· 1587 1588 static ssize_t show_no_turbo(struct kobject *kobj, 1588 1589 struct kobj_attribute *attr, char *buf) 1589 1590 { 1590 - ssize_t ret; 1591 + guard(mutex)(&intel_pstate_driver_lock); 1591 1592 1592 - mutex_lock(&intel_pstate_driver_lock); 1593 - 1594 - if (!intel_pstate_driver) { 1595 - mutex_unlock(&intel_pstate_driver_lock); 1593 + if (!intel_pstate_driver) 1596 1594 return -EAGAIN; 1597 - } 1598 1595 1599 - ret = sprintf(buf, "%u\n", global.no_turbo); 1600 - 1601 - mutex_unlock(&intel_pstate_driver_lock); 1602 - 1603 - return ret; 1596 + return sprintf(buf, "%u\n", global.no_turbo); 1604 1597 } 1605 1598 1606 1599 static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b, ··· 1604 1613 if (sscanf(buf, "%u", &input) != 1) 1605 1614 return -EINVAL; 1606 1615 1607 - mutex_lock(&intel_pstate_driver_lock); 1616 + guard(mutex)(&intel_pstate_driver_lock); 1608 1617 1609 - if (!intel_pstate_driver) { 1610 - count = -EAGAIN; 1611 - goto unlock_driver; 1612 - } 1618 + if (!intel_pstate_driver) 1619 + return -EAGAIN; 1613 1620 1614 1621 no_turbo = !!clamp_t(int, input, 0, 1); 1615 1622 1616 1623 WRITE_ONCE(global.turbo_disabled, turbo_is_disabled()); 1617 1624 if (global.turbo_disabled && !no_turbo) { 1618 1625 pr_notice("Turbo disabled by BIOS or unavailable on processor\n"); 1619 - count = -EPERM; 1620 1626 if (global.no_turbo) 1621 - goto unlock_driver; 1622 - else 1623 - no_turbo = 1; 1627 + return -EPERM; 1628 + 1629 + no_turbo = 1; 1624 1630 } 1625 1631 1626 - if (no_turbo == global.no_turbo) { 1627 - goto unlock_driver; 1628 - } 1632 + if (no_turbo == global.no_turbo) 1633 + return count; 1629 1634 1630 1635 WRITE_ONCE(global.no_turbo, no_turbo); 1631 1636 ··· 1640 1653 1641 1654 intel_pstate_update_limits_for_all(); 1642 1655 arch_set_max_freq_ratio(no_turbo); 1643 - 1644 - unlock_driver: 1645 - mutex_unlock(&intel_pstate_driver_lock); 1646 1656 1647 1657 return count; 1648 1658 } ··· 1690 1706 if (ret != 1) 1691 1707 return -EINVAL; 1692 1708 1693 - mutex_lock(&intel_pstate_driver_lock); 1709 + guard(mutex)(&intel_pstate_driver_lock); 1694 1710 1695 - if (!intel_pstate_driver) { 1696 - mutex_unlock(&intel_pstate_driver_lock); 1711 + if (!intel_pstate_driver) 1697 1712 return -EAGAIN; 1698 - } 1699 1713 1700 1714 mutex_lock(&intel_pstate_limits_lock); 1701 1715 ··· 1705 1723 intel_pstate_update_policies(); 1706 1724 else 1707 1725 update_qos_requests(FREQ_QOS_MAX); 1708 - 1709 - mutex_unlock(&intel_pstate_driver_lock); 1710 1726 1711 1727 return count; 1712 1728 } ··· 1719 1739 if (ret != 1) 1720 1740 return -EINVAL; 1721 1741 1722 - mutex_lock(&intel_pstate_driver_lock); 1742 + guard(mutex)(&intel_pstate_driver_lock); 1723 1743 1724 - if (!intel_pstate_driver) { 1725 - mutex_unlock(&intel_pstate_driver_lock); 1744 + if (!intel_pstate_driver) 1726 1745 return -EAGAIN; 1727 - } 1728 1746 1729 1747 mutex_lock(&intel_pstate_limits_lock); 1730 1748 ··· 1735 1757 intel_pstate_update_policies(); 1736 1758 else 1737 1759 update_qos_requests(FREQ_QOS_MIN); 1738 - 1739 - mutex_unlock(&intel_pstate_driver_lock); 1740 1760 1741 1761 return count; 1742 1762 } ··· 1756 1780 if (ret) 1757 1781 return ret; 1758 1782 1759 - mutex_lock(&intel_pstate_driver_lock); 1783 + guard(mutex)(&intel_pstate_driver_lock); 1784 + 1760 1785 hwp_boost = !!input; 1761 1786 intel_pstate_update_policies(); 1762 - mutex_unlock(&intel_pstate_driver_lock); 1763 1787 1764 1788 return count; 1765 1789 } ··· 2048 2072 intel_pstate_update_epp_defaults(cpudata); 2049 2073 } 2050 2074 2075 + static u64 get_perf_ctl_val(int pstate) 2076 + { 2077 + u64 val; 2078 + 2079 + val = (u64)pstate << 8; 2080 + if (READ_ONCE(global.no_turbo) && !READ_ONCE(global.turbo_disabled) && 2081 + cpu_feature_enabled(X86_FEATURE_IDA)) 2082 + val |= (u64)1 << 32; 2083 + 2084 + return val; 2085 + } 2086 + 2051 2087 static int atom_get_min_pstate(int not_used) 2052 2088 { 2053 2089 u64 value; ··· 2086 2098 2087 2099 static u64 atom_get_val(struct cpudata *cpudata, int pstate) 2088 2100 { 2089 - u64 val; 2101 + u64 val = get_perf_ctl_val(pstate); 2090 2102 int32_t vid_fp; 2091 2103 u32 vid; 2092 - 2093 - val = (u64)pstate << 8; 2094 - if (READ_ONCE(global.no_turbo) && !READ_ONCE(global.turbo_disabled) && 2095 - cpu_feature_enabled(X86_FEATURE_IDA)) 2096 - val |= (u64)1 << 32; 2097 2104 2098 2105 vid_fp = cpudata->vid.min + mul_fp( 2099 2106 int_tofp(pstate - cpudata->pstate.min_pstate), ··· 2249 2266 2250 2267 static u64 core_get_val(struct cpudata *cpudata, int pstate) 2251 2268 { 2252 - u64 val; 2253 - 2254 - val = (u64)pstate << 8; 2255 - if (READ_ONCE(global.no_turbo) && !READ_ONCE(global.turbo_disabled) && 2256 - cpu_feature_enabled(X86_FEATURE_IDA)) 2257 - val |= (u64)1 << 32; 2258 - 2259 - return val; 2269 + return get_perf_ctl_val(pstate); 2260 2270 } 2261 2271 2262 2272 static int knl_get_aperf_mperf_shift(void) ··· 2273 2297 static int hwp_get_cpu_scaling(int cpu) 2274 2298 { 2275 2299 if (hybrid_scaling_factor) { 2276 - struct cpuinfo_x86 *c = &cpu_data(cpu); 2277 - u8 cpu_type = c->topo.intel_type; 2278 - 2279 2300 /* 2280 2301 * Return the hybrid scaling factor for P-cores and use the 2281 2302 * default core scaling for E-cores. 2282 2303 */ 2283 - if (cpu_type == INTEL_CPU_TYPE_CORE) 2304 + if (hybrid_get_cpu_type(cpu) == INTEL_CPU_TYPE_CORE) 2284 2305 return hybrid_scaling_factor; 2285 2306 2286 - if (cpu_type == INTEL_CPU_TYPE_ATOM) 2287 - return core_get_scaling(); 2307 + return core_get_scaling(); 2288 2308 } 2289 2309 2290 2310 /* Use core scaling on non-hybrid systems. */ ··· 2315 2343 2316 2344 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) 2317 2345 { 2318 - int perf_ctl_max_phys = pstate_funcs.get_max_physical(cpu->cpu); 2319 2346 int perf_ctl_scaling = pstate_funcs.get_scaling(); 2320 2347 2348 + cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical(cpu->cpu); 2321 2349 cpu->pstate.min_pstate = pstate_funcs.get_min(cpu->cpu); 2322 - cpu->pstate.max_pstate_physical = perf_ctl_max_phys; 2323 2350 cpu->pstate.perf_ctl_scaling = perf_ctl_scaling; 2324 2351 2325 2352 if (hwp_active && !hwp_mode_bdw) { ··· 2326 2355 2327 2356 if (pstate_funcs.get_cpu_scaling) { 2328 2357 cpu->pstate.scaling = pstate_funcs.get_cpu_scaling(cpu->cpu); 2329 - if (cpu->pstate.scaling != perf_ctl_scaling) { 2330 - intel_pstate_hybrid_hwp_adjust(cpu); 2331 - hwp_is_hybrid = true; 2332 - } 2358 + intel_pstate_hybrid_hwp_adjust(cpu); 2333 2359 } else { 2334 2360 cpu->pstate.scaling = perf_ctl_scaling; 2335 2361 } ··· 2728 2760 X86_MATCH(INTEL_ATOM_CRESTMONT, core_funcs), 2729 2761 X86_MATCH(INTEL_ATOM_CRESTMONT_X, core_funcs), 2730 2762 X86_MATCH(INTEL_ATOM_DARKMONT_X, core_funcs), 2763 + X86_MATCH(INTEL_DIAMONDRAPIDS_X, core_funcs), 2731 2764 {} 2732 2765 }; 2733 2766 #endif ··· 3881 3912 3882 3913 } 3883 3914 3884 - mutex_lock(&intel_pstate_driver_lock); 3885 - rc = intel_pstate_register_driver(default_driver); 3886 - mutex_unlock(&intel_pstate_driver_lock); 3915 + scoped_guard(mutex, &intel_pstate_driver_lock) { 3916 + rc = intel_pstate_register_driver(default_driver); 3917 + } 3887 3918 if (rc) { 3888 3919 intel_pstate_sysfs_remove(); 3889 3920 return rc;
+33 -2
drivers/cpufreq/qcom-cpufreq-nvmem.c
··· 256 256 return ret; 257 257 } 258 258 259 + static const struct of_device_id qcom_cpufreq_ipq806x_match_list[] __maybe_unused = { 260 + { .compatible = "qcom,ipq8062", .data = (const void *)QCOM_ID_IPQ8062 }, 261 + { .compatible = "qcom,ipq8064", .data = (const void *)QCOM_ID_IPQ8064 }, 262 + { .compatible = "qcom,ipq8065", .data = (const void *)QCOM_ID_IPQ8065 }, 263 + { .compatible = "qcom,ipq8066", .data = (const void *)QCOM_ID_IPQ8066 }, 264 + { .compatible = "qcom,ipq8068", .data = (const void *)QCOM_ID_IPQ8068 }, 265 + { .compatible = "qcom,ipq8069", .data = (const void *)QCOM_ID_IPQ8069 }, 266 + }; 267 + 259 268 static int qcom_cpufreq_ipq8064_name_version(struct device *cpu_dev, 260 269 struct nvmem_cell *speedbin_nvmem, 261 270 char **pvs_name, 262 271 struct qcom_cpufreq_drv *drv) 263 272 { 273 + int msm_id = -1, ret = 0; 264 274 int speed = 0, pvs = 0; 265 - int msm_id, ret = 0; 266 275 u8 *speedbin; 267 276 size_t len; 268 277 ··· 288 279 get_krait_bin_format_a(cpu_dev, &speed, &pvs, speedbin); 289 280 290 281 ret = qcom_smem_get_soc_id(&msm_id); 291 - if (ret) 282 + if (ret == -ENODEV) { 283 + const struct of_device_id *match; 284 + struct device_node *root; 285 + 286 + root = of_find_node_by_path("/"); 287 + if (!root) { 288 + ret = -ENODEV; 289 + goto exit; 290 + } 291 + 292 + /* Fallback to compatible match with no SMEM initialized */ 293 + match = of_match_node(qcom_cpufreq_ipq806x_match_list, root); 294 + of_node_put(root); 295 + if (!match) { 296 + ret = -ENODEV; 297 + goto exit; 298 + } 299 + 300 + /* We found a matching device, get the msm_id from the data entry */ 301 + msm_id = (int)(uintptr_t)match->data; 302 + ret = 0; 303 + } else if (ret) { 292 304 goto exit; 305 + } 293 306 294 307 switch (msm_id) { 295 308 case QCOM_ID_IPQ8062:
+4 -2
drivers/cpufreq/s5pv210-cpufreq.c
··· 518 518 519 519 if (policy->cpu != 0) { 520 520 ret = -EINVAL; 521 - goto out_dmc1; 521 + goto out; 522 522 } 523 523 524 524 /* ··· 530 530 if ((mem_type != LPDDR) && (mem_type != LPDDR2)) { 531 531 pr_err("CPUFreq doesn't support this memory type\n"); 532 532 ret = -EINVAL; 533 - goto out_dmc1; 533 + goto out; 534 534 } 535 535 536 536 /* Find current refresh counter and frequency each DMC */ ··· 544 544 cpufreq_generic_init(policy, s5pv210_freq_table, 40000); 545 545 return 0; 546 546 547 + out: 548 + clk_put(dmc1_clk); 547 549 out_dmc1: 548 550 clk_put(dmc0_clk); 549 551 out_dmc0:
+143 -7
drivers/cpufreq/tegra186-cpufreq.c
··· 8 8 #include <linux/module.h> 9 9 #include <linux/of.h> 10 10 #include <linux/platform_device.h> 11 + #include <linux/units.h> 11 12 12 13 #include <soc/tegra/bpmp.h> 13 14 #include <soc/tegra/bpmp-abi.h> ··· 59 58 }; 60 59 61 60 struct tegra186_cpufreq_cluster { 62 - struct cpufreq_frequency_table *table; 61 + struct cpufreq_frequency_table *bpmp_lut; 63 62 u32 ref_clk_khz; 64 63 u32 div; 65 64 }; ··· 67 66 struct tegra186_cpufreq_data { 68 67 void __iomem *regs; 69 68 const struct tegra186_cpufreq_cpu *cpus; 69 + bool icc_dram_bw_scaling; 70 70 struct tegra186_cpufreq_cluster clusters[]; 71 71 }; 72 + 73 + static int tegra_cpufreq_set_bw(struct cpufreq_policy *policy, unsigned long freq_khz) 74 + { 75 + struct tegra186_cpufreq_data *data = cpufreq_get_driver_data(); 76 + struct device *dev; 77 + int ret; 78 + 79 + dev = get_cpu_device(policy->cpu); 80 + if (!dev) 81 + return -ENODEV; 82 + 83 + struct dev_pm_opp *opp __free(put_opp) = 84 + dev_pm_opp_find_freq_exact(dev, freq_khz * HZ_PER_KHZ, true); 85 + if (IS_ERR(opp)) 86 + return PTR_ERR(opp); 87 + 88 + ret = dev_pm_opp_set_opp(dev, opp); 89 + if (ret) 90 + data->icc_dram_bw_scaling = false; 91 + 92 + return ret; 93 + } 94 + 95 + static int tegra_cpufreq_init_cpufreq_table(struct cpufreq_policy *policy, 96 + struct cpufreq_frequency_table *bpmp_lut, 97 + struct cpufreq_frequency_table **opp_table) 98 + { 99 + struct tegra186_cpufreq_data *data = cpufreq_get_driver_data(); 100 + struct cpufreq_frequency_table *freq_table = NULL; 101 + struct cpufreq_frequency_table *pos; 102 + struct device *cpu_dev; 103 + unsigned long rate; 104 + int ret, max_opps; 105 + int j = 0; 106 + 107 + cpu_dev = get_cpu_device(policy->cpu); 108 + if (!cpu_dev) { 109 + pr_err("%s: failed to get cpu%d device\n", __func__, policy->cpu); 110 + return -ENODEV; 111 + } 112 + 113 + /* Initialize OPP table mentioned in operating-points-v2 property in DT */ 114 + ret = dev_pm_opp_of_add_table_indexed(cpu_dev, 0); 115 + if (ret) { 116 + dev_err(cpu_dev, "Invalid or empty opp table in device tree\n"); 117 + data->icc_dram_bw_scaling = false; 118 + return ret; 119 + } 120 + 121 + max_opps = dev_pm_opp_get_opp_count(cpu_dev); 122 + if (max_opps <= 0) { 123 + dev_err(cpu_dev, "Failed to add OPPs\n"); 124 + return max_opps; 125 + } 126 + 127 + /* Disable all opps and cross-validate against LUT later */ 128 + for (rate = 0; ; rate++) { 129 + struct dev_pm_opp *opp __free(put_opp) = 130 + dev_pm_opp_find_freq_ceil(cpu_dev, &rate); 131 + if (IS_ERR(opp)) 132 + break; 133 + 134 + dev_pm_opp_disable(cpu_dev, rate); 135 + } 136 + 137 + freq_table = kcalloc((max_opps + 1), sizeof(*freq_table), GFP_KERNEL); 138 + if (!freq_table) 139 + return -ENOMEM; 140 + 141 + /* 142 + * Cross check the frequencies from BPMP-FW LUT against the OPP's present in DT. 143 + * Enable only those DT OPP's which are present in LUT also. 144 + */ 145 + cpufreq_for_each_valid_entry(pos, bpmp_lut) { 146 + struct dev_pm_opp *opp __free(put_opp) = 147 + dev_pm_opp_find_freq_exact(cpu_dev, pos->frequency * HZ_PER_KHZ, false); 148 + if (IS_ERR(opp)) 149 + continue; 150 + 151 + ret = dev_pm_opp_enable(cpu_dev, pos->frequency * HZ_PER_KHZ); 152 + if (ret < 0) 153 + return ret; 154 + 155 + freq_table[j].driver_data = pos->driver_data; 156 + freq_table[j].frequency = pos->frequency; 157 + j++; 158 + } 159 + 160 + freq_table[j].driver_data = pos->driver_data; 161 + freq_table[j].frequency = CPUFREQ_TABLE_END; 162 + 163 + *opp_table = &freq_table[0]; 164 + 165 + dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus); 166 + 167 + /* Prime interconnect data */ 168 + tegra_cpufreq_set_bw(policy, freq_table[j - 1].frequency); 169 + 170 + return ret; 171 + } 72 172 73 173 static int tegra186_cpufreq_init(struct cpufreq_policy *policy) 74 174 { 75 175 struct tegra186_cpufreq_data *data = cpufreq_get_driver_data(); 76 176 unsigned int cluster = data->cpus[policy->cpu].bpmp_cluster_id; 177 + struct cpufreq_frequency_table *freq_table; 178 + struct cpufreq_frequency_table *bpmp_lut; 77 179 u32 cpu; 180 + int ret; 78 181 79 - policy->freq_table = data->clusters[cluster].table; 80 182 policy->cpuinfo.transition_latency = 300 * 1000; 81 183 policy->driver_data = NULL; 82 184 ··· 188 84 if (data->cpus[cpu].bpmp_cluster_id == cluster) 189 85 cpumask_set_cpu(cpu, policy->cpus); 190 86 } 87 + 88 + bpmp_lut = data->clusters[cluster].bpmp_lut; 89 + 90 + if (data->icc_dram_bw_scaling) { 91 + ret = tegra_cpufreq_init_cpufreq_table(policy, bpmp_lut, &freq_table); 92 + if (!ret) { 93 + policy->freq_table = freq_table; 94 + return 0; 95 + } 96 + } 97 + 98 + data->icc_dram_bw_scaling = false; 99 + policy->freq_table = bpmp_lut; 100 + pr_info("OPP tables missing from DT, EMC frequency scaling disabled\n"); 191 101 192 102 return 0; 193 103 } ··· 219 101 edvd_offset = data->cpus[cpu].edvd_offset; 220 102 writel(edvd_val, data->regs + edvd_offset); 221 103 } 104 + 105 + if (data->icc_dram_bw_scaling) 106 + tegra_cpufreq_set_bw(policy, tbl->frequency); 107 + 222 108 223 109 return 0; 224 110 } ··· 256 134 .init = tegra186_cpufreq_init, 257 135 }; 258 136 259 - static struct cpufreq_frequency_table *init_vhint_table( 137 + static struct cpufreq_frequency_table *tegra_cpufreq_bpmp_read_lut( 260 138 struct platform_device *pdev, struct tegra_bpmp *bpmp, 261 139 struct tegra186_cpufreq_cluster *cluster, unsigned int cluster_id, 262 140 int *num_rates) ··· 351 229 { 352 230 struct tegra186_cpufreq_data *data; 353 231 struct tegra_bpmp *bpmp; 232 + struct device *cpu_dev; 354 233 unsigned int i = 0, err, edvd_offset; 355 234 int num_rates = 0; 356 235 u32 edvd_val, cpu; ··· 377 254 for (i = 0; i < TEGRA186_NUM_CLUSTERS; i++) { 378 255 struct tegra186_cpufreq_cluster *cluster = &data->clusters[i]; 379 256 380 - cluster->table = init_vhint_table(pdev, bpmp, cluster, i, &num_rates); 381 - if (IS_ERR(cluster->table)) { 382 - err = PTR_ERR(cluster->table); 257 + cluster->bpmp_lut = tegra_cpufreq_bpmp_read_lut(pdev, bpmp, cluster, i, &num_rates); 258 + if (IS_ERR(cluster->bpmp_lut)) { 259 + err = PTR_ERR(cluster->bpmp_lut); 383 260 goto put_bpmp; 384 261 } else if (!num_rates) { 385 262 err = -EINVAL; ··· 388 265 389 266 for (cpu = 0; cpu < ARRAY_SIZE(tegra186_cpus); cpu++) { 390 267 if (data->cpus[cpu].bpmp_cluster_id == i) { 391 - edvd_val = cluster->table[num_rates - 1].driver_data; 268 + edvd_val = cluster->bpmp_lut[num_rates - 1].driver_data; 392 269 edvd_offset = data->cpus[cpu].edvd_offset; 393 270 writel(edvd_val, data->regs + edvd_offset); 394 271 } ··· 396 273 } 397 274 398 275 tegra186_cpufreq_driver.driver_data = data; 276 + 277 + /* Check for optional OPPv2 and interconnect paths on CPU0 to enable ICC scaling */ 278 + cpu_dev = get_cpu_device(0); 279 + if (!cpu_dev) { 280 + err = -EPROBE_DEFER; 281 + goto put_bpmp; 282 + } 283 + 284 + if (dev_pm_opp_of_get_opp_desc_node(cpu_dev)) { 285 + err = dev_pm_opp_of_find_icc_paths(cpu_dev, NULL); 286 + if (!err) 287 + data->icc_dram_bw_scaling = true; 288 + } 399 289 400 290 err = cpufreq_register_driver(&tegra186_cpufreq_driver); 401 291
+2 -1
drivers/cpufreq/tegra194-cpufreq.c
··· 750 750 if (IS_ERR(bpmp)) 751 751 return PTR_ERR(bpmp); 752 752 753 - read_counters_wq = alloc_workqueue("read_counters_wq", __WQ_LEGACY, 1); 753 + read_counters_wq = alloc_workqueue("read_counters_wq", 754 + __WQ_LEGACY | WQ_PERCPU, 1); 754 755 if (!read_counters_wq) { 755 756 dev_err(&pdev->dev, "fail to create_workqueue\n"); 756 757 err = -EINVAL;