Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'kvm-s390-master-7.0-4' of https://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux into HEAD
KVM: s390: One very last second fix
Fix one more gmap-rewrite issue: races with partial gmap invalidations.
+280
-275
+2
-3
Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml
+2
-3
Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml
···
33
33
- const: core
34
34
35
35
iommus:
36
-
maxItems: 2
36
+
maxItems: 1
37
37
38
38
interconnects:
39
39
items:
···
107
107
interconnect-names = "mdp0-mem",
108
108
"cpu-cfg";
109
109
110
-
iommus = <&apps_smmu 0x420 0x2>,
111
-
<&apps_smmu 0x421 0x0>;
110
+
iommus = <&apps_smmu 0x420 0x2>;
112
111
ranges;
113
112
114
113
display-controller@5e01000 {
+2
-5
Documentation/devicetree/bindings/media/qcom,qcm2290-venus.yaml
+2
-5
Documentation/devicetree/bindings/media/qcom,qcm2290-venus.yaml
···
42
42
- const: vcodec0_bus
43
43
44
44
iommus:
45
-
maxItems: 5
45
+
maxItems: 2
46
46
47
47
interconnects:
48
48
maxItems: 2
···
102
102
memory-region = <&pil_video_mem>;
103
103
104
104
iommus = <&apps_smmu 0x860 0x0>,
105
-
<&apps_smmu 0x880 0x0>,
106
-
<&apps_smmu 0x861 0x04>,
107
-
<&apps_smmu 0x863 0x0>,
108
-
<&apps_smmu 0x804 0xe0>;
105
+
<&apps_smmu 0x880 0x0>;
109
106
110
107
interconnects = <&mmnrt_virt MASTER_VIDEO_P0 RPM_ALWAYS_TAG
111
108
&bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,
+1
-1
arch/arm/boot/dts/microchip/sam9x7.dtsi
+1
-1
arch/arm/boot/dts/microchip/sam9x7.dtsi
+1
-5
arch/arm/boot/dts/nxp/imx/imx6-logicpd-som.dtsi
+1
-5
arch/arm/boot/dts/nxp/imx/imx6-logicpd-som.dtsi
+1
-5
arch/arm/boot/dts/nxp/imx/imx6qdl-icore.dtsi
+1
-5
arch/arm/boot/dts/nxp/imx/imx6qdl-icore.dtsi
+1
-5
arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pfla02.dtsi
+1
-5
arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pfla02.dtsi
+1
-5
arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi
+1
-5
arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi
+1
-5
arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi
+1
-5
arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi
···
260
260
&gpmi {
261
261
pinctrl-names = "default";
262
262
pinctrl-0 = <&pinctrl_gpmi_nand>;
263
+
nand-on-flash-bbt;
263
264
#address-cells = <1>;
264
265
#size-cells = <0>;
265
266
status = "okay";
266
-
267
-
nand@0 {
268
-
reg = <0>;
269
-
nand-on-flash-bbt;
270
-
};
271
267
};
272
268
273
269
&i2c3 {
+1
-5
arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi
+1
-5
arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi
+1
-5
arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts
+1
-5
arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts
+1
-5
arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi
+1
-5
arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi
+1
-5
arch/arm/boot/dts/nxp/imx/imx6ul-phytec-phycore-som.dtsi
+1
-5
arch/arm/boot/dts/nxp/imx/imx6ul-phytec-phycore-som.dtsi
+1
-5
arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi
+1
-5
arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi
+4
-8
arch/arm/boot/dts/nxp/imx/imx6ull-colibri.dtsi
+4
-8
arch/arm/boot/dts/nxp/imx/imx6ull-colibri.dtsi
···
160
160
pinctrl-names = "default";
161
161
pinctrl-0 = <&pinctrl_gpmi_nand>;
162
162
fsl,use-minimum-ecc;
163
+
nand-on-flash-bbt;
164
+
nand-ecc-mode = "hw";
165
+
nand-ecc-strength = <8>;
166
+
nand-ecc-step-size = <512>;
163
167
status = "okay";
164
-
165
-
nand@0 {
166
-
reg = <0>;
167
-
nand-on-flash-bbt;
168
-
nand-ecc-mode = "hw";
169
-
nand-ecc-strength = <8>;
170
-
nand-ecc-step-size = <512>;
171
-
};
172
168
};
173
169
174
170
/* I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) */
+4
-8
arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea.dtsi
+4
-8
arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea.dtsi
···
43
43
&gpmi {
44
44
pinctrl-names = "default";
45
45
pinctrl-0 = <&pinctrl_gpmi_nand>;
46
+
nand-ecc-mode = "hw";
47
+
nand-ecc-strength = <0>;
48
+
nand-ecc-step-size = <0>;
49
+
nand-on-flash-bbt;
46
50
status = "okay";
47
-
48
-
nand@0 {
49
-
reg = <0>;
50
-
nand-ecc-mode = "hw";
51
-
nand-ecc-strength = <0>;
52
-
nand-ecc-step-size = <0>;
53
-
nand-on-flash-bbt;
54
-
};
55
51
};
56
52
57
53
&iomuxc {
+1
-5
arch/arm/boot/dts/nxp/imx/imx6ull-myir-mys-6ulx.dtsi
+1
-5
arch/arm/boot/dts/nxp/imx/imx6ull-myir-mys-6ulx.dtsi
+1
-5
arch/arm/boot/dts/nxp/imx/imx6ulz-bsh-smm-m2.dts
+1
-5
arch/arm/boot/dts/nxp/imx/imx6ulz-bsh-smm-m2.dts
+2
-6
arch/arm/boot/dts/nxp/imx/imx7-colibri.dtsi
+2
-6
arch/arm/boot/dts/nxp/imx/imx7-colibri.dtsi
···
375
375
/* NAND on such SKUs */
376
376
&gpmi {
377
377
fsl,use-minimum-ecc;
378
+
nand-ecc-mode = "hw";
379
+
nand-on-flash-bbt;
378
380
pinctrl-names = "default";
379
381
pinctrl-0 = <&pinctrl_gpmi_nand>;
380
-
381
-
nand@0 {
382
-
reg = <0>;
383
-
nand-ecc-mode = "hw";
384
-
nand-on-flash-bbt;
385
-
};
386
382
};
387
383
388
384
/* On-module Power I2C */
+1
-1
arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
+1
-1
arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
···
901
901
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
902
902
clocks = <&r_ccu CLK_BUS_R_SPI>, <&r_ccu CLK_R_SPI>;
903
903
clock-names = "ahb", "mod";
904
-
dmas = <&dma 53>, <&dma 53>;
904
+
dmas = <&mcu_dma 13>, <&mcu_dma 13>;
905
905
dma-names = "rx", "tx";
906
906
resets = <&r_ccu RST_BUS_R_SPI>;
907
907
status = "disabled";
+1
-1
arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts
+1
-1
arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts
+7
-17
arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi
+7
-17
arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi
···
880
880
regulator-max-microvolt = <1300000>;
881
881
regulator-boot-on;
882
882
regulator-ramp-delay = <1250>;
883
-
rohm,dvs-run-voltage = <880000>;
884
-
rohm,dvs-idle-voltage = <820000>;
885
-
rohm,dvs-suspend-voltage = <810000>;
883
+
rohm,dvs-run-voltage = <900000>;
884
+
rohm,dvs-idle-voltage = <850000>;
885
+
rohm,dvs-suspend-voltage = <850000>;
886
886
regulator-always-on;
887
887
};
888
888
···
892
892
regulator-max-microvolt = <1300000>;
893
893
regulator-boot-on;
894
894
regulator-ramp-delay = <1250>;
895
-
rohm,dvs-run-voltage = <950000>;
896
-
rohm,dvs-idle-voltage = <850000>;
895
+
rohm,dvs-run-voltage = <1000000>;
896
+
rohm,dvs-idle-voltage = <900000>;
897
897
regulator-always-on;
898
898
};
899
899
···
902
902
regulator-min-microvolt = <700000>;
903
903
regulator-max-microvolt = <1300000>;
904
904
regulator-boot-on;
905
-
rohm,dvs-run-voltage = <850000>;
905
+
rohm,dvs-run-voltage = <900000>;
906
906
};
907
907
908
908
buck4_reg: BUCK4 {
909
909
regulator-name = "buck4";
910
910
regulator-min-microvolt = <700000>;
911
911
regulator-max-microvolt = <1300000>;
912
-
rohm,dvs-run-voltage = <930000>;
912
+
rohm,dvs-run-voltage = <1000000>;
913
913
};
914
914
915
915
buck5_reg: BUCK5 {
···
1447
1447
pinctrl-0 = <&pinctrl_wdog>;
1448
1448
fsl,ext-reset-output;
1449
1449
status = "okay";
1450
-
};
1451
-
1452
-
&a53_opp_table {
1453
-
opp-1000000000 {
1454
-
opp-microvolt = <850000>;
1455
-
};
1456
-
1457
-
opp-1500000000 {
1458
-
opp-microvolt = <950000>;
1459
-
};
1460
1450
};
+1
-1
arch/arm64/boot/dts/freescale/imx8mq.dtsi
+1
-1
arch/arm64/boot/dts/freescale/imx8mq.dtsi
+10
-10
arch/arm64/boot/dts/freescale/imx91-tqma9131.dtsi
+10
-10
arch/arm64/boot/dts/freescale/imx91-tqma9131.dtsi
···
272
272
/* enable SION for data and cmd pad due to ERR052021 */
273
273
pinctrl_usdhc1: usdhc1grp {
274
274
fsl,pins = /* PD | FSEL 3 | DSE X5 */
275
-
<MX91_PAD_SD1_CLK__USDHC1_CLK 0x5be>,
275
+
<MX91_PAD_SD1_CLK__USDHC1_CLK 0x59e>,
276
276
/* HYS | FSEL 0 | no drive */
277
277
<MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1000>,
278
278
/* HYS | FSEL 3 | X5 */
279
-
<MX91_PAD_SD1_CMD__USDHC1_CMD 0x400011be>,
279
+
<MX91_PAD_SD1_CMD__USDHC1_CMD 0x4000139e>,
280
280
/* HYS | FSEL 3 | X4 */
281
-
<MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x4000119e>,
282
-
<MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x4000119e>,
283
-
<MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x4000119e>,
284
-
<MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x4000119e>,
285
-
<MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x4000119e>,
286
-
<MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x4000119e>,
287
-
<MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x4000119e>,
288
-
<MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x4000119e>;
281
+
<MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x4000139e>,
282
+
<MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x4000139e>,
283
+
<MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x4000139e>,
284
+
<MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x4000139e>,
285
+
<MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x4000139e>,
286
+
<MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x4000139e>,
287
+
<MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x4000139e>,
288
+
<MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x4000139e>;
289
289
};
290
290
291
291
pinctrl_wdog: wdoggrp {
+2
arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts
+2
arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts
···
507
507
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
508
508
bus-width = <8>;
509
509
non-removable;
510
+
fsl,tuning-step = <1>;
510
511
status = "okay";
511
512
};
512
513
···
520
519
vmmc-supply = <®_usdhc2_vmmc>;
521
520
bus-width = <4>;
522
521
no-mmc;
522
+
fsl,tuning-step = <1>;
523
523
status = "okay";
524
524
};
525
525
+13
-13
arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi
+13
-13
arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi
···
271
271
/* enable SION for data and cmd pad due to ERR052021 */
272
272
pinctrl_usdhc1: usdhc1grp {
273
273
fsl,pins = <
274
-
/* PD | FSEL 3 | DSE X5 */
275
-
MX93_PAD_SD1_CLK__USDHC1_CLK 0x5be
274
+
/* PD | FSEL 3 | DSE X4 */
275
+
MX93_PAD_SD1_CLK__USDHC1_CLK 0x59e
276
276
/* HYS | FSEL 0 | no drive */
277
277
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1000
278
-
/* HYS | FSEL 3 | X5 */
279
-
MX93_PAD_SD1_CMD__USDHC1_CMD 0x400011be
280
-
/* HYS | FSEL 3 | X4 */
281
-
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000119e
282
-
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000119e
283
-
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000119e
284
-
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000119e
285
-
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000119e
286
-
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000119e
287
-
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000119e
288
-
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000119e
278
+
/* HYS | PU | FSEL 3 | DSE X4 */
279
+
MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e
280
+
/* HYS | PU | FSEL 3 | DSE X4 */
281
+
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000139e
282
+
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000139e
283
+
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000139e
284
+
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000139e
285
+
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000139e
286
+
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000139e
287
+
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000139e
288
+
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000139e
289
289
>;
290
290
};
291
291
+1
-1
arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts
+1
-1
arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts
+1
arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
+1
arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
+3
-8
arch/arm64/boot/dts/qcom/agatti.dtsi
+3
-8
arch/arm64/boot/dts/qcom/agatti.dtsi
···
1669
1669
&bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
1670
1670
interconnect-names = "gfx-mem";
1671
1671
1672
-
iommus = <&adreno_smmu 0 1>,
1673
-
<&adreno_smmu 2 0>;
1672
+
iommus = <&adreno_smmu 0 1>;
1674
1673
operating-points-v2 = <&gpu_opp_table>;
1675
1674
power-domains = <&rpmpd QCM2290_VDDCX>;
1676
1675
qcom,gmu = <&gmu_wrapper>;
···
1950
1951
1951
1952
power-domains = <&dispcc MDSS_GDSC>;
1952
1953
1953
-
iommus = <&apps_smmu 0x420 0x2>,
1954
-
<&apps_smmu 0x421 0x0>;
1954
+
iommus = <&apps_smmu 0x420 0x2>;
1955
1955
interconnects = <&mmrt_virt MASTER_MDP0 RPM_ALWAYS_TAG
1956
1956
&bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,
1957
1957
<&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
···
2434
2436
2435
2437
memory-region = <&pil_video_mem>;
2436
2438
iommus = <&apps_smmu 0x860 0x0>,
2437
-
<&apps_smmu 0x880 0x0>,
2438
-
<&apps_smmu 0x861 0x04>,
2439
-
<&apps_smmu 0x863 0x0>,
2440
-
<&apps_smmu 0x804 0xe0>;
2439
+
<&apps_smmu 0x880 0x0>;
2441
2440
2442
2441
interconnects = <&mmnrt_virt MASTER_VIDEO_P0 RPM_ALWAYS_TAG
2443
2442
&bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,
+1
-1
arch/arm64/boot/dts/qcom/hamoa.dtsi
+1
-1
arch/arm64/boot/dts/qcom/hamoa.dtsi
+7
-2
arch/arm64/boot/dts/qcom/monaco.dtsi
+7
-2
arch/arm64/boot/dts/qcom/monaco.dtsi
···
765
765
hwlocks = <&tcsr_mutex 3>;
766
766
};
767
767
768
+
gunyah_md_mem: gunyah-md-region@91a80000 {
769
+
reg = <0x0 0x91a80000 0x0 0x80000>;
770
+
no-map;
771
+
};
772
+
768
773
lpass_machine_learning_mem: lpass-machine-learning-region@93b00000 {
769
774
reg = <0x0 0x93b00000 0x0 0xf00000>;
770
775
no-map;
···
6419
6414
};
6420
6415
6421
6416
qup_uart10_rts: qup-uart10-rts-state {
6422
-
pins = "gpio84";
6417
+
pins = "gpio85";
6423
6418
function = "qup1_se2";
6424
6419
};
6425
6420
6426
6421
qup_uart10_tx: qup-uart10-tx-state {
6427
-
pins = "gpio85";
6422
+
pins = "gpio86";
6428
6423
function = "qup1_se2";
6429
6424
};
6430
6425
+1
-1
arch/arm64/boot/dts/qcom/qcm6490-idp.dts
+1
-1
arch/arm64/boot/dts/qcom/qcm6490-idp.dts
+10
-6
arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi
+10
-6
arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi
···
1032
1032
};
1033
1033
1034
1034
&pcie4 {
1035
-
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
1036
-
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
1037
-
1038
1035
pinctrl-0 = <&pcie4_default>;
1039
1036
pinctrl-names = "default";
1040
1037
···
1045
1048
status = "okay";
1046
1049
};
1047
1050
1048
-
&pcie6a {
1049
-
perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
1050
-
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
1051
+
&pcie4_port0 {
1052
+
reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
1053
+
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
1054
+
};
1051
1055
1056
+
&pcie6a {
1052
1057
vddpe-3v3-supply = <&vreg_nvme>;
1053
1058
1054
1059
pinctrl-0 = <&pcie6a_default>;
···
1064
1065
vdda-pll-supply = <&vreg_l2j_1p2>;
1065
1066
1066
1067
status = "okay";
1068
+
};
1069
+
1070
+
&pcie6a_port0 {
1071
+
reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
1072
+
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
1067
1073
};
1068
1074
1069
1075
&pm8550_gpios {
+15
-9
arch/arm64/boot/dts/qcom/x1-crd.dtsi
+15
-9
arch/arm64/boot/dts/qcom/x1-crd.dtsi
···
1216
1216
};
1217
1217
1218
1218
&pcie4 {
1219
-
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
1220
-
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
1221
-
1222
1219
pinctrl-0 = <&pcie4_default>;
1223
1220
pinctrl-names = "default";
1224
1221
1225
1222
status = "okay";
1223
+
};
1224
+
1225
+
&pcie4_port0 {
1226
+
reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
1227
+
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
1226
1228
};
1227
1229
1228
1230
&pcie4_phy {
···
1235
1233
};
1236
1234
1237
1235
&pcie5 {
1238
-
perst-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
1239
-
wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
1240
-
1241
1236
vddpe-3v3-supply = <&vreg_wwan>;
1242
1237
1243
1238
pinctrl-0 = <&pcie5_default>;
···
1250
1251
status = "okay";
1251
1252
};
1252
1253
1253
-
&pcie6a {
1254
-
perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
1255
-
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
1254
+
&pcie5_port0 {
1255
+
reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
1256
+
wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
1257
+
};
1256
1258
1259
+
&pcie6a {
1257
1260
vddpe-3v3-supply = <&vreg_nvme>;
1258
1261
1259
1262
pinctrl-names = "default";
···
1269
1268
vdda-pll-supply = <&vreg_l2j_1p2>;
1270
1269
1271
1270
status = "okay";
1271
+
};
1272
+
1273
+
&pcie6a_port0 {
1274
+
reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
1275
+
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
1272
1276
};
1273
1277
1274
1278
&pm8550_gpios {
+8
-6
arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi
+8
-6
arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi
···
1081
1081
};
1082
1082
1083
1083
&pcie4 {
1084
-
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
1085
-
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
1086
-
1087
1084
pinctrl-0 = <&pcie4_default>;
1088
1085
pinctrl-names = "default";
1089
1086
···
1095
1098
};
1096
1099
1097
1100
&pcie4_port0 {
1101
+
reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
1102
+
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
1103
+
1098
1104
wifi@0 {
1099
1105
compatible = "pci17cb,1107";
1100
1106
reg = <0x10000 0x0 0x0 0x0 0x0>;
···
1115
1115
};
1116
1116
1117
1117
&pcie6a {
1118
-
perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
1119
-
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
1120
-
1121
1118
vddpe-3v3-supply = <&vreg_nvme>;
1122
1119
1123
1120
pinctrl-0 = <&pcie6a_default>;
1124
1121
pinctrl-names = "default";
1125
1122
1126
1123
status = "okay";
1124
+
};
1125
+
1126
+
&pcie6a_port0 {
1127
+
reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
1128
+
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
1127
1129
};
1128
1130
1129
1131
&pcie6a_phy {
+8
-6
arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi
+8
-6
arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi
···
1065
1065
};
1066
1066
1067
1067
&pcie4 {
1068
-
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
1069
-
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
1070
-
1071
1068
pinctrl-0 = <&pcie4_default>;
1072
1069
pinctrl-names = "default";
1073
1070
···
1079
1082
};
1080
1083
1081
1084
&pcie4_port0 {
1085
+
reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
1086
+
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
1087
+
1082
1088
wifi@0 {
1083
1089
compatible = "pci17cb,1107";
1084
1090
reg = <0x10000 0x0 0x0 0x0 0x0>;
···
1099
1099
};
1100
1100
1101
1101
&pcie6a {
1102
-
perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
1103
-
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
1104
-
1105
1102
vddpe-3v3-supply = <&vreg_nvme>;
1106
1103
1107
1104
pinctrl-0 = <&pcie6a_default>;
1108
1105
pinctrl-names = "default";
1109
1106
1110
1107
status = "okay";
1108
+
};
1109
+
1110
+
&pcie6a_port0 {
1111
+
reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
1112
+
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
1111
1113
};
1112
1114
1113
1115
&pcie6a_phy {
+5
-3
arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi
+5
-3
arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi
···
964
964
};
965
965
966
966
&pcie6a {
967
-
perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
968
-
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
969
-
970
967
vddpe-3v3-supply = <&vreg_nvme>;
971
968
972
969
pinctrl-0 = <&pcie6a_default>;
···
977
980
vdda-pll-supply = <&vreg_l2j_1p2>;
978
981
979
982
status = "okay";
983
+
};
984
+
985
+
&pcie6a_port0 {
986
+
reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
987
+
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
980
988
};
981
989
982
990
&pm8550_gpios {
+3
-3
arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts
+3
-3
arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts
···
1126
1126
};
1127
1127
1128
1128
&pcie4 {
1129
-
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
1130
-
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
1131
-
1132
1129
pinctrl-0 = <&pcie4_default>;
1133
1130
pinctrl-names = "default";
1134
1131
···
1140
1143
};
1141
1144
1142
1145
&pcie4_port0 {
1146
+
reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
1147
+
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
1148
+
1143
1149
wifi@0 {
1144
1150
compatible = "pci17cb,1107";
1145
1151
reg = <0x10000 0x0 0x0 0x0 0x0>;
+8
-7
arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts
+8
-7
arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts
···
1033
1033
};
1034
1034
1035
1035
&pcie4 {
1036
-
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
1037
-
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
1038
-
1039
1036
pinctrl-0 = <&pcie4_default>;
1040
1037
pinctrl-names = "default";
1041
1038
···
1047
1050
};
1048
1051
1049
1052
&pcie4_port0 {
1053
+
reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
1054
+
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
1055
+
1050
1056
wifi@0 {
1051
1057
compatible = "pci17cb,1107";
1052
1058
reg = <0x10000 0x0 0x0 0x0 0x0>;
···
1067
1067
};
1068
1068
1069
1069
&pcie6a {
1070
-
perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
1071
-
1072
-
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
1073
-
1074
1070
vddpe-3v3-supply = <&vreg_nvme>;
1075
1071
1076
1072
pinctrl-0 = <&pcie6a_default>;
···
1080
1084
vdda-pll-supply = <&vreg_l2j_1p2>;
1081
1085
1082
1086
status = "okay";
1087
+
};
1088
+
1089
+
&pcie6a_port0 {
1090
+
reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
1091
+
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
1083
1092
};
1084
1093
1085
1094
&pm8550_gpios {
+8
-6
arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts
+8
-6
arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts
···
1131
1131
};
1132
1132
1133
1133
&pcie4 {
1134
-
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
1135
-
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
1136
-
1137
1134
pinctrl-0 = <&pcie4_default>;
1138
1135
pinctrl-names = "default";
1139
1136
···
1145
1148
};
1146
1149
1147
1150
&pcie4_port0 {
1151
+
reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
1152
+
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
1153
+
1148
1154
wifi@0 {
1149
1155
compatible = "pci17cb,1107";
1150
1156
reg = <0x10000 0x0 0x0 0x0 0x0>;
···
1165
1165
};
1166
1166
1167
1167
&pcie6a {
1168
-
perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
1169
-
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
1170
-
1171
1168
vddpe-3v3-supply = <&vreg_nvme>;
1172
1169
1173
1170
pinctrl-0 = <&pcie6a_default>;
···
1178
1181
vdda-pll-supply = <&vreg_l2j_1p2>;
1179
1182
1180
1183
status = "okay";
1184
+
};
1185
+
1186
+
&pcie6a_port0 {
1187
+
reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
1188
+
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
1181
1189
};
1182
1190
1183
1191
&pm8550_pwm {
+11
arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts
+11
arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts
···
118
118
reg = <0x6 0x00000000 0x1 0x00000000>;
119
119
};
120
120
121
+
reserved-memory {
122
+
#address-cells = <2>;
123
+
#size-cells = <2>;
124
+
ranges;
125
+
126
+
tfa@40000000 {
127
+
reg = <0x0 0x40000000 0x0 0x8000000>;
128
+
no-map;
129
+
};
130
+
};
131
+
121
132
/* Page 27 / DSI to Display */
122
133
dp-con {
123
134
compatible = "dp-connector";
-18
arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
-18
arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
···
879
879
};
880
880
};
881
881
882
-
wifi {
883
-
wifi_host_wake_l: wifi-host-wake-l {
884
-
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
885
-
};
886
-
};
887
-
888
882
wireless-bluetooth {
889
883
bt_wake_pin: bt-wake-pin {
890
884
rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
···
936
942
pinctrl-names = "default";
937
943
pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
938
944
sd-uhs-sdr104;
939
-
#address-cells = <1>;
940
-
#size-cells = <0>;
941
945
status = "okay";
942
-
943
-
brcmf: wifi@1 {
944
-
compatible = "brcm,bcm4329-fmac";
945
-
reg = <1>;
946
-
interrupt-parent = <&gpio0>;
947
-
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>;
948
-
interrupt-names = "host-wake";
949
-
pinctrl-names = "default";
950
-
pinctrl-0 = <&wifi_host_wake_l>;
951
-
};
952
946
};
953
947
954
948
&sdhci {
+5
-4
arch/s390/kvm/gaccess.c
+5
-4
arch/s390/kvm/gaccess.c
···
1449
1449
pgste_set_unlock(ptep_h, pgste);
1450
1450
if (rc)
1451
1451
return rc;
1452
-
if (!sg->parent)
1452
+
if (sg->invalidated)
1453
1453
return -EAGAIN;
1454
1454
1455
1455
newpte = _pte(f->pfn, 0, !p, 0);
···
1479
1479
1480
1480
do {
1481
1481
/* _gmap_crstep_xchg_atomic() could have unshadowed this shadow gmap */
1482
-
if (!sg->parent)
1482
+
if (sg->invalidated)
1483
1483
return -EAGAIN;
1484
1484
oldcrste = READ_ONCE(*host);
1485
1485
newcrste = _crste_fc1(f->pfn, oldcrste.h.tt, f->writable, !p);
···
1492
1492
if (!newcrste.h.p && !f->writable)
1493
1493
return -EOPNOTSUPP;
1494
1494
} while (!_gmap_crstep_xchg_atomic(sg->parent, host, oldcrste, newcrste, f->gfn, false));
1495
-
if (!sg->parent)
1495
+
if (sg->invalidated)
1496
1496
return -EAGAIN;
1497
1497
1498
1498
newcrste = _crste_fc1(f->pfn, oldcrste.h.tt, 0, !p);
···
1545
1545
entries[i].pfn, i + 1, entries[i].writable);
1546
1546
if (rc)
1547
1547
return rc;
1548
-
if (!sg->parent)
1548
+
if (sg->invalidated)
1549
1549
return -EAGAIN;
1550
1550
}
1551
1551
···
1601
1601
scoped_guard(spinlock, &parent->children_lock) {
1602
1602
if (READ_ONCE(sg->parent) != parent)
1603
1603
return -EAGAIN;
1604
+
sg->invalidated = false;
1604
1605
rc = _gaccess_do_shadow(vcpu->arch.mc, sg, saddr, walk);
1605
1606
}
1606
1607
if (rc == -ENOMEM)
+3
arch/s390/kvm/gmap.c
+3
arch/s390/kvm/gmap.c
···
181
181
182
182
list_del(&child->list);
183
183
child->parent = NULL;
184
+
child->invalidated = true;
184
185
}
185
186
186
187
/**
···
1070
1069
if (level > TABLE_TYPE_PAGE_TABLE)
1071
1070
align = 1UL << (11 * level + _SEGMENT_SHIFT);
1072
1071
kvm_s390_vsie_gmap_notifier(sg, ALIGN_DOWN(gaddr, align), ALIGN(gaddr + 1, align));
1072
+
sg->invalidated = true;
1073
1073
if (dat_entry_walk(NULL, r_gfn, sg->asce, 0, level, &crstep, &ptep))
1074
1074
return;
1075
1075
if (ptep) {
···
1176
1174
scoped_guard(spinlock, &parent->children_lock) {
1177
1175
if (READ_ONCE(sg->parent) != parent)
1178
1176
return -EAGAIN;
1177
+
sg->invalidated = false;
1179
1178
for (i = 0; i < CRST_TABLE_PAGES; i++) {
1180
1179
if (!context->f[i].valid)
1181
1180
continue;
+1
arch/s390/kvm/gmap.h
+1
arch/s390/kvm/gmap.h
+6
-4
drivers/firmware/microchip/mpfs-auto-update.c
+6
-4
drivers/firmware/microchip/mpfs-auto-update.c
···
113
113
* be added here.
114
114
*/
115
115
116
-
priv->flash = mpfs_sys_controller_get_flash(priv->sys_controller);
117
-
if (!priv->flash)
118
-
return FW_UPLOAD_ERR_HW_ERROR;
119
-
120
116
erase_size = round_up(erase_size, (u64)priv->flash->erasesize);
121
117
122
118
/*
···
422
426
if (IS_ERR(priv->sys_controller))
423
427
return dev_err_probe(dev, PTR_ERR(priv->sys_controller),
424
428
"Could not register as a sub device of the system controller\n");
429
+
430
+
priv->flash = mpfs_sys_controller_get_flash(priv->sys_controller);
431
+
if (IS_ERR_OR_NULL(priv->flash)) {
432
+
dev_dbg(dev, "No flash connected to the system controller, auto-update not supported\n");
433
+
return -ENODEV;
434
+
}
425
435
426
436
priv->dev = dev;
427
437
platform_set_drvdata(pdev, priv);
-1
drivers/reset/core.c
-1
drivers/reset/core.c
+1
-1
drivers/reset/reset-rzg2l-usbphy-ctrl.c
+1
-1
drivers/reset/reset-rzg2l-usbphy-ctrl.c
+36
-24
drivers/reset/spacemit/reset-spacemit-k3.c
+36
-24
drivers/reset/spacemit/reset-spacemit-k3.c
···
112
112
[RESET_APMU_SDH0] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)),
113
113
[RESET_APMU_SDH1] = RESET_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)),
114
114
[RESET_APMU_SDH2] = RESET_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)),
115
-
[RESET_APMU_USB2] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0,
116
-
BIT(1)|BIT(2)|BIT(3)),
117
-
[RESET_APMU_USB3_PORTA] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0,
118
-
BIT(5)|BIT(6)|BIT(7)),
119
-
[RESET_APMU_USB3_PORTB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0,
120
-
BIT(9)|BIT(10)|BIT(11)),
121
-
[RESET_APMU_USB3_PORTC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0,
122
-
BIT(13)|BIT(14)|BIT(15)),
123
-
[RESET_APMU_USB3_PORTD] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0,
124
-
BIT(17)|BIT(18)|BIT(19)),
115
+
[RESET_APMU_USB2_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(1)),
116
+
[RESET_APMU_USB2_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(2)),
117
+
[RESET_APMU_USB2_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(3)),
118
+
[RESET_APMU_USB3_A_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(5)),
119
+
[RESET_APMU_USB3_A_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(6)),
120
+
[RESET_APMU_USB3_A_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(7)),
121
+
[RESET_APMU_USB3_B_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(9)),
122
+
[RESET_APMU_USB3_B_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(10)),
123
+
[RESET_APMU_USB3_B_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(11)),
124
+
[RESET_APMU_USB3_C_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(13)),
125
+
[RESET_APMU_USB3_C_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(14)),
126
+
[RESET_APMU_USB3_C_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(15)),
127
+
[RESET_APMU_USB3_D_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(17)),
128
+
[RESET_APMU_USB3_D_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(18)),
129
+
[RESET_APMU_USB3_D_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(19)),
125
130
[RESET_APMU_QSPI] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(1)),
126
131
[RESET_APMU_QSPI_BUS] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(0)),
127
132
[RESET_APMU_DMA] = RESET_DATA(APMU_DMA_CLK_RES_CTRL, 0, BIT(0)),
···
156
151
[RESET_APMU_CPU7_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(26), 0),
157
152
[RESET_APMU_C1_MPSUB_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(28), 0),
158
153
[RESET_APMU_MPSUB_DBG] = RESET_DATA(APMU_PMU_CC2_AP, BIT(29), 0),
159
-
[RESET_APMU_UCIE] = RESET_DATA(APMU_UCIE_CTRL,
160
-
BIT(1) | BIT(2) | BIT(3), 0),
161
-
[RESET_APMU_RCPU] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0,
162
-
BIT(3) | BIT(2) | BIT(0)),
154
+
[RESET_APMU_UCIE_IP] = RESET_DATA(APMU_UCIE_CTRL, BIT(1), 0),
155
+
[RESET_APMU_UCIE_HOT] = RESET_DATA(APMU_UCIE_CTRL, BIT(2), 0),
156
+
[RESET_APMU_UCIE_MON] = RESET_DATA(APMU_UCIE_CTRL, BIT(3), 0),
157
+
[RESET_APMU_RCPU_AUDIO_SYS] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, BIT(0)),
158
+
[RESET_APMU_RCPU_MCU_CORE] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, BIT(2)),
159
+
[RESET_APMU_RCPU_AUDIO_APMU] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, BIT(3)),
163
160
[RESET_APMU_DSI4LN2_ESCCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL3, 0, BIT(3)),
164
161
[RESET_APMU_DSI4LN2_LCD_SW] = RESET_DATA(APMU_LCD_CLK_RES_CTRL3, 0, BIT(4)),
165
162
[RESET_APMU_DSI4LN2_LCD_MCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL4, 0, BIT(9)),
···
171
164
[RESET_APMU_UFS_ACLK] = RESET_DATA(APMU_UFS_CLK_RES_CTRL, 0, BIT(0)),
172
165
[RESET_APMU_EDP0] = RESET_DATA(APMU_LCD_EDP_CTRL, 0, BIT(0)),
173
166
[RESET_APMU_EDP1] = RESET_DATA(APMU_LCD_EDP_CTRL, 0, BIT(16)),
174
-
[RESET_APMU_PCIE_PORTA] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0,
175
-
BIT(5) | BIT(4) | BIT(3)),
176
-
[RESET_APMU_PCIE_PORTB] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0,
177
-
BIT(5) | BIT(4) | BIT(3)),
178
-
[RESET_APMU_PCIE_PORTC] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0,
179
-
BIT(5) | BIT(4) | BIT(3)),
180
-
[RESET_APMU_PCIE_PORTD] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0,
181
-
BIT(5) | BIT(4) | BIT(3)),
182
-
[RESET_APMU_PCIE_PORTE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0,
183
-
BIT(5) | BIT(4) | BIT(3)),
167
+
[RESET_APMU_PCIE_A_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, BIT(3)),
168
+
[RESET_APMU_PCIE_A_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, BIT(4)),
169
+
[RESET_APMU_PCIE_A_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, BIT(5)),
170
+
[RESET_APMU_PCIE_B_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, BIT(3)),
171
+
[RESET_APMU_PCIE_B_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, BIT(4)),
172
+
[RESET_APMU_PCIE_B_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, BIT(5)),
173
+
[RESET_APMU_PCIE_C_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, BIT(3)),
174
+
[RESET_APMU_PCIE_C_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, BIT(4)),
175
+
[RESET_APMU_PCIE_C_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, BIT(5)),
176
+
[RESET_APMU_PCIE_D_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, BIT(3)),
177
+
[RESET_APMU_PCIE_D_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, BIT(4)),
178
+
[RESET_APMU_PCIE_D_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, BIT(5)),
179
+
[RESET_APMU_PCIE_E_DBI] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, BIT(3)),
180
+
[RESET_APMU_PCIE_E_SLAVE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, BIT(4)),
181
+
[RESET_APMU_PCIE_E_MASTER] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, BIT(5)),
184
182
[RESET_APMU_EMAC0] = RESET_DATA(APMU_EMAC0_CLK_RES_CTRL, 0, BIT(1)),
185
183
[RESET_APMU_EMAC1] = RESET_DATA(APMU_EMAC1_CLK_RES_CTRL, 0, BIT(1)),
186
184
[RESET_APMU_EMAC2] = RESET_DATA(APMU_EMAC2_CLK_RES_CTRL, 0, BIT(1)),
+1
-1
drivers/soc/aspeed/aspeed-socinfo.c
+1
-1
drivers/soc/aspeed/aspeed-socinfo.c
+4
-2
drivers/soc/microchip/mpfs-control-scb.c
+4
-2
drivers/soc/microchip/mpfs-control-scb.c
···
14
14
{
15
15
struct device *dev = &pdev->dev;
16
16
17
-
return mfd_add_devices(dev, PLATFORM_DEVID_NONE, mpfs_control_scb_devs,
18
-
ARRAY_SIZE(mpfs_control_scb_devs), NULL, 0, NULL);
17
+
return devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE,
18
+
mpfs_control_scb_devs,
19
+
ARRAY_SIZE(mpfs_control_scb_devs), NULL, 0,
20
+
NULL);
19
21
}
20
22
21
23
static const struct of_device_id mpfs_control_scb_of_match[] = {
+4
-2
drivers/soc/microchip/mpfs-mss-top-sysreg.c
+4
-2
drivers/soc/microchip/mpfs-mss-top-sysreg.c
···
16
16
struct device *dev = &pdev->dev;
17
17
int ret;
18
18
19
-
ret = mfd_add_devices(dev, PLATFORM_DEVID_NONE, mpfs_mss_top_sysreg_devs,
20
-
ARRAY_SIZE(mpfs_mss_top_sysreg_devs) , NULL, 0, NULL);
19
+
ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE,
20
+
mpfs_mss_top_sysreg_devs,
21
+
ARRAY_SIZE(mpfs_mss_top_sysreg_devs), NULL,
22
+
0, NULL);
21
23
if (ret)
22
24
return ret;
23
25
+1
-1
drivers/soc/qcom/pdr_internal.h
+1
-1
drivers/soc/qcom/pdr_internal.h
+28
-11
drivers/soc/qcom/pmic_glink_altmode.c
+28
-11
drivers/soc/qcom/pmic_glink_altmode.c
···
62
62
u8 orientation;
63
63
u8 mux_ctrl;
64
64
#define MUX_CTRL_STATE_NO_CONN 0
65
+
#define MUX_CTRL_STATE_USB3_ONLY 1
66
+
#define MUX_CTRL_STATE_DP4LN 2
67
+
#define MUX_CTRL_STATE_USB3_DP 3
65
68
#define MUX_CTRL_STATE_TUNNELING 4
66
69
67
70
u8 res;
···
353
350
354
351
typec_switch_set(alt_port->typec_switch, alt_port->orientation);
355
352
356
-
if (alt_port->mux_ctrl == MUX_CTRL_STATE_NO_CONN) {
357
-
pmic_glink_altmode_safe(altmode, alt_port);
358
-
} else if (alt_port->svid == USB_TYPEC_TBT_SID) {
359
-
pmic_glink_altmode_enable_tbt(altmode, alt_port);
360
-
} else if (alt_port->svid == USB_TYPEC_DP_SID) {
361
-
pmic_glink_altmode_enable_dp(altmode, alt_port,
362
-
alt_port->mode,
363
-
alt_port->hpd_state,
364
-
alt_port->hpd_irq);
353
+
/*
354
+
* MUX_CTRL_STATE_DP4LN/USB3_DP may only be set if SVID=DP, but we need
355
+
* to special-case the SVID=DP && mux_ctrl=NO_CONN case to deliver a
356
+
* HPD notification
357
+
*/
358
+
if (alt_port->svid == USB_TYPEC_DP_SID) {
359
+
if (alt_port->mux_ctrl == MUX_CTRL_STATE_NO_CONN) {
360
+
pmic_glink_altmode_safe(altmode, alt_port);
361
+
} else {
362
+
pmic_glink_altmode_enable_dp(altmode, alt_port,
363
+
alt_port->mode,
364
+
alt_port->hpd_state,
365
+
alt_port->hpd_irq);
366
+
}
365
367
366
368
if (alt_port->hpd_state)
367
369
conn_status = connector_status_connected;
···
375
367
376
368
drm_aux_hpd_bridge_notify(&alt_port->bridge->dev, conn_status);
377
369
} else if (alt_port->mux_ctrl == MUX_CTRL_STATE_TUNNELING) {
378
-
pmic_glink_altmode_enable_usb4(altmode, alt_port);
379
-
} else {
370
+
if (alt_port->svid == USB_TYPEC_TBT_SID)
371
+
pmic_glink_altmode_enable_tbt(altmode, alt_port);
372
+
else
373
+
pmic_glink_altmode_enable_usb4(altmode, alt_port);
374
+
} else if (alt_port->mux_ctrl == MUX_CTRL_STATE_USB3_ONLY) {
380
375
pmic_glink_altmode_enable_usb(altmode, alt_port);
376
+
} else if (alt_port->mux_ctrl == MUX_CTRL_STATE_NO_CONN) {
377
+
pmic_glink_altmode_safe(altmode, alt_port);
378
+
} else {
379
+
dev_err(altmode->dev, "Got unknown mux_ctrl: %u on port %u, forcing safe mode\n",
380
+
alt_port->mux_ctrl, alt_port->index);
381
+
pmic_glink_altmode_safe(altmode, alt_port);
381
382
}
382
383
383
384
pmic_glink_altmode_request(altmode, ALTMODE_PAN_ACK, alt_port->index);
+1
-1
drivers/soc/qcom/qcom_pdr_msg.c
+1
-1
drivers/soc/qcom/qcom_pdr_msg.c
+36
-12
include/dt-bindings/reset/spacemit,k3-resets.h
+36
-12
include/dt-bindings/reset/spacemit,k3-resets.h
···
97
97
#define RESET_APMU_SDH0 13
98
98
#define RESET_APMU_SDH1 14
99
99
#define RESET_APMU_SDH2 15
100
-
#define RESET_APMU_USB2 16
101
-
#define RESET_APMU_USB3_PORTA 17
102
-
#define RESET_APMU_USB3_PORTB 18
103
-
#define RESET_APMU_USB3_PORTC 19
104
-
#define RESET_APMU_USB3_PORTD 20
100
+
#define RESET_APMU_USB2_AHB 16
101
+
#define RESET_APMU_USB2_VCC 17
102
+
#define RESET_APMU_USB2_PHY 18
103
+
#define RESET_APMU_USB3_A_AHB 19
104
+
#define RESET_APMU_USB3_A_VCC 20
105
105
#define RESET_APMU_QSPI 21
106
106
#define RESET_APMU_QSPI_BUS 22
107
107
#define RESET_APMU_DMA 23
···
132
132
#define RESET_APMU_CPU7_SW 48
133
133
#define RESET_APMU_C1_MPSUB_SW 49
134
134
#define RESET_APMU_MPSUB_DBG 50
135
-
#define RESET_APMU_UCIE 51
136
-
#define RESET_APMU_RCPU 52
135
+
#define RESET_APMU_USB3_A_PHY 51 /* USB3 A */
136
+
#define RESET_APMU_USB3_B_AHB 52
137
137
#define RESET_APMU_DSI4LN2_ESCCLK 53
138
138
#define RESET_APMU_DSI4LN2_LCD_SW 54
139
139
#define RESET_APMU_DSI4LN2_LCD_MCLK 55
···
143
143
#define RESET_APMU_UFS_ACLK 59
144
144
#define RESET_APMU_EDP0 60
145
145
#define RESET_APMU_EDP1 61
146
-
#define RESET_APMU_PCIE_PORTA 62
147
-
#define RESET_APMU_PCIE_PORTB 63
148
-
#define RESET_APMU_PCIE_PORTC 64
149
-
#define RESET_APMU_PCIE_PORTD 65
150
-
#define RESET_APMU_PCIE_PORTE 66
146
+
#define RESET_APMU_USB3_B_VCC 62 /* USB3 B */
147
+
#define RESET_APMU_USB3_B_PHY 63
148
+
#define RESET_APMU_USB3_C_AHB 64
149
+
#define RESET_APMU_USB3_C_VCC 65
150
+
#define RESET_APMU_USB3_C_PHY 66
151
151
#define RESET_APMU_EMAC0 67
152
152
#define RESET_APMU_EMAC1 68
153
153
#define RESET_APMU_EMAC2 69
154
154
#define RESET_APMU_ESPI_MCLK 70
155
155
#define RESET_APMU_ESPI_SCLK 71
156
+
#define RESET_APMU_USB3_D_AHB 72 /* USB3 D */
157
+
#define RESET_APMU_USB3_D_VCC 73
158
+
#define RESET_APMU_USB3_D_PHY 74
159
+
#define RESET_APMU_UCIE_IP 75
160
+
#define RESET_APMU_UCIE_HOT 76
161
+
#define RESET_APMU_UCIE_MON 77
162
+
#define RESET_APMU_RCPU_AUDIO_SYS 78
163
+
#define RESET_APMU_RCPU_MCU_CORE 79
164
+
#define RESET_APMU_RCPU_AUDIO_APMU 80
165
+
#define RESET_APMU_PCIE_A_DBI 81
166
+
#define RESET_APMU_PCIE_A_SLAVE 82
167
+
#define RESET_APMU_PCIE_A_MASTER 83
168
+
#define RESET_APMU_PCIE_B_DBI 84
169
+
#define RESET_APMU_PCIE_B_SLAVE 85
170
+
#define RESET_APMU_PCIE_B_MASTER 86
171
+
#define RESET_APMU_PCIE_C_DBI 87
172
+
#define RESET_APMU_PCIE_C_SLAVE 88
173
+
#define RESET_APMU_PCIE_C_MASTER 89
174
+
#define RESET_APMU_PCIE_D_DBI 90
175
+
#define RESET_APMU_PCIE_D_SLAVE 91
176
+
#define RESET_APMU_PCIE_D_MASTER 92
177
+
#define RESET_APMU_PCIE_E_DBI 93
178
+
#define RESET_APMU_PCIE_E_SLAVE 94
179
+
#define RESET_APMU_PCIE_E_MASTER 95
156
180
157
181
/* DCIU resets*/
158
182
#define RESET_DCIU_HDMA 0