Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
ASoC: rt1320: add mic function
This patch adds the mic function.
Signed-off-by: Shuming Fan <shumingf@realtek.com>
Link: https://patch.msgid.link/20241025081259.1419518-1-shumingf@realtek.com
Signed-off-by: Mark Brown <broonie@kernel.org>
authored by
Shuming Fan
and committed by
Mark Brown
20079dd9
a2f4b8c8
+313
-14
+309
-14
sound/soc/codecs/rt1320-sdw.c
+309
-14
sound/soc/codecs/rt1320-sdw.c
···
21
21
#include <sound/tlv.h>
22
22
#include <sound/sdw.h>
23
23
#include "rt1320-sdw.h"
24
+
#include "rt-sdw-common.h"
24
25
25
26
/*
26
27
* The 'blind writes' is an SDCA term to deal with platform-specific initialization.
···
107
106
{ 0x1000db09, 0x00 },
108
107
{ 0x1000db0a, 0x40 },
109
108
{ 0x0000d540, 0x01 },
109
+
{ 0xd172, 0x2a },
110
+
{ 0xc5d6, 0x01 },
110
111
};
111
112
112
113
static const struct reg_sequence rt1320_vc_blind_write[] = {
···
228
225
{ 0x0000d540, 0x01 },
229
226
{ 0x0000c081, 0xfc },
230
227
{ 0x0000f01e, 0x80 },
228
+
{ 0xc01b, 0xfc },
229
+
{ 0xc5d1, 0x89 },
230
+
{ 0xc5d8, 0x0a },
231
+
{ 0xc5f7, 0x22 },
232
+
{ 0xc5f6, 0x22 },
233
+
{ 0xc065, 0xa5 },
234
+
{ 0xc06b, 0x0a },
235
+
{ 0xd172, 0x2a },
236
+
{ 0xc5d6, 0x01 },
231
237
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
232
238
};
233
239
234
240
static const struct reg_default rt1320_reg_defaults[] = {
241
+
{ SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
242
+
{ SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 },
243
+
{ SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 },
244
+
{ SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 },
245
+
{ SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 },
246
+
{ SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 },
247
+
{ SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x0b },
248
+
{ SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), 0x03 },
235
249
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 },
236
250
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 },
237
251
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE27, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
238
252
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
239
253
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0), 0x00 },
240
-
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 },
241
-
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x0b },
242
254
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 },
243
255
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), 0x03 },
244
256
};
245
257
246
258
static const struct reg_default rt1320_mbq_defaults[] = {
259
+
{ SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 },
260
+
{ SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 },
261
+
{ SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 },
262
+
{ SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 },
247
263
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 },
248
264
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 },
249
265
};
···
328
306
case 0x1000f021:
329
307
case 0x3fe2e000 ... 0x3fe2e003:
330
308
case 0x3fc2ab80 ... 0x3fc2abd4:
309
+
/* 0x40801508/0x40801809/0x4080180a/0x40801909/0x4080190a */
310
+
case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_REQ_POWER_STATE, 0):
311
+
case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01):
312
+
case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_02):
313
+
case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_01):
314
+
case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_02):
315
+
/* 0x40880900/0x40880980 */
316
+
case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0):
317
+
case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0):
318
+
/* 0x40881500 */
319
+
case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0):
331
320
/* 0x41000189/0x4100018a */
332
321
case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01):
333
322
case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02):
···
421
388
case 0x3fc2bf80 ... 0x3fc2bf83:
422
389
case 0x3fc2bfc0 ... 0x3fc2bfc7:
423
390
case 0x3fe2e000 ... 0x3fe2e003:
391
+
case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0):
424
392
case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0):
425
393
case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_MODE, 0):
426
394
case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS, 0):
···
435
401
static bool rt1320_mbq_readable_register(struct device *dev, unsigned int reg)
436
402
{
437
403
switch (reg) {
404
+
case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01):
405
+
case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_02):
406
+
case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01):
407
+
case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_02):
438
408
case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01):
439
409
case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02):
440
410
return true;
···
494
456
prop->lane_control_support = true;
495
457
496
458
/* first we need to allocate memory for set bits in port lists */
497
-
prop->source_ports = BIT(4);
459
+
prop->source_ports = BIT(4) | BIT(8) | BIT(10);
498
460
prop->sink_ports = BIT(1);
499
461
500
462
nval = hweight32(prop->source_ports);
···
538
500
return 0;
539
501
}
540
502
541
-
static int rt1320_pde_transition_delay(struct rt1320_sdw_priv *rt1320, unsigned char ps)
503
+
static int rt1320_pde_transition_delay(struct rt1320_sdw_priv *rt1320, unsigned char func,
504
+
unsigned char entity, unsigned char ps)
542
505
{
543
506
unsigned int delay = 1000, val;
544
507
···
548
509
/* waiting for Actual PDE becomes to PS0/PS3 */
549
510
while (delay) {
550
511
regmap_read(rt1320->regmap,
551
-
SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23,
552
-
RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), &val);
512
+
SDW_SDCA_CTL(func, entity, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), &val);
553
513
if (val == ps)
554
514
break;
555
515
···
665
627
usleep_range(delay, delay + 1000);
666
628
667
629
if (reg == SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0))
668
-
rt1320_pde_transition_delay(rt1320, val);
630
+
rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, val);
669
631
}
670
632
}
671
633
···
771
733
return rt1320_io_init(&slave->dev, slave);
772
734
}
773
735
736
+
static int rt1320_pde11_event(struct snd_soc_dapm_widget *w,
737
+
struct snd_kcontrol *kcontrol, int event)
738
+
{
739
+
struct snd_soc_component *component =
740
+
snd_soc_dapm_to_component(w->dapm);
741
+
struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
742
+
unsigned char ps0 = 0x0, ps3 = 0x3;
743
+
744
+
switch (event) {
745
+
case SND_SOC_DAPM_POST_PMU:
746
+
regmap_write(rt1320->regmap,
747
+
SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11,
748
+
RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps0);
749
+
rt1320_pde_transition_delay(rt1320, FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, ps0);
750
+
break;
751
+
case SND_SOC_DAPM_PRE_PMD:
752
+
regmap_write(rt1320->regmap,
753
+
SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11,
754
+
RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps3);
755
+
rt1320_pde_transition_delay(rt1320, FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, ps3);
756
+
break;
757
+
default:
758
+
break;
759
+
}
760
+
761
+
return 0;
762
+
}
763
+
774
764
static int rt1320_pde23_event(struct snd_soc_dapm_widget *w,
775
765
struct snd_kcontrol *kcontrol, int event)
776
766
{
···
812
746
regmap_write(rt1320->regmap,
813
747
SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23,
814
748
RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps0);
815
-
rt1320_pde_transition_delay(rt1320, ps0);
749
+
rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, ps0);
816
750
break;
817
751
case SND_SOC_DAPM_PRE_PMD:
818
752
regmap_write(rt1320->regmap,
819
753
SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23,
820
754
RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps3);
821
-
rt1320_pde_transition_delay(rt1320, ps3);
755
+
rt1320_pde_transition_delay(rt1320, FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, ps3);
822
756
break;
823
757
default:
824
758
break;
···
837
771
unsigned int gain_l_val, gain_r_val;
838
772
unsigned int lvalue, rvalue;
839
773
const unsigned int interval_offset = 0xc0;
774
+
unsigned int changed = 0, reg_base;
775
+
struct rt_sdca_dmic_kctrl_priv *p;
776
+
unsigned int regvalue[4], gain_val[4], i;
777
+
int err;
778
+
779
+
if (strstr(ucontrol->id.name, "FU Capture Volume"))
780
+
goto _dmic_vol_;
840
781
841
782
regmap_read(rt1320->mbq_regmap, mc->reg, &lvalue);
842
783
regmap_read(rt1320->mbq_regmap, mc->rreg, &rvalue);
···
869
796
regmap_write(rt1320->mbq_regmap, mc->reg, gain_l_val);
870
797
/* Rch */
871
798
regmap_write(rt1320->mbq_regmap, mc->rreg, gain_r_val);
799
+
goto _done_;
872
800
801
+
_dmic_vol_:
802
+
p = (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value;
803
+
804
+
/* check all channels */
805
+
for (i = 0; i < p->count; i++) {
806
+
if (i < 2) {
807
+
reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
808
+
regmap_read(rt1320->mbq_regmap, reg_base + i, ®value[i]);
809
+
} else {
810
+
reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
811
+
regmap_read(rt1320->mbq_regmap, reg_base + i - 2, ®value[i]);
812
+
}
813
+
814
+
gain_val[i] = ucontrol->value.integer.value[i];
815
+
if (gain_val[i] > p->max)
816
+
gain_val[i] = p->max;
817
+
818
+
gain_val[i] = 0x1e00 - ((p->max - gain_val[i]) * interval_offset);
819
+
gain_val[i] &= 0xffff;
820
+
if (regvalue[i] != gain_val[i])
821
+
changed = 1;
822
+
}
823
+
824
+
if (!changed)
825
+
return 0;
826
+
827
+
for (i = 0; i < p->count; i++) {
828
+
if (i < 2) {
829
+
reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
830
+
err = regmap_write(rt1320->mbq_regmap, reg_base + i, gain_val[i]);
831
+
} else {
832
+
reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
833
+
err = regmap_write(rt1320->mbq_regmap, reg_base + i - 2, gain_val[i]);
834
+
}
835
+
836
+
if (err < 0)
837
+
dev_err(&rt1320->sdw_slave->dev, "0x%08x can't be set\n", reg_base + i);
838
+
}
839
+
840
+
_done_:
873
841
return 1;
874
842
}
875
843
···
923
809
(struct soc_mixer_control *)kcontrol->private_value;
924
810
unsigned int read_l, read_r, ctl_l = 0, ctl_r = 0;
925
811
const unsigned int interval_offset = 0xc0;
812
+
unsigned int reg_base, regvalue, ctl, i;
813
+
struct rt_sdca_dmic_kctrl_priv *p;
814
+
815
+
if (strstr(ucontrol->id.name, "FU Capture Volume"))
816
+
goto _dmic_vol_;
926
817
927
818
regmap_read(rt1320->mbq_regmap, mc->reg, &read_l);
928
819
regmap_read(rt1320->mbq_regmap, mc->rreg, &read_r);
···
941
822
942
823
ucontrol->value.integer.value[0] = ctl_l;
943
824
ucontrol->value.integer.value[1] = ctl_r;
825
+
goto _done_;
826
+
827
+
_dmic_vol_:
828
+
p = (struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value;
829
+
830
+
/* check all channels */
831
+
for (i = 0; i < p->count; i++) {
832
+
if (i < 2) {
833
+
reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
834
+
regmap_read(rt1320->mbq_regmap, reg_base + i, ®value);
835
+
} else {
836
+
reg_base = SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01);
837
+
regmap_read(rt1320->mbq_regmap, reg_base + i - 2, ®value);
838
+
}
839
+
840
+
ctl = p->max - (((0x1e00 - regvalue) & 0xffff) / interval_offset);
841
+
ucontrol->value.integer.value[i] = ctl;
842
+
}
843
+
_done_:
844
+
return 0;
845
+
}
846
+
847
+
static int rt1320_set_fu_capture_ctl(struct rt1320_sdw_priv *rt1320)
848
+
{
849
+
int err, i;
850
+
unsigned int ch_mute;
851
+
852
+
for (i = 0; i < ARRAY_SIZE(rt1320->fu_mixer_mute); i++) {
853
+
ch_mute = (rt1320->fu_dapm_mute || rt1320->fu_mixer_mute[i]) ? 0x01 : 0x00;
854
+
855
+
if (i < 2)
856
+
err = regmap_write(rt1320->regmap,
857
+
SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113,
858
+
RT1320_SDCA_CTL_FU_MUTE, CH_01) + i, ch_mute);
859
+
else
860
+
err = regmap_write(rt1320->regmap,
861
+
SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14,
862
+
RT1320_SDCA_CTL_FU_MUTE, CH_01) + i - 2, ch_mute);
863
+
if (err < 0)
864
+
return err;
865
+
}
866
+
867
+
return 0;
868
+
}
869
+
870
+
static int rt1320_dmic_fu_capture_get(struct snd_kcontrol *kcontrol,
871
+
struct snd_ctl_elem_value *ucontrol)
872
+
{
873
+
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
874
+
struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
875
+
struct rt_sdca_dmic_kctrl_priv *p =
876
+
(struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value;
877
+
unsigned int i;
878
+
879
+
for (i = 0; i < p->count; i++)
880
+
ucontrol->value.integer.value[i] = !rt1320->fu_mixer_mute[i];
881
+
882
+
return 0;
883
+
}
884
+
885
+
static int rt1320_dmic_fu_capture_put(struct snd_kcontrol *kcontrol,
886
+
struct snd_ctl_elem_value *ucontrol)
887
+
{
888
+
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
889
+
struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
890
+
struct rt_sdca_dmic_kctrl_priv *p =
891
+
(struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value;
892
+
int err, changed = 0, i;
893
+
894
+
for (i = 0; i < p->count; i++) {
895
+
if (rt1320->fu_mixer_mute[i] != !ucontrol->value.integer.value[i])
896
+
changed = 1;
897
+
rt1320->fu_mixer_mute[i] = !ucontrol->value.integer.value[i];
898
+
}
899
+
900
+
err = rt1320_set_fu_capture_ctl(rt1320);
901
+
if (err < 0)
902
+
return err;
903
+
904
+
return changed;
905
+
}
906
+
907
+
static int rt1320_dmic_fu_info(struct snd_kcontrol *kcontrol,
908
+
struct snd_ctl_elem_info *uinfo)
909
+
{
910
+
struct rt_sdca_dmic_kctrl_priv *p =
911
+
(struct rt_sdca_dmic_kctrl_priv *)kcontrol->private_value;
912
+
913
+
if (p->max == 1)
914
+
uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
915
+
else
916
+
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
917
+
uinfo->count = p->count;
918
+
uinfo->value.integer.min = 0;
919
+
uinfo->value.integer.max = p->max;
920
+
return 0;
921
+
}
922
+
923
+
static int rt1320_dmic_fu_event(struct snd_soc_dapm_widget *w,
924
+
struct snd_kcontrol *kcontrol, int event)
925
+
{
926
+
struct snd_soc_component *component =
927
+
snd_soc_dapm_to_component(w->dapm);
928
+
struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
929
+
930
+
switch (event) {
931
+
case SND_SOC_DAPM_POST_PMU:
932
+
rt1320->fu_dapm_mute = false;
933
+
rt1320_set_fu_capture_ctl(rt1320);
934
+
break;
935
+
case SND_SOC_DAPM_PRE_PMD:
936
+
rt1320->fu_dapm_mute = true;
937
+
rt1320_set_fu_capture_ctl(rt1320);
938
+
break;
939
+
}
944
940
return 0;
945
941
}
946
942
···
1076
842
rt1320_rx_data_ch_select);
1077
843
1078
844
static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6525, 75, 0);
845
+
static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -1725, 75, 0);
1079
846
1080
847
static const struct snd_kcontrol_new rt1320_snd_controls[] = {
1081
848
SOC_DOUBLE_R_EXT_TLV("FU21 Playback Volume",
···
1084
849
SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02),
1085
850
0, 0x57, 0, rt1320_set_gain_get, rt1320_set_gain_put, out_vol_tlv),
1086
851
SOC_ENUM("RX Channel Select", rt1320_rx_data_ch_enum),
852
+
853
+
RT_SDCA_FU_CTRL("FU Capture Switch",
854
+
SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01),
855
+
1, 1, 4, rt1320_dmic_fu_info, rt1320_dmic_fu_capture_get, rt1320_dmic_fu_capture_put),
856
+
RT_SDCA_EXT_TLV("FU Capture Volume",
857
+
SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01),
858
+
rt1320_set_gain_get, rt1320_set_gain_put, 4, 0x3f, in_vol_tlv, rt1320_dmic_fu_info),
1087
859
};
1088
860
1089
861
static const struct snd_kcontrol_new rt1320_spk_l_dac =
···
1106
864
/* Audio Interface */
1107
865
SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0),
1108
866
SND_SOC_DAPM_AIF_OUT("DP4TX", "DP4 Capture", 0, SND_SOC_NOPM, 0, 0),
867
+
SND_SOC_DAPM_AIF_OUT("DP8-10TX", "DP8-10 Capture", 0, SND_SOC_NOPM, 0, 0),
1109
868
1110
869
/* Digital Interface */
1111
870
SND_SOC_DAPM_PGA("FU21", SND_SOC_NOPM, 0, 0, NULL, 0),
1112
871
SND_SOC_DAPM_SUPPLY("PDE 23", SND_SOC_NOPM, 0, 0,
1113
872
rt1320_pde23_event,
1114
873
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
874
+
SND_SOC_DAPM_SUPPLY("PDE 11", SND_SOC_NOPM, 0, 0,
875
+
rt1320_pde11_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
876
+
SND_SOC_DAPM_ADC("FU 113", NULL, SND_SOC_NOPM, 0, 0),
877
+
SND_SOC_DAPM_ADC("FU 14", NULL, SND_SOC_NOPM, 0, 0),
878
+
SND_SOC_DAPM_PGA_E("FU", SND_SOC_NOPM, 0, 0, NULL, 0,
879
+
rt1320_dmic_fu_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1115
880
1116
881
/* Output */
1117
882
SND_SOC_DAPM_SWITCH("OT23 L", SND_SOC_NOPM, 0, 0, &rt1320_spk_l_dac),
···
1129
880
/* Input */
1130
881
SND_SOC_DAPM_PGA("AEC Data", SND_SOC_NOPM, 0, 0, NULL, 0),
1131
882
SND_SOC_DAPM_SIGGEN("AEC Gen"),
883
+
SND_SOC_DAPM_INPUT("DMIC1"),
884
+
SND_SOC_DAPM_INPUT("DMIC2"),
1132
885
};
1133
886
1134
887
static const struct snd_soc_dapm_route rt1320_dapm_routes[] = {
···
1143
892
1144
893
{ "AEC Data", NULL, "AEC Gen" },
1145
894
{ "DP4TX", NULL, "AEC Data" },
895
+
896
+
{"DP8-10TX", NULL, "FU"},
897
+
{"FU", NULL, "PDE 11"},
898
+
{"FU", NULL, "FU 113"},
899
+
{"FU", NULL, "FU 14"},
900
+
{"FU 113", NULL, "DMIC1"},
901
+
{"FU 14", NULL, "DMIC2"},
1146
902
};
1147
903
1148
904
static int rt1320_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
···
1173
915
snd_soc_component_get_drvdata(component);
1174
916
struct sdw_stream_config stream_config;
1175
917
struct sdw_port_config port_config;
918
+
struct sdw_port_config dmic_port_config[2];
1176
919
struct sdw_stream_runtime *sdw_stream;
1177
920
int retval;
1178
921
unsigned int sampling_rate;
···
1198
939
} else {
1199
940
if (dai->id == RT1320_AIF1)
1200
941
port_config.num = 4;
1201
-
else
942
+
else if (dai->id == RT1320_AIF2) {
943
+
dmic_port_config[0].ch_mask = BIT(0) | BIT(1);
944
+
dmic_port_config[0].num = 8;
945
+
dmic_port_config[1].ch_mask = BIT(0) | BIT(1);
946
+
dmic_port_config[1].num = 10;
947
+
} else
1202
948
return -EINVAL;
1203
949
}
1204
950
1205
-
retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config,
951
+
if (dai->id == RT1320_AIF1)
952
+
retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config,
1206
953
&port_config, 1, sdw_stream);
954
+
else if (dai->id == RT1320_AIF2)
955
+
retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config,
956
+
dmic_port_config, 2, sdw_stream);
957
+
else
958
+
return -EINVAL;
1207
959
if (retval) {
1208
960
dev_err(dai->dev, "%s: Unable to configure port\n", __func__);
1209
961
return retval;
···
1247
977
}
1248
978
1249
979
/* set sampling frequency */
1250
-
regmap_write(rt1320->regmap,
1251
-
SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0),
1252
-
sampling_rate);
980
+
if (dai->id == RT1320_AIF1)
981
+
regmap_write(rt1320->regmap,
982
+
SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0),
983
+
sampling_rate);
984
+
else {
985
+
regmap_write(rt1320->regmap,
986
+
SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0),
987
+
sampling_rate);
988
+
regmap_write(rt1320->regmap,
989
+
SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0),
990
+
sampling_rate);
991
+
}
1253
992
1254
993
return 0;
1255
994
}
···
1349
1070
},
1350
1071
.ops = &rt1320_aif_dai_ops,
1351
1072
},
1073
+
/* DMIC: DP8 2ch + DP10 2ch */
1074
+
{
1075
+
.name = "rt1320-aif2",
1076
+
.id = RT1320_AIF2,
1077
+
.capture = {
1078
+
.stream_name = "DP8-10 Capture",
1079
+
.channels_min = 1,
1080
+
.channels_max = 4,
1081
+
.rates = RT1320_STEREO_RATES,
1082
+
.formats = RT1320_FORMATS,
1083
+
},
1084
+
.ops = &rt1320_aif_dai_ops,
1085
+
},
1352
1086
};
1353
1087
1354
1088
static int rt1320_sdw_init(struct device *dev, struct regmap *regmap,
···
1389
1097
rt1320->hw_init = false;
1390
1098
rt1320->first_hw_init = false;
1391
1099
rt1320->version_id = -1;
1100
+
rt1320->fu_dapm_mute = true;
1101
+
rt1320->fu_mixer_mute[0] = rt1320->fu_mixer_mute[1] =
1102
+
rt1320->fu_mixer_mute[2] = rt1320->fu_mixer_mute[3] = true;
1392
1103
1393
1104
ret = devm_snd_soc_register_component(dev,
1394
1105
&soc_component_sdw_rt1320,
+4
sound/soc/codecs/rt1320-sdw.h
+4
sound/soc/codecs/rt1320-sdw.h
···
26
26
27
27
/* RT1320 SDCA Control - function number */
28
28
#define FUNC_NUM_AMP 0x04
29
+
#define FUNC_NUM_MIC 0x02
29
30
30
31
/* RT1320 SDCA entity */
31
32
#define RT1320_SDCA_ENT0 0x00
···
70
69
71
70
enum {
72
71
RT1320_AIF1,
72
+
RT1320_AIF2,
73
73
};
74
74
75
75
/*
···
96
94
bool hw_init;
97
95
bool first_hw_init;
98
96
int version_id;
97
+
bool fu_dapm_mute;
98
+
bool fu_mixer_mute[4];
99
99
};
100
100
101
101
#endif /* __RT1320_SDW_H__ */