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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
[IA64] Update Altix nofault code
Montecito and Montvale behaves slightly differently than previous
Itanium processors, resulting in the MCA due to a failed PIO read
to sometimes surfacing outside the nofault code. This code is
based on discussions with Intel CPU architects and verified at
customer sites.
Signed-off-by: Russ Anderson <rja@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
authored by
Russ Anderson
and committed by
Tony Luck
2022c1f1
4ca8ad7e
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arch/ia64/sn/kernel/xp_nofault.S
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arch/ia64/sn/kernel/xp_nofault.S
···
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (c) 2004-2005 Silicon Graphics, Inc. All Rights Reserved.
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* Copyright (c) 2004-2007 Silicon Graphics, Inc. All Rights Reserved.
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*/
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···
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* PIO read fails, the MCA handler will force the error to look
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* corrected and vector to the xp_error_PIOR which will return an error.
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*
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* The definition of "consumption" and the time it takes for an MCA
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* to surface is processor implementation specific. This code
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* is sufficient on Itanium through the Montvale processor family.
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* It may need to be adjusted for future processor implementations.
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*
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* extern int xp_nofault_PIOR(void *remote_register);
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*/
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···
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mov r8=r0 // Stage a success return value
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ld8.acq r9=[r32];; // PIO Read the specified register
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adds r9=1,r9;; // Add to force consumption
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or r9=r9,r9;; // Or to force consumption
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srlz.i;; // Allow time for MCA to surface
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br.ret.sptk.many b0;; // Return success
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.global xp_error_PIOR
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xp_error_PIOR:
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mov r8=1 // Return value of 1
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br.ret.sptk.many b0;; // Return failure
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