Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2024-08-30' of https://gitlab.freedesktop.org/drm/kernel
Pull drm fixes from Dave Airlie:
"Another week, another set of GPU fixes. amdgpu and vmwgfx leading the
charge, then i915 and xe changes along with v3d and some other bits.
The TTM revert is due to some stuttering graphical apps probably due
to longer stalls while prefaulting.
Seems pretty much where I'd expect things,
ttm:
- revert prefault change, caused stutters
aperture:
- handle non-VGA devices bettter
amdgpu:
- SWSMU gaming stability fix
- SMU 13.0.7 fix
- SWSMU documentation alignment fix
- SMU 14.0.x fixes
- GC 12.x fix
- Display fix
- IP discovery fix
- SMU 13.0.6 fix
i915:
- Fix #11195: The external display connect via USB type-C dock stays
blank after re-connect the dock
- Make DSI backlight work for 2G version of Lenovo Yoga Tab 3 X90F
- Move ARL GuC firmware to correct version
xe:
- Invalidate media_gt TLBs
- Fix HWMON i1 power setup write command
vmwgfx:
- prevent unmapping active read buffers
- fix prime with external buffers
- disable coherent dumb buffers without 3d
v3d:
- disable preemption while updating GPU stats"
* tag 'drm-fixes-2024-08-30' of https://gitlab.freedesktop.org/drm/kernel:
drm/xe/hwmon: Fix WRITE_I1 param from u32 to u16
drm/v3d: Disable preemption while updating GPU stats
drm/amd/pm: Drop unsupported features on smu v14_0_2
drm/amd/pm: Add support for new P2S table revision
drm/amdgpu: support for gc_info table v1.3
drm/amd/display: avoid using null object of framebuffer
drm/amdgpu/gfx12: set UNORD_DISPATCH in compute MQDs
drm/amd/pm: update message interface for smu v14.0.2/3
drm/amdgpu/swsmu: always force a state reprogram on init
drm/amdgpu/smu13.0.7: print index for profiles
drm/amdgpu: align pp_power_profile_mode with kernel docs
drm/i915/dp_mst: Fix MST state after a sink reset
drm/xe: Invalidate media_gt TLBs
drm/i915: ARL requires a newer GSC firmware
drm/i915/dsi: Make Lenovo Yoga Tab 3 X90F DMI match less strict
video/aperture: optionally match the device in sysfb_disable()
drm/vmwgfx: Disable coherent dumb buffers without 3d
drm/vmwgfx: Fix prime with external buffers
drm/vmwgfx: Prevent unmapping active read buffers
Revert "drm/ttm: increase ttm pre-fault value to PMD size"
+399
-127
+13
-6
drivers/firmware/sysfb.c
+13
-6
drivers/firmware/sysfb.c
···
39
39
static DEFINE_MUTEX(disable_lock);
40
40
static bool disabled;
41
41
42
+
static struct device *sysfb_parent_dev(const struct screen_info *si);
43
+
42
44
static bool sysfb_unregister(void)
43
45
{
44
46
if (IS_ERR_OR_NULL(pd))
···
54
52
55
53
/**
56
54
* sysfb_disable() - disable the Generic System Framebuffers support
55
+
* @dev: the device to check if non-NULL
57
56
*
58
57
* This disables the registration of system framebuffer devices that match the
59
58
* generic drivers that make use of the system framebuffer set up by firmware.
···
64
61
* Context: The function can sleep. A @disable_lock mutex is acquired to serialize
65
62
* against sysfb_init(), that registers a system framebuffer device.
66
63
*/
67
-
void sysfb_disable(void)
64
+
void sysfb_disable(struct device *dev)
68
65
{
66
+
struct screen_info *si = &screen_info;
67
+
69
68
mutex_lock(&disable_lock);
70
-
sysfb_unregister();
71
-
disabled = true;
69
+
if (!dev || dev == sysfb_parent_dev(si)) {
70
+
sysfb_unregister();
71
+
disabled = true;
72
+
}
72
73
mutex_unlock(&disable_lock);
73
74
}
74
75
EXPORT_SYMBOL_GPL(sysfb_disable);
75
76
76
77
#if defined(CONFIG_PCI)
77
-
static __init bool sysfb_pci_dev_is_enabled(struct pci_dev *pdev)
78
+
static bool sysfb_pci_dev_is_enabled(struct pci_dev *pdev)
78
79
{
79
80
/*
80
81
* TODO: Try to integrate this code into the PCI subsystem
···
94
87
return true;
95
88
}
96
89
#else
97
-
static __init bool sysfb_pci_dev_is_enabled(struct pci_dev *pdev)
90
+
static bool sysfb_pci_dev_is_enabled(struct pci_dev *pdev)
98
91
{
99
92
return false;
100
93
}
101
94
#endif
102
95
103
-
static __init struct device *sysfb_parent_dev(const struct screen_info *si)
96
+
static struct device *sysfb_parent_dev(const struct screen_info *si)
104
97
{
105
98
struct pci_dev *pdev;
106
99
+11
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+11
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
···
1500
1500
struct gc_info_v1_0 v1;
1501
1501
struct gc_info_v1_1 v1_1;
1502
1502
struct gc_info_v1_2 v1_2;
1503
+
struct gc_info_v1_3 v1_3;
1503
1504
struct gc_info_v2_0 v2;
1504
1505
struct gc_info_v2_1 v2_1;
1505
1506
};
···
1558
1557
adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa);
1559
1558
adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance);
1560
1559
adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu);
1560
+
}
1561
+
if (le16_to_cpu(gc_info->v1.header.version_minor) >= 3) {
1562
+
adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v1_3.gc_tcp_size_per_cu);
1563
+
adev->gfx.config.gc_tcp_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcp_cache_line_size);
1564
+
adev->gfx.config.gc_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_size_per_sqc);
1565
+
adev->gfx.config.gc_instruction_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_line_size);
1566
+
adev->gfx.config.gc_scalar_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_size_per_sqc);
1567
+
adev->gfx.config.gc_scalar_data_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_line_size);
1568
+
adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v1_3.gc_tcc_size);
1569
+
adev->gfx.config.gc_tcc_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcc_cache_line_size);
1561
1570
}
1562
1571
break;
1563
1572
case 2:
+6
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+6
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
···
240
240
uint32_t gc_tcp_size_per_cu;
241
241
uint32_t gc_num_cu_per_sqc;
242
242
uint32_t gc_tcc_size;
243
+
uint32_t gc_tcp_cache_line_size;
244
+
uint32_t gc_instruction_cache_size_per_sqc;
245
+
uint32_t gc_instruction_cache_line_size;
246
+
uint32_t gc_scalar_data_cache_size_per_sqc;
247
+
uint32_t gc_scalar_data_cache_line_size;
248
+
uint32_t gc_tcc_cache_line_size;
243
249
};
244
250
245
251
struct amdgpu_cu_info {
+1
-1
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+1
-1
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
···
3005
3005
(order_base_2(prop->queue_size / 4) - 1));
3006
3006
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3007
3007
(order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
3008
-
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3008
+
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
3009
3009
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
3010
3010
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3011
3011
tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
+1
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c
+1
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c
···
187
187
m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;
188
188
m->cp_hqd_pq_control |=
189
189
ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1;
190
+
m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK;
190
191
pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);
191
192
192
193
m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
+7
-2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
+7
-2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
···
28
28
#include <drm/drm_blend.h>
29
29
#include <drm/drm_gem_atomic_helper.h>
30
30
#include <drm/drm_plane_helper.h>
31
+
#include <drm/drm_gem_framebuffer_helper.h>
31
32
#include <drm/drm_fourcc.h>
32
33
33
34
#include "amdgpu.h"
···
936
935
}
937
936
938
937
afb = to_amdgpu_framebuffer(new_state->fb);
939
-
obj = new_state->fb->obj[0];
938
+
obj = drm_gem_fb_get_obj(new_state->fb, 0);
939
+
if (!obj) {
940
+
DRM_ERROR("Failed to get obj from framebuffer\n");
941
+
return -EINVAL;
942
+
}
943
+
940
944
rbo = gem_to_amdgpu_bo(obj);
941
945
adev = amdgpu_ttm_adev(rbo->tbo.bdev);
942
-
943
946
r = amdgpu_bo_reserve(rbo, true);
944
947
if (r) {
945
948
dev_err(adev->dev, "fail to reserve bo (%d)\n", r);
+42
drivers/gpu/drm/amd/include/discovery.h
+42
drivers/gpu/drm/amd/include/discovery.h
···
258
258
uint32_t gc_gl2c_per_gpu;
259
259
};
260
260
261
+
struct gc_info_v1_3 {
262
+
struct gpu_info_header header;
263
+
uint32_t gc_num_se;
264
+
uint32_t gc_num_wgp0_per_sa;
265
+
uint32_t gc_num_wgp1_per_sa;
266
+
uint32_t gc_num_rb_per_se;
267
+
uint32_t gc_num_gl2c;
268
+
uint32_t gc_num_gprs;
269
+
uint32_t gc_num_max_gs_thds;
270
+
uint32_t gc_gs_table_depth;
271
+
uint32_t gc_gsprim_buff_depth;
272
+
uint32_t gc_parameter_cache_depth;
273
+
uint32_t gc_double_offchip_lds_buffer;
274
+
uint32_t gc_wave_size;
275
+
uint32_t gc_max_waves_per_simd;
276
+
uint32_t gc_max_scratch_slots_per_cu;
277
+
uint32_t gc_lds_size;
278
+
uint32_t gc_num_sc_per_se;
279
+
uint32_t gc_num_sa_per_se;
280
+
uint32_t gc_num_packer_per_sc;
281
+
uint32_t gc_num_gl2a;
282
+
uint32_t gc_num_tcp_per_sa;
283
+
uint32_t gc_num_sdp_interface;
284
+
uint32_t gc_num_tcps;
285
+
uint32_t gc_num_tcp_per_wpg;
286
+
uint32_t gc_tcp_l1_size;
287
+
uint32_t gc_num_sqc_per_wgp;
288
+
uint32_t gc_l1_instruction_cache_size_per_sqc;
289
+
uint32_t gc_l1_data_cache_size_per_sqc;
290
+
uint32_t gc_gl1c_per_sa;
291
+
uint32_t gc_gl1c_size_per_instance;
292
+
uint32_t gc_gl2c_per_gpu;
293
+
uint32_t gc_tcp_size_per_cu;
294
+
uint32_t gc_tcp_cache_line_size;
295
+
uint32_t gc_instruction_cache_size_per_sqc;
296
+
uint32_t gc_instruction_cache_line_size;
297
+
uint32_t gc_scalar_data_cache_size_per_sqc;
298
+
uint32_t gc_scalar_data_cache_line_size;
299
+
uint32_t gc_tcc_size;
300
+
uint32_t gc_tcc_cache_line_size;
301
+
};
302
+
261
303
struct gc_info_v2_0 {
262
304
struct gpu_info_header header;
263
305
+11
-10
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+11
-10
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
···
2224
2224
}
2225
2225
2226
2226
static int smu_adjust_power_state_dynamic(struct smu_context *smu,
2227
-
enum amd_dpm_forced_level level,
2228
-
bool skip_display_settings)
2227
+
enum amd_dpm_forced_level level,
2228
+
bool skip_display_settings,
2229
+
bool force_update)
2229
2230
{
2230
2231
int ret = 0;
2231
2232
int index = 0;
···
2255
2254
}
2256
2255
}
2257
2256
2258
-
if (smu_dpm_ctx->dpm_level != level) {
2257
+
if (force_update || smu_dpm_ctx->dpm_level != level) {
2259
2258
ret = smu_asic_set_performance_level(smu, level);
2260
2259
if (ret) {
2261
2260
dev_err(smu->adev->dev, "Failed to set performance level!");
···
2266
2265
smu_dpm_ctx->dpm_level = level;
2267
2266
}
2268
2267
2269
-
if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
2270
-
smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
2268
+
if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
2271
2269
index = fls(smu->workload_mask);
2272
2270
index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
2273
2271
workload[0] = smu->workload_setting[index];
2274
2272
2275
-
if (smu->power_profile_mode != workload[0])
2273
+
if (force_update || smu->power_profile_mode != workload[0])
2276
2274
smu_bump_power_profile_mode(smu, workload, 0);
2277
2275
}
2278
2276
···
2292
2292
ret = smu_pre_display_config_changed(smu);
2293
2293
if (ret)
2294
2294
return ret;
2295
-
ret = smu_adjust_power_state_dynamic(smu, level, false);
2295
+
ret = smu_adjust_power_state_dynamic(smu, level, false, false);
2296
2296
break;
2297
2297
case AMD_PP_TASK_COMPLETE_INIT:
2298
+
ret = smu_adjust_power_state_dynamic(smu, level, true, true);
2299
+
break;
2298
2300
case AMD_PP_TASK_READJUST_POWER_STATE:
2299
-
ret = smu_adjust_power_state_dynamic(smu, level, true);
2301
+
ret = smu_adjust_power_state_dynamic(smu, level, true, false);
2300
2302
break;
2301
2303
default:
2302
2304
break;
···
2345
2343
workload[0] = smu->workload_setting[index];
2346
2344
}
2347
2345
2348
-
if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
2349
-
smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)
2346
+
if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)
2350
2347
smu_bump_power_profile_mode(smu, workload, 0);
2351
2348
2352
2349
return 0;
+14
-4
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_2_ppsmc.h
+14
-4
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_2_ppsmc.h
···
92
92
93
93
//Resets
94
94
#define PPSMC_MSG_PrepareMp1ForUnload 0x2E
95
-
#define PPSMC_MSG_Mode1Reset 0x2F
96
95
97
96
//Set SystemVirtual DramAddrHigh
98
97
#define PPSMC_MSG_SetSystemVirtualDramAddrHigh 0x30
···
118
119
119
120
//STB to dram log
120
121
#define PPSMC_MSG_DumpSTBtoDram 0x3D
121
-
#define PPSMC_MSG_STBtoDramLogSetDramAddrHigh 0x3E
122
-
#define PPSMC_MSG_STBtoDramLogSetDramAddrLow 0x3F
122
+
#define PPSMC_MSG_STBtoDramLogSetDramAddress 0x3E
123
+
#define PPSMC_MSG_DummyUndefined 0x3F
123
124
#define PPSMC_MSG_STBtoDramLogSetDramSize 0x40
124
125
#define PPSMC_MSG_SetOBMTraceBufferLogging 0x41
125
126
127
+
#define PPSMC_MSG_UseProfilingMode 0x42
126
128
#define PPSMC_MSG_AllowGfxDcs 0x43
127
129
#define PPSMC_MSG_DisallowGfxDcs 0x44
128
130
#define PPSMC_MSG_EnableAudioStutterWA 0x45
···
135
135
#define PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel 0x4B
136
136
#define PPSMC_MSG_SetPriorityDeltaGain 0x4C
137
137
#define PPSMC_MSG_AllowIHHostInterrupt 0x4D
138
+
#define PPSMC_MSG_EnableShadowDpm 0x4E
138
139
#define PPSMC_MSG_Mode3Reset 0x4F
139
-
#define PPSMC_Message_Count 0x50
140
+
#define PPSMC_MSG_SetDriverDramAddr 0x50
141
+
#define PPSMC_MSG_SetToolsDramAddr 0x51
142
+
#define PPSMC_MSG_TransferTableSmu2DramWithAddr 0x52
143
+
#define PPSMC_MSG_TransferTableDram2SmuWithAddr 0x53
144
+
#define PPSMC_MSG_GetAllRunningSmuFeatures 0x54
145
+
#define PPSMC_MSG_GetSvi3Voltage 0x55
146
+
#define PPSMC_MSG_UpdatePolicy 0x56
147
+
#define PPSMC_MSG_ExtPwrConnSupport 0x57
148
+
#define PPSMC_MSG_PreloadSwPstateForUclkOverDrive 0x58
149
+
#define PPSMC_Message_Count 0x59
140
150
#endif
+6
-1
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
+6
-1
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
···
121
121
122
122
#define P2S_TABLE_ID_A 0x50325341
123
123
#define P2S_TABLE_ID_X 0x50325358
124
+
#define P2S_TABLE_ID_3 0x50325303
124
125
125
126
// clang-format off
126
127
static const struct cmn2asic_msg_mapping smu_v13_0_6_message_map[SMU_MSG_MAX_COUNT] = {
···
272
271
struct amdgpu_device *adev = smu->adev;
273
272
uint32_t p2s_table_id = P2S_TABLE_ID_A;
274
273
int ret = 0, i, p2stable_count;
274
+
int var = (adev->pdev->device & 0xF);
275
275
char ucode_prefix[15];
276
276
277
277
/* No need to load P2S tables in IOV mode */
278
278
if (amdgpu_sriov_vf(adev))
279
279
return 0;
280
280
281
-
if (!(adev->flags & AMD_IS_APU))
281
+
if (!(adev->flags & AMD_IS_APU)) {
282
282
p2s_table_id = P2S_TABLE_ID_X;
283
+
if (var == 0x5)
284
+
p2s_table_id = P2S_TABLE_ID_3;
285
+
}
283
286
284
287
amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix,
285
288
sizeof(ucode_prefix));
+2
-2
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+2
-2
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
···
2378
2378
2379
2379
size += sysfs_emit_at(buf, size, " ");
2380
2380
for (i = 0; i <= PP_SMC_POWER_PROFILE_WINDOW3D; i++)
2381
-
size += sysfs_emit_at(buf, size, "%-14s%s", amdgpu_pp_profile_name[i],
2381
+
size += sysfs_emit_at(buf, size, "%d %-14s%s", i, amdgpu_pp_profile_name[i],
2382
2382
(i == smu->power_profile_mode) ? "* " : " ");
2383
2383
2384
2384
size += sysfs_emit_at(buf, size, "\n");
···
2408
2408
do { \
2409
2409
size += sysfs_emit_at(buf, size, "%-30s", #field); \
2410
2410
for (j = 0; j <= PP_SMC_POWER_PROFILE_WINDOW3D; j++) \
2411
-
size += sysfs_emit_at(buf, size, "%-16d", activity_monitor_external[j].DpmActivityMonitorCoeffInt.field); \
2411
+
size += sysfs_emit_at(buf, size, "%-18d", activity_monitor_external[j].DpmActivityMonitorCoeffInt.field); \
2412
2412
size += sysfs_emit_at(buf, size, "\n"); \
2413
2413
} while (0)
2414
2414
-48
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
-48
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
···
115
115
MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
116
116
MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
117
117
MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
118
-
MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
119
118
MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0),
120
119
MSG_MAP(DFCstateControl, PPSMC_MSG_SetExternalClientDfCstateAllow, 0),
121
120
MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
···
1823
1824
smu->debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_54);
1824
1825
}
1825
1826
1826
-
static int smu_v14_0_2_smu_send_bad_mem_page_num(struct smu_context *smu,
1827
-
uint32_t size)
1828
-
{
1829
-
int ret = 0;
1830
-
1831
-
/* message SMU to update the bad page number on SMUBUS */
1832
-
ret = smu_cmn_send_smc_msg_with_param(smu,
1833
-
SMU_MSG_SetNumBadMemoryPagesRetired,
1834
-
size, NULL);
1835
-
if (ret)
1836
-
dev_err(smu->adev->dev,
1837
-
"[%s] failed to message SMU to update bad memory pages number\n",
1838
-
__func__);
1839
-
1840
-
return ret;
1841
-
}
1842
-
1843
-
static int smu_v14_0_2_send_bad_mem_channel_flag(struct smu_context *smu,
1844
-
uint32_t size)
1845
-
{
1846
-
int ret = 0;
1847
-
1848
-
/* message SMU to update the bad channel info on SMUBUS */
1849
-
ret = smu_cmn_send_smc_msg_with_param(smu,
1850
-
SMU_MSG_SetBadMemoryPagesRetiredFlagsPerChannel,
1851
-
size, NULL);
1852
-
if (ret)
1853
-
dev_err(smu->adev->dev,
1854
-
"[%s] failed to message SMU to update bad memory pages channel info\n",
1855
-
__func__);
1856
-
1857
-
return ret;
1858
-
}
1859
-
1860
-
static ssize_t smu_v14_0_2_get_ecc_info(struct smu_context *smu,
1861
-
void *table)
1862
-
{
1863
-
int ret = 0;
1864
-
1865
-
// TODO
1866
-
1867
-
return ret;
1868
-
}
1869
-
1870
1827
static ssize_t smu_v14_0_2_get_gpu_metrics(struct smu_context *smu,
1871
1828
void **table)
1872
1829
{
···
1970
2015
.enable_gfx_features = smu_v14_0_2_enable_gfx_features,
1971
2016
.set_mp1_state = smu_v14_0_2_set_mp1_state,
1972
2017
.set_df_cstate = smu_v14_0_2_set_df_cstate,
1973
-
.send_hbm_bad_pages_num = smu_v14_0_2_smu_send_bad_mem_page_num,
1974
-
.send_hbm_bad_channel_flag = smu_v14_0_2_send_bad_mem_channel_flag,
1975
2018
#if 0
1976
2019
.gpo_control = smu_v14_0_gpo_control,
1977
2020
#endif
1978
-
.get_ecc_info = smu_v14_0_2_get_ecc_info,
1979
2021
};
1980
2022
1981
2023
void smu_v14_0_2_set_ppt_funcs(struct smu_context *smu)
+12
drivers/gpu/drm/i915/display/intel_dp.c
+12
drivers/gpu/drm/i915/display/intel_dp.c
···
5935
5935
else
5936
5936
status = connector_status_disconnected;
5937
5937
5938
+
if (status != connector_status_disconnected &&
5939
+
!intel_dp_mst_verify_dpcd_state(intel_dp))
5940
+
/*
5941
+
* This requires retrying detection for instance to re-enable
5942
+
* the MST mode that got reset via a long HPD pulse. The retry
5943
+
* will happen either via the hotplug handler's retry logic,
5944
+
* ensured by setting the connector here to SST/disconnected,
5945
+
* or via a userspace connector probing in response to the
5946
+
* hotplug uevent sent when removing the MST connectors.
5947
+
*/
5948
+
status = connector_status_disconnected;
5949
+
5938
5950
if (status == connector_status_disconnected) {
5939
5951
memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5940
5952
memset(intel_connector->dp.dsc_dpcd, 0, sizeof(intel_connector->dp.dsc_dpcd));
+40
drivers/gpu/drm/i915/display/intel_dp_mst.c
+40
drivers/gpu/drm/i915/display/intel_dp_mst.c
···
1998
1998
1999
1999
return false;
2000
2000
}
2001
+
2002
+
/*
2003
+
* intel_dp_mst_verify_dpcd_state - verify the MST SW enabled state wrt. the DPCD
2004
+
* @intel_dp: DP port object
2005
+
*
2006
+
* Verify if @intel_dp's MST enabled SW state matches the corresponding DPCD
2007
+
* state. A long HPD pulse - not long enough to be detected as a disconnected
2008
+
* state - could've reset the DPCD state, which requires tearing
2009
+
* down/recreating the MST topology.
2010
+
*
2011
+
* Returns %true if the SW MST enabled and DPCD states match, %false
2012
+
* otherwise.
2013
+
*/
2014
+
bool intel_dp_mst_verify_dpcd_state(struct intel_dp *intel_dp)
2015
+
{
2016
+
struct intel_display *display = to_intel_display(intel_dp);
2017
+
struct intel_connector *connector = intel_dp->attached_connector;
2018
+
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2019
+
struct intel_encoder *encoder = &dig_port->base;
2020
+
int ret;
2021
+
u8 val;
2022
+
2023
+
if (!intel_dp->is_mst)
2024
+
return true;
2025
+
2026
+
ret = drm_dp_dpcd_readb(intel_dp->mst_mgr.aux, DP_MSTM_CTRL, &val);
2027
+
2028
+
/* Adjust the expected register value for SST + SideBand. */
2029
+
if (ret < 0 || val != (DP_MST_EN | DP_UP_REQ_EN | DP_UPSTREAM_IS_SRC)) {
2030
+
drm_dbg_kms(display->drm,
2031
+
"[CONNECTOR:%d:%s][ENCODER:%d:%s] MST mode got reset, removing topology (ret=%d, ctrl=0x%02x)\n",
2032
+
connector->base.base.id, connector->base.name,
2033
+
encoder->base.base.id, encoder->base.name,
2034
+
ret, val);
2035
+
2036
+
return false;
2037
+
}
2038
+
2039
+
return true;
2040
+
}
+1
drivers/gpu/drm/i915/display/intel_dp_mst.h
+1
drivers/gpu/drm/i915/display/intel_dp_mst.h
-1
drivers/gpu/drm/i915/display/vlv_dsi.c
-1
drivers/gpu/drm/i915/display/vlv_dsi.c
···
1870
1870
/* Lenovo Yoga Tab 3 Pro YT3-X90F */
1871
1871
.matches = {
1872
1872
DMI_MATCH(DMI_SYS_VENDOR, "Intel Corporation"),
1873
-
DMI_MATCH(DMI_PRODUCT_NAME, "CHERRYVIEW D1 PLATFORM"),
1874
1873
DMI_MATCH(DMI_PRODUCT_VERSION, "Blade3-10A-001"),
1875
1874
},
1876
1875
.driver_data = (void *)vlv_dsi_lenovo_yoga_tab3_backlight_fixup,
+31
drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
+31
drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
···
212
212
}
213
213
}
214
214
215
+
if (IS_ARROWLAKE(gt->i915)) {
216
+
bool too_old = false;
217
+
218
+
/*
219
+
* ARL requires a newer firmware than MTL did (102.0.10.1878) but the
220
+
* firmware is actually common. So, need to do an explicit version check
221
+
* here rather than using a separate table entry. And if the older
222
+
* MTL-only version is found, then just don't use GSC rather than aborting
223
+
* the driver load.
224
+
*/
225
+
if (gsc->release.major < 102) {
226
+
too_old = true;
227
+
} else if (gsc->release.major == 102) {
228
+
if (gsc->release.minor == 0) {
229
+
if (gsc->release.patch < 10) {
230
+
too_old = true;
231
+
} else if (gsc->release.patch == 10) {
232
+
if (gsc->release.build < 1878)
233
+
too_old = true;
234
+
}
235
+
}
236
+
}
237
+
238
+
if (too_old) {
239
+
gt_info(gt, "GSC firmware too old for ARL, got %d.%d.%d.%d but need at least 102.0.10.1878",
240
+
gsc->release.major, gsc->release.minor,
241
+
gsc->release.patch, gsc->release.build);
242
+
return -EINVAL;
243
+
}
244
+
}
245
+
215
246
return 0;
216
247
}
217
248
+8
-2
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+8
-2
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
···
698
698
const struct firmware *fw,
699
699
struct intel_uc_fw *uc_fw)
700
700
{
701
+
int ret;
702
+
701
703
switch (uc_fw->type) {
702
704
case INTEL_UC_FW_TYPE_HUC:
703
-
intel_huc_fw_get_binary_info(uc_fw, fw->data, fw->size);
705
+
ret = intel_huc_fw_get_binary_info(uc_fw, fw->data, fw->size);
706
+
if (ret)
707
+
return ret;
704
708
break;
705
709
case INTEL_UC_FW_TYPE_GSC:
706
-
intel_gsc_fw_get_binary_info(uc_fw, fw->data, fw->size);
710
+
ret = intel_gsc_fw_get_binary_info(uc_fw, fw->data, fw->size);
711
+
if (ret)
712
+
return ret;
707
713
break;
708
714
default:
709
715
MISSING_CASE(uc_fw->type);
+2
drivers/gpu/drm/i915/i915_drv.h
+2
drivers/gpu/drm/i915/i915_drv.h
···
546
546
#define IS_LUNARLAKE(i915) (0 && i915)
547
547
#define IS_BATTLEMAGE(i915) (0 && i915)
548
548
549
+
#define IS_ARROWLAKE(i915) \
550
+
IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL)
549
551
#define IS_DG2_G10(i915) \
550
552
IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10)
551
553
#define IS_DG2_G11(i915) \
+7
drivers/gpu/drm/i915/intel_device_info.c
+7
drivers/gpu/drm/i915/intel_device_info.c
···
203
203
INTEL_DG2_G12_IDS(ID),
204
204
};
205
205
206
+
static const u16 subplatform_arl_ids[] = {
207
+
INTEL_ARL_IDS(ID),
208
+
};
209
+
206
210
static bool find_devid(u16 id, const u16 *p, unsigned int num)
207
211
{
208
212
for (; num; num--, p++) {
···
264
260
} else if (find_devid(devid, subplatform_g12_ids,
265
261
ARRAY_SIZE(subplatform_g12_ids))) {
266
262
mask = BIT(INTEL_SUBPLATFORM_G12);
263
+
} else if (find_devid(devid, subplatform_arl_ids,
264
+
ARRAY_SIZE(subplatform_arl_ids))) {
265
+
mask = BIT(INTEL_SUBPLATFORM_ARL);
267
266
}
268
267
269
268
GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK);
+3
drivers/gpu/drm/i915/intel_device_info.h
+3
drivers/gpu/drm/i915/intel_device_info.h
+6
drivers/gpu/drm/v3d/v3d_sched.c
+6
drivers/gpu/drm/v3d/v3d_sched.c
···
134
134
struct v3d_stats *local_stats = &file->stats[queue];
135
135
u64 now = local_clock();
136
136
137
+
preempt_disable();
138
+
137
139
write_seqcount_begin(&local_stats->lock);
138
140
local_stats->start_ns = now;
139
141
write_seqcount_end(&local_stats->lock);
···
143
141
write_seqcount_begin(&global_stats->lock);
144
142
global_stats->start_ns = now;
145
143
write_seqcount_end(&global_stats->lock);
144
+
145
+
preempt_enable();
146
146
}
147
147
148
148
static void
···
166
162
struct v3d_stats *local_stats = &file->stats[queue];
167
163
u64 now = local_clock();
168
164
165
+
preempt_disable();
169
166
v3d_stats_update(local_stats, now);
170
167
v3d_stats_update(global_stats, now);
168
+
preempt_enable();
171
169
}
172
170
173
171
static struct dma_fence *v3d_bin_job_run(struct drm_sched_job *sched_job)
+110
-4
drivers/gpu/drm/vmwgfx/vmwgfx_blit.c
+110
-4
drivers/gpu/drm/vmwgfx/vmwgfx_blit.c
···
27
27
**************************************************************************/
28
28
29
29
#include "vmwgfx_drv.h"
30
+
31
+
#include "vmwgfx_bo.h"
30
32
#include <linux/highmem.h>
31
33
32
34
/*
···
422
420
return 0;
423
421
}
424
422
423
+
static void *map_external(struct vmw_bo *bo, struct iosys_map *map)
424
+
{
425
+
struct vmw_private *vmw =
426
+
container_of(bo->tbo.bdev, struct vmw_private, bdev);
427
+
void *ptr = NULL;
428
+
int ret;
429
+
430
+
if (bo->tbo.base.import_attach) {
431
+
ret = dma_buf_vmap(bo->tbo.base.dma_buf, map);
432
+
if (ret) {
433
+
drm_dbg_driver(&vmw->drm,
434
+
"Wasn't able to map external bo!\n");
435
+
goto out;
436
+
}
437
+
ptr = map->vaddr;
438
+
} else {
439
+
ptr = vmw_bo_map_and_cache(bo);
440
+
}
441
+
442
+
out:
443
+
return ptr;
444
+
}
445
+
446
+
static void unmap_external(struct vmw_bo *bo, struct iosys_map *map)
447
+
{
448
+
if (bo->tbo.base.import_attach)
449
+
dma_buf_vunmap(bo->tbo.base.dma_buf, map);
450
+
else
451
+
vmw_bo_unmap(bo);
452
+
}
453
+
454
+
static int vmw_external_bo_copy(struct vmw_bo *dst, u32 dst_offset,
455
+
u32 dst_stride, struct vmw_bo *src,
456
+
u32 src_offset, u32 src_stride,
457
+
u32 width_in_bytes, u32 height,
458
+
struct vmw_diff_cpy *diff)
459
+
{
460
+
struct vmw_private *vmw =
461
+
container_of(dst->tbo.bdev, struct vmw_private, bdev);
462
+
size_t dst_size = dst->tbo.resource->size;
463
+
size_t src_size = src->tbo.resource->size;
464
+
struct iosys_map dst_map = {0};
465
+
struct iosys_map src_map = {0};
466
+
int ret, i;
467
+
int x_in_bytes;
468
+
u8 *vsrc;
469
+
u8 *vdst;
470
+
471
+
vsrc = map_external(src, &src_map);
472
+
if (!vsrc) {
473
+
drm_dbg_driver(&vmw->drm, "Wasn't able to map src\n");
474
+
ret = -ENOMEM;
475
+
goto out;
476
+
}
477
+
478
+
vdst = map_external(dst, &dst_map);
479
+
if (!vdst) {
480
+
drm_dbg_driver(&vmw->drm, "Wasn't able to map dst\n");
481
+
ret = -ENOMEM;
482
+
goto out;
483
+
}
484
+
485
+
vsrc += src_offset;
486
+
vdst += dst_offset;
487
+
if (src_stride == dst_stride) {
488
+
dst_size -= dst_offset;
489
+
src_size -= src_offset;
490
+
memcpy(vdst, vsrc,
491
+
min(dst_stride * height, min(dst_size, src_size)));
492
+
} else {
493
+
WARN_ON(dst_stride < width_in_bytes);
494
+
for (i = 0; i < height; ++i) {
495
+
memcpy(vdst, vsrc, width_in_bytes);
496
+
vsrc += src_stride;
497
+
vdst += dst_stride;
498
+
}
499
+
}
500
+
501
+
x_in_bytes = (dst_offset % dst_stride);
502
+
diff->rect.x1 = x_in_bytes / diff->cpp;
503
+
diff->rect.y1 = ((dst_offset - x_in_bytes) / dst_stride);
504
+
diff->rect.x2 = diff->rect.x1 + width_in_bytes / diff->cpp;
505
+
diff->rect.y2 = diff->rect.y1 + height;
506
+
507
+
ret = 0;
508
+
out:
509
+
unmap_external(src, &src_map);
510
+
unmap_external(dst, &dst_map);
511
+
512
+
return ret;
513
+
}
514
+
425
515
/**
426
516
* vmw_bo_cpu_blit - in-kernel cpu blit.
427
517
*
428
-
* @dst: Destination buffer object.
518
+
* @vmw_dst: Destination buffer object.
429
519
* @dst_offset: Destination offset of blit start in bytes.
430
520
* @dst_stride: Destination stride in bytes.
431
-
* @src: Source buffer object.
521
+
* @vmw_src: Source buffer object.
432
522
* @src_offset: Source offset of blit start in bytes.
433
523
* @src_stride: Source stride in bytes.
434
524
* @w: Width of blit.
···
538
444
* Neither of the buffer objects may be placed in PCI memory
539
445
* (Fixed memory in TTM terminology) when using this function.
540
446
*/
541
-
int vmw_bo_cpu_blit(struct ttm_buffer_object *dst,
447
+
int vmw_bo_cpu_blit(struct vmw_bo *vmw_dst,
542
448
u32 dst_offset, u32 dst_stride,
543
-
struct ttm_buffer_object *src,
449
+
struct vmw_bo *vmw_src,
544
450
u32 src_offset, u32 src_stride,
545
451
u32 w, u32 h,
546
452
struct vmw_diff_cpy *diff)
547
453
{
454
+
struct ttm_buffer_object *src = &vmw_src->tbo;
455
+
struct ttm_buffer_object *dst = &vmw_dst->tbo;
548
456
struct ttm_operation_ctx ctx = {
549
457
.interruptible = false,
550
458
.no_wait_gpu = false
···
556
460
int ret = 0;
557
461
struct page **dst_pages = NULL;
558
462
struct page **src_pages = NULL;
463
+
bool src_external = (src->ttm->page_flags & TTM_TT_FLAG_EXTERNAL) != 0;
464
+
bool dst_external = (dst->ttm->page_flags & TTM_TT_FLAG_EXTERNAL) != 0;
465
+
466
+
if (WARN_ON(dst == src))
467
+
return -EINVAL;
559
468
560
469
/* Buffer objects need to be either pinned or reserved: */
561
470
if (!(dst->pin_count))
···
579
478
if (ret)
580
479
return ret;
581
480
}
481
+
482
+
if (src_external || dst_external)
483
+
return vmw_external_bo_copy(vmw_dst, dst_offset, dst_stride,
484
+
vmw_src, src_offset, src_stride,
485
+
w, h, diff);
582
486
583
487
if (!src->ttm->pages && src->ttm->sg) {
584
488
src_pages = kvmalloc_array(src->ttm->num_pages,
+11
-2
drivers/gpu/drm/vmwgfx/vmwgfx_bo.c
+11
-2
drivers/gpu/drm/vmwgfx/vmwgfx_bo.c
···
360
360
void *virtual;
361
361
int ret;
362
362
363
+
atomic_inc(&vbo->map_count);
364
+
363
365
virtual = ttm_kmap_obj_virtual(&vbo->map, ¬_used);
364
366
if (virtual)
365
367
return virtual;
···
385
383
*/
386
384
void vmw_bo_unmap(struct vmw_bo *vbo)
387
385
{
386
+
int map_count;
387
+
388
388
if (vbo->map.bo == NULL)
389
389
return;
390
390
391
-
ttm_bo_kunmap(&vbo->map);
392
-
vbo->map.bo = NULL;
391
+
map_count = atomic_dec_return(&vbo->map_count);
392
+
393
+
if (!map_count) {
394
+
ttm_bo_kunmap(&vbo->map);
395
+
vbo->map.bo = NULL;
396
+
}
393
397
}
394
398
395
399
···
429
421
vmw_bo->tbo.priority = 3;
430
422
vmw_bo->res_tree = RB_ROOT;
431
423
xa_init(&vmw_bo->detached_resources);
424
+
atomic_set(&vmw_bo->map_count, 0);
432
425
433
426
params->size = ALIGN(params->size, PAGE_SIZE);
434
427
drm_gem_private_object_init(vdev, &vmw_bo->tbo.base, params->size);
+3
drivers/gpu/drm/vmwgfx/vmwgfx_bo.h
+3
drivers/gpu/drm/vmwgfx/vmwgfx_bo.h
···
71
71
* @map: Kmap object for semi-persistent mappings
72
72
* @res_tree: RB tree of resources using this buffer object as a backing MOB
73
73
* @res_prios: Eviction priority counts for attached resources
74
+
* @map_count: The number of currently active maps. Will differ from the
75
+
* cpu_writers because it includes kernel maps.
74
76
* @cpu_writers: Number of synccpu write grabs. Protected by reservation when
75
77
* increased. May be decreased without reservation.
76
78
* @dx_query_ctx: DX context if this buffer object is used as a DX query MOB
···
92
90
u32 res_prios[TTM_MAX_BO_PRIORITY];
93
91
struct xarray detached_resources;
94
92
93
+
atomic_t map_count;
95
94
atomic_t cpu_writers;
96
95
/* Not ref-counted. Protected by binding_mutex */
97
96
struct vmw_resource *dx_query_ctx;
+2
-2
drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
+2
-2
drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
···
1353
1353
1354
1354
void vmw_memcpy(struct vmw_diff_cpy *diff, u8 *dest, const u8 *src, size_t n);
1355
1355
1356
-
int vmw_bo_cpu_blit(struct ttm_buffer_object *dst,
1356
+
int vmw_bo_cpu_blit(struct vmw_bo *dst,
1357
1357
u32 dst_offset, u32 dst_stride,
1358
-
struct ttm_buffer_object *src,
1358
+
struct vmw_bo *src,
1359
1359
u32 src_offset, u32 src_stride,
1360
1360
u32 w, u32 h,
1361
1361
struct vmw_diff_cpy *diff);
+6
-6
drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
+6
-6
drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
···
502
502
container_of(dirty->unit, typeof(*stdu), base);
503
503
s32 width, height;
504
504
s32 src_pitch, dst_pitch;
505
-
struct ttm_buffer_object *src_bo, *dst_bo;
505
+
struct vmw_bo *src_bo, *dst_bo;
506
506
u32 src_offset, dst_offset;
507
507
struct vmw_diff_cpy diff = VMW_CPU_BLIT_DIFF_INITIALIZER(stdu->cpp);
508
508
···
517
517
518
518
/* Assume we are blitting from Guest (bo) to Host (display_srf) */
519
519
src_pitch = stdu->display_srf->metadata.base_size.width * stdu->cpp;
520
-
src_bo = &stdu->display_srf->res.guest_memory_bo->tbo;
520
+
src_bo = stdu->display_srf->res.guest_memory_bo;
521
521
src_offset = ddirty->top * src_pitch + ddirty->left * stdu->cpp;
522
522
523
523
dst_pitch = ddirty->pitch;
524
-
dst_bo = &ddirty->buf->tbo;
524
+
dst_bo = ddirty->buf;
525
525
dst_offset = ddirty->fb_top * dst_pitch + ddirty->fb_left * stdu->cpp;
526
526
527
527
(void) vmw_bo_cpu_blit(dst_bo, dst_offset, dst_pitch,
···
1170
1170
struct vmw_diff_cpy diff = VMW_CPU_BLIT_DIFF_INITIALIZER(0);
1171
1171
struct vmw_stdu_update_gb_image *cmd_img = cmd;
1172
1172
struct vmw_stdu_update *cmd_update;
1173
-
struct ttm_buffer_object *src_bo, *dst_bo;
1173
+
struct vmw_bo *src_bo, *dst_bo;
1174
1174
u32 src_offset, dst_offset;
1175
1175
s32 src_pitch, dst_pitch;
1176
1176
s32 width, height;
···
1184
1184
1185
1185
diff.cpp = stdu->cpp;
1186
1186
1187
-
dst_bo = &stdu->display_srf->res.guest_memory_bo->tbo;
1187
+
dst_bo = stdu->display_srf->res.guest_memory_bo;
1188
1188
dst_pitch = stdu->display_srf->metadata.base_size.width * stdu->cpp;
1189
1189
dst_offset = bb->y1 * dst_pitch + bb->x1 * stdu->cpp;
1190
1190
1191
-
src_bo = &vfbbo->buffer->tbo;
1191
+
src_bo = vfbbo->buffer;
1192
1192
src_pitch = update->vfb->base.pitches[0];
1193
1193
src_offset = bo_update->fb_top * src_pitch + bo_update->fb_left *
1194
1194
stdu->cpp;
+4
-2
drivers/gpu/drm/vmwgfx/vmwgfx_surface.c
+4
-2
drivers/gpu/drm/vmwgfx/vmwgfx_surface.c
···
2283
2283
/*
2284
2284
* Without mob support we're just going to use raw memory buffer
2285
2285
* because we wouldn't be able to support full surface coherency
2286
-
* without mobs
2286
+
* without mobs. There also no reason to support surface coherency
2287
+
* without 3d (i.e. gpu usage on the host) because then all the
2288
+
* contents is going to be rendered guest side.
2287
2289
*/
2288
-
if (!dev_priv->has_mob) {
2290
+
if (!dev_priv->has_mob || !vmw_supports_3d(dev_priv)) {
2289
2291
int cpp = DIV_ROUND_UP(args->bpp, 8);
2290
2292
2291
2293
switch (cpp) {
+1
-1
drivers/gpu/drm/xe/xe_hwmon.c
+1
-1
drivers/gpu/drm/xe/xe_hwmon.c
+24
-13
drivers/gpu/drm/xe/xe_vm.c
+24
-13
drivers/gpu/drm/xe/xe_vm.c
···
3341
3341
{
3342
3342
struct xe_device *xe = xe_vma_vm(vma)->xe;
3343
3343
struct xe_tile *tile;
3344
-
struct xe_gt_tlb_invalidation_fence fence[XE_MAX_TILES_PER_DEVICE];
3345
-
u32 tile_needs_invalidate = 0;
3344
+
struct xe_gt_tlb_invalidation_fence
3345
+
fence[XE_MAX_TILES_PER_DEVICE * XE_MAX_GT_PER_TILE];
3346
3346
u8 id;
3347
+
u32 fence_id = 0;
3347
3348
int ret = 0;
3348
3349
3349
3350
xe_assert(xe, !xe_vma_is_null(vma));
···
3372
3371
if (xe_pt_zap_ptes(tile, vma)) {
3373
3372
xe_device_wmb(xe);
3374
3373
xe_gt_tlb_invalidation_fence_init(tile->primary_gt,
3375
-
&fence[id], true);
3374
+
&fence[fence_id],
3375
+
true);
3376
3376
3377
-
/*
3378
-
* FIXME: We potentially need to invalidate multiple
3379
-
* GTs within the tile
3380
-
*/
3381
3377
ret = xe_gt_tlb_invalidation_vma(tile->primary_gt,
3382
-
&fence[id], vma);
3378
+
&fence[fence_id], vma);
3383
3379
if (ret < 0) {
3384
-
xe_gt_tlb_invalidation_fence_fini(&fence[id]);
3380
+
xe_gt_tlb_invalidation_fence_fini(&fence[fence_id]);
3385
3381
goto wait;
3386
3382
}
3383
+
++fence_id;
3387
3384
3388
-
tile_needs_invalidate |= BIT(id);
3385
+
if (!tile->media_gt)
3386
+
continue;
3387
+
3388
+
xe_gt_tlb_invalidation_fence_init(tile->media_gt,
3389
+
&fence[fence_id],
3390
+
true);
3391
+
3392
+
ret = xe_gt_tlb_invalidation_vma(tile->media_gt,
3393
+
&fence[fence_id], vma);
3394
+
if (ret < 0) {
3395
+
xe_gt_tlb_invalidation_fence_fini(&fence[fence_id]);
3396
+
goto wait;
3397
+
}
3398
+
++fence_id;
3389
3399
}
3390
3400
}
3391
3401
3392
3402
wait:
3393
-
for_each_tile(tile, xe, id)
3394
-
if (tile_needs_invalidate & BIT(id))
3395
-
xe_gt_tlb_invalidation_fence_wait(&fence[id]);
3403
+
for (id = 0; id < fence_id; ++id)
3404
+
xe_gt_tlb_invalidation_fence_wait(&fence[id]);
3396
3405
3397
3406
vma->tile_invalidated = vma->tile_mask;
3398
3407
+1
-1
drivers/of/platform.c
+1
-1
drivers/of/platform.c
+3
-8
drivers/video/aperture.c
+3
-8
drivers/video/aperture.c
···
293
293
* ask for this, so let's assume that a real driver for the display
294
294
* was already probed and prevent sysfb to register devices later.
295
295
*/
296
-
sysfb_disable();
296
+
sysfb_disable(NULL);
297
297
298
298
aperture_detach_devices(base, size);
299
299
···
346
346
*/
347
347
int aperture_remove_conflicting_pci_devices(struct pci_dev *pdev, const char *name)
348
348
{
349
-
bool primary = false;
350
349
resource_size_t base, size;
351
350
int bar, ret = 0;
352
351
353
-
if (pdev == vga_default_device())
354
-
primary = true;
355
-
356
-
if (primary)
357
-
sysfb_disable();
352
+
sysfb_disable(&pdev->dev);
358
353
359
354
for (bar = 0; bar < PCI_STD_NUM_BARS; ++bar) {
360
355
if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM))
···
365
370
* that consumes the VGA framebuffer I/O range. Remove this
366
371
* device as well.
367
372
*/
368
-
if (primary)
373
+
if (pdev == vga_default_device())
369
374
ret = __aperture_remove_legacy_vga_devices(pdev);
370
375
371
376
return ret;
+8
-5
include/drm/intel/i915_pciids.h
+8
-5
include/drm/intel/i915_pciids.h
···
772
772
INTEL_ATS_M75_IDS(MACRO__, ## __VA_ARGS__)
773
773
774
774
/* MTL */
775
-
#define INTEL_MTL_IDS(MACRO__, ...) \
776
-
MACRO__(0x7D40, ## __VA_ARGS__), \
775
+
#define INTEL_ARL_IDS(MACRO__, ...) \
777
776
MACRO__(0x7D41, ## __VA_ARGS__), \
778
-
MACRO__(0x7D45, ## __VA_ARGS__), \
779
777
MACRO__(0x7D51, ## __VA_ARGS__), \
778
+
MACRO__(0x7D67, ## __VA_ARGS__), \
779
+
MACRO__(0x7DD1, ## __VA_ARGS__)
780
+
781
+
#define INTEL_MTL_IDS(MACRO__, ...) \
782
+
INTEL_ARL_IDS(MACRO__, ## __VA_ARGS__), \
783
+
MACRO__(0x7D40, ## __VA_ARGS__), \
784
+
MACRO__(0x7D45, ## __VA_ARGS__), \
780
785
MACRO__(0x7D55, ## __VA_ARGS__), \
781
786
MACRO__(0x7D60, ## __VA_ARGS__), \
782
-
MACRO__(0x7D67, ## __VA_ARGS__), \
783
-
MACRO__(0x7DD1, ## __VA_ARGS__), \
784
787
MACRO__(0x7DD5, ## __VA_ARGS__)
785
788
786
789
/* LNL */
-4
include/drm/ttm/ttm_bo.h
-4
include/drm/ttm/ttm_bo.h
···
39
39
#include "ttm_device.h"
40
40
41
41
/* Default number of pre-faulted pages in the TTM fault handler */
42
-
#if CONFIG_PGTABLE_LEVELS > 2
43
-
#define TTM_BO_VM_NUM_PREFAULT (1 << (PMD_SHIFT - PAGE_SHIFT))
44
-
#else
45
42
#define TTM_BO_VM_NUM_PREFAULT 16
46
-
#endif
47
43
48
44
struct iosys_map;
49
45
+2
-2
include/linux/sysfb.h
+2
-2
include/linux/sysfb.h