Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
pinctrl: generic: rename PIN_CONFIG_OUTPUT to LEVEL
This generic pin config property is confusingly named so let's
rename it to make things clearer.
There are already drivers in the tree that use PIN_CONFIG_OUTPUT
to *read* the value of an output driven pin, which is a big
semantic confusion for the head: are we then reading the
setting of the output or the actual value/level that is put
out on the pin?
We already have PIN_CONFIG_OUTPUT_ENABLE that turns on driver
buffers for output, so this can by logical conclusion only
drive the voltage level if it should be any different.
But if we read the pin, are we then reading the *setting* of
the output value or the *actual* value we can see on the
line?
If the pin has not first been set into output mode with
PIN_CONFIG_OUTPUT_ENABLE, but is instead in some input mode
or tristate, what will reading this property actually
return?
Reading the current users reading this property it is clear
that what we read is the logical level of the pin as 0 or 1
depending on if it is low or high.
Rename it to PIN_CONFIG_LEVEL so it is crystal clear that
we set or read the voltage level of the pin and nothing else.
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+91
-87
+2
-2
Documentation/driver-api/pin-control.rst
+2
-2
Documentation/driver-api/pin-control.rst
···
863
863
a certain pin config setting. Look in e.g. ``<linux/pinctrl/pinconf-generic.h>``
864
864
and you find this in the documentation:
865
865
866
-
PIN_CONFIG_OUTPUT:
866
+
PIN_CONFIG_LEVEL:
867
867
this will configure the pin in output, use argument
868
868
1 to indicate high level, argument 0 to indicate low level.
869
869
···
897
897
};
898
898
899
899
static unsigned long uart_sleep_mode[] = {
900
-
PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0),
900
+
PIN_CONF_PACKED(PIN_CONFIG_LEVEL, 0),
901
901
};
902
902
903
903
static struct pinctrl_map pinmap[] __initdata = {
+1
-1
drivers/gpio/gpio-rockchip.c
+1
-1
drivers/gpio/gpio-rockchip.c
···
769
769
list_del(&cfg->head);
770
770
771
771
switch (cfg->param) {
772
-
case PIN_CONFIG_OUTPUT:
772
+
case PIN_CONFIG_LEVEL:
773
773
ret = rockchip_gpio_direction_output(&bank->gpio_chip, cfg->pin, cfg->arg);
774
774
if (ret)
775
775
dev_warn(dev, "setting output pin %u to %u failed\n", cfg->pin,
+3
-3
drivers/pinctrl/bcm/pinctrl-bcm2835.c
+3
-3
drivers/pinctrl/bcm/pinctrl-bcm2835.c
···
1023
1023
/* No way to read back bias config in HW */
1024
1024
1025
1025
switch (param) {
1026
-
case PIN_CONFIG_OUTPUT:
1026
+
case PIN_CONFIG_LEVEL:
1027
1027
if (fsel != BCM2835_FSEL_GPIO_OUT)
1028
1028
return -EINVAL;
1029
1029
···
1091
1091
break;
1092
1092
1093
1093
/* Set output-high or output-low */
1094
-
case PIN_CONFIG_OUTPUT:
1094
+
case PIN_CONFIG_LEVEL:
1095
1095
bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
1096
1096
break;
1097
1097
···
1202
1202
break;
1203
1203
1204
1204
/* Set output-high or output-low */
1205
-
case PIN_CONFIG_OUTPUT:
1205
+
case PIN_CONFIG_LEVEL:
1206
1206
bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
1207
1207
break;
1208
1208
+2
-2
drivers/pinctrl/cirrus/pinctrl-madera-core.c
+2
-2
drivers/pinctrl/cirrus/pinctrl-madera-core.c
···
804
804
if (conf[0] & MADERA_GP1_IP_CFG_MASK)
805
805
result = 1;
806
806
break;
807
-
case PIN_CONFIG_OUTPUT:
807
+
case PIN_CONFIG_LEVEL:
808
808
if ((conf[1] & MADERA_GP1_DIR_MASK) &&
809
809
(conf[0] & MADERA_GP1_LVL_MASK))
810
810
result = 1;
···
902
902
mask[1] |= MADERA_GP1_DIR_MASK;
903
903
conf[1] |= MADERA_GP1_DIR;
904
904
break;
905
-
case PIN_CONFIG_OUTPUT:
905
+
case PIN_CONFIG_LEVEL:
906
906
val = pinconf_to_config_argument(*configs);
907
907
mask[0] |= MADERA_GP1_LVL_MASK;
908
908
if (val)
+2
-2
drivers/pinctrl/mediatek/pinctrl-airoha.c
+2
-2
drivers/pinctrl/mediatek/pinctrl-airoha.c
···
2765
2765
break;
2766
2766
case PIN_CONFIG_OUTPUT_ENABLE:
2767
2767
case PIN_CONFIG_INPUT_ENABLE:
2768
-
case PIN_CONFIG_OUTPUT: {
2768
+
case PIN_CONFIG_LEVEL: {
2769
2769
bool input = param == PIN_CONFIG_INPUT_ENABLE;
2770
2770
int err;
2771
2771
···
2774
2774
if (err)
2775
2775
return err;
2776
2776
2777
-
if (param == PIN_CONFIG_OUTPUT) {
2777
+
if (param == PIN_CONFIG_LEVEL) {
2778
2778
err = airoha_pinconf_set_pin_value(pctrl_dev,
2779
2779
pin, !!arg);
2780
2780
if (err)
+1
-1
drivers/pinctrl/mediatek/pinctrl-moore.c
+1
-1
drivers/pinctrl/mediatek/pinctrl-moore.c
+1
-1
drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+1
-1
drivers/pinctrl/mediatek/pinctrl-mtk-common.c
···
384
384
mtk_pmx_gpio_set_direction(pctldev, NULL, pin, true);
385
385
ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
386
386
break;
387
-
case PIN_CONFIG_OUTPUT:
387
+
case PIN_CONFIG_LEVEL:
388
388
mtk_gpio_set(pctl->chip, pin, arg);
389
389
ret = mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false);
390
390
break;
+2
-2
drivers/pinctrl/mediatek/pinctrl-paris.c
+2
-2
drivers/pinctrl/mediatek/pinctrl-paris.c
···
169
169
if (!ret)
170
170
err = -EINVAL;
171
171
break;
172
-
case PIN_CONFIG_OUTPUT:
172
+
case PIN_CONFIG_LEVEL:
173
173
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &ret);
174
174
if (err)
175
175
break;
···
292
292
/* regard all non-zero value as enable */
293
293
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SR, !!arg);
294
294
break;
295
-
case PIN_CONFIG_OUTPUT:
295
+
case PIN_CONFIG_LEVEL:
296
296
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO,
297
297
arg);
298
298
if (err)
+3
-3
drivers/pinctrl/meson/pinctrl-amlogic-a4.c
+3
-3
drivers/pinctrl/meson/pinctrl-amlogic-a4.c
···
422
422
return -EINVAL;
423
423
arg = 1;
424
424
break;
425
-
case PIN_CONFIG_OUTPUT:
425
+
case PIN_CONFIG_LEVEL:
426
426
ret = aml_pinconf_get_output(info, pin);
427
427
if (ret <= 0)
428
428
return -EINVAL;
···
568
568
switch (param) {
569
569
case PIN_CONFIG_DRIVE_STRENGTH_UA:
570
570
case PIN_CONFIG_OUTPUT_ENABLE:
571
-
case PIN_CONFIG_OUTPUT:
571
+
case PIN_CONFIG_LEVEL:
572
572
arg = pinconf_to_config_argument(configs[i]);
573
573
break;
574
574
···
592
592
case PIN_CONFIG_OUTPUT_ENABLE:
593
593
ret = aml_pinconf_set_output(info, pin, arg);
594
594
break;
595
-
case PIN_CONFIG_OUTPUT:
595
+
case PIN_CONFIG_LEVEL:
596
596
ret = aml_pinconf_set_output_drive(info, pin, arg);
597
597
break;
598
598
default:
+3
-3
drivers/pinctrl/meson/pinctrl-meson.c
+3
-3
drivers/pinctrl/meson/pinctrl-meson.c
···
360
360
switch (param) {
361
361
case PIN_CONFIG_DRIVE_STRENGTH_UA:
362
362
case PIN_CONFIG_OUTPUT_ENABLE:
363
-
case PIN_CONFIG_OUTPUT:
363
+
case PIN_CONFIG_LEVEL:
364
364
arg = pinconf_to_config_argument(configs[i]);
365
365
break;
366
366
···
384
384
case PIN_CONFIG_OUTPUT_ENABLE:
385
385
ret = meson_pinconf_set_output(pc, pin, arg);
386
386
break;
387
-
case PIN_CONFIG_OUTPUT:
387
+
case PIN_CONFIG_LEVEL:
388
388
ret = meson_pinconf_set_output_drive(pc, pin, arg);
389
389
break;
390
390
default:
···
502
502
return -EINVAL;
503
503
arg = 1;
504
504
break;
505
-
case PIN_CONFIG_OUTPUT:
505
+
case PIN_CONFIG_LEVEL:
506
506
ret = meson_pinconf_get_output(pc, pin);
507
507
if (ret <= 0)
508
508
return -EINVAL;
+3
-3
drivers/pinctrl/nomadik/pinctrl-abx500.c
+3
-3
drivers/pinctrl/nomadik/pinctrl-abx500.c
···
860
860
861
861
dev_dbg(chip->parent, "pin %d [%#lx]: %s %s\n",
862
862
pin, configs[i],
863
-
(param == PIN_CONFIG_OUTPUT) ? "output " : "input",
864
-
(param == PIN_CONFIG_OUTPUT) ?
863
+
(param == PIN_CONFIG_LEVEL) ? "output " : "input",
864
+
(param == PIN_CONFIG_LEVEL) ?
865
865
str_high_low(argument) :
866
866
(argument ? "pull up" : "pull down"));
867
867
···
907
907
ret = abx500_gpio_direction_input(chip, offset);
908
908
break;
909
909
910
-
case PIN_CONFIG_OUTPUT:
910
+
case PIN_CONFIG_LEVEL:
911
911
ret = abx500_gpio_direction_output(chip, offset,
912
912
argument);
913
913
break;
+3
-3
drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
+3
-3
drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
···
1700
1700
else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
1701
1701
rc = (!pu && pd);
1702
1702
break;
1703
-
case PIN_CONFIG_OUTPUT:
1703
+
case PIN_CONFIG_LEVEL:
1704
1704
case PIN_CONFIG_INPUT_ENABLE:
1705
1705
ie = ioread32(bank->base + NPCM7XX_GP_N_IEM) & pinmask;
1706
1706
oe = ioread32(bank->base + NPCM7XX_GP_N_OE) & pinmask;
1707
1707
if (param == PIN_CONFIG_INPUT_ENABLE)
1708
1708
rc = (ie && !oe);
1709
-
else if (param == PIN_CONFIG_OUTPUT)
1709
+
else if (param == PIN_CONFIG_LEVEL)
1710
1710
rc = (!ie && oe);
1711
1711
break;
1712
1712
case PIN_CONFIG_DRIVE_PUSH_PULL:
···
1765
1765
iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC);
1766
1766
bank->direction_input(&bank->chip.gc, pin % bank->chip.gc.ngpio);
1767
1767
break;
1768
-
case PIN_CONFIG_OUTPUT:
1768
+
case PIN_CONFIG_LEVEL:
1769
1769
bank->direction_output(&bank->chip.gc, pin % bank->chip.gc.ngpio, arg);
1770
1770
iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES);
1771
1771
break;
+3
-3
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
+3
-3
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
···
2187
2187
else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
2188
2188
rc = !pu && pd;
2189
2189
break;
2190
-
case PIN_CONFIG_OUTPUT:
2190
+
case PIN_CONFIG_LEVEL:
2191
2191
case PIN_CONFIG_INPUT_ENABLE:
2192
2192
ie = ioread32(bank->base + NPCM8XX_GP_N_IEM) & pinmask;
2193
2193
oe = ioread32(bank->base + NPCM8XX_GP_N_OE) & pinmask;
2194
2194
if (param == PIN_CONFIG_INPUT_ENABLE)
2195
2195
rc = (ie && !oe);
2196
-
else if (param == PIN_CONFIG_OUTPUT)
2196
+
else if (param == PIN_CONFIG_LEVEL)
2197
2197
rc = (!ie && oe);
2198
2198
break;
2199
2199
case PIN_CONFIG_DRIVE_PUSH_PULL:
···
2251
2251
iowrite32(gpio, bank->base + NPCM8XX_GP_N_OEC);
2252
2252
bank->direction_input(&bank->chip.gc, pin % bank->chip.gc.ngpio);
2253
2253
break;
2254
-
case PIN_CONFIG_OUTPUT:
2254
+
case PIN_CONFIG_LEVEL:
2255
2255
bank->direction_output(&bank->chip.gc, pin % bank->chip.gc.ngpio, arg);
2256
2256
iowrite32(gpio, bank->base + NPCM8XX_GP_N_OES);
2257
2257
break;
+3
-3
drivers/pinctrl/pinconf-generic.c
+3
-3
drivers/pinctrl/pinconf-generic.c
···
48
48
PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT_ENABLE, "input schmitt enabled", NULL, false),
49
49
PCONFDUMP(PIN_CONFIG_MODE_LOW_POWER, "pin low power", "mode", true),
50
50
PCONFDUMP(PIN_CONFIG_OUTPUT_ENABLE, "output enabled", NULL, false),
51
-
PCONFDUMP(PIN_CONFIG_OUTPUT, "pin output", "level", true),
51
+
PCONFDUMP(PIN_CONFIG_LEVEL, "pin output", "level", true),
52
52
PCONFDUMP(PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS, "output impedance", "ohms", true),
53
53
PCONFDUMP(PIN_CONFIG_POWER_SOURCE, "pin power source", "selector", true),
54
54
PCONFDUMP(PIN_CONFIG_SLEEP_HARDWARE_STATE, "sleep hardware state", NULL, false),
···
183
183
{ "low-power-enable", PIN_CONFIG_MODE_LOW_POWER, 1 },
184
184
{ "output-disable", PIN_CONFIG_OUTPUT_ENABLE, 0 },
185
185
{ "output-enable", PIN_CONFIG_OUTPUT_ENABLE, 1 },
186
-
{ "output-high", PIN_CONFIG_OUTPUT, 1, },
186
+
{ "output-high", PIN_CONFIG_LEVEL, 1, },
187
187
{ "output-impedance-ohms", PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS, 0 },
188
-
{ "output-low", PIN_CONFIG_OUTPUT, 0, },
188
+
{ "output-low", PIN_CONFIG_LEVEL, 0, },
189
189
{ "power-source", PIN_CONFIG_POWER_SOURCE, 0 },
190
190
{ "sleep-hardware-state", PIN_CONFIG_SLEEP_HARDWARE_STATE, 0 },
191
191
{ "slew-rate", PIN_CONFIG_SLEW_RATE, 0 },
+1
-1
drivers/pinctrl/pinctrl-at91-pio4.c
+1
-1
drivers/pinctrl/pinctrl-at91-pio4.c
+3
-3
drivers/pinctrl/pinctrl-aw9523.c
+3
-3
drivers/pinctrl/pinctrl-aw9523.c
···
215
215
case PIN_CONFIG_OUTPUT_ENABLE:
216
216
reg = AW9523_REG_CONF_STATE(pin);
217
217
break;
218
-
case PIN_CONFIG_OUTPUT:
218
+
case PIN_CONFIG_LEVEL:
219
219
reg = AW9523_REG_OUT_STATE(pin);
220
220
break;
221
221
default:
···
249
249
switch (param) {
250
250
case PIN_CONFIG_BIAS_PULL_UP:
251
251
case PIN_CONFIG_INPUT_ENABLE:
252
-
case PIN_CONFIG_OUTPUT:
252
+
case PIN_CONFIG_LEVEL:
253
253
val &= BIT(regbit);
254
254
break;
255
255
case PIN_CONFIG_BIAS_PULL_DOWN:
···
301
301
goto end;
302
302
303
303
switch (param) {
304
-
case PIN_CONFIG_OUTPUT:
304
+
case PIN_CONFIG_LEVEL:
305
305
/* First, enable pin output */
306
306
rc = regmap_update_bits(awi->regmap,
307
307
AW9523_REG_CONF_STATE(pin),
+1
-1
drivers/pinctrl/pinctrl-cy8c95x0.c
+1
-1
drivers/pinctrl/pinctrl-cy8c95x0.c
+2
-2
drivers/pinctrl/pinctrl-ingenic.c
+2
-2
drivers/pinctrl/pinctrl-ingenic.c
···
4264
4264
case PIN_CONFIG_BIAS_PULL_UP:
4265
4265
case PIN_CONFIG_BIAS_PULL_DOWN:
4266
4266
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
4267
-
case PIN_CONFIG_OUTPUT:
4267
+
case PIN_CONFIG_LEVEL:
4268
4268
case PIN_CONFIG_SLEW_RATE:
4269
4269
continue;
4270
4270
default:
···
4305
4305
ingenic_set_schmitt_trigger(jzpc, pin, arg);
4306
4306
break;
4307
4307
4308
-
case PIN_CONFIG_OUTPUT:
4308
+
case PIN_CONFIG_LEVEL:
4309
4309
ret = pinctrl_gpio_direction_output(jzpc->gc,
4310
4310
pin - jzpc->gc->base);
4311
4311
if (ret)
+1
-1
drivers/pinctrl/pinctrl-k210.c
+1
-1
drivers/pinctrl/pinctrl-k210.c
+2
-2
drivers/pinctrl/pinctrl-microchip-sgpio.c
+2
-2
drivers/pinctrl/pinctrl-microchip-sgpio.c
···
371
371
val = !bank->is_input;
372
372
break;
373
373
374
-
case PIN_CONFIG_OUTPUT:
374
+
case PIN_CONFIG_LEVEL:
375
375
if (bank->is_input)
376
376
return -EINVAL;
377
377
val = sgpio_output_get(priv, &addr);
···
402
402
arg = pinconf_to_config_argument(configs[cfg]);
403
403
404
404
switch (param) {
405
-
case PIN_CONFIG_OUTPUT:
405
+
case PIN_CONFIG_LEVEL:
406
406
if (bank->is_input)
407
407
return -EINVAL;
408
408
err = sgpio_output_set(priv, &addr, arg);
+2
-2
drivers/pinctrl/pinctrl-ocelot.c
+2
-2
drivers/pinctrl/pinctrl-ocelot.c
···
1656
1656
return err;
1657
1657
break;
1658
1658
1659
-
case PIN_CONFIG_OUTPUT:
1659
+
case PIN_CONFIG_LEVEL:
1660
1660
err = regmap_read(info->map, REG(OCELOT_GPIO_OUT, info, pin),
1661
1661
&val);
1662
1662
if (err)
···
1735
1735
1736
1736
case PIN_CONFIG_OUTPUT_ENABLE:
1737
1737
case PIN_CONFIG_INPUT_ENABLE:
1738
-
case PIN_CONFIG_OUTPUT:
1738
+
case PIN_CONFIG_LEVEL:
1739
1739
p = pin % 32;
1740
1740
if (arg)
1741
1741
regmap_write(info->map,
+2
-2
drivers/pinctrl/pinctrl-pic32.c
+2
-2
drivers/pinctrl/pinctrl-pic32.c
···
1905
1905
case PIN_CONFIG_INPUT_ENABLE:
1906
1906
arg = !!(readl(bank->reg_base + TRIS_REG) & mask);
1907
1907
break;
1908
-
case PIN_CONFIG_OUTPUT:
1908
+
case PIN_CONFIG_LEVEL:
1909
1909
arg = !(readl(bank->reg_base + TRIS_REG) & mask);
1910
1910
break;
1911
1911
default:
···
1960
1960
case PIN_CONFIG_INPUT_ENABLE:
1961
1961
pic32_gpio_direction_input(&bank->gpio_chip, offset);
1962
1962
break;
1963
-
case PIN_CONFIG_OUTPUT:
1963
+
case PIN_CONFIG_LEVEL:
1964
1964
pic32_gpio_direction_output(&bank->gpio_chip,
1965
1965
offset, arg);
1966
1966
break;
+2
-2
drivers/pinctrl/pinctrl-rk805.c
+2
-2
drivers/pinctrl/pinctrl-rk805.c
···
541
541
u32 arg = 0;
542
542
543
543
switch (param) {
544
-
case PIN_CONFIG_OUTPUT:
544
+
case PIN_CONFIG_LEVEL:
545
545
case PIN_CONFIG_INPUT_ENABLE:
546
546
arg = rk805_gpio_get(&pci->gpio_chip, pin);
547
547
break;
···
568
568
arg = pinconf_to_config_argument(configs[i]);
569
569
570
570
switch (param) {
571
-
case PIN_CONFIG_OUTPUT:
571
+
case PIN_CONFIG_LEVEL:
572
572
rk805_gpio_set(&pci->gpio_chip, pin, arg);
573
573
rk805_pmx_gpio_set_direction(pctldev, NULL, pin, false);
574
574
break;
+3
-3
drivers/pinctrl/pinctrl-rockchip.c
+3
-3
drivers/pinctrl/pinctrl-rockchip.c
···
3272
3272
param = pinconf_to_config_param(configs[i]);
3273
3273
arg = pinconf_to_config_argument(configs[i]);
3274
3274
3275
-
if (param == PIN_CONFIG_OUTPUT || param == PIN_CONFIG_INPUT_ENABLE) {
3275
+
if (param == PIN_CONFIG_LEVEL || param == PIN_CONFIG_INPUT_ENABLE) {
3276
3276
/*
3277
3277
* Check for gpio driver not being probed yet.
3278
3278
* The lock makes sure that either gpio-probe has completed
···
3313
3313
if (rc)
3314
3314
return rc;
3315
3315
break;
3316
-
case PIN_CONFIG_OUTPUT:
3316
+
case PIN_CONFIG_LEVEL:
3317
3317
rc = rockchip_set_mux(bank, pin - bank->pin_base,
3318
3318
RK_FUNC_GPIO);
3319
3319
if (rc != RK_FUNC_GPIO)
···
3392
3392
3393
3393
arg = 1;
3394
3394
break;
3395
-
case PIN_CONFIG_OUTPUT:
3395
+
case PIN_CONFIG_LEVEL:
3396
3396
rc = rockchip_get_mux(bank, pin - bank->pin_base);
3397
3397
if (rc != RK_FUNC_GPIO)
3398
3398
return -EINVAL;
+1
-1
drivers/pinctrl/pinctrl-rp1.c
+1
-1
drivers/pinctrl/pinctrl-rp1.c
+1
-1
drivers/pinctrl/pinctrl-scmi.c
+1
-1
drivers/pinctrl/pinctrl-scmi.c
+2
-2
drivers/pinctrl/pinctrl-stmfx.c
+2
-2
drivers/pinctrl/pinctrl-stmfx.c
···
267
267
if ((!dir && !type) || (dir && type))
268
268
arg = 1;
269
269
break;
270
-
case PIN_CONFIG_OUTPUT:
270
+
case PIN_CONFIG_LEVEL:
271
271
if (dir)
272
272
return -EINVAL;
273
273
···
334
334
if (ret)
335
335
return ret;
336
336
break;
337
-
case PIN_CONFIG_OUTPUT:
337
+
case PIN_CONFIG_LEVEL:
338
338
ret = stmfx_gpio_direction_output(&pctl->gpio_chip,
339
339
pin, arg);
340
340
if (ret)
+4
-4
drivers/pinctrl/pinctrl-sx150x.c
+4
-4
drivers/pinctrl/pinctrl-sx150x.c
···
611
611
if (sx150x_pin_is_oscio(pctl, pin)) {
612
612
switch (param) {
613
613
case PIN_CONFIG_DRIVE_PUSH_PULL:
614
-
case PIN_CONFIG_OUTPUT:
614
+
case PIN_CONFIG_LEVEL:
615
615
ret = regmap_read(pctl->regmap,
616
616
pctl->data->pri.x789.reg_clock,
617
617
&data);
···
705
705
}
706
706
break;
707
707
708
-
case PIN_CONFIG_OUTPUT:
708
+
case PIN_CONFIG_LEVEL:
709
709
ret = sx150x_gpio_get_direction(&pctl->gpio, pin);
710
710
if (ret < 0)
711
711
return ret;
···
744
744
arg = pinconf_to_config_argument(configs[i]);
745
745
746
746
if (sx150x_pin_is_oscio(pctl, pin)) {
747
-
if (param == PIN_CONFIG_OUTPUT) {
747
+
if (param == PIN_CONFIG_LEVEL) {
748
748
ret = sx150x_gpio_direction_output(&pctl->gpio,
749
749
pin, arg);
750
750
if (ret < 0)
···
816
816
817
817
break;
818
818
819
-
case PIN_CONFIG_OUTPUT:
819
+
case PIN_CONFIG_LEVEL:
820
820
ret = sx150x_gpio_direction_output(&pctl->gpio,
821
821
pin, arg);
822
822
if (ret < 0)
+4
-4
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
+4
-4
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
···
174
174
arg = 1;
175
175
break;
176
176
case PIN_CONFIG_INPUT_ENABLE:
177
-
case PIN_CONFIG_OUTPUT:
177
+
case PIN_CONFIG_LEVEL:
178
178
if (is_out)
179
179
arg = 1;
180
180
break;
···
252
252
case PIN_CONFIG_INPUT_ENABLE:
253
253
output_enabled = false;
254
254
break;
255
-
case PIN_CONFIG_OUTPUT:
255
+
case PIN_CONFIG_LEVEL:
256
256
output_enabled = true;
257
257
value = arg;
258
258
break;
···
314
314
struct lpi_pinctrl *state = gpiochip_get_data(chip);
315
315
unsigned long config;
316
316
317
-
config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
317
+
config = pinconf_to_config_packed(PIN_CONFIG_LEVEL, val);
318
318
319
319
return lpi_config_set(state->ctrl, pin, &config, 1);
320
320
}
···
332
332
struct lpi_pinctrl *state = gpiochip_get_data(chip);
333
333
unsigned long config;
334
334
335
-
config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
335
+
config = pinconf_to_config_packed(PIN_CONFIG_LEVEL, value);
336
336
337
337
return lpi_config_set(state->ctrl, pin, &config, 1);
338
338
}
+3
-3
drivers/pinctrl/qcom/pinctrl-msm.c
+3
-3
drivers/pinctrl/qcom/pinctrl-msm.c
···
295
295
*bit = g->drv_bit;
296
296
*mask = 7;
297
297
break;
298
-
case PIN_CONFIG_OUTPUT:
298
+
case PIN_CONFIG_LEVEL:
299
299
case PIN_CONFIG_INPUT_ENABLE:
300
300
case PIN_CONFIG_OUTPUT_ENABLE:
301
301
*bit = g->oe_bit;
···
385
385
case PIN_CONFIG_DRIVE_STRENGTH:
386
386
arg = msm_regval_to_drive(arg);
387
387
break;
388
-
case PIN_CONFIG_OUTPUT:
388
+
case PIN_CONFIG_LEVEL:
389
389
/* Pin is not output */
390
390
if (!arg)
391
391
return -EINVAL;
···
464
464
else
465
465
arg = (arg / 2) - 1;
466
466
break;
467
-
case PIN_CONFIG_OUTPUT:
467
+
case PIN_CONFIG_LEVEL:
468
468
/* set output value */
469
469
raw_spin_lock_irqsave(&pctrl->lock, flags);
470
470
val = msm_readl_io(pctrl, g);
+4
-4
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
+4
-4
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
···
438
438
case PIN_CONFIG_OUTPUT_ENABLE:
439
439
arg = pad->output_enabled;
440
440
break;
441
-
case PIN_CONFIG_OUTPUT:
441
+
case PIN_CONFIG_LEVEL:
442
442
arg = pad->out_value;
443
443
break;
444
444
case PMIC_GPIO_CONF_PULL_UP:
···
530
530
case PIN_CONFIG_OUTPUT_ENABLE:
531
531
pad->output_enabled = arg ? true : false;
532
532
break;
533
-
case PIN_CONFIG_OUTPUT:
533
+
case PIN_CONFIG_LEVEL:
534
534
pad->output_enabled = true;
535
535
pad->out_value = arg;
536
536
break;
···
737
737
struct pmic_gpio_state *state = gpiochip_get_data(chip);
738
738
unsigned long config;
739
739
740
-
config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
740
+
config = pinconf_to_config_packed(PIN_CONFIG_LEVEL, val);
741
741
742
742
return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
743
743
}
···
769
769
struct pmic_gpio_state *state = gpiochip_get_data(chip);
770
770
unsigned long config;
771
771
772
-
config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
772
+
config = pinconf_to_config_packed(PIN_CONFIG_LEVEL, value);
773
773
774
774
return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
775
775
}
+4
-4
drivers/pinctrl/qcom/pinctrl-spmi-mpp.c
+4
-4
drivers/pinctrl/qcom/pinctrl-spmi-mpp.c
···
370
370
return -EINVAL;
371
371
arg = 1;
372
372
break;
373
-
case PIN_CONFIG_OUTPUT:
373
+
case PIN_CONFIG_LEVEL:
374
374
arg = pad->out_value;
375
375
break;
376
376
case PMIC_MPP_CONF_DTEST_SELECTOR:
···
447
447
case PIN_CONFIG_INPUT_ENABLE:
448
448
pad->input_enabled = arg ? true : false;
449
449
break;
450
-
case PIN_CONFIG_OUTPUT:
450
+
case PIN_CONFIG_LEVEL:
451
451
pad->output_enabled = true;
452
452
pad->out_value = arg;
453
453
break;
···
576
576
struct pmic_mpp_state *state = gpiochip_get_data(chip);
577
577
unsigned long config;
578
578
579
-
config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
579
+
config = pinconf_to_config_packed(PIN_CONFIG_LEVEL, val);
580
580
581
581
return pmic_mpp_config_set(state->ctrl, pin, &config, 1);
582
582
}
···
605
605
struct pmic_mpp_state *state = gpiochip_get_data(chip);
606
606
unsigned long config;
607
607
608
-
config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
608
+
config = pinconf_to_config_packed(PIN_CONFIG_LEVEL, value);
609
609
610
610
return pmic_mpp_config_set(state->ctrl, pin, &config, 1);
611
611
}
+2
-2
drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c
+2
-2
drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c
···
282
282
return -EINVAL;
283
283
arg = 1;
284
284
break;
285
-
case PIN_CONFIG_OUTPUT:
285
+
case PIN_CONFIG_LEVEL:
286
286
if (pin->mode & PM8XXX_GPIO_MODE_OUTPUT)
287
287
arg = pin->output_value;
288
288
else
···
364
364
pin->mode = PM8XXX_GPIO_MODE_INPUT;
365
365
banks |= BIT(0) | BIT(1);
366
366
break;
367
-
case PIN_CONFIG_OUTPUT:
367
+
case PIN_CONFIG_LEVEL:
368
368
pin->mode = PM8XXX_GPIO_MODE_OUTPUT;
369
369
pin->output_value = !!arg;
370
370
banks |= BIT(0) | BIT(1);
+2
-2
drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c
+2
-2
drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c
···
337
337
case PIN_CONFIG_INPUT_ENABLE:
338
338
arg = pin->input;
339
339
break;
340
-
case PIN_CONFIG_OUTPUT:
340
+
case PIN_CONFIG_LEVEL:
341
341
arg = pin->output_value;
342
342
break;
343
343
case PIN_CONFIG_POWER_SOURCE:
···
392
392
case PIN_CONFIG_INPUT_ENABLE:
393
393
pin->input = true;
394
394
break;
395
-
case PIN_CONFIG_OUTPUT:
395
+
case PIN_CONFIG_LEVEL:
396
396
pin->output = true;
397
397
pin->output_value = !!arg;
398
398
break;
+1
-1
drivers/pinctrl/renesas/pinctrl-rza1.c
+1
-1
drivers/pinctrl/renesas/pinctrl-rza1.c
···
933
933
case PIN_CONFIG_INPUT_ENABLE:
934
934
pinmux_flags |= MUX_FLAGS_SWIO_INPUT;
935
935
break;
936
-
case PIN_CONFIG_OUTPUT: /* for DT backwards compatibility */
936
+
case PIN_CONFIG_LEVEL: /* for DT backwards compatibility */
937
937
case PIN_CONFIG_OUTPUT_ENABLE:
938
938
pinmux_flags |= MUX_FLAGS_SWIO_OUTPUT;
939
939
break;
+1
-1
drivers/pinctrl/stm32/pinctrl-stm32.c
+1
-1
drivers/pinctrl/stm32/pinctrl-stm32.c
···
1236
1236
case PIN_CONFIG_BIAS_PULL_DOWN:
1237
1237
ret = stm32_pconf_set_bias(bank, offset, 2);
1238
1238
break;
1239
-
case PIN_CONFIG_OUTPUT:
1239
+
case PIN_CONFIG_LEVEL:
1240
1240
__stm32_gpio_set(bank, offset, arg);
1241
1241
ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false);
1242
1242
break;
+2
-2
drivers/pinctrl/sunplus/sppctl.c
+2
-2
drivers/pinctrl/sunplus/sppctl.c
···
488
488
case PIN_CONFIG_INPUT_ENABLE:
489
489
break;
490
490
491
-
case PIN_CONFIG_OUTPUT:
491
+
case PIN_CONFIG_LEVEL:
492
492
return sppctl_gpio_direction_output(chip, offset, 0);
493
493
494
494
case PIN_CONFIG_PERSIST_STATE:
···
580
580
arg = 0;
581
581
break;
582
582
583
-
case PIN_CONFIG_OUTPUT:
583
+
case PIN_CONFIG_LEVEL:
584
584
if (!sppctl_first_get(&pctl->spp_gchip->chip, pin))
585
585
return -EINVAL;
586
586
if (!sppctl_master_get(&pctl->spp_gchip->chip, pin))
+8
-4
include/linux/pinctrl/pinconf-generic.h
+8
-4
include/linux/pinctrl/pinconf-generic.h
···
88
88
* passed in the argument on a custom form, else just use argument 1
89
89
* to indicate low power mode, argument 0 turns low power mode off.
90
90
* @PIN_CONFIG_MODE_PWM: this will configure the pin for PWM
91
-
* @PIN_CONFIG_OUTPUT: this will configure the pin as an output and drive a
92
-
* value on the line. Use argument 1 to indicate high level, argument 0 to
93
-
* indicate low level. (Please see Documentation/driver-api/pin-control.rst,
91
+
* @PIN_CONFIG_LEVEL: setting this will configure the pin as an output and
92
+
* drive a value on the line. Use argument 1 to indicate high level,
93
+
* argument 0 to indicate low level. Conversely the value of the line
94
+
* can be read using this parameter, if and only if that value can be
95
+
* represented as a binary 0 or 1 where 0 indicate a low voltage level
96
+
* and 1 indicate a high voltage level.
97
+
* (Please see Documentation/driver-api/pin-control.rst,
94
98
* section "GPIO mode pitfalls" for a discussion around this parameter.)
95
99
* @PIN_CONFIG_OUTPUT_ENABLE: this will enable the pin's output mode
96
100
* without driving a value there. For most platforms this reduces to
···
141
137
PIN_CONFIG_INPUT_SCHMITT_UV,
142
138
PIN_CONFIG_MODE_LOW_POWER,
143
139
PIN_CONFIG_MODE_PWM,
144
-
PIN_CONFIG_OUTPUT,
140
+
PIN_CONFIG_LEVEL,
145
141
PIN_CONFIG_OUTPUT_ENABLE,
146
142
PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS,
147
143
PIN_CONFIG_PERSIST_STATE,