Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"A handful of fixes. I've been queuing them up a bit too long so the
list is longer than it otherwise would have been spread out across a
few -rcs.
In general, it's a scattering of fixes across several platforms,
nothing truly serious enough to point out.
There's a slightly larger batch of them for the Davinci platforms due
to work to bring them back to life after some time, so there's a
handful of regressions, some of them going back very far, others more
recent.
There's also a few patches fixing DT on Renesas platforms since they
changed some bindings without remaining backwards compatible,
splitting up describing LVDS as a proper bridge instead of having it
as part of the display unit.
We could push for them to be backwards compatible with old device
trees, but it's likely to regress eventually if nobody's actually
using said compatibility"
* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (36 commits)
ARM: davinci: board-dm646x-evm: set VPIF capture card name
ARM: davinci: board-dm646x-evm: pass correct I2C adapter id for VPIF
ARM: davinci: dm646x: fix timer interrupt generation
ARM: keystone: fix platform_domain_notifier array overrun
arm64: dts: exynos: Fix interrupt type for I2S1 device on Exynos5433
ARM: dts: imx51-zii-rdu1: fix touchscreen bindings
firmware: arm_scmi: Use after free in scmi_create_protocol_device()
ARM: dts: cygnus: fix irq type for arm global timer
Revert "ARM: dts: logicpd-som-lv: Fix pinmux controller references"
tee: check shm references are consistent in offset/size
tee: shm: fix use-after-free via temporarily dropped reference
ARM: dts: imx7s: Pass the 'fsl,sec-era' property
ARM: dts: tegra20: Revert "Fix ULPI regression on Tegra20"
ARM: dts: correct missing "compatible" entry for ti81xx SoCs
ARM: OMAP1: ams-delta: fix deferred_fiq handler
arm64: tegra: Make BCM89610 PHY interrupt as active low
ARM: davinci: fix GPIO lookup for I2C
ARM: dts: logicpd-som-lv: Fix pinmux controller references
ARM: dts: logicpd-som-lv: Fix Audio Mute
ARM: dts: logicpd-som-lv: Fix WL127x Startup Issues
...
+299
-95
+5
-4
Documentation/devicetree/bindings/net/marvell-pp2.txt
+5
-4
Documentation/devicetree/bindings/net/marvell-pp2.txt
···
21
21
- main controller clock (for both armada-375-pp2 and armada-7k-pp2)
22
22
- GOP clock (for both armada-375-pp2 and armada-7k-pp2)
23
23
- MG clock (only for armada-7k-pp2)
24
+
- MG Core clock (only for armada-7k-pp2)
24
25
- AXI clock (only for armada-7k-pp2)
25
-
- clock-names: names of used clocks, must be "pp_clk", "gop_clk", "mg_clk"
26
-
and "axi_clk" (the 2 latter only for armada-7k-pp2).
26
+
- clock-names: names of used clocks, must be "pp_clk", "gop_clk", "mg_clk",
27
+
"mg_core_clk" and "axi_clk" (the 3 latter only for armada-7k-pp2).
27
28
28
29
The ethernet ports are represented by subnodes. At least one port is
29
30
required.
···
81
80
compatible = "marvell,armada-7k-pp22";
82
81
reg = <0x0 0x100000>, <0x129000 0xb000>;
83
82
clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>,
84
-
<&cpm_syscon0 1 5>, <&cpm_syscon0 1 18>;
85
-
clock-names = "pp_clk", "gop_clk", "gp_clk", "axi_clk";
83
+
<&cpm_syscon0 1 5>, <&cpm_syscon0 1 6>, <&cpm_syscon0 1 18>;
84
+
clock-names = "pp_clk", "gop_clk", "mg_clk", "mg_core_clk", "axi_clk";
86
85
87
86
eth0: eth0 {
88
87
interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
+1
-1
arch/arm/boot/dts/bcm-cygnus.dtsi
+1
-1
arch/arm/boot/dts/bcm-cygnus.dtsi
+2
-2
arch/arm/boot/dts/da850-lcdk.dts
+2
-2
arch/arm/boot/dts/da850-lcdk.dts
+10
-3
arch/arm/boot/dts/da850.dtsi
+10
-3
arch/arm/boot/dts/da850.dtsi
···
7
7
* Free Software Foundation; either version 2 of the License, or (at your
8
8
* option) any later version.
9
9
*/
10
-
#include "skeleton.dtsi"
11
10
#include <dt-bindings/interrupt-controller/irq.h>
12
11
13
12
/ {
13
+
#address-cells = <1>;
14
+
#size-cells = <1>;
15
+
chosen { };
16
+
aliases { };
17
+
18
+
memory@c0000000 {
19
+
device_type = "memory";
20
+
reg = <0xc0000000 0x0>;
21
+
};
22
+
14
23
arm {
15
24
#address-cells = <1>;
16
25
#size-cells = <1>;
···
55
46
pmx_core: pinmux@14120 {
56
47
compatible = "pinctrl-single";
57
48
reg = <0x14120 0x50>;
58
-
#address-cells = <1>;
59
-
#size-cells = <0>;
60
49
#pinctrl-cells = <2>;
61
50
pinctrl-single,bit-per-mux;
62
51
pinctrl-single,register-width = <32>;
+1
-1
arch/arm/boot/dts/dm8148-evm.dts
+1
-1
arch/arm/boot/dts/dm8148-evm.dts
+1
-1
arch/arm/boot/dts/dm8148-t410.dts
+1
-1
arch/arm/boot/dts/dm8148-t410.dts
+1
-1
arch/arm/boot/dts/dm8168-evm.dts
+1
-1
arch/arm/boot/dts/dm8168-evm.dts
+1
-1
arch/arm/boot/dts/dra62x-j5eco-evm.dts
+1
-1
arch/arm/boot/dts/dra62x-j5eco-evm.dts
+3
-3
arch/arm/boot/dts/imx51-zii-rdu1.dts
+3
-3
arch/arm/boot/dts/imx51-zii-rdu1.dts
···
523
523
};
524
524
525
525
touchscreen@20 {
526
-
compatible = "syna,rmi4_i2c";
526
+
compatible = "syna,rmi4-i2c";
527
527
reg = <0x20>;
528
528
pinctrl-names = "default";
529
529
pinctrl-0 = <&pinctrl_ts>;
···
541
541
542
542
rmi4-f11@11 {
543
543
reg = <0x11>;
544
-
touch-inverted-y;
545
-
touch-swapped-x-y;
544
+
touchscreen-inverted-y;
545
+
touchscreen-swapped-x-y;
546
546
syna,sensor-type = <1>;
547
547
};
548
548
};
+1
arch/arm/boot/dts/imx7s.dtsi
+1
arch/arm/boot/dts/imx7s.dtsi
+9
-2
arch/arm/boot/dts/logicpd-som-lv.dtsi
+9
-2
arch/arm/boot/dts/logicpd-som-lv.dtsi
···
26
26
gpio = <&gpio1 3 0>; /* gpio_3 */
27
27
startup-delay-us = <70000>;
28
28
enable-active-high;
29
-
vin-supply = <&vmmc2>;
29
+
vin-supply = <&vaux3>;
30
30
};
31
31
32
32
/* HS USB Host PHY on PORT 1 */
···
82
82
twl_audio: audio {
83
83
compatible = "ti,twl4030-audio";
84
84
codec {
85
+
ti,hs_extmute_gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>;
85
86
};
86
87
};
87
88
};
···
200
199
pinctrl-single,pins = <
201
200
OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
202
201
OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
202
+
OMAP3_CORE1_IOPAD(0x20ba, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs6.gpio_57 */
203
203
>;
204
204
};
205
205
};
···
215
213
};
216
214
wl127x_gpio: pinmux_wl127x_gpio_pin {
217
215
pinctrl-single,pins = <
218
-
OMAP3_WKUP_IOPAD(0x2a0c, PIN_INPUT | MUX_MODE4) /* sys_boot0.gpio_2 */
216
+
OMAP3_WKUP_IOPAD(0x2a0a, PIN_INPUT | MUX_MODE4) /* sys_boot0.gpio_2 */
219
217
OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */
220
218
>;
221
219
};
···
261
259
262
260
#include "twl4030.dtsi"
263
261
#include "twl4030_omap3.dtsi"
262
+
263
+
&vaux3 {
264
+
regulator-min-microvolt = <2800000>;
265
+
regulator-max-microvolt = <2800000>;
266
+
};
264
267
265
268
&twl {
266
269
twl_power: power {
+17
-5
arch/arm/boot/dts/r8a7790-lager.dts
+17
-5
arch/arm/boot/dts/r8a7790-lager.dts
···
379
379
port@0 {
380
380
reg = <0>;
381
381
adv7511_in: endpoint {
382
-
remote-endpoint = <&du_out_lvds0>;
382
+
remote-endpoint = <&lvds0_out>;
383
383
};
384
384
};
385
385
···
467
467
status = "okay";
468
468
469
469
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>,
470
-
<&cpg CPG_MOD 726>, <&cpg CPG_MOD 725>,
471
470
<&x13_clk>, <&x2_clk>;
472
-
clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1",
473
-
"dclkin.0", "dclkin.1";
471
+
clock-names = "du.0", "du.1", "du.2", "dclkin.0", "dclkin.1";
474
472
475
473
ports {
476
474
port@0 {
···
476
478
remote-endpoint = <&adv7123_in>;
477
479
};
478
480
};
481
+
};
482
+
};
483
+
484
+
&lvds0 {
485
+
status = "okay";
486
+
487
+
ports {
479
488
port@1 {
480
489
endpoint {
481
490
remote-endpoint = <&adv7511_in>;
482
491
};
483
492
};
484
-
port@2 {
493
+
};
494
+
};
495
+
496
+
&lvds1 {
497
+
status = "okay";
498
+
499
+
ports {
500
+
port@1 {
485
501
lvds_connector: endpoint {
486
502
};
487
503
};
+57
-8
arch/arm/boot/dts/r8a7790.dtsi
+57
-8
arch/arm/boot/dts/r8a7790.dtsi
···
1627
1627
1628
1628
du: display@feb00000 {
1629
1629
compatible = "renesas,du-r8a7790";
1630
-
reg = <0 0xfeb00000 0 0x70000>,
1631
-
<0 0xfeb90000 0 0x1c>,
1632
-
<0 0xfeb94000 0 0x1c>;
1633
-
reg-names = "du", "lvds.0", "lvds.1";
1630
+
reg = <0 0xfeb00000 0 0x70000>;
1634
1631
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1635
1632
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
1636
1633
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
1637
1634
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
1638
-
<&cpg CPG_MOD 722>, <&cpg CPG_MOD 726>,
1639
-
<&cpg CPG_MOD 725>;
1640
-
clock-names = "du.0", "du.1", "du.2", "lvds.0",
1641
-
"lvds.1";
1635
+
<&cpg CPG_MOD 722>;
1636
+
clock-names = "du.0", "du.1", "du.2";
1642
1637
status = "disabled";
1643
1638
1644
1639
ports {
···
1648
1653
port@1 {
1649
1654
reg = <1>;
1650
1655
du_out_lvds0: endpoint {
1656
+
remote-endpoint = <&lvds0_in>;
1651
1657
};
1652
1658
};
1653
1659
port@2 {
1654
1660
reg = <2>;
1655
1661
du_out_lvds1: endpoint {
1662
+
remote-endpoint = <&lvds1_in>;
1663
+
};
1664
+
};
1665
+
};
1666
+
};
1667
+
1668
+
lvds0: lvds@feb90000 {
1669
+
compatible = "renesas,r8a7790-lvds";
1670
+
reg = <0 0xfeb90000 0 0x1c>;
1671
+
clocks = <&cpg CPG_MOD 726>;
1672
+
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1673
+
resets = <&cpg 726>;
1674
+
status = "disabled";
1675
+
1676
+
ports {
1677
+
#address-cells = <1>;
1678
+
#size-cells = <0>;
1679
+
1680
+
port@0 {
1681
+
reg = <0>;
1682
+
lvds0_in: endpoint {
1683
+
remote-endpoint = <&du_out_lvds0>;
1684
+
};
1685
+
};
1686
+
port@1 {
1687
+
reg = <1>;
1688
+
lvds0_out: endpoint {
1689
+
};
1690
+
};
1691
+
};
1692
+
};
1693
+
1694
+
lvds1: lvds@feb94000 {
1695
+
compatible = "renesas,r8a7790-lvds";
1696
+
reg = <0 0xfeb94000 0 0x1c>;
1697
+
clocks = <&cpg CPG_MOD 725>;
1698
+
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1699
+
resets = <&cpg 725>;
1700
+
status = "disabled";
1701
+
1702
+
ports {
1703
+
#address-cells = <1>;
1704
+
#size-cells = <0>;
1705
+
1706
+
port@0 {
1707
+
reg = <0>;
1708
+
lvds1_in: endpoint {
1709
+
remote-endpoint = <&du_out_lvds1>;
1710
+
};
1711
+
};
1712
+
port@1 {
1713
+
reg = <1>;
1714
+
lvds1_out: endpoint {
1656
1715
};
1657
1716
};
1658
1717
};
+9
-3
arch/arm/boot/dts/r8a7791-koelsch.dts
+9
-3
arch/arm/boot/dts/r8a7791-koelsch.dts
···
468
468
pinctrl-names = "default";
469
469
status = "okay";
470
470
471
-
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>,
471
+
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
472
472
<&x13_clk>, <&x2_clk>;
473
-
clock-names = "du.0", "du.1", "lvds.0",
474
-
"dclkin.0", "dclkin.1";
473
+
clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
475
474
476
475
ports {
477
476
port@0 {
···
478
479
remote-endpoint = <&adv7511_in>;
479
480
};
480
481
};
482
+
};
483
+
};
484
+
485
+
&lvds0 {
486
+
status = "okay";
487
+
488
+
ports {
481
489
port@1 {
482
490
lvds_connector: endpoint {
483
491
};
+13
-3
arch/arm/boot/dts/r8a7791-porter.dts
+13
-3
arch/arm/boot/dts/r8a7791-porter.dts
···
441
441
pinctrl-names = "default";
442
442
status = "okay";
443
443
444
-
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>,
444
+
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
445
445
<&x3_clk>, <&x16_clk>;
446
-
clock-names = "du.0", "du.1", "lvds.0",
447
-
"dclkin.0", "dclkin.1";
446
+
clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
448
447
449
448
ports {
450
449
port@0 {
451
450
endpoint {
452
451
remote-endpoint = <&adv7511_in>;
452
+
};
453
+
};
454
+
};
455
+
};
456
+
457
+
&lvds0 {
458
+
status = "okay";
459
+
460
+
ports {
461
+
port@1 {
462
+
lvds_connector: endpoint {
453
463
};
454
464
};
455
465
};
+30
-6
arch/arm/boot/dts/r8a7791.dtsi
+30
-6
arch/arm/boot/dts/r8a7791.dtsi
···
1633
1633
1634
1634
du: display@feb00000 {
1635
1635
compatible = "renesas,du-r8a7791";
1636
-
reg = <0 0xfeb00000 0 0x40000>,
1637
-
<0 0xfeb90000 0 0x1c>;
1638
-
reg-names = "du", "lvds.0";
1636
+
reg = <0 0xfeb00000 0 0x40000>;
1639
1637
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1640
1638
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
1641
1639
clocks = <&cpg CPG_MOD 724>,
1642
-
<&cpg CPG_MOD 723>,
1643
-
<&cpg CPG_MOD 726>;
1644
-
clock-names = "du.0", "du.1", "lvds.0";
1640
+
<&cpg CPG_MOD 723>;
1641
+
clock-names = "du.0", "du.1";
1645
1642
status = "disabled";
1646
1643
1647
1644
ports {
···
1653
1656
port@1 {
1654
1657
reg = <1>;
1655
1658
du_out_lvds0: endpoint {
1659
+
remote-endpoint = <&lvds0_in>;
1660
+
};
1661
+
};
1662
+
};
1663
+
};
1664
+
1665
+
lvds0: lvds@feb90000 {
1666
+
compatible = "renesas,r8a7791-lvds";
1667
+
reg = <0 0xfeb90000 0 0x1c>;
1668
+
clocks = <&cpg CPG_MOD 726>;
1669
+
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1670
+
resets = <&cpg 726>;
1671
+
status = "disabled";
1672
+
1673
+
ports {
1674
+
#address-cells = <1>;
1675
+
#size-cells = <0>;
1676
+
1677
+
port@0 {
1678
+
reg = <0>;
1679
+
lvds0_in: endpoint {
1680
+
remote-endpoint = <&du_out_lvds0>;
1681
+
};
1682
+
};
1683
+
port@1 {
1684
+
reg = <1>;
1685
+
lvds0_out: endpoint {
1656
1686
};
1657
1687
};
1658
1688
};
+7
-3
arch/arm/boot/dts/r8a7793-gose.dts
+7
-3
arch/arm/boot/dts/r8a7793-gose.dts
···
447
447
pinctrl-names = "default";
448
448
status = "okay";
449
449
450
-
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>,
450
+
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
451
451
<&x13_clk>, <&x2_clk>;
452
-
clock-names = "du.0", "du.1", "lvds.0",
453
-
"dclkin.0", "dclkin.1";
452
+
clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
454
453
455
454
ports {
456
455
port@0 {
···
457
458
remote-endpoint = <&adv7511_in>;
458
459
};
459
460
};
461
+
};
462
+
};
463
+
464
+
&lvds0 {
465
+
ports {
460
466
port@1 {
461
467
lvds_connector: endpoint {
462
468
};
+31
-6
arch/arm/boot/dts/r8a7793.dtsi
+31
-6
arch/arm/boot/dts/r8a7793.dtsi
···
1292
1292
1293
1293
du: display@feb00000 {
1294
1294
compatible = "renesas,du-r8a7793";
1295
-
reg = <0 0xfeb00000 0 0x40000>,
1296
-
<0 0xfeb90000 0 0x1c>;
1297
-
reg-names = "du", "lvds.0";
1295
+
reg = <0 0xfeb00000 0 0x40000>;
1298
1296
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1299
1297
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
1300
1298
clocks = <&cpg CPG_MOD 724>,
1301
-
<&cpg CPG_MOD 723>,
1302
-
<&cpg CPG_MOD 726>;
1303
-
clock-names = "du.0", "du.1", "lvds.0";
1299
+
<&cpg CPG_MOD 723>;
1300
+
clock-names = "du.0", "du.1";
1304
1301
status = "disabled";
1305
1302
1306
1303
ports {
···
1312
1315
port@1 {
1313
1316
reg = <1>;
1314
1317
du_out_lvds0: endpoint {
1318
+
remote-endpoint = <&lvds0_in>;
1319
+
};
1320
+
};
1321
+
};
1322
+
};
1323
+
1324
+
lvds0: lvds@feb90000 {
1325
+
compatible = "renesas,r8a7793-lvds";
1326
+
reg = <0 0xfeb90000 0 0x1c>;
1327
+
clocks = <&cpg CPG_MOD 726>;
1328
+
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1329
+
resets = <&cpg 726>;
1330
+
1331
+
status = "disabled";
1332
+
1333
+
ports {
1334
+
#address-cells = <1>;
1335
+
#size-cells = <0>;
1336
+
1337
+
port@0 {
1338
+
reg = <0>;
1339
+
lvds0_in: endpoint {
1340
+
remote-endpoint = <&du_out_lvds0>;
1341
+
};
1342
+
};
1343
+
port@1 {
1344
+
reg = <1>;
1345
+
lvds0_out: endpoint {
1315
1346
};
1316
1347
};
1317
1348
};
+1
-1
arch/arm/boot/dts/tegra20.dtsi
+1
-1
arch/arm/boot/dts/tegra20.dtsi
···
741
741
phy_type = "ulpi";
742
742
clocks = <&tegra_car TEGRA20_CLK_USB2>,
743
743
<&tegra_car TEGRA20_CLK_PLL_U>,
744
-
<&tegra_car TEGRA20_CLK_PLL_P_OUT4>;
744
+
<&tegra_car TEGRA20_CLK_CDEV2>;
745
745
clock-names = "reg", "pll_u", "ulpi-link";
746
746
resets = <&tegra_car 58>, <&tegra_car 22>;
747
747
reset-names = "usb", "utmi-pads";
+7
-2
arch/arm/mach-davinci/board-da830-evm.c
+7
-2
arch/arm/mach-davinci/board-da830-evm.c
···
205
205
-1
206
206
};
207
207
208
+
#define DA830_MMCSD_WP_PIN GPIO_TO_PIN(2, 1)
209
+
#define DA830_MMCSD_CD_PIN GPIO_TO_PIN(2, 2)
210
+
208
211
static struct gpiod_lookup_table mmc_gpios_table = {
209
212
.dev_id = "da830-mmc.0",
210
213
.table = {
211
214
/* gpio chip 1 contains gpio range 32-63 */
212
-
GPIO_LOOKUP("davinci_gpio.1", 2, "cd", GPIO_ACTIVE_LOW),
213
-
GPIO_LOOKUP("davinci_gpio.1", 1, "wp", GPIO_ACTIVE_LOW),
215
+
GPIO_LOOKUP("davinci_gpio.0", DA830_MMCSD_CD_PIN, "cd",
216
+
GPIO_ACTIVE_LOW),
217
+
GPIO_LOOKUP("davinci_gpio.0", DA830_MMCSD_WP_PIN, "wp",
218
+
GPIO_ACTIVE_LOW),
214
219
},
215
220
};
216
221
+7
-2
arch/arm/mach-davinci/board-da850-evm.c
+7
-2
arch/arm/mach-davinci/board-da850-evm.c
···
763
763
-1
764
764
};
765
765
766
+
#define DA850_MMCSD_CD_PIN GPIO_TO_PIN(4, 0)
767
+
#define DA850_MMCSD_WP_PIN GPIO_TO_PIN(4, 1)
768
+
766
769
static struct gpiod_lookup_table mmc_gpios_table = {
767
770
.dev_id = "da830-mmc.0",
768
771
.table = {
769
772
/* gpio chip 2 contains gpio range 64-95 */
770
-
GPIO_LOOKUP("davinci_gpio.2", 0, "cd", GPIO_ACTIVE_LOW),
771
-
GPIO_LOOKUP("davinci_gpio.2", 1, "wp", GPIO_ACTIVE_LOW),
773
+
GPIO_LOOKUP("davinci_gpio.0", DA850_MMCSD_CD_PIN, "cd",
774
+
GPIO_ACTIVE_LOW),
775
+
GPIO_LOOKUP("davinci_gpio.0", DA850_MMCSD_WP_PIN, "wp",
776
+
GPIO_ACTIVE_LOW),
772
777
},
773
778
};
774
779
+12
-3
arch/arm/mach-davinci/board-dm355-evm.c
+12
-3
arch/arm/mach-davinci/board-dm355-evm.c
···
19
19
#include <linux/gpio.h>
20
20
#include <linux/gpio/machine.h>
21
21
#include <linux/clk.h>
22
+
#include <linux/dm9000.h>
22
23
#include <linux/videodev2.h>
23
24
#include <media/i2c/tvp514x.h>
24
25
#include <linux/spi/spi.h>
···
110
109
},
111
110
};
112
111
112
+
#define DM355_I2C_SDA_PIN GPIO_TO_PIN(0, 15)
113
+
#define DM355_I2C_SCL_PIN GPIO_TO_PIN(0, 14)
114
+
113
115
static struct gpiod_lookup_table i2c_recovery_gpiod_table = {
114
-
.dev_id = "i2c_davinci",
116
+
.dev_id = "i2c_davinci.1",
115
117
.table = {
116
-
GPIO_LOOKUP("davinci_gpio", 15, "sda",
118
+
GPIO_LOOKUP("davinci_gpio.0", DM355_I2C_SDA_PIN, "sda",
117
119
GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
118
-
GPIO_LOOKUP("davinci_gpio", 14, "scl",
120
+
GPIO_LOOKUP("davinci_gpio.0", DM355_I2C_SCL_PIN, "scl",
119
121
GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
120
122
},
121
123
};
···
183
179
},
184
180
};
185
181
182
+
static struct dm9000_plat_data dm335evm_dm9000_platdata;
183
+
186
184
static struct platform_device dm355evm_dm9000 = {
187
185
.name = "dm9000",
188
186
.id = -1,
189
187
.resource = dm355evm_dm9000_rsrc,
190
188
.num_resources = ARRAY_SIZE(dm355evm_dm9000_rsrc),
189
+
.dev = {
190
+
.platform_data = &dm335evm_dm9000_platdata,
191
+
},
191
192
};
192
193
193
194
static struct tvp514x_platform_data tvp5146_pdata = {
+7
-3
arch/arm/mach-davinci/board-dm644x-evm.c
+7
-3
arch/arm/mach-davinci/board-dm644x-evm.c
···
17
17
#include <linux/i2c.h>
18
18
#include <linux/platform_data/pcf857x.h>
19
19
#include <linux/platform_data/at24.h>
20
+
#include <linux/platform_data/gpio-davinci.h>
20
21
#include <linux/mtd/mtd.h>
21
22
#include <linux/mtd/rawnand.h>
22
23
#include <linux/mtd/partitions.h>
···
597
596
},
598
597
};
599
598
599
+
#define DM644X_I2C_SDA_PIN GPIO_TO_PIN(2, 12)
600
+
#define DM644X_I2C_SCL_PIN GPIO_TO_PIN(2, 11)
601
+
600
602
static struct gpiod_lookup_table i2c_recovery_gpiod_table = {
601
-
.dev_id = "i2c_davinci",
603
+
.dev_id = "i2c_davinci.1",
602
604
.table = {
603
-
GPIO_LOOKUP("davinci_gpio", 44, "sda",
605
+
GPIO_LOOKUP("davinci_gpio.0", DM644X_I2C_SDA_PIN, "sda",
604
606
GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
605
-
GPIO_LOOKUP("davinci_gpio", 43, "scl",
607
+
GPIO_LOOKUP("davinci_gpio.0", DM644X_I2C_SCL_PIN, "scl",
606
608
GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
607
609
},
608
610
};
+4
-1
arch/arm/mach-davinci/board-dm646x-evm.c
+4
-1
arch/arm/mach-davinci/board-dm646x-evm.c
···
532
532
.set_clock = set_vpif_clock,
533
533
.subdevinfo = dm646x_vpif_subdev,
534
534
.subdev_count = ARRAY_SIZE(dm646x_vpif_subdev),
535
+
.i2c_adapter_id = 1,
535
536
.chan_config[0] = {
536
537
.outputs = dm6467_ch0_outputs,
537
538
.output_count = ARRAY_SIZE(dm6467_ch0_outputs),
538
539
},
539
-
.card_name = "DM646x EVM",
540
+
.card_name = "DM646x EVM Video Display",
540
541
};
541
542
542
543
/**
···
675
674
.setup_input_channel_mode = setup_vpif_input_channel_mode,
676
675
.subdev_info = vpif_capture_sdev_info,
677
676
.subdev_count = ARRAY_SIZE(vpif_capture_sdev_info),
677
+
.i2c_adapter_id = 1,
678
678
.chan_config[0] = {
679
679
.inputs = dm6467_ch0_inputs,
680
680
.input_count = ARRAY_SIZE(dm6467_ch0_inputs),
···
696
694
.fid_pol = 0,
697
695
},
698
696
},
697
+
.card_name = "DM646x EVM Video Capture",
699
698
};
700
699
701
700
static void __init evm_init_video(void)
+7
-3
arch/arm/mach-davinci/board-omapl138-hawk.c
+7
-3
arch/arm/mach-davinci/board-omapl138-hawk.c
···
123
123
-1
124
124
};
125
125
126
+
#define DA850_HAWK_MMCSD_CD_PIN GPIO_TO_PIN(3, 12)
127
+
#define DA850_HAWK_MMCSD_WP_PIN GPIO_TO_PIN(3, 13)
128
+
126
129
static struct gpiod_lookup_table mmc_gpios_table = {
127
130
.dev_id = "da830-mmc.0",
128
131
.table = {
129
-
/* CD: gpio3_12: gpio60: chip 1 contains gpio range 32-63*/
130
-
GPIO_LOOKUP("davinci_gpio.0", 28, "cd", GPIO_ACTIVE_LOW),
131
-
GPIO_LOOKUP("davinci_gpio.0", 29, "wp", GPIO_ACTIVE_LOW),
132
+
GPIO_LOOKUP("davinci_gpio.0", DA850_HAWK_MMCSD_CD_PIN, "cd",
133
+
GPIO_ACTIVE_LOW),
134
+
GPIO_LOOKUP("davinci_gpio.0", DA850_HAWK_MMCSD_WP_PIN, "wp",
135
+
GPIO_ACTIVE_LOW),
132
136
},
133
137
};
134
138
+2
-1
arch/arm/mach-davinci/dm646x.c
+2
-1
arch/arm/mach-davinci/dm646x.c
···
488
488
[IRQ_DM646X_MCASP0TXINT] = 7,
489
489
[IRQ_DM646X_MCASP0RXINT] = 7,
490
490
[IRQ_DM646X_RESERVED_3] = 7,
491
-
[IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */
491
+
[IRQ_DM646X_MCASP1TXINT] = 7,
492
+
[IRQ_TINT0_TINT12] = 7, /* clockevent */
492
493
[IRQ_TINT0_TINT34] = 7, /* clocksource */
493
494
[IRQ_TINT1_TINT12] = 7, /* DSP timer */
494
495
[IRQ_TINT1_TINT34] = 7, /* system tick */
+1
arch/arm/mach-keystone/pm_domain.c
+1
arch/arm/mach-keystone/pm_domain.c
+14
-12
arch/arm/mach-omap1/ams-delta-fiq.c
+14
-12
arch/arm/mach-omap1/ams-delta-fiq.c
···
58
58
irq_num = gpio_to_irq(gpio);
59
59
fiq_count = fiq_buffer[FIQ_CNT_INT_00 + gpio];
60
60
61
-
while (irq_counter[gpio] < fiq_count) {
62
-
if (gpio != AMS_DELTA_GPIO_PIN_KEYBRD_CLK) {
63
-
struct irq_data *d = irq_get_irq_data(irq_num);
61
+
if (irq_counter[gpio] < fiq_count &&
62
+
gpio != AMS_DELTA_GPIO_PIN_KEYBRD_CLK) {
63
+
struct irq_data *d = irq_get_irq_data(irq_num);
64
64
65
-
/*
66
-
* It looks like handle_edge_irq() that
67
-
* OMAP GPIO edge interrupts default to,
68
-
* expects interrupt already unmasked.
69
-
*/
70
-
if (irq_chip && irq_chip->irq_unmask)
65
+
/*
66
+
* handle_simple_irq() that OMAP GPIO edge
67
+
* interrupts default to since commit 80ac93c27441
68
+
* requires interrupt already acked and unmasked.
69
+
*/
70
+
if (irq_chip) {
71
+
if (irq_chip->irq_ack)
72
+
irq_chip->irq_ack(d);
73
+
if (irq_chip->irq_unmask)
71
74
irq_chip->irq_unmask(d);
72
75
}
73
-
generic_handle_irq(irq_num);
74
-
75
-
irq_counter[gpio]++;
76
76
}
77
+
for (; irq_counter[gpio] < fiq_count; irq_counter[gpio]++)
78
+
generic_handle_irq(irq_num);
77
79
}
78
80
return IRQ_HANDLED;
79
81
}
+2
-2
arch/arm/mach-omap2/powerdomain.c
+2
-2
arch/arm/mach-omap2/powerdomain.c
···
188
188
((prev & OMAP_POWERSTATE_MASK) << 0));
189
189
trace_power_domain_target_rcuidle(pwrdm->name,
190
190
trace_state,
191
-
smp_processor_id());
191
+
raw_smp_processor_id());
192
192
}
193
193
break;
194
194
default:
···
518
518
if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst) {
519
519
/* Trace the pwrdm desired target state */
520
520
trace_power_domain_target_rcuidle(pwrdm->name, pwrst,
521
-
smp_processor_id());
521
+
raw_smp_processor_id());
522
522
/* Program the pwrdm desired target state */
523
523
ret = arch_pwrdm->pwrdm_set_next_pwrst(pwrdm, pwrst);
524
524
}
+1
-1
arch/arm64/boot/dts/exynos/exynos5433.dtsi
+1
-1
arch/arm64/boot/dts/exynos/exynos5433.dtsi
···
1317
1317
reg = <0x14d60000 0x100>;
1318
1318
dmas = <&pdma0 31 &pdma0 30>;
1319
1319
dma-names = "tx", "rx";
1320
-
interrupts = <GIC_SPI 435 IRQ_TYPE_NONE>;
1320
+
interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>;
1321
1321
clocks = <&cmu_peric CLK_PCLK_I2S1>,
1322
1322
<&cmu_peric CLK_PCLK_I2S1>,
1323
1323
<&cmu_peric CLK_SCLK_I2S1>;
+5
-2
arch/arm64/boot/dts/marvell/armada-cp110.dtsi
+5
-2
arch/arm64/boot/dts/marvell/armada-cp110.dtsi
···
38
38
compatible = "marvell,armada-7k-pp22";
39
39
reg = <0x0 0x100000>, <0x129000 0xb000>;
40
40
clocks = <&CP110_LABEL(clk) 1 3>, <&CP110_LABEL(clk) 1 9>,
41
-
<&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 18>;
41
+
<&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>,
42
+
<&CP110_LABEL(clk) 1 18>;
42
43
clock-names = "pp_clk", "gop_clk",
43
-
"mg_clk", "axi_clk";
44
+
"mg_clk", "mg_core_clk", "axi_clk";
44
45
marvell,system-controller = <&CP110_LABEL(syscon0)>;
45
46
status = "disabled";
46
47
dma-coherent;
···
142
141
#size-cells = <0>;
143
142
compatible = "marvell,xmdio";
144
143
reg = <0x12a600 0x10>;
144
+
clocks = <&CP110_LABEL(clk) 1 5>,
145
+
<&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>;
145
146
status = "disabled";
146
147
};
147
148
+1
-1
arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
+1
-1
arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
+1
-1
arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
+1
-1
arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
···
414
414
mmc-ddr-1_8v;
415
415
mmc-hs200-1_8v;
416
416
mmc-pwrseq = <&emmc_pwrseq>;
417
-
cdns,phy-input-delay-legacy = <4>;
417
+
cdns,phy-input-delay-legacy = <9>;
418
418
cdns,phy-input-delay-mmc-highspeed = <2>;
419
419
cdns,phy-input-delay-mmc-ddr = <3>;
420
420
cdns,phy-dll-delay-sdclk = <21>;
+8
arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts
+8
arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts
+1
-1
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
+1
-1
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
···
519
519
mmc-ddr-1_8v;
520
520
mmc-hs200-1_8v;
521
521
mmc-pwrseq = <&emmc_pwrseq>;
522
-
cdns,phy-input-delay-legacy = <4>;
522
+
cdns,phy-input-delay-legacy = <9>;
523
523
cdns,phy-input-delay-mmc-highspeed = <2>;
524
524
cdns,phy-input-delay-mmc-ddr = <3>;
525
525
cdns,phy-dll-delay-sdclk = <21>;
+1
-1
arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
+1
-1
arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
···
334
334
mmc-ddr-1_8v;
335
335
mmc-hs200-1_8v;
336
336
mmc-pwrseq = <&emmc_pwrseq>;
337
-
cdns,phy-input-delay-legacy = <4>;
337
+
cdns,phy-input-delay-legacy = <9>;
338
338
cdns,phy-input-delay-mmc-highspeed = <2>;
339
339
cdns,phy-input-delay-mmc-ddr = <3>;
340
340
cdns,phy-dll-delay-sdclk = <21>;
+1
drivers/firmware/arm_scmi/driver.c
+1
drivers/firmware/arm_scmi/driver.c
+3
-3
drivers/reset/reset-uniphier.c
+3
-3
drivers/reset/reset-uniphier.c
···
110
110
UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */
111
111
UNIPHIER_RESETX(6, 0x200c, 6), /* Ether */
112
112
UNIPHIER_RESETX(8, 0x200c, 8), /* STDMAC (HSC) */
113
-
UNIPHIER_RESETX(12, 0x200c, 5), /* GIO (PCIe, USB3) */
113
+
UNIPHIER_RESETX(14, 0x200c, 5), /* USB30 */
114
114
UNIPHIER_RESETX(16, 0x200c, 12), /* USB30-PHY0 */
115
115
UNIPHIER_RESETX(17, 0x200c, 13), /* USB30-PHY1 */
116
116
UNIPHIER_RESETX(18, 0x200c, 14), /* USB30-PHY2 */
···
127
127
UNIPHIER_RESETX(6, 0x200c, 9), /* Ether0 */
128
128
UNIPHIER_RESETX(7, 0x200c, 10), /* Ether1 */
129
129
UNIPHIER_RESETX(8, 0x200c, 12), /* STDMAC */
130
-
UNIPHIER_RESETX(12, 0x200c, 4), /* USB30 link (GIO0) */
131
-
UNIPHIER_RESETX(13, 0x200c, 5), /* USB31 link (GIO1) */
130
+
UNIPHIER_RESETX(12, 0x200c, 4), /* USB30 link */
131
+
UNIPHIER_RESETX(13, 0x200c, 5), /* USB31 link */
132
132
UNIPHIER_RESETX(16, 0x200c, 16), /* USB30-PHY0 */
133
133
UNIPHIER_RESETX(17, 0x200c, 18), /* USB30-PHY1 */
134
134
UNIPHIER_RESETX(18, 0x200c, 20), /* USB30-PHY2 */
+11
drivers/tee/tee_core.c
+11
drivers/tee/tee_core.c
···
238
238
if (IS_ERR(shm))
239
239
return PTR_ERR(shm);
240
240
241
+
/*
242
+
* Ensure offset + size does not overflow offset
243
+
* and does not overflow the size of the referred
244
+
* shared memory object.
245
+
*/
246
+
if ((ip.a + ip.b) < ip.a ||
247
+
(ip.a + ip.b) > shm->size) {
248
+
tee_shm_put(shm);
249
+
return -EINVAL;
250
+
}
251
+
241
252
params[n].u.memref.shm_offs = ip.a;
242
253
params[n].u.memref.size = ip.b;
243
254
params[n].u.memref.shm = shm;
+3
-2
drivers/tee/tee_shm.c
+3
-2
drivers/tee/tee_shm.c