Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-msm-next-2026-01-23' of https://gitlab.freedesktop.org/drm/msm into drm-next
Changes for v6.20
GPU:
- Document a612/RGMU dt bindings
- UBWC 6.0 support (for A840 / Kaanapali)
- a225 support
- Fixes
DPU:
- Switched to use virtual planes by default
- Fixed DSI CMD panels on DPU 3.x
- Rewrote format handling to remove intermediate representation
- Fixed watchdog on DPU 8.x+
- Fixed TE / Vsync source setting on DPU 8.x+
- Added 3D_Mux on SC7280
- Kaanapali platform support
- Fixed UBWC register programming
- Made RM reserve DSPP-enabled mixers for CRTCs with LMs.
- Gamma correction support
DP:
- Enabled support for eDP 1.4+ link rate tables
- Fixed MDSS1 DP indices on SA8775P, making them to work
- Fixed msm_dp_ctrl_config_msa() to work with LLVM 20
DSI:
- Documented QCS8300 as compatible with SA8775P
- Kaanapali platform support
DSI PHY:
- switched to divider_determine_rate()
MDP5:
- Dropped support for MSM8998, SDM660 and SDM630 (switched over
to DPU)
MDSS:
- Kaanapali platform support
- Fixed UBWC register programming
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Rob Clark <rob.clark@oss.qualcomm.com>
Link: https://patch.msgid.link/CACSVV03Sbeca93A+gGh-TKpzFYVabbkWVgPCCicG0_NQG+5Y2A@mail.gmail.com
+2783
-2258
+7
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
+7
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
···
15
15
- items:
16
16
- enum:
17
17
- qcom,apq8064-dsi-ctrl
18
+
- qcom,kaanapali-dsi-ctrl
18
19
- qcom,msm8226-dsi-ctrl
19
20
- qcom,msm8916-dsi-ctrl
20
21
- qcom,msm8953-dsi-ctrl
···
45
44
- qcom,sm8550-dsi-ctrl
46
45
- qcom,sm8650-dsi-ctrl
47
46
- qcom,sm8750-dsi-ctrl
47
+
- const: qcom,mdss-dsi-ctrl
48
+
- items:
49
+
- enum:
50
+
- qcom,qcs8300-dsi-ctrl
51
+
- const: qcom,sa8775p-dsi-ctrl
48
52
- const: qcom,mdss-dsi-ctrl
49
53
- enum:
50
54
- qcom,dsi-ctrl-6g-qcm2290
···
375
369
compatible:
376
370
contains:
377
371
enum:
372
+
- qcom,kaanapali-dsi-ctrl
378
373
- qcom,sm8750-dsi-ctrl
379
374
then:
380
375
properties:
+19
-12
Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
+19
-12
Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
···
14
14
15
15
properties:
16
16
compatible:
17
-
enum:
18
-
- qcom,dsi-phy-7nm
19
-
- qcom,dsi-phy-7nm-8150
20
-
- qcom,sa8775p-dsi-phy-5nm
21
-
- qcom,sar2130p-dsi-phy-5nm
22
-
- qcom,sc7280-dsi-phy-7nm
23
-
- qcom,sm6375-dsi-phy-7nm
24
-
- qcom,sm8350-dsi-phy-5nm
25
-
- qcom,sm8450-dsi-phy-5nm
26
-
- qcom,sm8550-dsi-phy-4nm
27
-
- qcom,sm8650-dsi-phy-4nm
28
-
- qcom,sm8750-dsi-phy-3nm
17
+
oneOf:
18
+
- items:
19
+
- enum:
20
+
- qcom,dsi-phy-7nm
21
+
- qcom,dsi-phy-7nm-8150
22
+
- qcom,kaanapali-dsi-phy-3nm
23
+
- qcom,sa8775p-dsi-phy-5nm
24
+
- qcom,sar2130p-dsi-phy-5nm
25
+
- qcom,sc7280-dsi-phy-7nm
26
+
- qcom,sm6375-dsi-phy-7nm
27
+
- qcom,sm8350-dsi-phy-5nm
28
+
- qcom,sm8450-dsi-phy-5nm
29
+
- qcom,sm8550-dsi-phy-4nm
30
+
- qcom,sm8650-dsi-phy-4nm
31
+
- qcom,sm8750-dsi-phy-3nm
32
+
- items:
33
+
- enum:
34
+
- qcom,qcs8300-dsi-phy-5nm
35
+
- const: qcom,sa8775p-dsi-phy-5nm
29
36
30
37
reg:
31
38
items:
+60
-21
Documentation/devicetree/bindings/display/msm/gpu.yaml
+60
-21
Documentation/devicetree/bindings/display/msm/gpu.yaml
···
45
45
- const: amd,imageon
46
46
47
47
clocks:
48
-
minItems: 2
48
+
minItems: 1
49
49
maxItems: 7
50
50
51
51
clock-names:
52
-
minItems: 2
52
+
minItems: 1
53
53
maxItems: 7
54
54
55
55
reg:
···
378
378
- const: xo
379
379
description: GPUCC clocksource clock
380
380
381
+
required:
382
+
- clocks
383
+
- clock-names
384
+
385
+
- if:
386
+
properties:
387
+
compatible:
388
+
contains:
389
+
const: qcom,adreno-612.0
390
+
then:
391
+
properties:
392
+
clocks:
393
+
items:
394
+
- description: GPU Core clock
395
+
396
+
clock-names:
397
+
items:
398
+
- const: core
399
+
400
+
reg:
401
+
minItems: 3
402
+
maxItems: 3
403
+
381
404
reg-names:
382
-
minItems: 1
383
405
items:
384
406
- const: kgsl_3d0_reg_memory
407
+
- const: cx_mem
385
408
- const: cx_dbgc
386
409
387
410
required:
388
411
- clocks
389
412
- clock-names
390
-
else:
391
-
if:
392
-
properties:
393
-
compatible:
394
-
contains:
395
-
oneOf:
396
-
- pattern: '^qcom,adreno-[67][0-9][0-9]\.[0-9]+$'
397
-
- pattern: '^qcom,adreno-[0-9a-f]{8}$'
398
413
399
-
then: # Starting with A6xx, the clocks are usually defined in the GMU node
400
-
properties:
401
-
clocks: false
402
-
clock-names: false
414
+
- if:
415
+
properties:
416
+
compatible:
417
+
contains:
418
+
enum:
419
+
- qcom,adreno-615.0
420
+
- qcom,adreno-618.0
421
+
- qcom,adreno-619.0
422
+
- qcom,adreno-621.0
423
+
- qcom,adreno-623.0
424
+
- qcom,adreno-630.2
425
+
- qcom,adreno-635.0
426
+
- qcom,adreno-640.1
427
+
- qcom,adreno-650.2
428
+
- qcom,adreno-660.1
429
+
- qcom,adreno-663.0
430
+
- qcom,adreno-680.1
431
+
- qcom,adreno-690.0
432
+
- qcom,adreno-730.1
433
+
- qcom,adreno-43030c00
434
+
- qcom,adreno-43050a01
435
+
- qcom,adreno-43050c01
436
+
- qcom,adreno-43051401
403
437
404
-
reg-names:
405
-
minItems: 1
406
-
items:
407
-
- const: kgsl_3d0_reg_memory
408
-
- const: cx_mem
409
-
- const: cx_dbgc
438
+
then: # Starting with A6xx, the clocks are usually defined in the GMU node
439
+
properties:
440
+
clocks: false
441
+
clock-names: false
442
+
443
+
reg-names:
444
+
minItems: 1
445
+
items:
446
+
- const: kgsl_3d0_reg_memory
447
+
- const: cx_mem
448
+
- const: cx_dbgc
410
449
411
450
examples:
412
451
- |
+126
Documentation/devicetree/bindings/display/msm/qcom,adreno-rgmu.yaml
+126
Documentation/devicetree/bindings/display/msm/qcom,adreno-rgmu.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
3
+
%YAML 1.2
4
+
---
5
+
6
+
$id: http://devicetree.org/schemas/display/msm/qcom,adreno-rgmu.yaml#
7
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
8
+
9
+
title: RGMU attached to certain Adreno GPUs
10
+
11
+
maintainers:
12
+
- Rob Clark <robin.clark@oss.qualcomm.com>
13
+
14
+
description:
15
+
RGMU (Reduced Graphics Management Unit) IP is present in some GPUs that
16
+
belong to Adreno A6xx family. It is a small state machine that helps to
17
+
toggle the GX GDSC (connected to CX rail) to implement IFPC feature and save
18
+
power.
19
+
20
+
properties:
21
+
compatible:
22
+
items:
23
+
- const: qcom,adreno-rgmu-612.0
24
+
- const: qcom,adreno-rgmu
25
+
26
+
reg:
27
+
items:
28
+
- description: Core RGMU registers
29
+
30
+
clocks:
31
+
items:
32
+
- description: GMU clock
33
+
- description: GPU CX clock
34
+
- description: GPU AXI clock
35
+
- description: GPU MEMNOC clock
36
+
- description: GPU SMMU vote clock
37
+
38
+
clock-names:
39
+
items:
40
+
- const: gmu
41
+
- const: cxo
42
+
- const: axi
43
+
- const: memnoc
44
+
- const: smmu_vote
45
+
46
+
power-domains:
47
+
items:
48
+
- description: CX GDSC power domain
49
+
- description: GX GDSC power domain
50
+
51
+
power-domain-names:
52
+
items:
53
+
- const: cx
54
+
- const: gx
55
+
56
+
interrupts:
57
+
items:
58
+
- description: GMU OOB interrupt
59
+
- description: GMU interrupt
60
+
61
+
interrupt-names:
62
+
items:
63
+
- const: oob
64
+
- const: gmu
65
+
66
+
operating-points-v2: true
67
+
opp-table:
68
+
type: object
69
+
70
+
required:
71
+
- compatible
72
+
- reg
73
+
- clocks
74
+
- clock-names
75
+
- power-domains
76
+
- power-domain-names
77
+
- interrupts
78
+
- interrupt-names
79
+
- operating-points-v2
80
+
81
+
additionalProperties: false
82
+
83
+
examples:
84
+
- |
85
+
#include <dt-bindings/clock/qcom,qcs615-gpucc.h>
86
+
#include <dt-bindings/clock/qcom,qcs615-gcc.h>
87
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
88
+
#include <dt-bindings/power/qcom,rpmhpd.h>
89
+
90
+
gmu@506a000 {
91
+
compatible = "qcom,adreno-rgmu-612.0", "qcom,adreno-rgmu";
92
+
93
+
reg = <0x05000000 0x90000>;
94
+
95
+
clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
96
+
<&gpucc GPU_CC_CXO_CLK>,
97
+
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
98
+
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
99
+
<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
100
+
clock-names = "gmu",
101
+
"cxo",
102
+
"axi",
103
+
"memnoc",
104
+
"smmu_vote";
105
+
106
+
power-domains = <&gpucc CX_GDSC>,
107
+
<&gpucc GX_GDSC>;
108
+
power-domain-names = "cx",
109
+
"gx";
110
+
111
+
interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
112
+
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
113
+
interrupt-names = "oob",
114
+
"gmu";
115
+
116
+
operating-points-v2 = <&gmu_opp_table>;
117
+
118
+
gmu_opp_table: opp-table {
119
+
compatible = "operating-points-v2";
120
+
121
+
opp-200000000 {
122
+
opp-hz = /bits/ 64 <200000000>;
123
+
required-opps = <&rpmhpd_opp_low_svs>;
124
+
};
125
+
};
126
+
};
+297
Documentation/devicetree/bindings/display/msm/qcom,kaanapali-mdss.yaml
+297
Documentation/devicetree/bindings/display/msm/qcom,kaanapali-mdss.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/display/msm/qcom,kaanapali-mdss.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Kaanapali Display MDSS
8
+
9
+
maintainers:
10
+
- Yongxing Mou <yongxing.mou@oss.qualcomm.com>
11
+
- Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
12
+
13
+
description:
14
+
Kaanapali MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks
15
+
like DPU display controller, DSI and DP interfaces etc.
16
+
17
+
$ref: /schemas/display/msm/mdss-common.yaml#
18
+
19
+
properties:
20
+
compatible:
21
+
const: qcom,kaanapali-mdss
22
+
23
+
clocks:
24
+
items:
25
+
- description: Display AHB
26
+
- description: Display hf AXI
27
+
- description: Display core
28
+
- description: Display AHB SWI
29
+
30
+
iommus:
31
+
maxItems: 1
32
+
33
+
interconnects:
34
+
items:
35
+
- description: Interconnect path from mdp0 port to the data bus
36
+
- description: Interconnect path from CPU to the reg bus
37
+
38
+
interconnect-names:
39
+
items:
40
+
- const: mdp0-mem
41
+
- const: cpu-cfg
42
+
43
+
patternProperties:
44
+
"^display-controller@[0-9a-f]+$":
45
+
type: object
46
+
additionalProperties: true
47
+
properties:
48
+
compatible:
49
+
const: qcom,kaanapali-dpu
50
+
51
+
"^dsi@[0-9a-f]+$":
52
+
type: object
53
+
additionalProperties: true
54
+
properties:
55
+
compatible:
56
+
contains:
57
+
const: qcom,kaanapali-dsi-ctrl
58
+
59
+
"^phy@[0-9a-f]+$":
60
+
type: object
61
+
additionalProperties: true
62
+
properties:
63
+
compatible:
64
+
const: qcom,kaanapali-dsi-phy-3nm
65
+
66
+
required:
67
+
- compatible
68
+
69
+
unevaluatedProperties: false
70
+
71
+
examples:
72
+
- |
73
+
#include <dt-bindings/clock/qcom,rpmh.h>
74
+
#include <dt-bindings/interconnect/qcom,icc.h>
75
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
76
+
#include <dt-bindings/phy/phy-qcom-qmp.h>
77
+
#include <dt-bindings/power/qcom,rpmhpd.h>
78
+
79
+
display-subsystem@9800000 {
80
+
compatible = "qcom,kaanapali-mdss";
81
+
reg = <0x09800000 0x1000>;
82
+
reg-names = "mdss";
83
+
84
+
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
85
+
86
+
clocks = <&disp_cc_mdss_ahb_clk>,
87
+
<&gcc_disp_hf_axi_clk>,
88
+
<&disp_cc_mdss_mdp_clk>,
89
+
<&disp_cc_mdss_ahb_swi_clk>;
90
+
resets = <&disp_cc_mdss_core_bcr>;
91
+
92
+
power-domains = <&mdss_gdsc>;
93
+
94
+
iommus = <&apps_smmu 0x800 0x2>;
95
+
96
+
interrupt-controller;
97
+
#interrupt-cells = <1>;
98
+
99
+
#address-cells = <1>;
100
+
#size-cells = <1>;
101
+
ranges;
102
+
103
+
display-controller@9801000 {
104
+
compatible = "qcom,kaanapali-dpu";
105
+
reg = <0x09801000 0x1c8000>,
106
+
<0x09b16000 0x3000>;
107
+
reg-names = "mdp",
108
+
"vbif";
109
+
110
+
interrupts-extended = <&mdss 0>;
111
+
112
+
clocks = <&gcc_disp_hf_axi_clk>,
113
+
<&disp_cc_mdss_ahb_clk>,
114
+
<&disp_cc_mdss_mdp_lut_clk>,
115
+
<&disp_cc_mdss_mdp_clk>,
116
+
<&disp_cc_mdss_vsync_clk>;
117
+
clock-names = "nrt_bus",
118
+
"iface",
119
+
"lut",
120
+
"core",
121
+
"vsync";
122
+
123
+
assigned-clocks = <&disp_cc_mdss_vsync_clk>;
124
+
assigned-clock-rates = <19200000>;
125
+
126
+
operating-points-v2 = <&mdp_opp_table>;
127
+
128
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
129
+
130
+
ports {
131
+
#address-cells = <1>;
132
+
#size-cells = <0>;
133
+
134
+
port@0 {
135
+
reg = <0>;
136
+
137
+
dpu_intf1_out: endpoint {
138
+
remote-endpoint = <&mdss_dsi0_in>;
139
+
};
140
+
};
141
+
142
+
port@1 {
143
+
reg = <1>;
144
+
145
+
dpu_intf2_out: endpoint {
146
+
remote-endpoint = <&mdss_dsi1_in>;
147
+
};
148
+
};
149
+
};
150
+
151
+
mdp_opp_table: opp-table {
152
+
compatible = "operating-points-v2";
153
+
154
+
opp-156000000 {
155
+
opp-hz = /bits/ 64 <156000000>;
156
+
required-opps = <&rpmhpd_opp_low_svs_d1>;
157
+
};
158
+
159
+
opp-207000000 {
160
+
opp-hz = /bits/ 64 <207000000>;
161
+
required-opps = <&rpmhpd_opp_low_svs>;
162
+
};
163
+
164
+
opp-337000000 {
165
+
opp-hz = /bits/ 64 <337000000>;
166
+
required-opps = <&rpmhpd_opp_svs>;
167
+
};
168
+
169
+
opp-417000000 {
170
+
opp-hz = /bits/ 64 <417000000>;
171
+
required-opps = <&rpmhpd_opp_svs_l1>;
172
+
};
173
+
174
+
opp-532000000 {
175
+
opp-hz = /bits/ 64 <532000000>;
176
+
required-opps = <&rpmhpd_opp_nom>;
177
+
};
178
+
179
+
opp-600000000 {
180
+
opp-hz = /bits/ 64 <600000000>;
181
+
required-opps = <&rpmhpd_opp_nom_l1>;
182
+
};
183
+
184
+
opp-650000000 {
185
+
opp-hz = /bits/ 64 <650000000>;
186
+
required-opps = <&rpmhpd_opp_turbo>;
187
+
};
188
+
};
189
+
};
190
+
191
+
dsi@9ac0000 {
192
+
compatible = "qcom,kaanapali-dsi-ctrl", "qcom,mdss-dsi-ctrl";
193
+
reg = <0x09ac0000 0x1000>;
194
+
reg-names = "dsi_ctrl";
195
+
196
+
interrupts-extended = <&mdss 4>;
197
+
198
+
clocks = <&disp_cc_mdss_byte0_clk>,
199
+
<&disp_cc_mdss_byte0_intf_clk>,
200
+
<&disp_cc_mdss_pclk0_clk>,
201
+
<&disp_cc_mdss_esc0_clk>,
202
+
<&disp_cc_mdss_ahb_clk>,
203
+
<&gcc_disp_hf_axi_clk>,
204
+
<&mdss_dsi0_phy 1>,
205
+
<&mdss_dsi0_phy 0>,
206
+
<&disp_cc_esync0_clk>,
207
+
<&disp_cc_osc_clk>,
208
+
<&disp_cc_mdss_byte0_clk_src>,
209
+
<&disp_cc_mdss_pclk0_clk_src>;
210
+
clock-names = "byte",
211
+
"byte_intf",
212
+
"pixel",
213
+
"core",
214
+
"iface",
215
+
"bus",
216
+
"dsi_pll_pixel",
217
+
"dsi_pll_byte",
218
+
"esync",
219
+
"osc",
220
+
"byte_src",
221
+
"pixel_src";
222
+
223
+
operating-points-v2 = <&mdss_dsi_opp_table>;
224
+
225
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
226
+
227
+
phys = <&mdss_dsi0_phy>;
228
+
phy-names = "dsi";
229
+
230
+
#address-cells = <1>;
231
+
#size-cells = <0>;
232
+
233
+
ports {
234
+
#address-cells = <1>;
235
+
#size-cells = <0>;
236
+
237
+
port@0 {
238
+
reg = <0>;
239
+
240
+
mdss_dsi0_in: endpoint {
241
+
remote-endpoint = <&dpu_intf1_out>;
242
+
};
243
+
};
244
+
245
+
port@1 {
246
+
reg = <1>;
247
+
248
+
mdss_dsi0_out: endpoint {
249
+
remote-endpoint = <&panel0_in>;
250
+
data-lanes = <0 1 2 3>;
251
+
};
252
+
};
253
+
};
254
+
255
+
mdss_dsi_opp_table: opp-table {
256
+
compatible = "operating-points-v2";
257
+
258
+
opp-187500000 {
259
+
opp-hz = /bits/ 64 <187500000>;
260
+
required-opps = <&rpmhpd_opp_low_svs_d1>;
261
+
};
262
+
263
+
opp-250000000 {
264
+
opp-hz = /bits/ 64 <250000000>;
265
+
required-opps = <&rpmhpd_opp_low_svs>;
266
+
};
267
+
268
+
opp-312500000 {
269
+
opp-hz = /bits/ 64 <312500000>;
270
+
required-opps = <&rpmhpd_opp_svs>;
271
+
};
272
+
273
+
opp-358000000 {
274
+
opp-hz = /bits/ 64 <358000000>;
275
+
required-opps = <&rpmhpd_opp_svs_l1>;
276
+
};
277
+
};
278
+
};
279
+
280
+
mdss_dsi0_phy: phy@9ac1000 {
281
+
compatible = "qcom,kaanapali-dsi-phy-3nm";
282
+
reg = <0x09ac1000 0x1cc>,
283
+
<0x09ac1200 0x80>,
284
+
<0x09ac1500 0x400>;
285
+
reg-names = "dsi_phy",
286
+
"dsi_phy_lane",
287
+
"dsi_pll";
288
+
289
+
clocks = <&disp_cc_mdss_ahb_clk>,
290
+
<&rpmhcc RPMH_CXO_CLK>;
291
+
clock-names = "iface",
292
+
"ref";
293
+
294
+
#clock-cells = <1>;
295
+
#phy-cells = <0>;
296
+
};
297
+
};
+101
-1
Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml
+101
-1
Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml
···
53
53
contains:
54
54
const: qcom,qcs8300-dp
55
55
56
+
"^dsi@[0-9a-f]+$":
57
+
type: object
58
+
additionalProperties: true
59
+
properties:
60
+
compatible:
61
+
contains:
62
+
const: qcom,qcs8300-dsi-ctrl
63
+
56
64
"^phy@[0-9a-f]+$":
57
65
type: object
58
66
additionalProperties: true
59
67
properties:
60
68
compatible:
61
69
contains:
62
-
const: qcom,qcs8300-edp-phy
70
+
enum:
71
+
- qcom,qcs8300-dsi-phy-5nm
72
+
- qcom,qcs8300-edp-phy
63
73
64
74
required:
65
75
- compatible
···
81
71
#include <dt-bindings/interconnect/qcom,icc.h>
82
72
#include <dt-bindings/interrupt-controller/arm-gic.h>
83
73
#include <dt-bindings/clock/qcom,qcs8300-gcc.h>
74
+
#include <dt-bindings/clock/qcom,rpmh.h>
84
75
#include <dt-bindings/clock/qcom,sa8775p-dispcc.h>
85
76
#include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h>
86
77
#include <dt-bindings/power/qcom,rpmhpd.h>
···
153
142
remote-endpoint = <&mdss_dp0_in>;
154
143
};
155
144
};
145
+
146
+
port@1 {
147
+
reg = <1>;
148
+
dpu_intf1_out: endpoint {
149
+
remote-endpoint = <&mdss_dsi0_in>;
150
+
};
151
+
};
156
152
};
157
153
158
154
mdp_opp_table: opp-table {
···
185
167
required-opps = <&rpmhpd_opp_turbo_l1>;
186
168
};
187
169
};
170
+
};
171
+
172
+
dsi@ae94000 {
173
+
compatible = "qcom,qcs8300-dsi-ctrl",
174
+
"qcom,sa8775p-dsi-ctrl",
175
+
"qcom,mdss-dsi-ctrl";
176
+
reg = <0x0ae94000 0x400>;
177
+
reg-names = "dsi_ctrl";
178
+
179
+
interrupt-parent = <&mdss>;
180
+
interrupts = <4>;
181
+
182
+
clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK>,
183
+
<&dispcc MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK>,
184
+
<&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK>,
185
+
<&dispcc MDSS_DISP_CC_MDSS_ESC0_CLK>,
186
+
<&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
187
+
<&gcc GCC_DISP_HF_AXI_CLK>;
188
+
clock-names = "byte",
189
+
"byte_intf",
190
+
"pixel",
191
+
"core",
192
+
"iface",
193
+
"bus";
194
+
assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC>,
195
+
<&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC>;
196
+
assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
197
+
phys = <&mdss_dsi0_phy>;
198
+
199
+
operating-points-v2 = <&dsi0_opp_table>;
200
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
201
+
202
+
vdda-supply = <&vreg_l5a>;
203
+
204
+
#address-cells = <1>;
205
+
#size-cells = <0>;
206
+
207
+
ports {
208
+
#address-cells = <1>;
209
+
#size-cells = <0>;
210
+
211
+
port@0 {
212
+
reg = <0>;
213
+
mdss0_dsi0_in: endpoint {
214
+
remote-endpoint = <&dpu_intf1_out>;
215
+
};
216
+
};
217
+
218
+
port@1 {
219
+
reg = <1>;
220
+
mdss0_dsi0_out: endpoint { };
221
+
};
222
+
};
223
+
224
+
dsi0_opp_table: opp-table {
225
+
compatible = "operating-points-v2";
226
+
227
+
opp-358000000 {
228
+
opp-hz = /bits/ 64 <358000000>;
229
+
required-opps = <&rpmhpd_opp_svs_l1>;
230
+
};
231
+
};
232
+
};
233
+
234
+
mdss_dsi0_phy: phy@ae94400 {
235
+
compatible = "qcom,qcs8300-dsi-phy-5nm",
236
+
"qcom,sa8775p-dsi-phy-5nm";
237
+
reg = <0x0ae94400 0x200>,
238
+
<0x0ae94600 0x280>,
239
+
<0x0ae94900 0x27c>;
240
+
reg-names = "dsi_phy",
241
+
"dsi_phy_lane",
242
+
"dsi_pll";
243
+
244
+
#clock-cells = <1>;
245
+
#phy-cells = <0>;
246
+
247
+
clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
248
+
<&rpmhcc RPMH_CXO_CLK>;
249
+
clock-names = "iface", "ref";
250
+
251
+
vdds-supply = <&vreg_l4a>;
188
252
};
189
253
190
254
mdss_dp0_phy: phy@aec2a00 {
+1
Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml
+1
Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml
+1
MAINTAINERS
+1
MAINTAINERS
···
7990
7990
B: https://gitlab.freedesktop.org/drm/msm/-/issues
7991
7991
T: git https://gitlab.freedesktop.org/drm/msm.git
7992
7992
F: Documentation/devicetree/bindings/display/msm/gpu.yaml
7993
+
F: Documentation/devicetree/bindings/display/msm/qcom,adreno-rgmu.yaml
7993
7994
F: Documentation/devicetree/bindings/opp/opp-v2-qcom-adreno.yaml
7994
7995
F: drivers/gpu/drm/msm/adreno/
7995
7996
F: drivers/gpu/drm/msm/msm_gpu.*
+4
drivers/gpu/drm/ci/xfails/msm-sc7180-trogdor-kingoftown-fails.txt
+4
drivers/gpu/drm/ci/xfails/msm-sc7180-trogdor-kingoftown-fails.txt
···
6
6
kms_color@ctm-negative,Fail
7
7
kms_color@ctm-red-to-blue,Fail
8
8
kms_color@ctm-signed,Fail
9
+
kms_color@gamma,Fail
10
+
kms_color@legacy-gamma,Fail
9
11
kms_cursor_legacy@cursor-vs-flip-toggle,Fail
10
12
kms_cursor_legacy@cursor-vs-flip-varying-size,Fail
11
13
kms_flip@flip-vs-modeset-vs-hang,Fail
12
14
kms_flip@flip-vs-panning-vs-hang,Fail
13
15
kms_lease@lease-uevent,Fail
14
16
kms_pipe_crc_basic@compare-crc-sanitycheck-nv12,Fail
17
+
kms_plane@pixel-format,Fail
18
+
kms_plane@pixel-format-source-clamping,Fail
15
19
kms_plane_alpha_blend@alpha-7efc,Fail
16
20
kms_plane_alpha_blend@coverage-7efc,Fail
17
21
kms_plane_alpha_blend@coverage-vs-premult-vs-constant,Fail
+4
drivers/gpu/drm/ci/xfails/msm-sc7180-trogdor-lazor-limozeen-fails.txt
+4
drivers/gpu/drm/ci/xfails/msm-sc7180-trogdor-lazor-limozeen-fails.txt
···
6
6
kms_color@ctm-negative,Fail
7
7
kms_color@ctm-red-to-blue,Fail
8
8
kms_color@ctm-signed,Fail
9
+
kms_color@gamma,Fail
10
+
kms_color@legacy-gamma,Fail
9
11
kms_cursor_legacy@cursor-vs-flip-toggle,Fail
10
12
kms_cursor_legacy@cursor-vs-flip-varying-size,Fail
11
13
kms_flip@flip-vs-modeset-vs-hang,Fail
12
14
kms_flip@flip-vs-panning-vs-hang,Fail
13
15
kms_lease@lease-uevent,Fail
14
16
kms_pipe_crc_basic@compare-crc-sanitycheck-nv12,Fail
17
+
kms_plane@pixel-format,Fail
18
+
kms_plane@pixel-format-source-clamping,Fail
15
19
kms_plane_alpha_blend@alpha-7efc,Fail
16
20
kms_plane_alpha_blend@coverage-7efc,Fail
17
21
kms_plane_alpha_blend@coverage-vs-premult-vs-constant,Fail
+1
drivers/gpu/drm/msm/Makefile
+1
drivers/gpu/drm/msm/Makefile
+12
drivers/gpu/drm/msm/adreno/a2xx_catalog.c
+12
drivers/gpu/drm/msm/adreno/a2xx_catalog.c
···
43
43
.gmem = SZ_512K,
44
44
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
45
45
.funcs = &a2xx_gpu_funcs,
46
+
}, {
47
+
/* Only for msm8960v3, v2 required a special firmware */
48
+
.chip_ids = ADRENO_CHIP_IDS(0x02020506),
49
+
.family = ADRENO_2XX_GEN2,
50
+
.revn = 225,
51
+
.fw = {
52
+
[ADRENO_FW_PM4] = "a225_pm4.fw",
53
+
[ADRENO_FW_PFP] = "a225_pfp.fw",
54
+
},
55
+
.gmem = SZ_512K,
56
+
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
57
+
.funcs = &a2xx_gpu_funcs,
46
58
}
47
59
};
48
60
DECLARE_ADRENO_GPULIST(a2xx);
+4
-1
drivers/gpu/drm/msm/adreno/a2xx_gpu.c
+4
-1
drivers/gpu/drm/msm/adreno/a2xx_gpu.c
···
77
77
78
78
/* Vertex and Pixel Shader Start Addresses in instructions
79
79
* (3 DWORDS per instruction) */
80
-
OUT_RING(ring, 0x80000180);
80
+
if (adreno_is_a225(adreno_gpu))
81
+
OUT_RING(ring, 0x80000300);
82
+
else
83
+
OUT_RING(ring, 0x80000180);
81
84
/* Maximum Contexts */
82
85
OUT_RING(ring, 0x00000001);
83
86
/* Write Confirm Interval and The CP will wait the
+1
-3
drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+1
-3
drivers/gpu/drm/msm/adreno/a6xx_catalog.c
···
501
501
{REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
502
502
{REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
503
503
{REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
504
-
{REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 0x10111},
505
-
{REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, 0x5555},
506
504
{}
507
505
};
508
506
···
1689
1691
{ REG_A7XX_SP_READ_SEL, 0x0001ff00, BIT(PIPE_NONE) },
1690
1692
{ REG_A6XX_TPL1_DBG_ECO_CNTL, 0x10000000, BIT(PIPE_NONE) },
1691
1693
/* BIT(26): Disable final clamp for bicubic filtering */
1692
-
{ REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x00000720, BIT(PIPE_NONE) },
1694
+
{ REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x04000720, BIT(PIPE_NONE) },
1693
1695
{ REG_A6XX_UCHE_MODE_CNTL, 0x80080000, BIT(PIPE_NONE) },
1694
1696
{ REG_A8XX_UCHE_CCHE_MODE_CNTL, 0x00001000, BIT(PIPE_NONE) },
1695
1697
{ REG_A8XX_UCHE_CCHE_CACHE_WAYS, 0x00000800, BIT(PIPE_NONE) },
+6
-8
drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+6
-8
drivers/gpu/drm/msm/adreno/a6xx_gmu.c
···
2029
2029
return 0;
2030
2030
}
2031
2031
2032
-
static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
2033
-
const char *name, resource_size_t *start)
2032
+
static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, resource_size_t *start)
2034
2033
{
2034
+
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2035
2035
void __iomem *ret;
2036
-
struct resource *res = platform_get_resource_byname(pdev,
2037
-
IORESOURCE_MEM, name);
2038
2036
2039
2037
if (!res) {
2040
-
DRM_DEV_ERROR(&pdev->dev, "Unable to find the %s registers\n", name);
2038
+
DRM_DEV_ERROR(&pdev->dev, "Unable to find the gmu core registers\n");
2041
2039
return ERR_PTR(-EINVAL);
2042
2040
}
2043
2041
2044
2042
ret = ioremap(res->start, resource_size(res));
2045
2043
if (!ret) {
2046
-
DRM_DEV_ERROR(&pdev->dev, "Unable to map the %s registers\n", name);
2044
+
DRM_DEV_ERROR(&pdev->dev, "Unable to map the gmu core registers\n");
2047
2045
return ERR_PTR(-EINVAL);
2048
2046
}
2049
2047
···
2083
2085
gmu->nr_clocks = ret;
2084
2086
2085
2087
/* Map the GMU registers */
2086
-
gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu", &start);
2088
+
gmu->mmio = a6xx_gmu_get_mmio(pdev, &start);
2087
2089
if (IS_ERR(gmu->mmio)) {
2088
2090
ret = PTR_ERR(gmu->mmio);
2089
2091
goto err_mmio;
···
2242
2244
goto err_memory;
2243
2245
2244
2246
/* Map the GMU registers */
2245
-
gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu", &start);
2247
+
gmu->mmio = a6xx_gmu_get_mmio(pdev, &start);
2246
2248
if (IS_ERR(gmu->mmio)) {
2247
2249
ret = PTR_ERR(gmu->mmio);
2248
2250
goto err_memory;
+4
drivers/gpu/drm/msm/adreno/a8xx_gpu.c
+4
drivers/gpu/drm/msm/adreno/a8xx_gpu.c
+1
-2
drivers/gpu/drm/msm/adreno/adreno_gpu.c
+1
-2
drivers/gpu/drm/msm/adreno/adreno_gpu.c
+492
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h
+492
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
4
+
*/
5
+
6
+
#ifndef _DPU_13_0_KAANAPALI_H
7
+
#define _DPU_13_0_KAANAPALI_H
8
+
9
+
static const struct dpu_caps kaanapali_dpu_caps = {
10
+
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
11
+
.max_mixer_blendstages = 0xb,
12
+
.has_src_split = true,
13
+
.has_dim_layer = true,
14
+
.has_idle_pc = true,
15
+
.has_3d_merge = true,
16
+
.max_linewidth = 8192,
17
+
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
18
+
};
19
+
20
+
static const struct dpu_mdp_cfg kaanapali_mdp = {
21
+
.name = "top_0",
22
+
.base = 0, .len = 0x494,
23
+
.clk_ctrls = {
24
+
[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
25
+
},
26
+
};
27
+
28
+
static const struct dpu_ctl_cfg kaanapali_ctl[] = {
29
+
{
30
+
.name = "ctl_0", .id = CTL_0,
31
+
.base = 0x1f000, .len = 0x1000,
32
+
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
33
+
}, {
34
+
.name = "ctl_1", .id = CTL_1,
35
+
.base = 0x20000, .len = 0x1000,
36
+
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
37
+
}, {
38
+
.name = "ctl_2", .id = CTL_2,
39
+
.base = 0x21000, .len = 0x1000,
40
+
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
41
+
}, {
42
+
.name = "ctl_3", .id = CTL_3,
43
+
.base = 0x22000, .len = 0x1000,
44
+
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
45
+
}, {
46
+
.name = "ctl_4", .id = CTL_4,
47
+
.base = 0x23000, .len = 0x1000,
48
+
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
49
+
}, {
50
+
.name = "ctl_5", .id = CTL_5,
51
+
.base = 0x24000, .len = 0x1000,
52
+
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
53
+
},
54
+
};
55
+
56
+
static const struct dpu_sspp_cfg kaanapali_sspp[] = {
57
+
{
58
+
.name = "sspp_0", .id = SSPP_VIG0,
59
+
.base = 0x2b000, .len = 0x84,
60
+
.features = VIG_SDM845_MASK_SDMA,
61
+
.sblk = &dpu_vig_sblk_qseed3_3_5,
62
+
.xin_id = 0,
63
+
.type = SSPP_TYPE_VIG,
64
+
}, {
65
+
.name = "sspp_1", .id = SSPP_VIG1,
66
+
.base = 0x34000, .len = 0x84,
67
+
.features = VIG_SDM845_MASK_SDMA,
68
+
.sblk = &dpu_vig_sblk_qseed3_3_5,
69
+
.xin_id = 4,
70
+
.type = SSPP_TYPE_VIG,
71
+
}, {
72
+
.name = "sspp_2", .id = SSPP_VIG2,
73
+
.base = 0x3d000, .len = 0x84,
74
+
.features = VIG_SDM845_MASK_SDMA,
75
+
.sblk = &dpu_vig_sblk_qseed3_3_5,
76
+
.xin_id = 8,
77
+
.type = SSPP_TYPE_VIG,
78
+
}, {
79
+
.name = "sspp_3", .id = SSPP_VIG3,
80
+
.base = 0x46000, .len = 0x84,
81
+
.features = VIG_SDM845_MASK_SDMA,
82
+
.sblk = &dpu_vig_sblk_qseed3_3_5,
83
+
.xin_id = 12,
84
+
.type = SSPP_TYPE_VIG,
85
+
}, {
86
+
.name = "sspp_8", .id = SSPP_DMA0,
87
+
.base = 0x97000, .len = 0x84,
88
+
.features = DMA_SDM845_MASK_SDMA,
89
+
.sblk = &dpu_dma_sblk,
90
+
.xin_id = 1,
91
+
.type = SSPP_TYPE_DMA,
92
+
}, {
93
+
.name = "sspp_9", .id = SSPP_DMA1,
94
+
.base = 0xa0000, .len = 0x84,
95
+
.features = DMA_SDM845_MASK_SDMA,
96
+
.sblk = &dpu_dma_sblk,
97
+
.xin_id = 5,
98
+
.type = SSPP_TYPE_DMA,
99
+
}, {
100
+
.name = "sspp_10", .id = SSPP_DMA2,
101
+
.base = 0xa9000, .len = 0x84,
102
+
.features = DMA_SDM845_MASK_SDMA,
103
+
.sblk = &dpu_dma_sblk,
104
+
.xin_id = 9,
105
+
.type = SSPP_TYPE_DMA,
106
+
}, {
107
+
.name = "sspp_11", .id = SSPP_DMA3,
108
+
.base = 0xb2000, .len = 0x84,
109
+
.features = DMA_SDM845_MASK_SDMA,
110
+
.sblk = &dpu_dma_sblk,
111
+
.xin_id = 13,
112
+
.type = SSPP_TYPE_DMA,
113
+
}, {
114
+
.name = "sspp_12", .id = SSPP_DMA4,
115
+
.base = 0xbb000, .len = 0x84,
116
+
.features = DMA_CURSOR_SDM845_MASK_SDMA,
117
+
.sblk = &dpu_dma_sblk,
118
+
.xin_id = 14,
119
+
.type = SSPP_TYPE_DMA,
120
+
}, {
121
+
.name = "sspp_13", .id = SSPP_DMA5,
122
+
.base = 0xc4000, .len = 0x84,
123
+
.features = DMA_CURSOR_SDM845_MASK_SDMA,
124
+
.sblk = &dpu_dma_sblk,
125
+
.xin_id = 15,
126
+
.type = SSPP_TYPE_DMA,
127
+
},
128
+
};
129
+
130
+
static const struct dpu_lm_cfg kaanapali_lm[] = {
131
+
{
132
+
.name = "lm_0", .id = LM_0,
133
+
.base = 0x103000, .len = 0x400,
134
+
.features = MIXER_MSM8998_MASK,
135
+
.sblk = &sm8750_lm_sblk,
136
+
.lm_pair = LM_1,
137
+
.pingpong = PINGPONG_0,
138
+
.dspp = DSPP_0,
139
+
}, {
140
+
.name = "lm_1", .id = LM_1,
141
+
.base = 0x10b000, .len = 0x400,
142
+
.features = MIXER_MSM8998_MASK,
143
+
.sblk = &sm8750_lm_sblk,
144
+
.lm_pair = LM_0,
145
+
.pingpong = PINGPONG_1,
146
+
.dspp = DSPP_1,
147
+
}, {
148
+
.name = "lm_2", .id = LM_2,
149
+
.base = 0x113000, .len = 0x400,
150
+
.features = MIXER_MSM8998_MASK,
151
+
.sblk = &sm8750_lm_sblk,
152
+
.lm_pair = LM_3,
153
+
.pingpong = PINGPONG_2,
154
+
.dspp = DSPP_2,
155
+
}, {
156
+
.name = "lm_3", .id = LM_3,
157
+
.base = 0x11b000, .len = 0x400,
158
+
.features = MIXER_MSM8998_MASK,
159
+
.sblk = &sm8750_lm_sblk,
160
+
.lm_pair = LM_2,
161
+
.pingpong = PINGPONG_3,
162
+
.dspp = DSPP_3,
163
+
}, {
164
+
.name = "lm_4", .id = LM_4,
165
+
.base = 0x123000, .len = 0x400,
166
+
.features = MIXER_MSM8998_MASK,
167
+
.sblk = &sm8750_lm_sblk,
168
+
.lm_pair = LM_5,
169
+
.pingpong = PINGPONG_4,
170
+
}, {
171
+
.name = "lm_5", .id = LM_5,
172
+
.base = 0x12b000, .len = 0x400,
173
+
.features = MIXER_MSM8998_MASK,
174
+
.sblk = &sm8750_lm_sblk,
175
+
.lm_pair = LM_4,
176
+
.pingpong = PINGPONG_5,
177
+
}, {
178
+
.name = "lm_6", .id = LM_6,
179
+
.base = 0x133000, .len = 0x400,
180
+
.features = MIXER_MSM8998_MASK,
181
+
.sblk = &sm8750_lm_sblk,
182
+
.lm_pair = LM_7,
183
+
.pingpong = PINGPONG_6,
184
+
}, {
185
+
.name = "lm_7", .id = LM_7,
186
+
.base = 0x13b000, .len = 0x400,
187
+
.features = MIXER_MSM8998_MASK,
188
+
.sblk = &sm8750_lm_sblk,
189
+
.lm_pair = LM_6,
190
+
.pingpong = PINGPONG_7,
191
+
},
192
+
};
193
+
194
+
static const struct dpu_dspp_cfg kaanapali_dspp[] = {
195
+
{
196
+
.name = "dspp_0", .id = DSPP_0,
197
+
.base = 0x105000, .len = 0x1800,
198
+
.sblk = &sm8750_dspp_sblk,
199
+
}, {
200
+
.name = "dspp_1", .id = DSPP_1,
201
+
.base = 0x10d000, .len = 0x1800,
202
+
.sblk = &sm8750_dspp_sblk,
203
+
}, {
204
+
.name = "dspp_2", .id = DSPP_2,
205
+
.base = 0x115000, .len = 0x1800,
206
+
.sblk = &sm8750_dspp_sblk,
207
+
}, {
208
+
.name = "dspp_3", .id = DSPP_3,
209
+
.base = 0x11d000, .len = 0x1800,
210
+
.sblk = &sm8750_dspp_sblk,
211
+
},
212
+
};
213
+
214
+
static const struct dpu_pingpong_cfg kaanapali_pp[] = {
215
+
{
216
+
.name = "pingpong_0", .id = PINGPONG_0,
217
+
.base = 0x108000, .len = 0,
218
+
.sblk = &kaanapali_pp_sblk,
219
+
.merge_3d = MERGE_3D_0,
220
+
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
221
+
}, {
222
+
.name = "pingpong_1", .id = PINGPONG_1,
223
+
.base = 0x110000, .len = 0,
224
+
.sblk = &kaanapali_pp_sblk,
225
+
.merge_3d = MERGE_3D_0,
226
+
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
227
+
}, {
228
+
.name = "pingpong_2", .id = PINGPONG_2,
229
+
.base = 0x118000, .len = 0,
230
+
.sblk = &kaanapali_pp_sblk,
231
+
.merge_3d = MERGE_3D_1,
232
+
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
233
+
}, {
234
+
.name = "pingpong_3", .id = PINGPONG_3,
235
+
.base = 0x120000, .len = 0,
236
+
.sblk = &kaanapali_pp_sblk,
237
+
.merge_3d = MERGE_3D_1,
238
+
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
239
+
}, {
240
+
.name = "pingpong_4", .id = PINGPONG_4,
241
+
.base = 0x128000, .len = 0,
242
+
.sblk = &kaanapali_pp_sblk,
243
+
.merge_3d = MERGE_3D_2,
244
+
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
245
+
}, {
246
+
.name = "pingpong_5", .id = PINGPONG_5,
247
+
.base = 0x130000, .len = 0,
248
+
.sblk = &kaanapali_pp_sblk,
249
+
.merge_3d = MERGE_3D_2,
250
+
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
251
+
}, {
252
+
.name = "pingpong_6", .id = PINGPONG_6,
253
+
.base = 0x138000, .len = 0,
254
+
.sblk = &kaanapali_pp_sblk,
255
+
.merge_3d = MERGE_3D_3,
256
+
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 20),
257
+
}, {
258
+
.name = "pingpong_7", .id = PINGPONG_7,
259
+
.base = 0x140000, .len = 0,
260
+
.sblk = &kaanapali_pp_sblk,
261
+
.merge_3d = MERGE_3D_3,
262
+
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 21),
263
+
}, {
264
+
.name = "pingpong_cwb_0", .id = PINGPONG_CWB_0,
265
+
.base = 0x169000, .len = 0,
266
+
.sblk = &kaanapali_pp_sblk,
267
+
.merge_3d = MERGE_3D_4,
268
+
}, {
269
+
.name = "pingpong_cwb_1", .id = PINGPONG_CWB_1,
270
+
.base = 0x169400, .len = 0,
271
+
.sblk = &kaanapali_pp_sblk,
272
+
.merge_3d = MERGE_3D_4,
273
+
}, {
274
+
.name = "pingpong_cwb_2", .id = PINGPONG_CWB_2,
275
+
.base = 0x16a000, .len = 0,
276
+
.sblk = &kaanapali_pp_sblk,
277
+
.merge_3d = MERGE_3D_5,
278
+
}, {
279
+
.name = "pingpong_cwb_3", .id = PINGPONG_CWB_3,
280
+
.base = 0x16a400, .len = 0,
281
+
.sblk = &kaanapali_pp_sblk,
282
+
.merge_3d = MERGE_3D_5,
283
+
},
284
+
};
285
+
286
+
static const struct dpu_merge_3d_cfg kaanapali_merge_3d[] = {
287
+
{
288
+
.name = "merge_3d_0", .id = MERGE_3D_0,
289
+
.base = 0x163000, .len = 0x1c,
290
+
}, {
291
+
.name = "merge_3d_1", .id = MERGE_3D_1,
292
+
.base = 0x164000, .len = 0x1c,
293
+
}, {
294
+
.name = "merge_3d_2", .id = MERGE_3D_2,
295
+
.base = 0x165000, .len = 0x1c,
296
+
}, {
297
+
.name = "merge_3d_3", .id = MERGE_3D_3,
298
+
.base = 0x166000, .len = 0x1c,
299
+
}, {
300
+
.name = "merge_3d_4", .id = MERGE_3D_4,
301
+
.base = 0x169700, .len = 0x1c,
302
+
}, {
303
+
.name = "merge_3d_5", .id = MERGE_3D_5,
304
+
.base = 0x16a700, .len = 0x1c,
305
+
},
306
+
};
307
+
308
+
/*
309
+
* NOTE: Each display compression engine (DCE) contains dual hard
310
+
* slice DSC encoders so both share same base address but with
311
+
* its own different sub block address.
312
+
*/
313
+
static const struct dpu_dsc_cfg kaanapali_dsc[] = {
314
+
{
315
+
.name = "dce_0_0", .id = DSC_0,
316
+
.base = 0x181000, .len = 0x8,
317
+
.features = BIT(DPU_DSC_NATIVE_42x_EN),
318
+
.sblk = &sm8750_dsc_sblk_0,
319
+
}, {
320
+
.name = "dce_0_1", .id = DSC_1,
321
+
.base = 0x181000, .len = 0x8,
322
+
.features = BIT(DPU_DSC_NATIVE_42x_EN),
323
+
.sblk = &sm8750_dsc_sblk_1,
324
+
}, {
325
+
.name = "dce_1_0", .id = DSC_2,
326
+
.base = 0x183000, .len = 0x8,
327
+
.features = BIT(DPU_DSC_NATIVE_42x_EN),
328
+
.sblk = &sm8750_dsc_sblk_0,
329
+
}, {
330
+
.name = "dce_1_1", .id = DSC_3,
331
+
.base = 0x183000, .len = 0x8,
332
+
.features = BIT(DPU_DSC_NATIVE_42x_EN),
333
+
.sblk = &sm8750_dsc_sblk_1,
334
+
}, {
335
+
.name = "dce_2_0", .id = DSC_4,
336
+
.base = 0x185000, .len = 0x8,
337
+
.features = BIT(DPU_DSC_NATIVE_42x_EN),
338
+
.sblk = &sm8750_dsc_sblk_0,
339
+
}, {
340
+
.name = "dce_2_1", .id = DSC_5,
341
+
.base = 0x185000, .len = 0x8,
342
+
.features = BIT(DPU_DSC_NATIVE_42x_EN),
343
+
.sblk = &sm8750_dsc_sblk_1,
344
+
}, {
345
+
.name = "dce_3_0", .id = DSC_6,
346
+
.base = 0x187000, .len = 0x8,
347
+
.features = BIT(DPU_DSC_NATIVE_42x_EN),
348
+
.sblk = &sm8750_dsc_sblk_0,
349
+
}, {
350
+
.name = "dce_3_1", .id = DSC_7,
351
+
.base = 0x187000, .len = 0x8,
352
+
.features = BIT(DPU_DSC_NATIVE_42x_EN),
353
+
.sblk = &sm8750_dsc_sblk_1,
354
+
},
355
+
};
356
+
357
+
static const struct dpu_wb_cfg kaanapali_wb[] = {
358
+
{
359
+
.name = "wb_2", .id = WB_2,
360
+
.base = 0x16e000, .len = 0x2c8,
361
+
.features = WB_SDM845_MASK,
362
+
.format_list = wb2_formats_rgb_yuv,
363
+
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
364
+
.xin_id = 6,
365
+
.vbif_idx = VBIF_RT,
366
+
.maxlinewidth = 4096,
367
+
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
368
+
},
369
+
};
370
+
371
+
static const struct dpu_cwb_cfg kaanapali_cwb[] = {
372
+
{
373
+
.name = "cwb_0", .id = CWB_0,
374
+
.base = 0x169200, .len = 0x20,
375
+
},
376
+
{
377
+
.name = "cwb_1", .id = CWB_1,
378
+
.base = 0x169600, .len = 0x20,
379
+
},
380
+
{
381
+
.name = "cwb_2", .id = CWB_2,
382
+
.base = 0x16a200, .len = 0x20,
383
+
},
384
+
{
385
+
.name = "cwb_3", .id = CWB_3,
386
+
.base = 0x16a600, .len = 0x20,
387
+
},
388
+
};
389
+
390
+
static const struct dpu_intf_cfg kaanapali_intf[] = {
391
+
{
392
+
.name = "intf_0", .id = INTF_0,
393
+
.base = 0x18d000, .len = 0x4bc,
394
+
.type = INTF_DP,
395
+
.controller_id = MSM_DP_CONTROLLER_0,
396
+
.prog_fetch_lines_worst_case = 24,
397
+
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
398
+
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
399
+
}, {
400
+
.name = "intf_1", .id = INTF_1,
401
+
.base = 0x18e000, .len = 0x4bc,
402
+
.type = INTF_DSI,
403
+
.controller_id = MSM_DSI_CONTROLLER_0,
404
+
.prog_fetch_lines_worst_case = 24,
405
+
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
406
+
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
407
+
.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
408
+
}, {
409
+
.name = "intf_2", .id = INTF_2,
410
+
.base = 0x18f000, .len = 0x4bc,
411
+
.type = INTF_DSI,
412
+
.controller_id = MSM_DSI_CONTROLLER_1,
413
+
.prog_fetch_lines_worst_case = 24,
414
+
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
415
+
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
416
+
.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
417
+
}, {
418
+
.name = "intf_3", .id = INTF_3,
419
+
.base = 0x190000, .len = 0x4bc,
420
+
.type = INTF_DP,
421
+
.controller_id = MSM_DP_CONTROLLER_1,
422
+
.prog_fetch_lines_worst_case = 24,
423
+
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
424
+
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
425
+
},
426
+
};
427
+
428
+
static const struct dpu_perf_cfg kaanapali_perf_data = {
429
+
.max_bw_low = 21400000,
430
+
.max_bw_high = 30200000,
431
+
.min_core_ib = 2500000,
432
+
.min_llcc_ib = 0,
433
+
.min_dram_ib = 800000,
434
+
.min_prefill_lines = 35,
435
+
.danger_lut_tbl = {0x0ffff, 0x0ffff, 0x0},
436
+
.safe_lut_tbl = {0xff00, 0xff00, 0xffff},
437
+
.qos_lut_tbl = {
438
+
{.nentry = ARRAY_SIZE(kaanapali_qos_linear),
439
+
.entries = kaanapali_qos_linear
440
+
},
441
+
{.nentry = ARRAY_SIZE(kaanapali_qos_macrotile),
442
+
.entries = kaanapali_qos_macrotile
443
+
},
444
+
{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
445
+
.entries = sc7180_qos_nrt
446
+
},
447
+
/* TODO: macrotile-qseed is different from macrotile */
448
+
},
449
+
.cdp_cfg = {
450
+
{.rd_enable = 1, .wr_enable = 1},
451
+
{.rd_enable = 1, .wr_enable = 0}
452
+
},
453
+
.clk_inefficiency_factor = 105,
454
+
.bw_inefficiency_factor = 120,
455
+
};
456
+
457
+
static const struct dpu_mdss_version kaanapali_mdss_ver = {
458
+
.core_major_ver = 13,
459
+
.core_minor_ver = 0,
460
+
};
461
+
462
+
const struct dpu_mdss_cfg dpu_kaanapali_cfg = {
463
+
.mdss_ver = &kaanapali_mdss_ver,
464
+
.caps = &kaanapali_dpu_caps,
465
+
.mdp = &kaanapali_mdp,
466
+
.cdm = &dpu_cdm_13_x,
467
+
.ctl_count = ARRAY_SIZE(kaanapali_ctl),
468
+
.ctl = kaanapali_ctl,
469
+
.sspp_count = ARRAY_SIZE(kaanapali_sspp),
470
+
.sspp = kaanapali_sspp,
471
+
.mixer_count = ARRAY_SIZE(kaanapali_lm),
472
+
.mixer = kaanapali_lm,
473
+
.dspp_count = ARRAY_SIZE(kaanapali_dspp),
474
+
.dspp = kaanapali_dspp,
475
+
.pingpong_count = ARRAY_SIZE(kaanapali_pp),
476
+
.pingpong = kaanapali_pp,
477
+
.dsc_count = ARRAY_SIZE(kaanapali_dsc),
478
+
.dsc = kaanapali_dsc,
479
+
.merge_3d_count = ARRAY_SIZE(kaanapali_merge_3d),
480
+
.merge_3d = kaanapali_merge_3d,
481
+
.wb_count = ARRAY_SIZE(kaanapali_wb),
482
+
.wb = kaanapali_wb,
483
+
.cwb_count = ARRAY_SIZE(kaanapali_cwb),
484
+
.cwb = sm8650_cwb,
485
+
.intf_count = ARRAY_SIZE(kaanapali_intf),
486
+
.intf = kaanapali_intf,
487
+
.vbif_count = ARRAY_SIZE(sm8650_vbif),
488
+
.vbif = sm8650_vbif,
489
+
.perf = &kaanapali_perf_data,
490
+
};
491
+
492
+
#endif
-5
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
-5
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
···
42
42
.name = "ctl_0", .id = CTL_0,
43
43
.base = 0x1000, .len = 0x94,
44
44
.features = BIT(DPU_CTL_SPLIT_DISPLAY),
45
-
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
46
45
}, {
47
46
.name = "ctl_1", .id = CTL_1,
48
47
.base = 0x1200, .len = 0x94,
49
-
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
50
48
}, {
51
49
.name = "ctl_2", .id = CTL_2,
52
50
.base = 0x1400, .len = 0x94,
53
51
.features = BIT(DPU_CTL_SPLIT_DISPLAY),
54
-
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
55
52
}, {
56
53
.name = "ctl_3", .id = CTL_3,
57
54
.base = 0x1600, .len = 0x94,
58
-
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
59
55
}, {
60
56
.name = "ctl_4", .id = CTL_4,
61
57
.base = 0x1800, .len = 0x94,
62
-
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
63
58
},
64
59
};
65
60
-5
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
-5
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
···
37
37
.name = "ctl_0", .id = CTL_0,
38
38
.base = 0x1000, .len = 0x94,
39
39
.features = BIT(DPU_CTL_SPLIT_DISPLAY),
40
-
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
41
40
}, {
42
41
.name = "ctl_1", .id = CTL_1,
43
42
.base = 0x1200, .len = 0x94,
44
-
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
45
43
}, {
46
44
.name = "ctl_2", .id = CTL_2,
47
45
.base = 0x1400, .len = 0x94,
48
46
.features = BIT(DPU_CTL_SPLIT_DISPLAY),
49
-
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
50
47
}, {
51
48
.name = "ctl_3", .id = CTL_3,
52
49
.base = 0x1600, .len = 0x94,
53
-
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
54
50
}, {
55
51
.name = "ctl_4", .id = CTL_4,
56
52
.base = 0x1800, .len = 0x94,
57
-
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
58
53
},
59
54
};
60
55
-5
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
-5
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
···
36
36
.name = "ctl_0", .id = CTL_0,
37
37
.base = 0x1000, .len = 0x94,
38
38
.features = BIT(DPU_CTL_SPLIT_DISPLAY),
39
-
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
40
39
}, {
41
40
.name = "ctl_1", .id = CTL_1,
42
41
.base = 0x1200, .len = 0x94,
43
-
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
44
42
}, {
45
43
.name = "ctl_2", .id = CTL_2,
46
44
.base = 0x1400, .len = 0x94,
47
45
.features = BIT(DPU_CTL_SPLIT_DISPLAY),
48
-
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
49
46
}, {
50
47
.name = "ctl_3", .id = CTL_3,
51
48
.base = 0x1600, .len = 0x94,
52
-
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
53
49
}, {
54
50
.name = "ctl_4", .id = CTL_4,
55
51
.base = 0x1800, .len = 0x94,
56
-
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
57
52
},
58
53
};
59
54
+12
-2
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+12
-2
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
···
13
13
.has_dim_layer = true,
14
14
.has_idle_pc = true,
15
15
.max_linewidth = 2400,
16
+
.has_3d_merge = true,
16
17
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
17
18
};
18
19
···
135
134
.name = "pingpong_2", .id = PINGPONG_2,
136
135
.base = 0x6b000, .len = 0,
137
136
.sblk = &sc7280_pp_sblk,
138
-
.merge_3d = 0,
137
+
.merge_3d = MERGE_3D_1,
139
138
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
140
139
}, {
141
140
.name = "pingpong_3", .id = PINGPONG_3,
142
141
.base = 0x6c000, .len = 0,
143
142
.sblk = &sc7280_pp_sblk,
144
-
.merge_3d = 0,
143
+
.merge_3d = MERGE_3D_1,
145
144
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
145
+
},
146
+
};
147
+
148
+
static const struct dpu_merge_3d_cfg sc7280_merge_3d[] = {
149
+
{
150
+
.name = "merge_3d_1", .id = MERGE_3D_1,
151
+
.base = 0x4f000, .len = 0x8,
146
152
},
147
153
};
148
154
···
255
247
.mixer = sc7280_lm,
256
248
.pingpong_count = ARRAY_SIZE(sc7280_pp),
257
249
.pingpong = sc7280_pp,
250
+
.merge_3d_count = ARRAY_SIZE(sc7280_merge_3d),
251
+
.merge_3d = sc7280_merge_3d,
258
252
.dsc_count = ARRAY_SIZE(sc7280_dsc),
259
253
.dsc = sc7280_dsc,
260
254
.wb_count = ARRAY_SIZE(sc7280_wb),
+72
-14
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+72
-14
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
···
819
819
cfg->b.b = CONVERT_S3_15(ctm->matrix[8]);
820
820
}
821
821
822
+
static void _dpu_crtc_get_gc_lut(struct drm_crtc_state *state,
823
+
struct dpu_hw_gc_lut *gc_lut)
824
+
{
825
+
struct drm_color_lut *lut;
826
+
int i;
827
+
u32 val_even, val_odd;
828
+
829
+
lut = (struct drm_color_lut *)state->gamma_lut->data;
830
+
831
+
if (!lut)
832
+
return;
833
+
834
+
/* Pack 1024 10-bit entries in 512 32-bit registers */
835
+
for (i = 0; i < PGC_TBL_LEN; i++) {
836
+
val_even = drm_color_lut_extract(lut[i * 2].green, 10);
837
+
val_odd = drm_color_lut_extract(lut[i * 2 + 1].green, 10);
838
+
gc_lut->c0[i] = val_even | (val_odd << 16);
839
+
val_even = drm_color_lut_extract(lut[i * 2].blue, 10);
840
+
val_odd = drm_color_lut_extract(lut[i * 2 + 1].blue, 10);
841
+
gc_lut->c1[i] = val_even | (val_odd << 16);
842
+
val_even = drm_color_lut_extract(lut[i * 2].red, 10);
843
+
val_odd = drm_color_lut_extract(lut[i * 2 + 1].red, 10);
844
+
gc_lut->c2[i] = val_even | (val_odd << 16);
845
+
}
846
+
847
+
/* Disable 8-bit rounding mode */
848
+
gc_lut->flags = 0;
849
+
}
850
+
822
851
static void _dpu_crtc_setup_cp_blocks(struct drm_crtc *crtc)
823
852
{
824
853
struct drm_crtc_state *state = crtc->state;
825
854
struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
826
855
struct dpu_crtc_mixer *mixer = cstate->mixers;
827
856
struct dpu_hw_pcc_cfg cfg;
857
+
struct dpu_hw_gc_lut *gc_lut;
828
858
struct dpu_hw_ctl *ctl;
829
859
struct dpu_hw_dspp *dspp;
830
860
int i;
···
867
837
ctl = mixer[i].lm_ctl;
868
838
dspp = mixer[i].hw_dspp;
869
839
870
-
if (!dspp || !dspp->ops.setup_pcc)
840
+
if (!dspp)
871
841
continue;
872
842
873
-
if (!state->ctm) {
874
-
dspp->ops.setup_pcc(dspp, NULL);
875
-
} else {
876
-
_dpu_crtc_get_pcc_coeff(state, &cfg);
877
-
dspp->ops.setup_pcc(dspp, &cfg);
843
+
if (dspp->ops.setup_pcc) {
844
+
if (!state->ctm) {
845
+
dspp->ops.setup_pcc(dspp, NULL);
846
+
} else {
847
+
_dpu_crtc_get_pcc_coeff(state, &cfg);
848
+
dspp->ops.setup_pcc(dspp, &cfg);
849
+
}
850
+
851
+
/* stage config flush mask */
852
+
ctl->ops.update_pending_flush_dspp(ctl,
853
+
mixer[i].hw_dspp->idx, DPU_DSPP_PCC);
878
854
}
879
855
880
-
/* stage config flush mask */
881
-
ctl->ops.update_pending_flush_dspp(ctl,
882
-
mixer[i].hw_dspp->idx, DPU_DSPP_PCC);
856
+
if (dspp->ops.setup_gc) {
857
+
if (!state->gamma_lut) {
858
+
dspp->ops.setup_gc(dspp, NULL);
859
+
} else {
860
+
gc_lut = kzalloc(sizeof(*gc_lut), GFP_KERNEL);
861
+
if (!gc_lut)
862
+
continue;
863
+
_dpu_crtc_get_gc_lut(state, gc_lut);
864
+
dspp->ops.setup_gc(dspp, gc_lut);
865
+
kfree(gc_lut);
866
+
}
867
+
868
+
/* stage config flush mask */
869
+
ctl->ops.update_pending_flush_dspp(ctl,
870
+
mixer[i].hw_dspp->idx, DPU_DSPP_GC);
871
+
}
883
872
}
884
873
}
885
874
···
1396
1347
*
1397
1348
* If DSC is enabled, use 2 LMs for 2:2:1 topology
1398
1349
*
1399
-
* Add dspps to the reservation requirements if ctm is requested
1350
+
* Add dspps to the reservation requirements if ctm or gamma_lut are requested
1400
1351
*
1401
1352
* Only hardcode num_lm to 2 for cases where num_intf == 2 and CWB is not
1402
1353
* enabled. This is because in cases where CWB is enabled, num_intf will
···
1415
1366
else
1416
1367
topology.num_lm = 1;
1417
1368
1418
-
if (crtc_state->ctm)
1369
+
if (crtc_state->ctm || crtc_state->gamma_lut)
1419
1370
topology.num_dspp = topology.num_lm;
1420
1371
1421
1372
return topology;
···
1527
1478
bool needs_dirtyfb = dpu_crtc_needs_dirtyfb(crtc_state);
1528
1479
1529
1480
/* don't reallocate resources if only ACTIVE has beeen changed */
1530
-
if (crtc_state->mode_changed || crtc_state->connectors_changed) {
1481
+
if (crtc_state->mode_changed || crtc_state->connectors_changed ||
1482
+
crtc_state->color_mgmt_changed) {
1531
1483
rc = dpu_crtc_assign_resources(crtc, crtc_state);
1532
1484
if (rc < 0)
1533
1485
return rc;
···
1891
1841
1892
1842
drm_crtc_helper_add(crtc, &dpu_crtc_helper_funcs);
1893
1843
1894
-
if (dpu_kms->catalog->dspp_count)
1895
-
drm_crtc_enable_color_mgmt(crtc, 0, true, 0);
1844
+
if (dpu_kms->catalog->dspp_count) {
1845
+
const struct dpu_dspp_cfg *dspp = &dpu_kms->catalog->dspp[0];
1846
+
1847
+
if (dspp->sblk->gc.base) {
1848
+
drm_mode_crtc_set_gamma_size(crtc, DPU_GAMMA_LUT_SIZE);
1849
+
drm_crtc_enable_color_mgmt(crtc, 0, true, DPU_GAMMA_LUT_SIZE);
1850
+
} else {
1851
+
drm_crtc_enable_color_mgmt(crtc, 0, true, 0);
1852
+
}
1853
+
}
1896
1854
1897
1855
/* save user friendly CRTC name for later */
1898
1856
snprintf(dpu_crtc->name, DPU_CRTC_NAME_SIZE, "crtc%u", crtc->base.id);
+9
-9
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+9
-9
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
···
785
785
return;
786
786
}
787
787
788
+
vsync_cfg.vsync_source = disp_info->vsync_source;
789
+
vsync_cfg.frame_rate = drm_mode_vrefresh(&dpu_enc->base.crtc->state->adjusted_mode);
790
+
788
791
if (hw_mdptop->ops.setup_vsync_source) {
789
792
for (i = 0; i < dpu_enc->num_phys_encs; i++)
790
793
vsync_cfg.ppnumber[i] = dpu_enc->hw_pp[i]->idx;
791
794
792
795
vsync_cfg.pp_count = dpu_enc->num_phys_encs;
793
-
vsync_cfg.frame_rate = drm_mode_vrefresh(&dpu_enc->base.crtc->state->adjusted_mode);
794
-
795
-
vsync_cfg.vsync_source = disp_info->vsync_source;
796
796
797
797
hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg);
798
+
}
798
799
799
-
for (i = 0; i < dpu_enc->num_phys_encs; i++) {
800
-
phys_enc = dpu_enc->phys_encs[i];
800
+
for (i = 0; i < dpu_enc->num_phys_encs; i++) {
801
+
phys_enc = dpu_enc->phys_encs[i];
801
802
802
-
if (phys_enc->has_intf_te && phys_enc->hw_intf->ops.vsync_sel)
803
-
phys_enc->hw_intf->ops.vsync_sel(phys_enc->hw_intf,
804
-
vsync_cfg.vsync_source);
805
-
}
803
+
if (phys_enc->has_intf_te && phys_enc->hw_intf->ops.vsync_sel)
804
+
phys_enc->hw_intf->ops.vsync_sel(phys_enc->hw_intf,
805
+
&vsync_cfg);
806
806
}
807
807
}
808
808
+4
-3
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+4
-3
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
···
681
681
if (!dpu_encoder_phys_cmd_is_master(phys_enc))
682
682
return 0;
683
683
684
-
if (phys_enc->hw_ctl->ops.is_started(phys_enc->hw_ctl))
685
-
return dpu_encoder_phys_cmd_wait_for_tx_complete(phys_enc);
684
+
if (phys_enc->irq[INTR_IDX_CTL_START] &&
685
+
!phys_enc->hw_ctl->ops.is_started(phys_enc->hw_ctl))
686
+
return _dpu_encoder_phys_cmd_wait_for_ctl_start(phys_enc);
686
687
687
-
return _dpu_encoder_phys_cmd_wait_for_ctl_start(phys_enc);
688
+
return dpu_encoder_phys_cmd_wait_for_tx_complete(phys_enc);
688
689
}
689
690
690
691
static void dpu_encoder_phys_cmd_handle_post_kickoff(
+77
-101
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
+77
-101
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
···
7
7
#include <uapi/drm/drm_fourcc.h>
8
8
#include <drm/drm_framebuffer.h>
9
9
10
-
#include "msm_media_info.h"
11
10
#include "dpu_kms.h"
12
11
#include "dpu_formats.h"
13
12
···
53
54
}
54
55
}
55
56
56
-
static int _dpu_format_get_media_color_ubwc(const struct msm_format *fmt)
57
-
{
58
-
static const struct dpu_media_color_map dpu_media_ubwc_map[] = {
59
-
{DRM_FORMAT_ABGR8888, COLOR_FMT_RGBA8888_UBWC},
60
-
{DRM_FORMAT_ARGB8888, COLOR_FMT_RGBA8888_UBWC},
61
-
{DRM_FORMAT_XBGR8888, COLOR_FMT_RGBA8888_UBWC},
62
-
{DRM_FORMAT_XRGB8888, COLOR_FMT_RGBA8888_UBWC},
63
-
{DRM_FORMAT_ABGR2101010, COLOR_FMT_RGBA1010102_UBWC},
64
-
{DRM_FORMAT_ARGB2101010, COLOR_FMT_RGBA1010102_UBWC},
65
-
{DRM_FORMAT_XRGB2101010, COLOR_FMT_RGBA1010102_UBWC},
66
-
{DRM_FORMAT_XBGR2101010, COLOR_FMT_RGBA1010102_UBWC},
67
-
{DRM_FORMAT_BGR565, COLOR_FMT_RGB565_UBWC},
68
-
};
69
-
int color_fmt = -1;
70
-
int i;
71
-
72
-
if (fmt->pixel_format == DRM_FORMAT_NV12 ||
73
-
fmt->pixel_format == DRM_FORMAT_P010) {
74
-
if (MSM_FORMAT_IS_DX(fmt)) {
75
-
if (fmt->flags & MSM_FORMAT_FLAG_UNPACK_TIGHT)
76
-
color_fmt = COLOR_FMT_NV12_BPP10_UBWC;
77
-
else
78
-
color_fmt = COLOR_FMT_P010_UBWC;
79
-
} else
80
-
color_fmt = COLOR_FMT_NV12_UBWC;
81
-
return color_fmt;
82
-
}
83
-
84
-
for (i = 0; i < ARRAY_SIZE(dpu_media_ubwc_map); ++i)
85
-
if (fmt->pixel_format == dpu_media_ubwc_map[i].format) {
86
-
color_fmt = dpu_media_ubwc_map[i].color;
87
-
break;
88
-
}
89
-
return color_fmt;
90
-
}
91
-
92
57
static int _dpu_format_populate_plane_sizes_ubwc(
93
58
const struct msm_format *fmt,
94
59
struct drm_framebuffer *fb,
95
60
struct dpu_hw_fmt_layout *layout)
96
61
{
97
-
int i;
98
-
int color;
99
62
bool meta = MSM_FORMAT_IS_UBWC(fmt);
100
63
101
-
memset(layout, 0, sizeof(struct dpu_hw_fmt_layout));
102
-
layout->width = fb->width;
103
-
layout->height = fb->height;
104
-
layout->num_planes = fmt->num_planes;
105
-
106
-
color = _dpu_format_get_media_color_ubwc(fmt);
107
-
if (color < 0) {
108
-
DRM_ERROR("UBWC format not supported for fmt: %p4cc\n",
109
-
&fmt->pixel_format);
110
-
return -EINVAL;
111
-
}
112
-
113
64
if (MSM_FORMAT_IS_YUV(fmt)) {
114
-
uint32_t y_sclines, uv_sclines;
115
-
uint32_t y_meta_scanlines = 0;
116
-
uint32_t uv_meta_scanlines = 0;
65
+
unsigned int stride, sclines;
66
+
unsigned int y_tile_width, y_tile_height;
67
+
unsigned int y_meta_stride, y_meta_scanlines;
68
+
unsigned int uv_meta_stride, uv_meta_scanlines;
117
69
118
-
layout->num_planes = 2;
119
-
layout->plane_pitch[0] = VENUS_Y_STRIDE(color, fb->width);
120
-
y_sclines = VENUS_Y_SCANLINES(color, fb->height);
121
-
layout->plane_size[0] = MSM_MEDIA_ALIGN(layout->plane_pitch[0] *
122
-
y_sclines, DPU_UBWC_PLANE_SIZE_ALIGNMENT);
70
+
if (MSM_FORMAT_IS_DX(fmt)) {
71
+
if (fmt->flags & MSM_FORMAT_FLAG_UNPACK_TIGHT) {
72
+
/* can't use round_up() here because 192 is NPoT */
73
+
stride = roundup(fb->width, 192);
74
+
stride = round_up(stride * 4 / 3, 256);
75
+
y_tile_width = 48;
76
+
} else {
77
+
stride = round_up(fb->width * 2, 256);
78
+
y_tile_width = 32;
79
+
}
123
80
124
-
layout->plane_pitch[1] = VENUS_UV_STRIDE(color, fb->width);
125
-
uv_sclines = VENUS_UV_SCANLINES(color, fb->height);
126
-
layout->plane_size[1] = MSM_MEDIA_ALIGN(layout->plane_pitch[1] *
127
-
uv_sclines, DPU_UBWC_PLANE_SIZE_ALIGNMENT);
81
+
sclines = round_up(fb->height, 16);
82
+
y_tile_height = 4;
83
+
} else {
84
+
stride = round_up(fb->width, 128);
85
+
y_tile_width = 32;
86
+
87
+
sclines = round_up(fb->height, 32);
88
+
y_tile_height = 8;
89
+
}
90
+
91
+
layout->plane_pitch[0] = stride;
92
+
layout->plane_size[0] = round_up(layout->plane_pitch[0] *
93
+
sclines, DPU_UBWC_PLANE_SIZE_ALIGNMENT);
94
+
95
+
layout->plane_pitch[1] = stride;
96
+
layout->plane_size[1] = round_up(layout->plane_pitch[1] *
97
+
sclines, DPU_UBWC_PLANE_SIZE_ALIGNMENT);
128
98
129
99
if (!meta)
130
-
goto done;
100
+
return 0;
131
101
132
-
layout->num_planes += 2;
133
-
layout->plane_pitch[2] = VENUS_Y_META_STRIDE(color, fb->width);
134
-
y_meta_scanlines = VENUS_Y_META_SCANLINES(color, fb->height);
135
-
layout->plane_size[2] = MSM_MEDIA_ALIGN(layout->plane_pitch[2] *
102
+
y_meta_stride = DIV_ROUND_UP(fb->width, y_tile_width);
103
+
layout->plane_pitch[2] = round_up(y_meta_stride, 64);
104
+
105
+
y_meta_scanlines = DIV_ROUND_UP(fb->height, y_tile_height);
106
+
y_meta_scanlines = round_up(y_meta_scanlines, 16);
107
+
layout->plane_size[2] = round_up(layout->plane_pitch[2] *
136
108
y_meta_scanlines, DPU_UBWC_PLANE_SIZE_ALIGNMENT);
137
109
138
-
layout->plane_pitch[3] = VENUS_UV_META_STRIDE(color, fb->width);
139
-
uv_meta_scanlines = VENUS_UV_META_SCANLINES(color, fb->height);
140
-
layout->plane_size[3] = MSM_MEDIA_ALIGN(layout->plane_pitch[3] *
110
+
uv_meta_stride = DIV_ROUND_UP((fb->width+1)>>1, y_tile_width / 2);
111
+
layout->plane_pitch[3] = round_up(uv_meta_stride, 64);
112
+
113
+
uv_meta_scanlines = DIV_ROUND_UP((fb->height+1)>>1, y_tile_height);
114
+
uv_meta_scanlines = round_up(uv_meta_scanlines, 16);
115
+
layout->plane_size[3] = round_up(layout->plane_pitch[3] *
141
116
uv_meta_scanlines, DPU_UBWC_PLANE_SIZE_ALIGNMENT);
142
-
143
117
} else {
144
-
uint32_t rgb_scanlines, rgb_meta_scanlines;
118
+
unsigned int rgb_scanlines, rgb_meta_scanlines, rgb_meta_stride;
145
119
146
-
layout->num_planes = 1;
147
-
148
-
layout->plane_pitch[0] = VENUS_RGB_STRIDE(color, fb->width);
149
-
rgb_scanlines = VENUS_RGB_SCANLINES(color, fb->height);
150
-
layout->plane_size[0] = MSM_MEDIA_ALIGN(layout->plane_pitch[0] *
120
+
layout->plane_pitch[0] = round_up(fb->width * fmt->bpp, 256);
121
+
rgb_scanlines = round_up(fb->height, 16);
122
+
layout->plane_size[0] = round_up(layout->plane_pitch[0] *
151
123
rgb_scanlines, DPU_UBWC_PLANE_SIZE_ALIGNMENT);
152
124
153
125
if (!meta)
154
-
goto done;
155
-
layout->num_planes += 2;
156
-
layout->plane_pitch[2] = VENUS_RGB_META_STRIDE(color, fb->width);
157
-
rgb_meta_scanlines = VENUS_RGB_META_SCANLINES(color, fb->height);
158
-
layout->plane_size[2] = MSM_MEDIA_ALIGN(layout->plane_pitch[2] *
126
+
return 0;
127
+
128
+
/* uAPI leaves plane[1] empty and plane[2] as meta */
129
+
layout->num_planes += 1;
130
+
131
+
rgb_meta_stride = DIV_ROUND_UP(fb->width, 16);
132
+
layout->plane_pitch[2] = round_up(rgb_meta_stride, 64);
133
+
134
+
rgb_meta_scanlines = DIV_ROUND_UP(fb->height, 4);
135
+
rgb_meta_scanlines = round_up(rgb_meta_scanlines, 16);
136
+
137
+
layout->plane_size[2] = round_up(layout->plane_pitch[2] *
159
138
rgb_meta_scanlines, DPU_UBWC_PLANE_SIZE_ALIGNMENT);
160
139
}
161
-
162
-
done:
163
-
for (i = 0; i < DPU_MAX_PLANES; i++)
164
-
layout->total_size += layout->plane_size[i];
165
140
166
141
return 0;
167
142
}
···
147
174
{
148
175
int i;
149
176
150
-
memset(layout, 0, sizeof(struct dpu_hw_fmt_layout));
151
-
layout->width = fb->width;
152
-
layout->height = fb->height;
153
-
layout->num_planes = fmt->num_planes;
154
-
155
177
/* Due to memset above, only need to set planes of interest */
156
178
if (fmt->fetch_type == MDP_PLANE_INTERLEAVED) {
157
-
layout->num_planes = 1;
158
179
layout->plane_size[0] = fb->width * fb->height * fmt->bpp;
159
180
layout->plane_pitch[0] = fb->width * fmt->bpp;
160
181
} else {
···
175
208
(fb->height / v_subsample);
176
209
177
210
if (fmt->fetch_type == MDP_PLANE_PSEUDO_PLANAR) {
178
-
layout->num_planes = 2;
179
211
layout->plane_size[1] *= 2;
180
212
layout->plane_pitch[1] *= 2;
181
213
} else {
182
214
/* planar */
183
-
layout->num_planes = 3;
184
215
layout->plane_size[2] = layout->plane_size[1];
185
216
layout->plane_pitch[2] = layout->plane_pitch[1];
186
217
}
···
200
235
}
201
236
}
202
237
203
-
for (i = 0; i < DPU_MAX_PLANES; i++)
204
-
layout->total_size += layout->plane_size[i];
205
-
206
238
return 0;
207
239
}
208
240
···
216
254
struct dpu_hw_fmt_layout *layout)
217
255
{
218
256
const struct msm_format *fmt;
257
+
int ret, i;
219
258
220
259
if (!layout || !fb) {
221
260
DRM_ERROR("invalid pointer\n");
···
231
268
232
269
fmt = msm_framebuffer_format(fb);
233
270
234
-
if (MSM_FORMAT_IS_UBWC(fmt) || MSM_FORMAT_IS_TILE(fmt))
235
-
return _dpu_format_populate_plane_sizes_ubwc(fmt, fb, layout);
271
+
memset(layout, 0, sizeof(struct dpu_hw_fmt_layout));
272
+
layout->width = fb->width;
273
+
layout->height = fb->height;
274
+
layout->num_planes = fmt->num_planes;
236
275
237
-
return _dpu_format_populate_plane_sizes_linear(fmt, fb, layout);
276
+
if (MSM_FORMAT_IS_UBWC(fmt) || MSM_FORMAT_IS_TILE(fmt))
277
+
ret = _dpu_format_populate_plane_sizes_ubwc(fmt, fb, layout);
278
+
else
279
+
ret = _dpu_format_populate_plane_sizes_linear(fmt, fb, layout);
280
+
281
+
if (ret)
282
+
return ret;
283
+
284
+
for (i = 0; i < DPU_MAX_PLANES; i++)
285
+
layout->total_size += layout->plane_size[i];
286
+
287
+
return 0;
238
288
}
239
289
240
290
static void _dpu_format_populate_addrs_ubwc(struct drm_framebuffer *fb,
+45
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+45
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
···
241
241
.rotation_cfg = NULL, \
242
242
}
243
243
244
+
/* kaanapali SSPP common configuration */
245
+
#define _VIG_SBLK_REC0_REC1(scaler_ver) \
246
+
{ \
247
+
.sspp_rec0_blk = {.name = "sspp_rec0", \
248
+
.base = 0x1000, .len = 0x180,}, \
249
+
.csc_blk = {.name = "csc", \
250
+
.base = 0x1800, .len = 0x100,}, \
251
+
.scaler_blk = {.name = "scaler", \
252
+
.version = scaler_ver, \
253
+
.base = 0x2000, .len = 0xec,}, \
254
+
.sspp_rec1_blk = {.name = "sspp_rec1", \
255
+
.base = 0x3000, .len = 0x180,}, \
256
+
.format_list = plane_formats_yuv, \
257
+
.num_formats = ARRAY_SIZE(plane_formats_yuv), \
258
+
.rotation_cfg = NULL, \
259
+
}
260
+
244
261
#define _VIG_SBLK_ROT(scaler_ver, rot_cfg) \
245
262
{ \
246
263
.scaler_blk = {.name = "scaler", \
···
346
329
static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_4 =
347
330
_VIG_SBLK(SSPP_SCALER_VER(3, 4));
348
331
332
+
static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_5 =
333
+
_VIG_SBLK_REC0_REC1(SSPP_SCALER_VER(3, 5));
334
+
349
335
static const struct dpu_sspp_sub_blks dpu_rgb_sblk = _RGB_SBLK();
350
336
351
337
static const struct dpu_sspp_sub_blks dpu_dma_sblk = _DMA_SBLK();
···
402
382
static const struct dpu_dspp_sub_blks msm8998_dspp_sblk = {
403
383
.pcc = {.name = "pcc", .base = 0x1700,
404
384
.len = 0x90, .version = 0x10007},
385
+
.gc = {.name = "gc", .base = 0x17c0,
386
+
.len = 0x40, .version = 0x10007},
405
387
};
406
388
407
389
static const struct dpu_dspp_sub_blks sdm845_dspp_sblk = {
408
390
.pcc = {.name = "pcc", .base = 0x1700,
409
391
.len = 0x90, .version = 0x40000},
392
+
.gc = {.name = "gc", .base = 0x17c0,
393
+
.len = 0x40, .version = 0x10008},
410
394
};
411
395
412
396
static const struct dpu_dspp_sub_blks sm8750_dspp_sblk = {
···
434
410
static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = {
435
411
.dither = {.name = "dither", .base = 0xe0,
436
412
.len = 0x20, .version = 0x20000},
413
+
};
414
+
415
+
static const struct dpu_pingpong_sub_blks kaanapali_pp_sblk = {
416
+
.dither = {.name = "dither", .base = 0xc0,
417
+
.len = 0x40, .version = 0x30000},
437
418
};
438
419
439
420
/*************************************************************
···
479
450
.id = CDM_0,
480
451
.len = 0x228,
481
452
.base = 0x79200,
453
+
};
454
+
455
+
static const struct dpu_cdm_cfg dpu_cdm_13_x = {
456
+
.name = "cdm_0",
457
+
.id = CDM_0,
458
+
.len = 0x240,
459
+
.base = 0x19e000,
482
460
};
483
461
484
462
/*************************************************************
···
675
639
{.fl = 0, .lut = 0x0011222222335777},
676
640
};
677
641
642
+
static const struct dpu_qos_lut_entry kaanapali_qos_linear[] = {
643
+
{.fl = 0, .lut = 0x0011223344556666},
644
+
};
645
+
678
646
static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
679
647
{.fl = 0, .lut = 0x0011223445566777 },
680
648
};
···
706
666
707
667
static const struct dpu_qos_lut_entry sc7180_qos_macrotile[] = {
708
668
{.fl = 0, .lut = 0x0011223344556677},
669
+
};
670
+
671
+
static const struct dpu_qos_lut_entry kaanapali_qos_macrotile[] = {
672
+
{.fl = 0, .lut = 0x0011223344556666},
709
673
};
710
674
711
675
static const struct dpu_qos_lut_entry sc8180x_qos_macrotile[] = {
···
771
727
#include "catalog/dpu_10_0_sm8650.h"
772
728
#include "catalog/dpu_12_0_sm8750.h"
773
729
#include "catalog/dpu_12_2_glymur.h"
730
+
#include "catalog/dpu_13_0_kaanapali.h"
+19
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+19
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
···
77
77
/**
78
78
* DSPP sub-blocks
79
79
* @DPU_DSPP_PCC Panel color correction block
80
+
* @DPU_DSPP_GC Gamma correction block
80
81
*/
81
82
enum {
82
83
DPU_DSPP_PCC = 0x1,
84
+
DPU_DSPP_GC,
83
85
DPU_DSPP_MAX
84
86
};
85
87
···
211
209
};
212
210
213
211
/**
212
+
* struct dpu_sspp_v13_rec_blk - SSPP REC sub-blk information
213
+
* @name: string name for debug purposes
214
+
* @base: offset of this sub-block relative to the block offset
215
+
* @len: register block length of this sub-block
216
+
*/
217
+
struct dpu_sspp_v13_rec_blk {
218
+
char name[DPU_HW_BLK_NAME_LEN];
219
+
u32 base;
220
+
u32 len;
221
+
};
222
+
223
+
/**
214
224
* enum dpu_qos_lut_usage - define QoS LUT use cases
215
225
*/
216
226
enum dpu_qos_lut_usage {
···
308
294
u32 qseed_ver;
309
295
struct dpu_scaler_blk scaler_blk;
310
296
struct dpu_pp_blk csc_blk;
297
+
struct dpu_sspp_v13_rec_blk sspp_rec0_blk;
298
+
struct dpu_sspp_v13_rec_blk sspp_rec1_blk;
311
299
312
300
const u32 *format_list;
313
301
u32 num_formats;
···
330
314
/**
331
315
* struct dpu_dspp_sub_blks: Information of DSPP block
332
316
* @pcc: pixel color correction block
317
+
* @gc: gamma correction block
333
318
*/
334
319
struct dpu_dspp_sub_blks {
335
320
struct dpu_pp_blk pcc;
321
+
struct dpu_pp_blk gc;
336
322
};
337
323
338
324
struct dpu_pingpong_sub_blks {
···
768
750
};
769
751
770
752
extern const struct dpu_mdss_cfg dpu_glymur_cfg;
753
+
extern const struct dpu_mdss_cfg dpu_kaanapali_cfg;
771
754
extern const struct dpu_mdss_cfg dpu_msm8917_cfg;
772
755
extern const struct dpu_mdss_cfg dpu_msm8937_cfg;
773
756
extern const struct dpu_mdss_cfg dpu_msm8953_cfg;
+3
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+3
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+54
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
+54
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
···
24
24
#define PCC_BLUE_G_OFF 0x24
25
25
#define PCC_BLUE_B_OFF 0x30
26
26
27
+
/* DSPP_GC */
28
+
#define GC_EN BIT(0)
29
+
#define GC_DIS 0
30
+
#define GC_8B_ROUND_EN BIT(1)
31
+
#define GC_LUT_SWAP_OFF 0x1c
32
+
#define GC_C0_OFF 0x4
33
+
#define GC_C1_OFF 0xc
34
+
#define GC_C2_OFF 0x14
35
+
#define GC_C0_INDEX_OFF 0x8
36
+
#define GC_C1_INDEX_OFF 0x10
37
+
#define GC_C2_INDEX_OFF 0x18
38
+
27
39
static void dpu_setup_dspp_pcc(struct dpu_hw_dspp *ctx,
28
40
struct dpu_hw_pcc_cfg *cfg)
29
41
{
···
75
63
DPU_REG_WRITE(&ctx->hw, base, PCC_EN);
76
64
}
77
65
66
+
static void dpu_setup_dspp_gc(struct dpu_hw_dspp *ctx,
67
+
struct dpu_hw_gc_lut *gc_lut)
68
+
{
69
+
int i = 0;
70
+
u32 base, reg;
71
+
72
+
if (!ctx) {
73
+
DRM_ERROR("invalid ctx\n");
74
+
return;
75
+
}
76
+
77
+
base = ctx->cap->sblk->gc.base;
78
+
79
+
if (!base) {
80
+
DRM_ERROR("invalid ctx %pK gc base\n", ctx);
81
+
return;
82
+
}
83
+
84
+
if (!gc_lut) {
85
+
DRM_DEBUG_DRIVER("disable gc feature\n");
86
+
DPU_REG_WRITE(&ctx->hw, base, GC_DIS);
87
+
return;
88
+
}
89
+
90
+
DPU_REG_WRITE(&ctx->hw, base + GC_C0_INDEX_OFF, 0);
91
+
DPU_REG_WRITE(&ctx->hw, base + GC_C1_INDEX_OFF, 0);
92
+
DPU_REG_WRITE(&ctx->hw, base + GC_C2_INDEX_OFF, 0);
93
+
94
+
for (i = 0; i < PGC_TBL_LEN; i++) {
95
+
DPU_REG_WRITE(&ctx->hw, base + GC_C0_OFF, gc_lut->c0[i]);
96
+
DPU_REG_WRITE(&ctx->hw, base + GC_C1_OFF, gc_lut->c1[i]);
97
+
DPU_REG_WRITE(&ctx->hw, base + GC_C2_OFF, gc_lut->c2[i]);
98
+
}
99
+
100
+
DPU_REG_WRITE(&ctx->hw, base + GC_LUT_SWAP_OFF, BIT(0));
101
+
102
+
reg = GC_EN | ((gc_lut->flags & PGC_8B_ROUND) ? GC_8B_ROUND_EN : 0);
103
+
DPU_REG_WRITE(&ctx->hw, base, reg);
104
+
}
105
+
78
106
/**
79
107
* dpu_hw_dspp_init() - Initializes the DSPP hw driver object.
80
108
* should be called once before accessing every DSPP.
···
144
92
c->cap = cfg;
145
93
if (c->cap->sblk->pcc.base)
146
94
c->ops.setup_pcc = dpu_setup_dspp_pcc;
95
+
if (c->cap->sblk->gc.base)
96
+
c->ops.setup_gc = dpu_setup_dspp_gc;
147
97
148
98
return c;
149
99
}
+26
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h
+26
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h
···
33
33
struct dpu_hw_pcc_coeff b;
34
34
};
35
35
36
+
#define DPU_GAMMA_LUT_SIZE 1024
37
+
#define PGC_TBL_LEN 512
38
+
#define PGC_8B_ROUND BIT(0)
39
+
40
+
/**
41
+
* struct dpu_hw_gc_lut - gc lut feature structure
42
+
* @flags: flags for the feature values can be:
43
+
* - PGC_8B_ROUND
44
+
* @c0: color0 component lut
45
+
* @c1: color1 component lut
46
+
* @c2: color2 component lut
47
+
*/
48
+
struct dpu_hw_gc_lut {
49
+
__u64 flags;
50
+
__u32 c0[PGC_TBL_LEN];
51
+
__u32 c1[PGC_TBL_LEN];
52
+
__u32 c2[PGC_TBL_LEN];
53
+
};
54
+
36
55
/**
37
56
* struct dpu_hw_dspp_ops - interface to the dspp hardware driver functions
38
57
* Caller must call the init function to get the dspp context for each dspp
···
64
45
* @cfg: Pointer to configuration
65
46
*/
66
47
void (*setup_pcc)(struct dpu_hw_dspp *ctx, struct dpu_hw_pcc_cfg *cfg);
48
+
49
+
/**
50
+
* setup_gc - setup dspp gc
51
+
* @ctx: Pointer to dspp context
52
+
* @gc_lut: Pointer to lut content
53
+
*/
54
+
void (*setup_gc)(struct dpu_hw_dspp *ctx, struct dpu_hw_gc_lut *gc_lut);
67
55
68
56
};
69
57
+88
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
+88
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
···
40
40
#define MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(intf) (MDP_INTF_REV_7xxx_TEAR_OFF(intf) + 0x004)
41
41
#define MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(intf) (MDP_INTF_REV_7xxx_TEAR_OFF(intf) + 0x008)
42
42
43
+
#define MDP_INTF_REV_13xx_OFF(intf) (0x18d000 + 0x1000 * (intf))
44
+
#define MDP_INTF_REV_13xx_INTR_EN(intf) (MDP_INTF_REV_13xx_OFF(intf) + 0x1c0)
45
+
#define MDP_INTF_REV_13xx_INTR_STATUS(intf) (MDP_INTF_REV_13xx_OFF(intf) + 0x1c4)
46
+
#define MDP_INTF_REV_13xx_INTR_CLEAR(intf) (MDP_INTF_REV_13xx_OFF(intf) + 0x1c8)
47
+
#define MDP_INTF_REV_13xx_TEAR_OFF(intf) (0x18d800 + 0x1000 * (intf))
48
+
#define MDP_INTF_REV_13xx_INTR_TEAR_EN(intf) (MDP_INTF_REV_13xx_TEAR_OFF(intf) + 0x000)
49
+
#define MDP_INTF_REV_13xx_INTR_TEAR_STATUS(intf) (MDP_INTF_REV_13xx_TEAR_OFF(intf) + 0x004)
50
+
#define MDP_INTF_REV_13xx_INTR_TEAR_CLEAR(intf) (MDP_INTF_REV_13xx_TEAR_OFF(intf) + 0x008)
51
+
43
52
/**
44
53
* struct dpu_intr_reg - array of DPU register sets
45
54
* @clr_off: offset to CLEAR reg
···
205
196
MDP_INTF_REV_7xxx_INTR_CLEAR(8),
206
197
MDP_INTF_REV_7xxx_INTR_EN(8),
207
198
MDP_INTF_REV_7xxx_INTR_STATUS(8)
199
+
},
200
+
};
201
+
202
+
/*
203
+
* dpu_intr_set_13xx - List of DPU interrupt registers for DPU >= 13.0
204
+
*/
205
+
static const struct dpu_intr_reg dpu_intr_set_13xx[] = {
206
+
[MDP_SSPP_TOP0_INTR] = {
207
+
INTR_CLEAR,
208
+
INTR_EN,
209
+
INTR_STATUS
210
+
},
211
+
[MDP_SSPP_TOP0_INTR2] = {
212
+
INTR2_CLEAR,
213
+
INTR2_EN,
214
+
INTR2_STATUS
215
+
},
216
+
[MDP_SSPP_TOP0_HIST_INTR] = {
217
+
HIST_INTR_CLEAR,
218
+
HIST_INTR_EN,
219
+
HIST_INTR_STATUS
220
+
},
221
+
[MDP_INTF0_INTR] = {
222
+
MDP_INTF_REV_13xx_INTR_CLEAR(0),
223
+
MDP_INTF_REV_13xx_INTR_EN(0),
224
+
MDP_INTF_REV_13xx_INTR_STATUS(0)
225
+
},
226
+
[MDP_INTF1_INTR] = {
227
+
MDP_INTF_REV_13xx_INTR_CLEAR(1),
228
+
MDP_INTF_REV_13xx_INTR_EN(1),
229
+
MDP_INTF_REV_13xx_INTR_STATUS(1)
230
+
},
231
+
[MDP_INTF1_TEAR_INTR] = {
232
+
MDP_INTF_REV_13xx_INTR_TEAR_CLEAR(1),
233
+
MDP_INTF_REV_13xx_INTR_TEAR_EN(1),
234
+
MDP_INTF_REV_13xx_INTR_TEAR_STATUS(1)
235
+
},
236
+
[MDP_INTF2_INTR] = {
237
+
MDP_INTF_REV_13xx_INTR_CLEAR(2),
238
+
MDP_INTF_REV_13xx_INTR_EN(2),
239
+
MDP_INTF_REV_13xx_INTR_STATUS(2)
240
+
},
241
+
[MDP_INTF2_TEAR_INTR] = {
242
+
MDP_INTF_REV_13xx_INTR_TEAR_CLEAR(2),
243
+
MDP_INTF_REV_13xx_INTR_TEAR_EN(2),
244
+
MDP_INTF_REV_13xx_INTR_TEAR_STATUS(2)
245
+
},
246
+
[MDP_INTF3_INTR] = {
247
+
MDP_INTF_REV_13xx_INTR_CLEAR(3),
248
+
MDP_INTF_REV_13xx_INTR_EN(3),
249
+
MDP_INTF_REV_13xx_INTR_STATUS(3)
250
+
},
251
+
[MDP_INTF4_INTR] = {
252
+
MDP_INTF_REV_13xx_INTR_CLEAR(4),
253
+
MDP_INTF_REV_13xx_INTR_EN(4),
254
+
MDP_INTF_REV_13xx_INTR_STATUS(4)
255
+
},
256
+
[MDP_INTF5_INTR] = {
257
+
MDP_INTF_REV_13xx_INTR_CLEAR(5),
258
+
MDP_INTF_REV_13xx_INTR_EN(5),
259
+
MDP_INTF_REV_13xx_INTR_STATUS(5)
260
+
},
261
+
[MDP_INTF6_INTR] = {
262
+
MDP_INTF_REV_13xx_INTR_CLEAR(6),
263
+
MDP_INTF_REV_13xx_INTR_EN(6),
264
+
MDP_INTF_REV_13xx_INTR_STATUS(6)
265
+
},
266
+
[MDP_INTF7_INTR] = {
267
+
MDP_INTF_REV_13xx_INTR_CLEAR(7),
268
+
MDP_INTF_REV_13xx_INTR_EN(7),
269
+
MDP_INTF_REV_13xx_INTR_STATUS(7)
270
+
},
271
+
[MDP_INTF8_INTR] = {
272
+
MDP_INTF_REV_13xx_INTR_CLEAR(8),
273
+
MDP_INTF_REV_13xx_INTR_EN(8),
274
+
MDP_INTF_REV_13xx_INTR_STATUS(8)
208
275
},
209
276
};
210
277
···
592
507
if (!intr)
593
508
return ERR_PTR(-ENOMEM);
594
509
595
-
if (m->mdss_ver->core_major_ver >= 7)
510
+
if (m->mdss_ver->core_major_ver >= 13)
511
+
intr->intr_set = dpu_intr_set_13xx;
512
+
else if (m->mdss_ver->core_major_ver >= 7)
596
513
intr->intr_set = dpu_intr_set_7xxx;
597
514
else
598
515
intr->intr_set = dpu_intr_set_legacy;
+46
-3
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+46
-3
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
···
67
67
#define INTF_MISR_CTRL 0x180
68
68
#define INTF_MISR_SIGNATURE 0x184
69
69
70
+
#define INTF_WD_TIMER_0_CTL 0x230
71
+
#define INTF_WD_TIMER_0_CTL2 0x234
72
+
#define INTF_WD_TIMER_0_LOAD_VALUE 0x238
73
+
70
74
#define INTF_MUX 0x25C
71
75
#define INTF_STATUS 0x26C
72
76
#define INTF_AVR_CONTROL 0x270
···
479
475
}
480
476
481
477
static void dpu_hw_intf_vsync_sel(struct dpu_hw_intf *intf,
482
-
enum dpu_vsync_source vsync_source)
478
+
struct dpu_vsync_source_cfg *cfg)
483
479
{
484
480
struct dpu_hw_blk_reg_map *c;
485
481
···
488
484
489
485
c = &intf->hw;
490
486
491
-
DPU_REG_WRITE(c, INTF_TEAR_MDP_VSYNC_SEL, (vsync_source & 0xf));
487
+
DPU_REG_WRITE(c, INTF_TEAR_MDP_VSYNC_SEL, (cfg->vsync_source & 0xf));
488
+
}
489
+
490
+
static void dpu_hw_intf_vsync_sel_v8(struct dpu_hw_intf *intf,
491
+
struct dpu_vsync_source_cfg *cfg)
492
+
{
493
+
struct dpu_hw_blk_reg_map *c;
494
+
495
+
if (!intf)
496
+
return;
497
+
498
+
c = &intf->hw;
499
+
500
+
if (cfg->vsync_source >= DPU_VSYNC_SOURCE_WD_TIMER_4 &&
501
+
cfg->vsync_source <= DPU_VSYNC_SOURCE_WD_TIMER_1) {
502
+
pr_warn_once("DPU 8.x supports only GPIOs and timer0 as TE sources\n");
503
+
return;
504
+
}
505
+
506
+
if (cfg->vsync_source == DPU_VSYNC_SOURCE_WD_TIMER_0) {
507
+
u32 reg;
508
+
509
+
DPU_REG_WRITE(c, INTF_WD_TIMER_0_LOAD_VALUE,
510
+
CALCULATE_WD_LOAD_VALUE(cfg->frame_rate));
511
+
512
+
DPU_REG_WRITE(c, INTF_WD_TIMER_0_CTL, BIT(0)); /* clear timer */
513
+
514
+
reg = BIT(8); /* enable heartbeat timer */
515
+
reg |= BIT(0); /* enable WD timer */
516
+
reg |= BIT(1); /* select default 16 clock ticks */
517
+
DPU_REG_WRITE(c, INTF_WD_TIMER_0_CTL2, reg);
518
+
519
+
/* make sure that timers are enabled/disabled for vsync state */
520
+
wmb();
521
+
}
522
+
523
+
dpu_hw_intf_vsync_sel(intf, cfg);
492
524
}
493
525
494
526
static void dpu_hw_intf_disable_autorefresh(struct dpu_hw_intf *intf,
···
638
598
c->ops.enable_tearcheck = dpu_hw_intf_enable_te;
639
599
c->ops.disable_tearcheck = dpu_hw_intf_disable_te;
640
600
c->ops.connect_external_te = dpu_hw_intf_connect_external_te;
641
-
c->ops.vsync_sel = dpu_hw_intf_vsync_sel;
601
+
if (mdss_rev->core_major_ver >= 8)
602
+
c->ops.vsync_sel = dpu_hw_intf_vsync_sel_v8;
603
+
else
604
+
c->ops.vsync_sel = dpu_hw_intf_vsync_sel;
642
605
c->ops.disable_autorefresh = dpu_hw_intf_disable_autorefresh;
643
606
}
644
607
+2
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
+2
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
···
12
12
#include "dpu_hw_util.h"
13
13
14
14
struct dpu_hw_intf;
15
+
struct dpu_vsync_source_cfg;
15
16
16
17
/* intf timing settings */
17
18
struct dpu_hw_intf_timing_params {
···
105
104
106
105
int (*connect_external_te)(struct dpu_hw_intf *intf, bool enable_external_te);
107
106
108
-
void (*vsync_sel)(struct dpu_hw_intf *intf, enum dpu_vsync_source vsync_source);
107
+
void (*vsync_sel)(struct dpu_hw_intf *intf, struct dpu_vsync_source_cfg *cfg);
109
108
110
109
void (*disable_autorefresh)(struct dpu_hw_intf *intf, uint32_t encoder_id, u16 vdisplay);
111
110
+112
-68
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+112
-68
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
···
72
72
#define SSPP_EXCL_REC_XY_REC1 0x188
73
73
#define SSPP_EXCL_REC_SIZE 0x1B4
74
74
#define SSPP_EXCL_REC_XY 0x1B8
75
+
#define SSPP_UBWC_STATIC_CTRL_REC1 0x1c0
76
+
#define SSPP_UBWC_ERROR_STATUS_REC1 0x1c8
75
77
#define SSPP_CLK_CTRL 0x330
76
78
77
79
/* SSPP_SRC_OP_MODE & OP_MODE_REC1 */
···
147
145
static void dpu_hw_sspp_setup_multirect(struct dpu_sw_pipe *pipe)
148
146
{
149
147
struct dpu_hw_sspp *ctx = pipe->sspp;
150
-
u32 mode_mask;
151
148
152
149
if (!ctx)
153
150
return;
151
+
152
+
dpu_hw_setup_multirect_impl(pipe, ctx, SSPP_MULTIRECT_OPMODE);
153
+
}
154
+
155
+
void dpu_hw_setup_multirect_impl(struct dpu_sw_pipe *pipe,
156
+
struct dpu_hw_sspp *ctx, u32 op_mode_off)
157
+
{
158
+
u32 mode_mask;
154
159
155
160
if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
156
161
/**
···
167
158
*/
168
159
mode_mask = 0;
169
160
} else {
170
-
mode_mask = DPU_REG_READ(&ctx->hw, SSPP_MULTIRECT_OPMODE);
161
+
mode_mask = DPU_REG_READ(&ctx->hw, op_mode_off);
171
162
mode_mask |= pipe->multirect_index;
172
163
if (pipe->multirect_mode == DPU_SSPP_MULTIRECT_TIME_MX)
173
164
mode_mask |= BIT(2);
···
175
166
mode_mask &= ~BIT(2);
176
167
}
177
168
178
-
DPU_REG_WRITE(&ctx->hw, SSPP_MULTIRECT_OPMODE, mode_mask);
169
+
DPU_REG_WRITE(&ctx->hw, op_mode_off, mode_mask);
179
170
}
180
171
181
-
static void _sspp_setup_opmode(struct dpu_hw_sspp *ctx,
172
+
void dpu_hw_sspp_setup_opmode(struct dpu_hw_sspp *ctx,
182
173
u32 mask, u8 en)
183
174
{
184
175
const struct dpu_sspp_sub_blks *sblk = ctx->cap->sblk;
···
198
189
DPU_REG_WRITE(&ctx->hw, sblk->scaler_blk.base + SSPP_VIG_OP_MODE, opmode);
199
190
}
200
191
201
-
static void _sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx,
192
+
void dpu_hw_sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx,
202
193
u32 mask, u8 en)
203
194
{
204
195
const struct dpu_sspp_sub_blks *sblk = ctx->cap->sblk;
···
220
211
const struct msm_format *fmt, u32 flags)
221
212
{
222
213
struct dpu_hw_sspp *ctx = pipe->sspp;
223
-
struct dpu_hw_blk_reg_map *c;
224
-
u32 chroma_samp, unpack, src_format;
225
-
u32 opmode = 0;
226
-
u32 fast_clear = 0;
227
-
u32 op_mode_off, unpack_pat_off, format_off;
214
+
u32 op_mode_off, unpack_pat_off, format_off, ubwc_ctrl_off, ubwc_error_off;
228
215
229
216
if (!ctx || !fmt)
230
217
return;
···
230
225
op_mode_off = SSPP_SRC_OP_MODE;
231
226
unpack_pat_off = SSPP_SRC_UNPACK_PATTERN;
232
227
format_off = SSPP_SRC_FORMAT;
228
+
ubwc_ctrl_off = SSPP_UBWC_STATIC_CTRL;
229
+
ubwc_error_off = SSPP_UBWC_ERROR_STATUS;
233
230
} else {
234
231
op_mode_off = SSPP_SRC_OP_MODE_REC1;
235
232
unpack_pat_off = SSPP_SRC_UNPACK_PATTERN_REC1;
236
233
format_off = SSPP_SRC_FORMAT_REC1;
234
+
235
+
/* reg wasn't present before DPU 8.0 */
236
+
if (ctx->mdss_ver->core_major_ver >= 8) {
237
+
ubwc_ctrl_off = SSPP_UBWC_STATIC_CTRL_REC1;
238
+
ubwc_error_off = SSPP_UBWC_ERROR_STATUS_REC1;
239
+
} else {
240
+
ubwc_ctrl_off = SSPP_UBWC_STATIC_CTRL;
241
+
ubwc_error_off = SSPP_UBWC_ERROR_STATUS;
242
+
}
237
243
}
244
+
245
+
if (fmt->fetch_mode != MDP_FETCH_LINEAR) {
246
+
u32 hbb = ctx->ubwc->highest_bank_bit - 13;
247
+
248
+
DPU_REG_WRITE(&ctx->hw, SSPP_FETCH_CONFIG,
249
+
DPU_FETCH_CONFIG_RESET_VALUE |
250
+
hbb << 18);
251
+
}
252
+
253
+
dpu_hw_setup_format_impl(pipe, fmt, flags, ctx, op_mode_off,
254
+
unpack_pat_off, format_off,
255
+
ubwc_ctrl_off, ubwc_error_off);
256
+
}
257
+
258
+
void dpu_hw_setup_format_impl(struct dpu_sw_pipe *pipe, const struct msm_format *fmt,
259
+
u32 flags, struct dpu_hw_sspp *ctx, u32 op_mode_off,
260
+
u32 unpack_pat_off, u32 format_off, u32 ubwc_ctrl_off,
261
+
u32 ubwc_error_off)
262
+
{
263
+
struct dpu_hw_blk_reg_map *c;
264
+
u32 chroma_samp, unpack, src_format;
265
+
u32 opmode;
266
+
u32 fast_clear;
238
267
239
268
c = &ctx->hw;
240
269
opmode = DPU_REG_READ(c, op_mode_off);
···
309
270
((fmt->bpp - 1) << 9);
310
271
311
272
if (fmt->fetch_mode != MDP_FETCH_LINEAR) {
273
+
u32 hbb = ctx->ubwc->highest_bank_bit - 13;
274
+
u32 ctrl_val;
275
+
312
276
if (MSM_FORMAT_IS_UBWC(fmt))
313
277
opmode |= MDSS_MDP_OP_BWC_EN;
314
278
src_format |= (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */
315
-
DPU_REG_WRITE(c, SSPP_FETCH_CONFIG,
316
-
DPU_FETCH_CONFIG_RESET_VALUE |
317
-
ctx->ubwc->highest_bank_bit << 18);
318
-
switch (ctx->ubwc->ubwc_enc_version) {
319
-
case UBWC_1_0:
279
+
280
+
if (ctx->ubwc->ubwc_enc_version == UBWC_1_0) {
320
281
fast_clear = fmt->alpha_enable ? BIT(31) : 0;
321
-
DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
322
-
fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) |
323
-
BIT(8) |
324
-
(ctx->ubwc->highest_bank_bit << 4));
325
-
break;
326
-
case UBWC_2_0:
282
+
ctrl_val = fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) |
283
+
BIT(8) | (hbb << 4);
284
+
} else if (ctx->ubwc->ubwc_enc_version == UBWC_2_0) {
327
285
fast_clear = fmt->alpha_enable ? BIT(31) : 0;
328
-
DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
329
-
fast_clear | (ctx->ubwc->ubwc_swizzle) |
330
-
(ctx->ubwc->highest_bank_bit << 4));
331
-
break;
332
-
case UBWC_3_0:
333
-
DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
334
-
BIT(30) | (ctx->ubwc->ubwc_swizzle) |
335
-
(ctx->ubwc->highest_bank_bit << 4));
336
-
break;
337
-
case UBWC_4_0:
338
-
DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
339
-
MSM_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
340
-
break;
286
+
ctrl_val = fast_clear | ctx->ubwc->ubwc_swizzle | (hbb << 4);
287
+
} else if (ctx->ubwc->ubwc_enc_version == UBWC_3_0) {
288
+
ctrl_val = BIT(30) | (ctx->ubwc->ubwc_swizzle) | (hbb << 4);
289
+
} else if (ctx->ubwc->ubwc_enc_version == UBWC_4_0) {
290
+
ctrl_val = MSM_FORMAT_IS_YUV(fmt) ? 0 : BIT(30);
291
+
} else if (ctx->ubwc->ubwc_enc_version <= UBWC_6_0) {
292
+
if (MSM_FORMAT_IS_YUV(fmt))
293
+
ctrl_val = 0;
294
+
else if (MSM_FORMAT_IS_DX(fmt)) /* or FP16, but it's unsupported */
295
+
ctrl_val = BIT(30);
296
+
else
297
+
ctrl_val = BIT(30) | BIT(31);
298
+
/* SDE also sets bits for lossy formats, but we don't support them yet */
299
+
} else {
300
+
DRM_WARN_ONCE("Unsupported UBWC version %x\n", ctx->ubwc->ubwc_enc_version);
301
+
ctrl_val = 0;
341
302
}
303
+
304
+
DPU_REG_WRITE(c, ubwc_ctrl_off, ctrl_val);
342
305
}
343
306
344
307
opmode |= MDSS_MDP_OP_PE_OVERRIDE;
···
354
313
355
314
/* update scaler opmode, if appropriate */
356
315
if (test_bit(DPU_SSPP_CSC, &ctx->cap->features))
357
-
_sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT,
316
+
dpu_hw_sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT,
358
317
MSM_FORMAT_IS_YUV(fmt));
359
318
else if (test_bit(DPU_SSPP_CSC_10BIT, &ctx->cap->features))
360
-
_sspp_setup_csc10_opmode(ctx,
319
+
dpu_hw_sspp_setup_csc10_opmode(ctx,
361
320
VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT,
362
321
MSM_FORMAT_IS_YUV(fmt));
363
322
···
366
325
DPU_REG_WRITE(c, op_mode_off, opmode);
367
326
368
327
/* clear previous UBWC error */
369
-
DPU_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS, BIT(31));
328
+
DPU_REG_WRITE(c, ubwc_error_off, BIT(31));
370
329
}
371
330
372
331
static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx,
···
426
385
tot_req_pixels[3]);
427
386
}
428
387
429
-
static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
388
+
void dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
430
389
struct dpu_hw_scaler3_cfg *scaler3_cfg,
431
390
const struct msm_format *format)
432
391
{
···
446
405
struct dpu_sw_pipe_cfg *cfg)
447
406
{
448
407
struct dpu_hw_sspp *ctx = pipe->sspp;
449
-
struct dpu_hw_blk_reg_map *c;
450
-
u32 src_size, src_xy, dst_size, dst_xy;
451
408
u32 src_size_off, src_xy_off, out_size_off, out_xy_off;
452
409
453
410
if (!ctx || !cfg)
454
411
return;
455
-
456
-
c = &ctx->hw;
457
412
458
413
if (pipe->multirect_index == DPU_SSPP_RECT_SOLO ||
459
414
pipe->multirect_index == DPU_SSPP_RECT_0) {
···
464
427
out_xy_off = SSPP_OUT_XY_REC1;
465
428
}
466
429
467
-
468
-
/* src and dest rect programming */
469
-
src_xy = (cfg->src_rect.y1 << 16) | cfg->src_rect.x1;
470
-
src_size = (drm_rect_height(&cfg->src_rect) << 16) |
471
-
drm_rect_width(&cfg->src_rect);
472
-
dst_xy = (cfg->dst_rect.y1 << 16) | cfg->dst_rect.x1;
473
-
dst_size = (drm_rect_height(&cfg->dst_rect) << 16) |
474
-
drm_rect_width(&cfg->dst_rect);
475
-
476
-
/* rectangle register programming */
477
-
DPU_REG_WRITE(c, src_size_off, src_size);
478
-
DPU_REG_WRITE(c, src_xy_off, src_xy);
479
-
DPU_REG_WRITE(c, out_size_off, dst_size);
480
-
DPU_REG_WRITE(c, out_xy_off, dst_xy);
430
+
dpu_hw_setup_rects_impl(pipe, cfg, ctx, src_size_off,
431
+
src_xy_off, out_size_off, out_xy_off);
481
432
}
482
433
483
434
static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
···
522
497
DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE1, ystride1);
523
498
}
524
499
525
-
static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
500
+
void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
526
501
const struct dpu_csc_cfg *data)
527
502
{
528
503
u32 offset;
···
544
519
static void dpu_hw_sspp_setup_solidfill(struct dpu_sw_pipe *pipe, u32 color)
545
520
{
546
521
struct dpu_hw_sspp *ctx = pipe->sspp;
547
-
struct dpu_hw_fmt_layout cfg;
522
+
u32 const_clr_off;
548
523
549
524
if (!ctx)
550
525
return;
526
+
527
+
if (pipe->multirect_index == DPU_SSPP_RECT_SOLO ||
528
+
pipe->multirect_index == DPU_SSPP_RECT_0)
529
+
const_clr_off = SSPP_SRC_CONSTANT_COLOR;
530
+
else
531
+
const_clr_off = SSPP_SRC_CONSTANT_COLOR_REC1;
532
+
533
+
dpu_hw_setup_solidfill_impl(pipe, color, ctx, const_clr_off);
534
+
}
535
+
536
+
void dpu_hw_setup_solidfill_impl(struct dpu_sw_pipe *pipe,
537
+
u32 color, struct dpu_hw_sspp *ctx,
538
+
u32 const_clr_off)
539
+
{
540
+
struct dpu_hw_fmt_layout cfg;
551
541
552
542
/* cleanup source addresses */
553
543
memset(&cfg, 0, sizeof(cfg));
554
544
ctx->ops.setup_sourceaddress(pipe, &cfg);
555
545
556
-
if (pipe->multirect_index == DPU_SSPP_RECT_SOLO ||
557
-
pipe->multirect_index == DPU_SSPP_RECT_0)
558
-
DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR, color);
559
-
else
560
-
DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR_REC1,
561
-
color);
546
+
DPU_REG_WRITE(&ctx->hw, const_clr_off, color);
562
547
}
563
548
564
549
static void dpu_hw_sspp_setup_qos_lut(struct dpu_hw_sspp *ctx,
···
582
547
cfg);
583
548
}
584
549
550
+
void dpu_hw_sspp_setup_qos_ctrl_impl(struct dpu_hw_sspp *ctx,
551
+
bool danger_safe_en, u32 ctrl_off)
552
+
{
553
+
DPU_REG_WRITE(&ctx->hw, ctrl_off,
554
+
danger_safe_en ? SSPP_QOS_CTRL_DANGER_SAFE_EN : 0);
555
+
}
556
+
585
557
static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp *ctx,
586
558
bool danger_safe_en)
587
559
{
588
560
if (!ctx)
589
561
return;
590
562
591
-
DPU_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL,
592
-
danger_safe_en ? SSPP_QOS_CTRL_DANGER_SAFE_EN : 0);
563
+
dpu_hw_sspp_setup_qos_ctrl_impl(ctx, danger_safe_en, SSPP_QOS_CTRL);
593
564
}
594
565
595
566
static void dpu_hw_sspp_setup_cdp(struct dpu_sw_pipe *pipe,
···
650
609
c->ops.setup_multirect = dpu_hw_sspp_setup_multirect;
651
610
652
611
if (test_bit(DPU_SSPP_SCALER_QSEED3_COMPATIBLE, &features))
653
-
c->ops.setup_scaler = _dpu_hw_sspp_setup_scaler3;
612
+
c->ops.setup_scaler = dpu_hw_sspp_setup_scaler3;
654
613
655
614
if (test_bit(DPU_SSPP_CDP, &features))
656
615
c->ops.setup_cdp = dpu_hw_sspp_setup_cdp;
···
747
706
748
707
hw_pipe->mdss_ver = mdss_rev;
749
708
750
-
_setup_layer_ops(hw_pipe, hw_pipe->cap->features, mdss_rev);
709
+
if (mdss_rev->core_major_ver >= 13)
710
+
dpu_hw_sspp_init_v13(hw_pipe, hw_pipe->cap->features, mdss_rev);
711
+
else
712
+
_setup_layer_ops(hw_pipe, hw_pipe->cap->features, mdss_rev);
751
713
752
714
return hw_pipe;
753
715
}
+56
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
+56
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
···
332
332
int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms,
333
333
struct dentry *entry);
334
334
335
+
void dpu_hw_sspp_setup_opmode(struct dpu_hw_sspp *ctx,
336
+
u32 mask, u8 en);
337
+
338
+
void dpu_hw_sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx,
339
+
u32 mask, u8 en);
340
+
341
+
void dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
342
+
struct dpu_hw_scaler3_cfg *scaler3_cfg,
343
+
const struct msm_format *format);
344
+
345
+
void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
346
+
const struct dpu_csc_cfg *data);
347
+
348
+
void dpu_hw_setup_multirect_impl(struct dpu_sw_pipe *pipe,
349
+
struct dpu_hw_sspp *ctx,
350
+
u32 op_mode_off);
351
+
352
+
void dpu_hw_setup_format_impl(struct dpu_sw_pipe *pipe, const struct msm_format *fmt,
353
+
u32 flags, struct dpu_hw_sspp *ctx,
354
+
u32 op_mode_off, u32 unpack_pat_off, u32 format_off,
355
+
u32 ubwc_ctrl_off, u32 ubwc_err_off);
356
+
357
+
static inline void dpu_hw_setup_rects_impl(struct dpu_sw_pipe *pipe, struct dpu_sw_pipe_cfg *cfg,
358
+
struct dpu_hw_sspp *ctx, u32 src_size_off,
359
+
u32 src_xy_off, u32 out_size_off, u32 out_xy_off)
360
+
{
361
+
struct dpu_hw_blk_reg_map *c;
362
+
u32 src_size, src_xy, dst_size, dst_xy;
363
+
364
+
c = &ctx->hw;
365
+
366
+
/* src and dest rect programming */
367
+
src_xy = (cfg->src_rect.y1 << 16) | cfg->src_rect.x1;
368
+
src_size = (drm_rect_height(&cfg->src_rect) << 16) |
369
+
drm_rect_width(&cfg->src_rect);
370
+
dst_xy = (cfg->dst_rect.y1 << 16) | cfg->dst_rect.x1;
371
+
dst_size = (drm_rect_height(&cfg->dst_rect) << 16) |
372
+
drm_rect_width(&cfg->dst_rect);
373
+
374
+
/* rectangle register programming */
375
+
DPU_REG_WRITE(c, src_size_off, src_size);
376
+
DPU_REG_WRITE(c, src_xy_off, src_xy);
377
+
DPU_REG_WRITE(c, out_size_off, dst_size);
378
+
DPU_REG_WRITE(c, out_xy_off, dst_xy);
379
+
}
380
+
381
+
void dpu_hw_setup_solidfill_impl(struct dpu_sw_pipe *pipe,
382
+
u32 color, struct dpu_hw_sspp *ctx, u32 const_clr_off);
383
+
384
+
void dpu_hw_sspp_setup_qos_ctrl_impl(struct dpu_hw_sspp *ctx,
385
+
bool danger_safe_en, u32 ctrl_off);
386
+
387
+
void dpu_hw_sspp_init_v13(struct dpu_hw_sspp *c,
388
+
unsigned long features,
389
+
const struct dpu_mdss_version *mdss_rev);
390
+
335
391
#endif /*_DPU_HW_SSPP_H */
336
392
+321
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c
+321
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c
···
1
+
// SPDX-License-Identifier: BSD-3-Clause
2
+
/*
3
+
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
4
+
*/
5
+
6
+
#include <linux/printk.h>
7
+
#include <linux/soc/qcom/ubwc.h>
8
+
9
+
#include "dpu_hw_sspp.h"
10
+
11
+
/* >= v13 DPU */
12
+
/* CMN Registers -> Source Surface Processing Pipe Common SSPP registers */
13
+
/* Name Offset */
14
+
#define SSPP_CMN_CLK_CTRL 0x0
15
+
#define SSPP_CMN_CLK_STATUS 0x4
16
+
#define SSPP_CMN_MULTI_REC_OP_MODE 0x10
17
+
#define SSPP_CMN_ADDR_CONFIG 0x14
18
+
#define SSPP_CMN_CAC_CTRL 0x20
19
+
#define SSPP_CMN_SYS_CACHE_MODE 0x24
20
+
#define SSPP_CMN_QOS_CTRL 0x28
21
+
22
+
#define SSPP_CMN_FILL_LEVEL_SCALE 0x3c
23
+
#define SSPP_CMN_FILL_LEVELS 0x40
24
+
#define SSPP_CMN_STATUS 0x44
25
+
#define SSPP_CMN_FETCH_DMA_RD_OTS 0x48
26
+
#define SSPP_CMN_FETCH_DTB_WR_PLANE0 0x4c
27
+
#define SSPP_CMN_FETCH_DTB_WR_PLANE1 0x50
28
+
#define SSPP_CMN_FETCH_DTB_WR_PLANE2 0x54
29
+
#define SSPP_CMN_DTB_UNPACK_RD_PLANE0 0x58
30
+
#define SSPP_CMN_DTB_UNPACK_RD_PLANE1 0x5c
31
+
#define SSPP_CMN_DTB_UNPACK_RD_PLANE2 0x60
32
+
#define SSPP_CMN_UNPACK_LINE_COUNT 0x64
33
+
#define SSPP_CMN_TPG_CONTROL 0x68
34
+
#define SSPP_CMN_TPG_CONFIG 0x6c
35
+
#define SSPP_CMN_TPG_COMPONENT_LIMITS 0x70
36
+
#define SSPP_CMN_TPG_RECTANGLE 0x74
37
+
#define SSPP_CMN_TPG_BLACK_WHITE_PATTERN_FRAMES 0x78
38
+
#define SSPP_CMN_TPG_RGB_MAPPING 0x7c
39
+
#define SSPP_CMN_TPG_PATTERN_GEN_INIT_VAL 0x80
40
+
41
+
/*RECRegisterset*/
42
+
/*Name Offset*/
43
+
#define SSPP_REC_SRC_FORMAT 0x0
44
+
#define SSPP_REC_SRC_UNPACK_PATTERN 0x4
45
+
#define SSPP_REC_SRC_OP_MODE 0x8
46
+
#define SSPP_REC_SRC_CONSTANT_COLOR 0xc
47
+
#define SSPP_REC_SRC_IMG_SIZE 0x10
48
+
#define SSPP_REC_SRC_SIZE 0x14
49
+
#define SSPP_REC_SRC_XY 0x18
50
+
#define SSPP_REC_OUT_SIZE 0x1c
51
+
#define SSPP_REC_OUT_XY 0x20
52
+
#define SSPP_REC_SW_PIX_EXT_LR 0x24
53
+
#define SSPP_REC_SW_PIX_EXT_TB 0x28
54
+
#define SSPP_REC_SRC_SIZE_ODX 0x30
55
+
#define SSPP_REC_SRC_XY_ODX 0x34
56
+
#define SSPP_REC_OUT_SIZE_ODX 0x38
57
+
#define SSPP_REC_OUT_XY_ODX 0x3c
58
+
#define SSPP_REC_SW_PIX_EXT_LR_ODX 0x40
59
+
#define SSPP_REC_SW_PIX_EXT_TB_ODX 0x44
60
+
#define SSPP_REC_PRE_DOWN_SCALE 0x48
61
+
#define SSPP_REC_SRC0_ADDR 0x4c
62
+
#define SSPP_REC_SRC1_ADDR 0x50
63
+
#define SSPP_REC_SRC2_ADDR 0x54
64
+
#define SSPP_REC_SRC3_ADDR 0x58
65
+
#define SSPP_REC_SRC_YSTRIDE0 0x5c
66
+
#define SSPP_REC_SRC_YSTRIDE1 0x60
67
+
#define SSPP_REC_CURRENT_SRC0_ADDR 0x64
68
+
#define SSPP_REC_CURRENT_SRC1_ADDR 0x68
69
+
#define SSPP_REC_CURRENT_SRC2_ADDR 0x6c
70
+
#define SSPP_REC_CURRENT_SRC3_ADDR 0x70
71
+
#define SSPP_REC_SRC_ADDR_SW_STATUS 0x74
72
+
#define SSPP_REC_CDP_CNTL 0x78
73
+
#define SSPP_REC_TRAFFIC_SHAPER 0x7c
74
+
#define SSPP_REC_TRAFFIC_SHAPER_PREFILL 0x80
75
+
#define SSPP_REC_PD_MEM_ALLOC 0x84
76
+
#define SSPP_REC_QOS_CLAMP 0x88
77
+
#define SSPP_REC_UIDLE_CTRL_VALUE 0x8c
78
+
#define SSPP_REC_UBWC_STATIC_CTRL 0x90
79
+
#define SSPP_REC_UBWC_STATIC_CTRL_OVERRIDE 0x94
80
+
#define SSPP_REC_UBWC_STATS_ROI 0x98
81
+
#define SSPP_REC_UBWC_STATS_WORST_TILE_ROW_BW_ROI0 0x9c
82
+
#define SSPP_REC_UBWC_STATS_TOTAL_BW_ROI0 0xa0
83
+
#define SSPP_REC_UBWC_STATS_WORST_TILE_ROW_BW_ROI1 0xa4
84
+
#define SSPP_REC_UBWC_STATS_TOTAL_BW_ROI1 0xa8
85
+
#define SSPP_REC_UBWC_STATS_WORST_TILE_ROW_BW_ROI2 0xac
86
+
#define SSPP_REC_UBWC_STATS_TOTAL_BW_ROI2 0xb0
87
+
#define SSPP_REC_EXCL_REC_CTRL 0xb4
88
+
#define SSPP_REC_EXCL_REC_SIZE 0xb8
89
+
#define SSPP_REC_EXCL_REC_XY 0xbc
90
+
#define SSPP_REC_LINE_INSERTION_CTRL 0xc0
91
+
#define SSPP_REC_LINE_INSERTION_OUT_SIZE 0xc4
92
+
#define SSPP_REC_FETCH_PIPE_ACTIVE 0xc8
93
+
#define SSPP_REC_META_ERROR_STATUS 0xcc
94
+
#define SSPP_REC_UBWC_ERROR_STATUS 0xd0
95
+
#define SSPP_REC_FLUSH_CTRL 0xd4
96
+
#define SSPP_REC_INTR_EN 0xd8
97
+
#define SSPP_REC_INTR_STATUS 0xdc
98
+
#define SSPP_REC_INTR_CLEAR 0xe0
99
+
#define SSPP_REC_HSYNC_STATUS 0xe4
100
+
#define SSPP_REC_FP16_CONFIG 0x150
101
+
#define SSPP_REC_FP16_CSC_MATRIX_COEFF_R_0 0x154
102
+
#define SSPP_REC_FP16_CSC_MATRIX_COEFF_R_1 0x158
103
+
#define SSPP_REC_FP16_CSC_MATRIX_COEFF_G_0 0x15c
104
+
#define SSPP_REC_FP16_CSC_MATRIX_COEFF_G_1 0x160
105
+
#define SSPP_REC_FP16_CSC_MATRIX_COEFF_B_0 0x164
106
+
#define SSPP_REC_FP16_CSC_MATRIX_COEFF_B_1 0x168
107
+
#define SSPP_REC_FP16_CSC_PRE_CLAMP_R 0x16c
108
+
#define SSPP_REC_FP16_CSC_PRE_CLAMP_G 0x170
109
+
#define SSPP_REC_FP16_CSC_PRE_CLAMP_B 0x174
110
+
#define SSPP_REC_FP16_CSC_POST_CLAMP 0x178
111
+
112
+
static inline u32 dpu_hw_sspp_calculate_rect_off(enum dpu_sspp_multirect_index rect_index,
113
+
struct dpu_hw_sspp *ctx)
114
+
{
115
+
return (rect_index == DPU_SSPP_RECT_SOLO || rect_index == DPU_SSPP_RECT_0) ?
116
+
ctx->cap->sblk->sspp_rec0_blk.base : ctx->cap->sblk->sspp_rec1_blk.base;
117
+
}
118
+
119
+
static void dpu_hw_sspp_setup_multirect_v13(struct dpu_sw_pipe *pipe)
120
+
{
121
+
struct dpu_hw_sspp *ctx = pipe->sspp;
122
+
123
+
if (!ctx)
124
+
return;
125
+
126
+
dpu_hw_setup_multirect_impl(pipe, ctx, SSPP_CMN_MULTI_REC_OP_MODE);
127
+
}
128
+
129
+
static void dpu_hw_sspp_setup_format_v13(struct dpu_sw_pipe *pipe,
130
+
const struct msm_format *fmt, u32 flags)
131
+
{
132
+
struct dpu_hw_sspp *ctx = pipe->sspp;
133
+
u32 op_mode_off, unpack_pat_off, format_off;
134
+
u32 ubwc_ctrl_off, ubwc_err_off;
135
+
u32 offset;
136
+
137
+
if (!ctx || !fmt)
138
+
return;
139
+
140
+
offset = dpu_hw_sspp_calculate_rect_off(pipe->multirect_index, ctx);
141
+
142
+
op_mode_off = offset + SSPP_REC_SRC_OP_MODE;
143
+
unpack_pat_off = offset + SSPP_REC_SRC_UNPACK_PATTERN;
144
+
format_off = offset + SSPP_REC_SRC_FORMAT;
145
+
ubwc_ctrl_off = offset + SSPP_REC_UBWC_STATIC_CTRL;
146
+
ubwc_err_off = offset + SSPP_REC_UBWC_ERROR_STATUS;
147
+
148
+
dpu_hw_setup_format_impl(pipe, fmt, flags, ctx, op_mode_off,
149
+
unpack_pat_off, format_off, ubwc_ctrl_off, ubwc_err_off);
150
+
}
151
+
152
+
static void dpu_hw_sspp_setup_pe_config_v13(struct dpu_hw_sspp *ctx,
153
+
struct dpu_hw_pixel_ext *pe_ext)
154
+
{
155
+
struct dpu_hw_blk_reg_map *c;
156
+
u8 color;
157
+
u32 lr_pe[4], tb_pe[4];
158
+
const u32 bytemask = 0xff;
159
+
u32 offset = ctx->cap->sblk->sspp_rec0_blk.base;
160
+
161
+
if (!ctx || !pe_ext)
162
+
return;
163
+
164
+
c = &ctx->hw;
165
+
/* program SW pixel extension override for all pipes*/
166
+
for (color = 0; color < DPU_MAX_PLANES; color++) {
167
+
/* color 2 has the same set of registers as color 1 */
168
+
if (color == 2)
169
+
continue;
170
+
171
+
lr_pe[color] = ((pe_ext->right_ftch[color] & bytemask) << 24) |
172
+
((pe_ext->right_rpt[color] & bytemask) << 16) |
173
+
((pe_ext->left_ftch[color] & bytemask) << 8) |
174
+
(pe_ext->left_rpt[color] & bytemask);
175
+
176
+
tb_pe[color] = ((pe_ext->btm_ftch[color] & bytemask) << 24) |
177
+
((pe_ext->btm_rpt[color] & bytemask) << 16) |
178
+
((pe_ext->top_ftch[color] & bytemask) << 8) |
179
+
(pe_ext->top_rpt[color] & bytemask);
180
+
}
181
+
182
+
/* color 0 */
183
+
DPU_REG_WRITE(c, SSPP_REC_SW_PIX_EXT_LR + offset, lr_pe[0]);
184
+
DPU_REG_WRITE(c, SSPP_REC_SW_PIX_EXT_TB + offset, tb_pe[0]);
185
+
186
+
/* color 1 and color 2 */
187
+
DPU_REG_WRITE(c, SSPP_REC_SW_PIX_EXT_LR_ODX + offset, lr_pe[1]);
188
+
DPU_REG_WRITE(c, SSPP_REC_SW_PIX_EXT_TB_ODX + offset, tb_pe[1]);
189
+
}
190
+
191
+
static void dpu_hw_sspp_setup_rects_v13(struct dpu_sw_pipe *pipe,
192
+
struct dpu_sw_pipe_cfg *cfg)
193
+
{
194
+
struct dpu_hw_sspp *ctx = pipe->sspp;
195
+
u32 src_size_off, src_xy_off, out_size_off, out_xy_off;
196
+
u32 offset;
197
+
198
+
if (!ctx || !cfg)
199
+
return;
200
+
201
+
offset = dpu_hw_sspp_calculate_rect_off(pipe->multirect_index, ctx);
202
+
203
+
src_size_off = offset + SSPP_REC_SRC_SIZE;
204
+
src_xy_off = offset + SSPP_REC_SRC_XY;
205
+
out_size_off = offset + SSPP_REC_OUT_SIZE;
206
+
out_xy_off = offset + SSPP_REC_OUT_XY;
207
+
208
+
dpu_hw_setup_rects_impl(pipe, cfg, ctx, src_size_off,
209
+
src_xy_off, out_size_off, out_xy_off);
210
+
}
211
+
212
+
static void dpu_hw_sspp_setup_sourceaddress_v13(struct dpu_sw_pipe *pipe,
213
+
struct dpu_hw_fmt_layout *layout)
214
+
{
215
+
struct dpu_hw_sspp *ctx = pipe->sspp;
216
+
int i;
217
+
u32 offset, ystride0, ystride1;
218
+
219
+
if (!ctx)
220
+
return;
221
+
222
+
offset = dpu_hw_sspp_calculate_rect_off(pipe->multirect_index, ctx);
223
+
224
+
for (i = 0; i < ARRAY_SIZE(layout->plane_addr); i++)
225
+
DPU_REG_WRITE(&ctx->hw, offset + SSPP_REC_SRC0_ADDR + i * 0x4,
226
+
layout->plane_addr[i]);
227
+
228
+
ystride0 = (layout->plane_pitch[0]) | (layout->plane_pitch[2] << 16);
229
+
ystride1 = (layout->plane_pitch[1]) | (layout->plane_pitch[3] << 16);
230
+
231
+
DPU_REG_WRITE(&ctx->hw, offset + SSPP_REC_SRC_YSTRIDE0, ystride0);
232
+
DPU_REG_WRITE(&ctx->hw, offset + SSPP_REC_SRC_YSTRIDE1, ystride1);
233
+
}
234
+
235
+
static void dpu_hw_sspp_setup_solidfill_v13(struct dpu_sw_pipe *pipe, u32 color)
236
+
{
237
+
struct dpu_hw_sspp *ctx = pipe->sspp;
238
+
u32 const_clr_off;
239
+
u32 offset;
240
+
241
+
if (!ctx)
242
+
return;
243
+
244
+
offset = dpu_hw_sspp_calculate_rect_off(pipe->multirect_index, ctx);
245
+
const_clr_off = offset + SSPP_REC_SRC_CONSTANT_COLOR;
246
+
247
+
dpu_hw_setup_solidfill_impl(pipe, color, ctx, const_clr_off);
248
+
}
249
+
250
+
static void dpu_hw_sspp_setup_qos_lut_v13(struct dpu_hw_sspp *ctx,
251
+
struct dpu_hw_qos_cfg *cfg)
252
+
{
253
+
if (!ctx || !cfg)
254
+
return;
255
+
256
+
dpu_hw_setup_qos_lut_v13(&ctx->hw, cfg);
257
+
}
258
+
259
+
static void dpu_hw_sspp_setup_qos_ctrl_v13(struct dpu_hw_sspp *ctx,
260
+
bool danger_safe_en)
261
+
{
262
+
if (!ctx)
263
+
return;
264
+
265
+
dpu_hw_sspp_setup_qos_ctrl_impl(ctx, danger_safe_en, SSPP_CMN_QOS_CTRL);
266
+
}
267
+
268
+
static void dpu_hw_sspp_setup_cdp_v13(struct dpu_sw_pipe *pipe,
269
+
const struct msm_format *fmt,
270
+
bool enable)
271
+
{
272
+
struct dpu_hw_sspp *ctx = pipe->sspp;
273
+
u32 offset = 0;
274
+
275
+
if (!ctx)
276
+
return;
277
+
278
+
offset = dpu_hw_sspp_calculate_rect_off(pipe->multirect_index, ctx);
279
+
dpu_setup_cdp(&ctx->hw, offset + SSPP_REC_CDP_CNTL, fmt, enable);
280
+
}
281
+
282
+
static bool dpu_hw_sspp_setup_clk_force_ctrl_v13(struct dpu_hw_sspp *ctx, bool enable)
283
+
{
284
+
static const struct dpu_clk_ctrl_reg sspp_clk_ctrl = {
285
+
.reg_off = SSPP_CMN_CLK_CTRL,
286
+
.bit_off = 0
287
+
};
288
+
289
+
return dpu_hw_clk_force_ctrl(&ctx->hw, &sspp_clk_ctrl, enable);
290
+
}
291
+
292
+
void dpu_hw_sspp_init_v13(struct dpu_hw_sspp *c,
293
+
unsigned long features, const struct dpu_mdss_version *mdss_rev)
294
+
{
295
+
c->ops.setup_format = dpu_hw_sspp_setup_format_v13;
296
+
c->ops.setup_rects = dpu_hw_sspp_setup_rects_v13;
297
+
c->ops.setup_sourceaddress = dpu_hw_sspp_setup_sourceaddress_v13;
298
+
c->ops.setup_solidfill = dpu_hw_sspp_setup_solidfill_v13;
299
+
c->ops.setup_pe = dpu_hw_sspp_setup_pe_config_v13;
300
+
301
+
if (test_bit(DPU_SSPP_QOS, &features)) {
302
+
c->ops.setup_qos_lut = dpu_hw_sspp_setup_qos_lut_v13;
303
+
c->ops.setup_qos_ctrl = dpu_hw_sspp_setup_qos_ctrl_v13;
304
+
}
305
+
306
+
if (test_bit(DPU_SSPP_CSC, &features) ||
307
+
test_bit(DPU_SSPP_CSC_10BIT, &features))
308
+
c->ops.setup_csc = dpu_hw_sspp_setup_csc;
309
+
310
+
if (test_bit(DPU_SSPP_SMART_DMA_V1, &c->cap->features) ||
311
+
test_bit(DPU_SSPP_SMART_DMA_V2, &c->cap->features))
312
+
c->ops.setup_multirect = dpu_hw_sspp_setup_multirect_v13;
313
+
314
+
if (test_bit(DPU_SSPP_SCALER_QSEED3_COMPATIBLE, &features))
315
+
c->ops.setup_scaler = dpu_hw_sspp_setup_scaler3;
316
+
317
+
if (test_bit(DPU_SSPP_CDP, &features))
318
+
c->ops.setup_cdp = dpu_hw_sspp_setup_cdp_v13;
319
+
320
+
c->ops.setup_clk_force_ctrl = dpu_hw_sspp_setup_clk_force_ctrl_v13;
321
+
}
-7
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
-7
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
···
22
22
#define TRAFFIC_SHAPER_WR_CLIENT(num) (0x060 + (num * 4))
23
23
#define TRAFFIC_SHAPER_FIXPOINT_FACTOR 4
24
24
25
-
#define MDP_TICK_COUNT 16
26
-
#define XO_CLK_RATE 19200
27
-
#define MS_TICKS_IN_SEC 1000
28
-
29
-
#define CALCULATE_WD_LOAD_VALUE(fps) \
30
-
((uint32_t)((MS_TICKS_IN_SEC * XO_CLK_RATE)/(MDP_TICK_COUNT * fps)))
31
-
32
25
static void dpu_hw_setup_split_pipe(struct dpu_hw_mdp *mdp,
33
26
struct split_pipe_cfg *cfg)
34
27
{
+18
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
+18
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
···
81
81
#define QOS_CREQ_LUT_0 0x14
82
82
#define QOS_CREQ_LUT_1 0x18
83
83
84
+
/* CMN_QOS_LUT */
85
+
#define SSPP_CMN_QOS_CTRL 0x28
86
+
#define SSPP_CMN_DANGER_LUT 0x2c
87
+
#define SSPP_CMN_SAFE_LUT 0x30
88
+
#define SSPP_CMN_CREQ_LUT_0 0x34
89
+
#define SSPP_CMN_CREQ_LUT_1 0x38
90
+
84
91
/* QOS_QOS_CTRL */
85
92
#define QOS_QOS_CTRL_DANGER_SAFE_EN BIT(0)
86
93
#define QOS_QOS_CTRL_DANGER_VBLANK_MASK GENMASK(5, 4)
···
479
472
}
480
473
481
474
DPU_REG_WRITE(c, offset + QOS_QOS_CTRL,
475
+
cfg->danger_safe_en ? QOS_QOS_CTRL_DANGER_SAFE_EN : 0);
476
+
}
477
+
478
+
void dpu_hw_setup_qos_lut_v13(struct dpu_hw_blk_reg_map *c,
479
+
const struct dpu_hw_qos_cfg *cfg)
480
+
{
481
+
DPU_REG_WRITE(c, SSPP_CMN_DANGER_LUT, cfg->danger_lut);
482
+
DPU_REG_WRITE(c, SSPP_CMN_SAFE_LUT, cfg->safe_lut);
483
+
DPU_REG_WRITE(c, SSPP_CMN_CREQ_LUT_0, cfg->creq_lut);
484
+
DPU_REG_WRITE(c, SSPP_CMN_CREQ_LUT_1, cfg->creq_lut >> 32);
485
+
DPU_REG_WRITE(c, SSPP_CMN_QOS_CTRL,
482
486
cfg->danger_safe_en ? QOS_QOS_CTRL_DANGER_SAFE_EN : 0);
483
487
}
484
488
+10
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
+10
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
···
21
21
22
22
#define TO_S15D16(_x_)((_x_) << 7)
23
23
24
+
#define MDP_TICK_COUNT 16
25
+
#define XO_CLK_RATE 19200
26
+
#define MS_TICKS_IN_SEC 1000
27
+
28
+
#define CALCULATE_WD_LOAD_VALUE(fps) \
29
+
((uint32_t)((MS_TICKS_IN_SEC * XO_CLK_RATE)/(MDP_TICK_COUNT * fps)))
30
+
24
31
extern const struct dpu_csc_cfg dpu_csc_YUV2RGB_601L;
25
32
extern const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L;
26
33
extern const struct dpu_csc_cfg dpu_csc10_rgb2yuv_601l;
···
366
359
void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *c, u32 offset,
367
360
bool qos_8lvl,
368
361
const struct dpu_hw_qos_cfg *cfg);
362
+
363
+
void dpu_hw_setup_qos_lut_v13(struct dpu_hw_blk_reg_map *c,
364
+
const struct dpu_hw_qos_cfg *cfg);
369
365
370
366
void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c,
371
367
u32 misr_ctrl_offset, u8 input_sel);
+15
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
+15
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
···
148
148
cfg);
149
149
}
150
150
151
+
static void dpu_hw_wb_setup_qos_lut_v13(struct dpu_hw_wb *ctx,
152
+
struct dpu_hw_qos_cfg *cfg)
153
+
{
154
+
if (!ctx || !cfg)
155
+
return;
156
+
157
+
dpu_hw_setup_qos_lut_v13(&ctx->hw, cfg);
158
+
}
159
+
151
160
static void dpu_hw_wb_setup_cdp(struct dpu_hw_wb *ctx,
152
161
const struct msm_format *fmt,
153
162
bool enable)
···
211
202
if (test_bit(DPU_WB_XY_ROI_OFFSET, &features))
212
203
ops->setup_roi = dpu_hw_wb_roi;
213
204
214
-
if (test_bit(DPU_WB_QOS, &features))
215
-
ops->setup_qos_lut = dpu_hw_wb_setup_qos_lut;
205
+
if (test_bit(DPU_WB_QOS, &features)) {
206
+
if (mdss_rev->core_major_ver >= 13)
207
+
ops->setup_qos_lut = dpu_hw_wb_setup_qos_lut_v13;
208
+
else
209
+
ops->setup_qos_lut = dpu_hw_wb_setup_qos_lut;
210
+
}
216
211
217
212
if (test_bit(DPU_WB_CDP, &features))
218
213
ops->setup_cdp = dpu_hw_wb_setup_cdp;
+1
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+1
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
···
1506
1506
1507
1507
static const struct of_device_id dpu_dt_match[] = {
1508
1508
{ .compatible = "qcom,glymur-dpu", .data = &dpu_glymur_cfg, },
1509
+
{ .compatible = "qcom,kaanapali-dpu", .data = &dpu_kaanapali_cfg, },
1509
1510
{ .compatible = "qcom,msm8917-mdp5", .data = &dpu_msm8917_cfg, },
1510
1511
{ .compatible = "qcom,msm8937-mdp5", .data = &dpu_msm8937_cfg, },
1511
1512
{ .compatible = "qcom,msm8953-mdp5", .data = &dpu_msm8953_cfg, },
+47
-25
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+47
-25
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
···
315
315
316
316
/* Already reserved? */
317
317
if (reserved_by_other(global_state->mixer_to_crtc_id, lm_idx, crtc_id)) {
318
-
DPU_DEBUG("lm %d already reserved\n", lm_idx + LM_0);
318
+
DPU_DEBUG("LM_%d already reserved\n", lm_idx);
319
319
return false;
320
320
}
321
321
322
322
lm_cfg = to_dpu_hw_mixer(rm->mixer_blks[lm_idx])->cap;
323
323
idx = lm_cfg->pingpong - PINGPONG_0;
324
-
if (idx < 0 || idx >= ARRAY_SIZE(rm->pingpong_blks)) {
325
-
DPU_ERROR("failed to get pp on lm %d\n", lm_cfg->pingpong);
324
+
if (idx < 0 || idx >= ARRAY_SIZE(rm->pingpong_blks) || !rm->pingpong_blks[idx]) {
325
+
DPU_ERROR("LM_%d, invalid PP_%d\n", lm_idx, idx);
326
326
return false;
327
327
}
328
328
329
329
if (reserved_by_other(global_state->pingpong_to_crtc_id, idx, crtc_id)) {
330
-
DPU_DEBUG("lm %d pp %d already reserved\n", lm_cfg->id,
331
-
lm_cfg->pingpong);
330
+
DPU_DEBUG("LM_%d PP_%d already reserved\n", lm_idx, idx);
332
331
return false;
333
332
}
334
333
*pp_idx = idx;
···
336
337
return true;
337
338
338
339
idx = lm_cfg->dspp - DSPP_0;
339
-
if (idx < 0 || idx >= ARRAY_SIZE(rm->dspp_blks)) {
340
-
DPU_ERROR("failed to get dspp on lm %d\n", lm_cfg->dspp);
340
+
if (idx < 0 || idx >= ARRAY_SIZE(rm->dspp_blks) || !rm->dspp_blks[idx]) {
341
+
DPU_ERROR("LM_%d, invalid DSPP_%d\n", lm_idx, idx);
341
342
return false;
342
343
}
343
344
344
345
if (reserved_by_other(global_state->dspp_to_crtc_id, idx, crtc_id)) {
345
-
DPU_DEBUG("lm %d dspp %d already reserved\n", lm_cfg->id,
346
-
lm_cfg->dspp);
346
+
DPU_DEBUG("LM_%d DSPP_%d already reserved\n", lm_idx, idx);
347
347
return false;
348
348
}
349
349
*dspp_idx = idx;
···
350
352
return true;
351
353
}
352
354
353
-
static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
354
-
struct dpu_global_state *global_state,
355
-
uint32_t crtc_id,
356
-
struct msm_display_topology *topology)
355
+
static bool dpu_rm_find_lms(struct dpu_rm *rm,
356
+
struct dpu_global_state *global_state,
357
+
uint32_t crtc_id, bool skip_dspp,
358
+
struct msm_display_topology *topology,
359
+
int *lm_idx, int *pp_idx, int *dspp_idx)
357
360
358
361
{
359
-
int lm_idx[MAX_BLOCKS];
360
-
int pp_idx[MAX_BLOCKS];
361
-
int dspp_idx[MAX_BLOCKS] = {0};
362
362
int i, lm_count = 0;
363
-
364
-
if (!topology->num_lm) {
365
-
DPU_ERROR("invalid number of lm: %d\n", topology->num_lm);
366
-
return -EINVAL;
367
-
}
368
363
369
364
/* Find a primary mixer */
370
365
for (i = 0; i < ARRAY_SIZE(rm->mixer_blks) &&
371
366
lm_count < topology->num_lm; i++) {
372
367
if (!rm->mixer_blks[i])
373
368
continue;
369
+
370
+
if (skip_dspp && to_dpu_hw_mixer(rm->mixer_blks[i])->cap->dspp) {
371
+
DPU_DEBUG("Skipping LM_%d, skipping LMs with DSPPs\n", i);
372
+
continue;
373
+
}
374
374
375
375
/*
376
376
* Reset lm_count to an even index. This will drop the previous
···
408
412
}
409
413
}
410
414
411
-
if (lm_count != topology->num_lm) {
415
+
return lm_count == topology->num_lm;
416
+
}
417
+
418
+
static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
419
+
struct dpu_global_state *global_state,
420
+
uint32_t crtc_id,
421
+
struct msm_display_topology *topology)
422
+
423
+
{
424
+
int lm_idx[MAX_BLOCKS];
425
+
int pp_idx[MAX_BLOCKS];
426
+
int dspp_idx[MAX_BLOCKS] = {0};
427
+
int i;
428
+
bool found;
429
+
430
+
if (!topology->num_lm) {
431
+
DPU_ERROR("zero LMs in topology\n");
432
+
return -EINVAL;
433
+
}
434
+
435
+
/* Try using non-DSPP LM blocks first */
436
+
found = dpu_rm_find_lms(rm, global_state, crtc_id, !topology->num_dspp,
437
+
topology, lm_idx, pp_idx, dspp_idx);
438
+
if (!found && !topology->num_dspp)
439
+
found = dpu_rm_find_lms(rm, global_state, crtc_id, false,
440
+
topology, lm_idx, pp_idx, dspp_idx);
441
+
if (!found) {
412
442
DPU_DEBUG("unable to find appropriate mixers\n");
413
443
return -ENAVAIL;
414
444
}
415
445
416
-
for (i = 0; i < lm_count; i++) {
446
+
for (i = 0; i < topology->num_lm; i++) {
417
447
global_state->mixer_to_crtc_id[lm_idx[i]] = crtc_id;
418
448
global_state->pingpong_to_crtc_id[pp_idx[i]] = crtc_id;
419
449
global_state->dspp_to_crtc_id[dspp_idx[i]] =
···
490
468
features = ctl->caps->features;
491
469
has_split_display = BIT(DPU_CTL_SPLIT_DISPLAY) & features;
492
470
493
-
DPU_DEBUG("ctl %d caps 0x%lX\n", j + CTL_0, features);
471
+
DPU_DEBUG("CTL_%d caps 0x%lX\n", j, features);
494
472
495
473
if (needs_split_display != has_split_display)
496
474
continue;
497
475
498
476
ctl_idx[i] = j;
499
-
DPU_DEBUG("ctl %d match\n", j + CTL_0);
477
+
DPU_DEBUG("CTL_%d match\n", j);
500
478
501
479
if (++i == num_ctls)
502
480
break;
-1155
drivers/gpu/drm/msm/disp/dpu1/msm_media_info.h
-1155
drivers/gpu/drm/msm/disp/dpu1/msm_media_info.h
···
1
-
#ifndef __MEDIA_INFO_H__
2
-
#define __MEDIA_INFO_H__
3
-
4
-
#ifndef MSM_MEDIA_ALIGN
5
-
#define MSM_MEDIA_ALIGN(__sz, __align) (((__align) & ((__align) - 1)) ?\
6
-
((((__sz) + (__align) - 1) / (__align)) * (__align)) :\
7
-
(((__sz) + (__align) - 1) & (~((__align) - 1))))
8
-
#endif
9
-
10
-
#ifndef MSM_MEDIA_ROUNDUP
11
-
#define MSM_MEDIA_ROUNDUP(__sz, __r) (((__sz) + ((__r) - 1)) / (__r))
12
-
#endif
13
-
14
-
#ifndef MSM_MEDIA_MAX
15
-
#define MSM_MEDIA_MAX(__a, __b) ((__a) > (__b)?(__a):(__b))
16
-
#endif
17
-
18
-
enum color_fmts {
19
-
/* Venus NV12:
20
-
* YUV 4:2:0 image with a plane of 8 bit Y samples followed
21
-
* by an interleaved U/V plane containing 8 bit 2x2 subsampled
22
-
* colour difference samples.
23
-
*
24
-
* <-------- Y/UV_Stride -------->
25
-
* <------- Width ------->
26
-
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . ^ ^
27
-
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | |
28
-
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . Height |
29
-
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | Y_Scanlines
30
-
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | |
31
-
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | |
32
-
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | |
33
-
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . V |
34
-
* . . . . . . . . . . . . . . . . |
35
-
* . . . . . . . . . . . . . . . . |
36
-
* . . . . . . . . . . . . . . . . |
37
-
* . . . . . . . . . . . . . . . . V
38
-
* U V U V U V U V U V U V . . . . ^
39
-
* U V U V U V U V U V U V . . . . |
40
-
* U V U V U V U V U V U V . . . . |
41
-
* U V U V U V U V U V U V . . . . UV_Scanlines
42
-
* . . . . . . . . . . . . . . . . |
43
-
* . . . . . . . . . . . . . . . . V
44
-
* . . . . . . . . . . . . . . . . --> Buffer size alignment
45
-
*
46
-
* Y_Stride : Width aligned to 128
47
-
* UV_Stride : Width aligned to 128
48
-
* Y_Scanlines: Height aligned to 32
49
-
* UV_Scanlines: Height/2 aligned to 16
50
-
* Extradata: Arbitrary (software-imposed) padding
51
-
* Total size = align((Y_Stride * Y_Scanlines
52
-
* + UV_Stride * UV_Scanlines
53
-
* + max(Extradata, Y_Stride * 8), 4096)
54
-
*/
55
-
COLOR_FMT_NV12,
56
-
57
-
/* Venus NV21:
58
-
* YUV 4:2:0 image with a plane of 8 bit Y samples followed
59
-
* by an interleaved V/U plane containing 8 bit 2x2 subsampled
60
-
* colour difference samples.
61
-
*
62
-
* <-------- Y/UV_Stride -------->
63
-
* <------- Width ------->
64
-
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . ^ ^
65
-
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | |
66
-
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . Height |
67
-
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | Y_Scanlines
68
-
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | |
69
-
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | |
70
-
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | |
71
-
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . V |
72
-
* . . . . . . . . . . . . . . . . |
73
-
* . . . . . . . . . . . . . . . . |
74
-
* . . . . . . . . . . . . . . . . |
75
-
* . . . . . . . . . . . . . . . . V
76
-
* V U V U V U V U V U V U . . . . ^
77
-
* V U V U V U V U V U V U . . . . |
78
-
* V U V U V U V U V U V U . . . . |
79
-
* V U V U V U V U V U V U . . . . UV_Scanlines
80
-
* . . . . . . . . . . . . . . . . |
81
-
* . . . . . . . . . . . . . . . . V
82
-
* . . . . . . . . . . . . . . . . --> Padding & Buffer size alignment
83
-
*
84
-
* Y_Stride : Width aligned to 128
85
-
* UV_Stride : Width aligned to 128
86
-
* Y_Scanlines: Height aligned to 32
87
-
* UV_Scanlines: Height/2 aligned to 16
88
-
* Extradata: Arbitrary (software-imposed) padding
89
-
* Total size = align((Y_Stride * Y_Scanlines
90
-
* + UV_Stride * UV_Scanlines
91
-
* + max(Extradata, Y_Stride * 8), 4096)
92
-
*/
93
-
COLOR_FMT_NV21,
94
-
/* Venus NV12_MVTB:
95
-
* Two YUV 4:2:0 images/views one after the other
96
-
* in a top-bottom layout, same as NV12
97
-
* with a plane of 8 bit Y samples followed
98
-
* by an interleaved U/V plane containing 8 bit 2x2 subsampled
99
-
* colour difference samples.
100
-
*
101
-
*
102
-
* <-------- Y/UV_Stride -------->
103
-
* <------- Width ------->
104
-
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . ^ ^ ^
105
-
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | |
106
-
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . Height | |
107
-
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | Y_Scanlines |
108
-
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | |
109
-
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | |
110
-
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | |
111
-
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . V | |
112
-
* . . . . . . . . . . . . . . . . | View_1
113
-
* . . . . . . . . . . . . . . . . | |
114
-
* . . . . . . . . . . . . . . . . | |
115
-
* . . . . . . . . . . . . . . . . V |
116
-
* U V U V U V U V U V U V . . . . ^ |
117
-
* U V U V U V U V U V U V . . . . | |
118
-
* U V U V U V U V U V U V . . . . | |
119
-
* U V U V U V U V U V U V . . . . UV_Scanlines |
120
-
* . . . . . . . . . . . . . . . . | |
121
-
* . . . . . . . . . . . . . . . . V V
122
-
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . ^ ^ ^
123
-
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | |
124
-
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . Height | |
125
-
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | Y_Scanlines |
126
-
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | |
127
-
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | |
128
-
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | |
129
-
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . V | |
130
-
* . . . . . . . . . . . . . . . . | View_2
131
-
* . . . . . . . . . . . . . . . . | |
132
-
* . . . . . . . . . . . . . . . . | |
133
-
* . . . . . . . . . . . . . . . . V |
134
-
* U V U V U V U V U V U V . . . . ^ |
135
-
* U V U V U V U V U V U V . . . . | |
136
-
* U V U V U V U V U V U V . . . . | |
137
-
* U V U V U V U V U V U V . . . . UV_Scanlines |
138
-
* . . . . . . . . . . . . . . . . | |
139
-
* . . . . . . . . . . . . . . . . V V
140
-
* . . . . . . . . . . . . . . . . --> Buffer size alignment
141
-
*
142
-
* Y_Stride : Width aligned to 128
143
-
* UV_Stride : Width aligned to 128
144
-
* Y_Scanlines: Height aligned to 32
145
-
* UV_Scanlines: Height/2 aligned to 16
146
-
* View_1 begin at: 0 (zero)
147
-
* View_2 begin at: Y_Stride * Y_Scanlines + UV_Stride * UV_Scanlines
148
-
* Extradata: Arbitrary (software-imposed) padding
149
-
* Total size = align((2*(Y_Stride * Y_Scanlines)
150
-
* + 2*(UV_Stride * UV_Scanlines) + Extradata), 4096)
151
-
*/
152
-
COLOR_FMT_NV12_MVTB,
153
-
/*
154
-
* The buffer can be of 2 types:
155
-
* (1) Venus NV12 UBWC Progressive
156
-
* (2) Venus NV12 UBWC Interlaced
157
-
*
158
-
* (1) Venus NV12 UBWC Progressive Buffer Format:
159
-
* Compressed Macro-tile format for NV12.
160
-
* Contains 4 planes in the following order -
161
-
* (A) Y_Meta_Plane
162
-
* (B) Y_UBWC_Plane
163
-
* (C) UV_Meta_Plane
164
-
* (D) UV_UBWC_Plane
165
-
*
166
-
* Y_Meta_Plane consists of meta information to decode compressed
167
-
* tile data in Y_UBWC_Plane.
168
-
* Y_UBWC_Plane consists of Y data in compressed macro-tile format.
169
-
* UBWC decoder block will use the Y_Meta_Plane data together with
170
-
* Y_UBWC_Plane data to produce loss-less uncompressed 8 bit Y samples.
171
-
*
172
-
* UV_Meta_Plane consists of meta information to decode compressed
173
-
* tile data in UV_UBWC_Plane.
174
-
* UV_UBWC_Plane consists of UV data in compressed macro-tile format.
175
-
* UBWC decoder block will use UV_Meta_Plane data together with
176
-
* UV_UBWC_Plane data to produce loss-less uncompressed 8 bit 2x2
177
-
* subsampled color difference samples.
178
-
*
179
-
* Each tile in Y_UBWC_Plane/UV_UBWC_Plane is independently decodable
180
-
* and randomly accessible. There is no dependency between tiles.
181
-
*
182
-
* <----- Y_Meta_Stride ---->
183
-
* <-------- Width ------>
184
-
* M M M M M M M M M M M M . . ^ ^
185
-
* M M M M M M M M M M M M . . | |
186
-
* M M M M M M M M M M M M . . Height |
187
-
* M M M M M M M M M M M M . . | Meta_Y_Scanlines
188
-
* M M M M M M M M M M M M . . | |
189
-
* M M M M M M M M M M M M . . | |
190
-
* M M M M M M M M M M M M . . | |
191
-
* M M M M M M M M M M M M . . V |
192
-
* . . . . . . . . . . . . . . |
193
-
* . . . . . . . . . . . . . . |
194
-
* . . . . . . . . . . . . . . -------> Buffer size aligned to 4k
195
-
* . . . . . . . . . . . . . . V
196
-
* <--Compressed tile Y Stride--->
197
-
* <------- Width ------->
198
-
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . ^ ^
199
-
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . | |
200
-
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . Height |
201
-
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . | Macro_tile_Y_Scanlines
202
-
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . | |
203
-
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . | |
204
-
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . | |
205
-
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . V |
206
-
* . . . . . . . . . . . . . . . . |
207
-
* . . . . . . . . . . . . . . . . |
208
-
* . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k
209
-
* . . . . . . . . . . . . . . . . V
210
-
* <----- UV_Meta_Stride ---->
211
-
* M M M M M M M M M M M M . . ^
212
-
* M M M M M M M M M M M M . . |
213
-
* M M M M M M M M M M M M . . |
214
-
* M M M M M M M M M M M M . . M_UV_Scanlines
215
-
* . . . . . . . . . . . . . . |
216
-
* . . . . . . . . . . . . . . V
217
-
* . . . . . . . . . . . . . . -------> Buffer size aligned to 4k
218
-
* <--Compressed tile UV Stride--->
219
-
* U* V* U* V* U* V* U* V* . . . . ^
220
-
* U* V* U* V* U* V* U* V* . . . . |
221
-
* U* V* U* V* U* V* U* V* . . . . |
222
-
* U* V* U* V* U* V* U* V* . . . . UV_Scanlines
223
-
* . . . . . . . . . . . . . . . . |
224
-
* . . . . . . . . . . . . . . . . V
225
-
* . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k
226
-
*
227
-
* Y_Stride = align(Width, 128)
228
-
* UV_Stride = align(Width, 128)
229
-
* Y_Scanlines = align(Height, 32)
230
-
* UV_Scanlines = align(Height/2, 16)
231
-
* Y_UBWC_Plane_size = align(Y_Stride * Y_Scanlines, 4096)
232
-
* UV_UBWC_Plane_size = align(UV_Stride * UV_Scanlines, 4096)
233
-
* Y_Meta_Stride = align(roundup(Width, Y_TileWidth), 64)
234
-
* Y_Meta_Scanlines = align(roundup(Height, Y_TileHeight), 16)
235
-
* Y_Meta_Plane_size = align(Y_Meta_Stride * Y_Meta_Scanlines, 4096)
236
-
* UV_Meta_Stride = align(roundup(Width, UV_TileWidth), 64)
237
-
* UV_Meta_Scanlines = align(roundup(Height, UV_TileHeight), 16)
238
-
* UV_Meta_Plane_size = align(UV_Meta_Stride * UV_Meta_Scanlines, 4096)
239
-
* Extradata = 8k
240
-
*
241
-
* Total size = align( Y_UBWC_Plane_size + UV_UBWC_Plane_size +
242
-
* Y_Meta_Plane_size + UV_Meta_Plane_size
243
-
* + max(Extradata, Y_Stride * 48), 4096)
244
-
*
245
-
*
246
-
* (2) Venus NV12 UBWC Interlaced Buffer Format:
247
-
* Compressed Macro-tile format for NV12 interlaced.
248
-
* Contains 8 planes in the following order -
249
-
* (A) Y_Meta_Top_Field_Plane
250
-
* (B) Y_UBWC_Top_Field_Plane
251
-
* (C) UV_Meta_Top_Field_Plane
252
-
* (D) UV_UBWC_Top_Field_Plane
253
-
* (E) Y_Meta_Bottom_Field_Plane
254
-
* (F) Y_UBWC_Bottom_Field_Plane
255
-
* (G) UV_Meta_Bottom_Field_Plane
256
-
* (H) UV_UBWC_Bottom_Field_Plane
257
-
* Y_Meta_Top_Field_Plane consists of meta information to decode
258
-
* compressed tile data for Y_UBWC_Top_Field_Plane.
259
-
* Y_UBWC_Top_Field_Plane consists of Y data in compressed macro-tile
260
-
* format for top field of an interlaced frame.
261
-
* UBWC decoder block will use the Y_Meta_Top_Field_Plane data together
262
-
* with Y_UBWC_Top_Field_Plane data to produce loss-less uncompressed
263
-
* 8 bit Y samples for top field of an interlaced frame.
264
-
*
265
-
* UV_Meta_Top_Field_Plane consists of meta information to decode
266
-
* compressed tile data in UV_UBWC_Top_Field_Plane.
267
-
* UV_UBWC_Top_Field_Plane consists of UV data in compressed macro-tile
268
-
* format for top field of an interlaced frame.
269
-
* UBWC decoder block will use UV_Meta_Top_Field_Plane data together
270
-
* with UV_UBWC_Top_Field_Plane data to produce loss-less uncompressed
271
-
* 8 bit subsampled color difference samples for top field of an
272
-
* interlaced frame.
273
-
*
274
-
* Each tile in Y_UBWC_Top_Field_Plane/UV_UBWC_Top_Field_Plane is
275
-
* independently decodable and randomly accessible. There is no
276
-
* dependency between tiles.
277
-
*
278
-
* Y_Meta_Bottom_Field_Plane consists of meta information to decode
279
-
* compressed tile data for Y_UBWC_Bottom_Field_Plane.
280
-
* Y_UBWC_Bottom_Field_Plane consists of Y data in compressed macro-tile
281
-
* format for bottom field of an interlaced frame.
282
-
* UBWC decoder block will use the Y_Meta_Bottom_Field_Plane data
283
-
* together with Y_UBWC_Bottom_Field_Plane data to produce loss-less
284
-
* uncompressed 8 bit Y samples for bottom field of an interlaced frame.
285
-
*
286
-
* UV_Meta_Bottom_Field_Plane consists of meta information to decode
287
-
* compressed tile data in UV_UBWC_Bottom_Field_Plane.
288
-
* UV_UBWC_Bottom_Field_Plane consists of UV data in compressed
289
-
* macro-tile format for bottom field of an interlaced frame.
290
-
* UBWC decoder block will use UV_Meta_Bottom_Field_Plane data together
291
-
* with UV_UBWC_Bottom_Field_Plane data to produce loss-less
292
-
* uncompressed 8 bit subsampled color difference samples for bottom
293
-
* field of an interlaced frame.
294
-
*
295
-
* Each tile in Y_UBWC_Bottom_Field_Plane/UV_UBWC_Bottom_Field_Plane is
296
-
* independently decodable and randomly accessible. There is no
297
-
* dependency between tiles.
298
-
*
299
-
* <-----Y_TF_Meta_Stride---->
300
-
* <-------- Width ------>
301
-
* M M M M M M M M M M M M . . ^ ^
302
-
* M M M M M M M M M M M M . . | |
303
-
* M M M M M M M M M M M M . . Half_height |
304
-
* M M M M M M M M M M M M . . | Meta_Y_TF_Scanlines
305
-
* M M M M M M M M M M M M . . | |
306
-
* M M M M M M M M M M M M . . | |
307
-
* M M M M M M M M M M M M . . | |
308
-
* M M M M M M M M M M M M . . V |
309
-
* . . . . . . . . . . . . . . |
310
-
* . . . . . . . . . . . . . . |
311
-
* . . . . . . . . . . . . . . -------> Buffer size aligned to 4k
312
-
* . . . . . . . . . . . . . . V
313
-
* <-Compressed tile Y_TF Stride->
314
-
* <------- Width ------->
315
-
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . ^ ^
316
-
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . | |
317
-
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . Half_height |
318
-
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . | Macro_tile_Y_TF_Scanlines
319
-
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . | |
320
-
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . | |
321
-
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . | |
322
-
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . V |
323
-
* . . . . . . . . . . . . . . . . |
324
-
* . . . . . . . . . . . . . . . . |
325
-
* . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k
326
-
* . . . . . . . . . . . . . . . . V
327
-
* <----UV_TF_Meta_Stride---->
328
-
* M M M M M M M M M M M M . . ^
329
-
* M M M M M M M M M M M M . . |
330
-
* M M M M M M M M M M M M . . |
331
-
* M M M M M M M M M M M M . . M_UV_TF_Scanlines
332
-
* . . . . . . . . . . . . . . |
333
-
* . . . . . . . . . . . . . . V
334
-
* . . . . . . . . . . . . . . -------> Buffer size aligned to 4k
335
-
* <-Compressed tile UV_TF Stride->
336
-
* U* V* U* V* U* V* U* V* . . . . ^
337
-
* U* V* U* V* U* V* U* V* . . . . |
338
-
* U* V* U* V* U* V* U* V* . . . . |
339
-
* U* V* U* V* U* V* U* V* . . . . UV_TF_Scanlines
340
-
* . . . . . . . . . . . . . . . . |
341
-
* . . . . . . . . . . . . . . . . V
342
-
* . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k
343
-
* <-----Y_BF_Meta_Stride---->
344
-
* <-------- Width ------>
345
-
* M M M M M M M M M M M M . . ^ ^
346
-
* M M M M M M M M M M M M . . | |
347
-
* M M M M M M M M M M M M . . Half_height |
348
-
* M M M M M M M M M M M M . . | Meta_Y_BF_Scanlines
349
-
* M M M M M M M M M M M M . . | |
350
-
* M M M M M M M M M M M M . . | |
351
-
* M M M M M M M M M M M M . . | |
352
-
* M M M M M M M M M M M M . . V |
353
-
* . . . . . . . . . . . . . . |
354
-
* . . . . . . . . . . . . . . |
355
-
* . . . . . . . . . . . . . . -------> Buffer size aligned to 4k
356
-
* . . . . . . . . . . . . . . V
357
-
* <-Compressed tile Y_BF Stride->
358
-
* <------- Width ------->
359
-
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . ^ ^
360
-
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . | |
361
-
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . Half_height |
362
-
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . | Macro_tile_Y_BF_Scanlines
363
-
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . | |
364
-
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . | |
365
-
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . | |
366
-
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . V |
367
-
* . . . . . . . . . . . . . . . . |
368
-
* . . . . . . . . . . . . . . . . |
369
-
* . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k
370
-
* . . . . . . . . . . . . . . . . V
371
-
* <----UV_BF_Meta_Stride---->
372
-
* M M M M M M M M M M M M . . ^
373
-
* M M M M M M M M M M M M . . |
374
-
* M M M M M M M M M M M M . . |
375
-
* M M M M M M M M M M M M . . M_UV_BF_Scanlines
376
-
* . . . . . . . . . . . . . . |
377
-
* . . . . . . . . . . . . . . V
378
-
* . . . . . . . . . . . . . . -------> Buffer size aligned to 4k
379
-
* <-Compressed tile UV_BF Stride->
380
-
* U* V* U* V* U* V* U* V* . . . . ^
381
-
* U* V* U* V* U* V* U* V* . . . . |
382
-
* U* V* U* V* U* V* U* V* . . . . |
383
-
* U* V* U* V* U* V* U* V* . . . . UV_BF_Scanlines
384
-
* . . . . . . . . . . . . . . . . |
385
-
* . . . . . . . . . . . . . . . . V
386
-
* . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k
387
-
*
388
-
* Half_height = (Height+1)>>1
389
-
* Y_TF_Stride = align(Width, 128)
390
-
* UV_TF_Stride = align(Width, 128)
391
-
* Y_TF_Scanlines = align(Half_height, 32)
392
-
* UV_TF_Scanlines = align((Half_height+1)/2, 32)
393
-
* Y_UBWC_TF_Plane_size = align(Y_TF_Stride * Y_TF_Scanlines, 4096)
394
-
* UV_UBWC_TF_Plane_size = align(UV_TF_Stride * UV_TF_Scanlines, 4096)
395
-
* Y_TF_Meta_Stride = align(roundup(Width, Y_TileWidth), 64)
396
-
* Y_TF_Meta_Scanlines = align(roundup(Half_height, Y_TileHeight), 16)
397
-
* Y_TF_Meta_Plane_size =
398
-
* align(Y_TF_Meta_Stride * Y_TF_Meta_Scanlines, 4096)
399
-
* UV_TF_Meta_Stride = align(roundup(Width, UV_TileWidth), 64)
400
-
* UV_TF_Meta_Scanlines = align(roundup(Half_height, UV_TileHeight), 16)
401
-
* UV_TF_Meta_Plane_size =
402
-
* align(UV_TF_Meta_Stride * UV_TF_Meta_Scanlines, 4096)
403
-
* Y_BF_Stride = align(Width, 128)
404
-
* UV_BF_Stride = align(Width, 128)
405
-
* Y_BF_Scanlines = align(Half_height, 32)
406
-
* UV_BF_Scanlines = align((Half_height+1)/2, 32)
407
-
* Y_UBWC_BF_Plane_size = align(Y_BF_Stride * Y_BF_Scanlines, 4096)
408
-
* UV_UBWC_BF_Plane_size = align(UV_BF_Stride * UV_BF_Scanlines, 4096)
409
-
* Y_BF_Meta_Stride = align(roundup(Width, Y_TileWidth), 64)
410
-
* Y_BF_Meta_Scanlines = align(roundup(Half_height, Y_TileHeight), 16)
411
-
* Y_BF_Meta_Plane_size =
412
-
* align(Y_BF_Meta_Stride * Y_BF_Meta_Scanlines, 4096)
413
-
* UV_BF_Meta_Stride = align(roundup(Width, UV_TileWidth), 64)
414
-
* UV_BF_Meta_Scanlines = align(roundup(Half_height, UV_TileHeight), 16)
415
-
* UV_BF_Meta_Plane_size =
416
-
* align(UV_BF_Meta_Stride * UV_BF_Meta_Scanlines, 4096)
417
-
* Extradata = 8k
418
-
*
419
-
* Total size = align( Y_UBWC_TF_Plane_size + UV_UBWC_TF_Plane_size +
420
-
* Y_TF_Meta_Plane_size + UV_TF_Meta_Plane_size +
421
-
* Y_UBWC_BF_Plane_size + UV_UBWC_BF_Plane_size +
422
-
* Y_BF_Meta_Plane_size + UV_BF_Meta_Plane_size +
423
-
* + max(Extradata, Y_TF_Stride * 48), 4096)
424
-
*/
425
-
COLOR_FMT_NV12_UBWC,
426
-
/* Venus NV12 10-bit UBWC:
427
-
* Compressed Macro-tile format for NV12.
428
-
* Contains 4 planes in the following order -
429
-
* (A) Y_Meta_Plane
430
-
* (B) Y_UBWC_Plane
431
-
* (C) UV_Meta_Plane
432
-
* (D) UV_UBWC_Plane
433
-
*
434
-
* Y_Meta_Plane consists of meta information to decode compressed
435
-
* tile data in Y_UBWC_Plane.
436
-
* Y_UBWC_Plane consists of Y data in compressed macro-tile format.
437
-
* UBWC decoder block will use the Y_Meta_Plane data together with
438
-
* Y_UBWC_Plane data to produce loss-less uncompressed 10 bit Y samples.
439
-
*
440
-
* UV_Meta_Plane consists of meta information to decode compressed
441
-
* tile data in UV_UBWC_Plane.
442
-
* UV_UBWC_Plane consists of UV data in compressed macro-tile format.
443
-
* UBWC decoder block will use UV_Meta_Plane data together with
444
-
* UV_UBWC_Plane data to produce loss-less uncompressed 10 bit 2x2
445
-
* subsampled color difference samples.
446
-
*
447
-
* Each tile in Y_UBWC_Plane/UV_UBWC_Plane is independently decodable
448
-
* and randomly accessible. There is no dependency between tiles.
449
-
*
450
-
* <----- Y_Meta_Stride ----->
451
-
* <-------- Width ------>
452
-
* M M M M M M M M M M M M . . ^ ^
453
-
* M M M M M M M M M M M M . . | |
454
-
* M M M M M M M M M M M M . . Height |
455
-
* M M M M M M M M M M M M . . | Meta_Y_Scanlines
456
-
* M M M M M M M M M M M M . . | |
457
-
* M M M M M M M M M M M M . . | |
458
-
* M M M M M M M M M M M M . . | |
459
-
* M M M M M M M M M M M M . . V |
460
-
* . . . . . . . . . . . . . . |
461
-
* . . . . . . . . . . . . . . |
462
-
* . . . . . . . . . . . . . . -------> Buffer size aligned to 4k
463
-
* . . . . . . . . . . . . . . V
464
-
* <--Compressed tile Y Stride--->
465
-
* <------- Width ------->
466
-
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . ^ ^
467
-
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . | |
468
-
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . Height |
469
-
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . | Macro_tile_Y_Scanlines
470
-
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . | |
471
-
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . | |
472
-
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . | |
473
-
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . V |
474
-
* . . . . . . . . . . . . . . . . |
475
-
* . . . . . . . . . . . . . . . . |
476
-
* . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k
477
-
* . . . . . . . . . . . . . . . . V
478
-
* <----- UV_Meta_Stride ---->
479
-
* M M M M M M M M M M M M . . ^
480
-
* M M M M M M M M M M M M . . |
481
-
* M M M M M M M M M M M M . . |
482
-
* M M M M M M M M M M M M . . M_UV_Scanlines
483
-
* . . . . . . . . . . . . . . |
484
-
* . . . . . . . . . . . . . . V
485
-
* . . . . . . . . . . . . . . -------> Buffer size aligned to 4k
486
-
* <--Compressed tile UV Stride--->
487
-
* U* V* U* V* U* V* U* V* . . . . ^
488
-
* U* V* U* V* U* V* U* V* . . . . |
489
-
* U* V* U* V* U* V* U* V* . . . . |
490
-
* U* V* U* V* U* V* U* V* . . . . UV_Scanlines
491
-
* . . . . . . . . . . . . . . . . |
492
-
* . . . . . . . . . . . . . . . . V
493
-
* . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k
494
-
*
495
-
*
496
-
* Y_Stride = align(Width * 4/3, 128)
497
-
* UV_Stride = align(Width * 4/3, 128)
498
-
* Y_Scanlines = align(Height, 32)
499
-
* UV_Scanlines = align(Height/2, 16)
500
-
* Y_UBWC_Plane_Size = align(Y_Stride * Y_Scanlines, 4096)
501
-
* UV_UBWC_Plane_Size = align(UV_Stride * UV_Scanlines, 4096)
502
-
* Y_Meta_Stride = align(roundup(Width, Y_TileWidth), 64)
503
-
* Y_Meta_Scanlines = align(roundup(Height, Y_TileHeight), 16)
504
-
* Y_Meta_Plane_size = align(Y_Meta_Stride * Y_Meta_Scanlines, 4096)
505
-
* UV_Meta_Stride = align(roundup(Width, UV_TileWidth), 64)
506
-
* UV_Meta_Scanlines = align(roundup(Height, UV_TileHeight), 16)
507
-
* UV_Meta_Plane_size = align(UV_Meta_Stride * UV_Meta_Scanlines, 4096)
508
-
* Extradata = 8k
509
-
*
510
-
* Total size = align(Y_UBWC_Plane_size + UV_UBWC_Plane_size +
511
-
* Y_Meta_Plane_size + UV_Meta_Plane_size
512
-
* + max(Extradata, Y_Stride * 48), 4096)
513
-
*/
514
-
COLOR_FMT_NV12_BPP10_UBWC,
515
-
/* Venus RGBA8888 format:
516
-
* Contains 1 plane in the following order -
517
-
* (A) RGBA plane
518
-
*
519
-
* <-------- RGB_Stride -------->
520
-
* <------- Width ------->
521
-
* R R R R R R R R R R R R . . . . ^ ^
522
-
* R R R R R R R R R R R R . . . . | |
523
-
* R R R R R R R R R R R R . . . . Height |
524
-
* R R R R R R R R R R R R . . . . | RGB_Scanlines
525
-
* R R R R R R R R R R R R . . . . | |
526
-
* R R R R R R R R R R R R . . . . | |
527
-
* R R R R R R R R R R R R . . . . | |
528
-
* R R R R R R R R R R R R . . . . V |
529
-
* . . . . . . . . . . . . . . . . |
530
-
* . . . . . . . . . . . . . . . . |
531
-
* . . . . . . . . . . . . . . . . |
532
-
* . . . . . . . . . . . . . . . . V
533
-
*
534
-
* RGB_Stride = align(Width * 4, 128)
535
-
* RGB_Scanlines = align(Height, 32)
536
-
* RGB_Plane_size = align(RGB_Stride * RGB_Scanlines, 4096)
537
-
* Extradata = 8k
538
-
*
539
-
* Total size = align(RGB_Plane_size + Extradata, 4096)
540
-
*/
541
-
COLOR_FMT_RGBA8888,
542
-
/* Venus RGBA8888 UBWC format:
543
-
* Contains 2 planes in the following order -
544
-
* (A) Meta plane
545
-
* (B) RGBA plane
546
-
*
547
-
* <--- RGB_Meta_Stride ---->
548
-
* <-------- Width ------>
549
-
* M M M M M M M M M M M M . . ^ ^
550
-
* M M M M M M M M M M M M . . | |
551
-
* M M M M M M M M M M M M . . Height |
552
-
* M M M M M M M M M M M M . . | Meta_RGB_Scanlines
553
-
* M M M M M M M M M M M M . . | |
554
-
* M M M M M M M M M M M M . . | |
555
-
* M M M M M M M M M M M M . . | |
556
-
* M M M M M M M M M M M M . . V |
557
-
* . . . . . . . . . . . . . . |
558
-
* . . . . . . . . . . . . . . |
559
-
* . . . . . . . . . . . . . . -------> Buffer size aligned to 4k
560
-
* . . . . . . . . . . . . . . V
561
-
* <-------- RGB_Stride -------->
562
-
* <------- Width ------->
563
-
* R R R R R R R R R R R R . . . . ^ ^
564
-
* R R R R R R R R R R R R . . . . | |
565
-
* R R R R R R R R R R R R . . . . Height |
566
-
* R R R R R R R R R R R R . . . . | RGB_Scanlines
567
-
* R R R R R R R R R R R R . . . . | |
568
-
* R R R R R R R R R R R R . . . . | |
569
-
* R R R R R R R R R R R R . . . . | |
570
-
* R R R R R R R R R R R R . . . . V |
571
-
* . . . . . . . . . . . . . . . . |
572
-
* . . . . . . . . . . . . . . . . |
573
-
* . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k
574
-
* . . . . . . . . . . . . . . . . V
575
-
*
576
-
* RGB_Stride = align(Width * 4, 128)
577
-
* RGB_Scanlines = align(Height, 32)
578
-
* RGB_Plane_size = align(RGB_Stride * RGB_Scanlines, 4096)
579
-
* RGB_Meta_Stride = align(roundup(Width, RGB_TileWidth), 64)
580
-
* RGB_Meta_Scanline = align(roundup(Height, RGB_TileHeight), 16)
581
-
* RGB_Meta_Plane_size = align(RGB_Meta_Stride *
582
-
* RGB_Meta_Scanlines, 4096)
583
-
* Extradata = 8k
584
-
*
585
-
* Total size = align(RGB_Meta_Plane_size + RGB_Plane_size +
586
-
* Extradata, 4096)
587
-
*/
588
-
COLOR_FMT_RGBA8888_UBWC,
589
-
/* Venus RGBA1010102 UBWC format:
590
-
* Contains 2 planes in the following order -
591
-
* (A) Meta plane
592
-
* (B) RGBA plane
593
-
*
594
-
* <--- RGB_Meta_Stride ---->
595
-
* <-------- Width ------>
596
-
* M M M M M M M M M M M M . . ^ ^
597
-
* M M M M M M M M M M M M . . | |
598
-
* M M M M M M M M M M M M . . Height |
599
-
* M M M M M M M M M M M M . . | Meta_RGB_Scanlines
600
-
* M M M M M M M M M M M M . . | |
601
-
* M M M M M M M M M M M M . . | |
602
-
* M M M M M M M M M M M M . . | |
603
-
* M M M M M M M M M M M M . . V |
604
-
* . . . . . . . . . . . . . . |
605
-
* . . . . . . . . . . . . . . |
606
-
* . . . . . . . . . . . . . . -------> Buffer size aligned to 4k
607
-
* . . . . . . . . . . . . . . V
608
-
* <-------- RGB_Stride -------->
609
-
* <------- Width ------->
610
-
* R R R R R R R R R R R R . . . . ^ ^
611
-
* R R R R R R R R R R R R . . . . | |
612
-
* R R R R R R R R R R R R . . . . Height |
613
-
* R R R R R R R R R R R R . . . . | RGB_Scanlines
614
-
* R R R R R R R R R R R R . . . . | |
615
-
* R R R R R R R R R R R R . . . . | |
616
-
* R R R R R R R R R R R R . . . . | |
617
-
* R R R R R R R R R R R R . . . . V |
618
-
* . . . . . . . . . . . . . . . . |
619
-
* . . . . . . . . . . . . . . . . |
620
-
* . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k
621
-
* . . . . . . . . . . . . . . . . V
622
-
*
623
-
* RGB_Stride = align(Width * 4, 256)
624
-
* RGB_Scanlines = align(Height, 16)
625
-
* RGB_Plane_size = align(RGB_Stride * RGB_Scanlines, 4096)
626
-
* RGB_Meta_Stride = align(roundup(Width, RGB_TileWidth), 64)
627
-
* RGB_Meta_Scanline = align(roundup(Height, RGB_TileHeight), 16)
628
-
* RGB_Meta_Plane_size = align(RGB_Meta_Stride *
629
-
* RGB_Meta_Scanlines, 4096)
630
-
* Extradata = 8k
631
-
*
632
-
* Total size = align(RGB_Meta_Plane_size + RGB_Plane_size +
633
-
* Extradata, 4096)
634
-
*/
635
-
COLOR_FMT_RGBA1010102_UBWC,
636
-
/* Venus RGB565 UBWC format:
637
-
* Contains 2 planes in the following order -
638
-
* (A) Meta plane
639
-
* (B) RGB plane
640
-
*
641
-
* <--- RGB_Meta_Stride ---->
642
-
* <-------- Width ------>
643
-
* M M M M M M M M M M M M . . ^ ^
644
-
* M M M M M M M M M M M M . . | |
645
-
* M M M M M M M M M M M M . . Height |
646
-
* M M M M M M M M M M M M . . | Meta_RGB_Scanlines
647
-
* M M M M M M M M M M M M . . | |
648
-
* M M M M M M M M M M M M . . | |
649
-
* M M M M M M M M M M M M . . | |
650
-
* M M M M M M M M M M M M . . V |
651
-
* . . . . . . . . . . . . . . |
652
-
* . . . . . . . . . . . . . . |
653
-
* . . . . . . . . . . . . . . -------> Buffer size aligned to 4k
654
-
* . . . . . . . . . . . . . . V
655
-
* <-------- RGB_Stride -------->
656
-
* <------- Width ------->
657
-
* R R R R R R R R R R R R . . . . ^ ^
658
-
* R R R R R R R R R R R R . . . . | |
659
-
* R R R R R R R R R R R R . . . . Height |
660
-
* R R R R R R R R R R R R . . . . | RGB_Scanlines
661
-
* R R R R R R R R R R R R . . . . | |
662
-
* R R R R R R R R R R R R . . . . | |
663
-
* R R R R R R R R R R R R . . . . | |
664
-
* R R R R R R R R R R R R . . . . V |
665
-
* . . . . . . . . . . . . . . . . |
666
-
* . . . . . . . . . . . . . . . . |
667
-
* . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k
668
-
* . . . . . . . . . . . . . . . . V
669
-
*
670
-
* RGB_Stride = align(Width * 2, 128)
671
-
* RGB_Scanlines = align(Height, 16)
672
-
* RGB_Plane_size = align(RGB_Stride * RGB_Scanlines, 4096)
673
-
* RGB_Meta_Stride = align(roundup(Width, RGB_TileWidth), 64)
674
-
* RGB_Meta_Scanline = align(roundup(Height, RGB_TileHeight), 16)
675
-
* RGB_Meta_Plane_size = align(RGB_Meta_Stride *
676
-
* RGB_Meta_Scanlines, 4096)
677
-
* Extradata = 8k
678
-
*
679
-
* Total size = align(RGB_Meta_Plane_size + RGB_Plane_size +
680
-
* Extradata, 4096)
681
-
*/
682
-
COLOR_FMT_RGB565_UBWC,
683
-
/* P010 UBWC:
684
-
* Compressed Macro-tile format for NV12.
685
-
* Contains 4 planes in the following order -
686
-
* (A) Y_Meta_Plane
687
-
* (B) Y_UBWC_Plane
688
-
* (C) UV_Meta_Plane
689
-
* (D) UV_UBWC_Plane
690
-
*
691
-
* Y_Meta_Plane consists of meta information to decode compressed
692
-
* tile data in Y_UBWC_Plane.
693
-
* Y_UBWC_Plane consists of Y data in compressed macro-tile format.
694
-
* UBWC decoder block will use the Y_Meta_Plane data together with
695
-
* Y_UBWC_Plane data to produce loss-less uncompressed 10 bit Y samples.
696
-
*
697
-
* UV_Meta_Plane consists of meta information to decode compressed
698
-
* tile data in UV_UBWC_Plane.
699
-
* UV_UBWC_Plane consists of UV data in compressed macro-tile format.
700
-
* UBWC decoder block will use UV_Meta_Plane data together with
701
-
* UV_UBWC_Plane data to produce loss-less uncompressed 10 bit 2x2
702
-
* subsampled color difference samples.
703
-
*
704
-
* Each tile in Y_UBWC_Plane/UV_UBWC_Plane is independently decodable
705
-
* and randomly accessible. There is no dependency between tiles.
706
-
*
707
-
* <----- Y_Meta_Stride ----->
708
-
* <-------- Width ------>
709
-
* M M M M M M M M M M M M . . ^ ^
710
-
* M M M M M M M M M M M M . . | |
711
-
* M M M M M M M M M M M M . . Height |
712
-
* M M M M M M M M M M M M . . | Meta_Y_Scanlines
713
-
* M M M M M M M M M M M M . . | |
714
-
* M M M M M M M M M M M M . . | |
715
-
* M M M M M M M M M M M M . . | |
716
-
* M M M M M M M M M M M M . . V |
717
-
* . . . . . . . . . . . . . . |
718
-
* . . . . . . . . . . . . . . |
719
-
* . . . . . . . . . . . . . . -------> Buffer size aligned to 4k
720
-
* . . . . . . . . . . . . . . V
721
-
* <--Compressed tile Y Stride--->
722
-
* <------- Width ------->
723
-
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . ^ ^
724
-
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . | |
725
-
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . Height |
726
-
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . | Macro_tile_Y_Scanlines
727
-
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . | |
728
-
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . | |
729
-
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . | |
730
-
* Y* Y* Y* Y* Y* Y* Y* Y* . . . . V |
731
-
* . . . . . . . . . . . . . . . . |
732
-
* . . . . . . . . . . . . . . . . |
733
-
* . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k
734
-
* . . . . . . . . . . . . . . . . V
735
-
* <----- UV_Meta_Stride ---->
736
-
* M M M M M M M M M M M M . . ^
737
-
* M M M M M M M M M M M M . . |
738
-
* M M M M M M M M M M M M . . |
739
-
* M M M M M M M M M M M M . . M_UV_Scanlines
740
-
* . . . . . . . . . . . . . . |
741
-
* . . . . . . . . . . . . . . V
742
-
* . . . . . . . . . . . . . . -------> Buffer size aligned to 4k
743
-
* <--Compressed tile UV Stride--->
744
-
* U* V* U* V* U* V* U* V* . . . . ^
745
-
* U* V* U* V* U* V* U* V* . . . . |
746
-
* U* V* U* V* U* V* U* V* . . . . |
747
-
* U* V* U* V* U* V* U* V* . . . . UV_Scanlines
748
-
* . . . . . . . . . . . . . . . . |
749
-
* . . . . . . . . . . . . . . . . V
750
-
* . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k
751
-
*
752
-
*
753
-
* Y_Stride = align(Width * 2, 256)
754
-
* UV_Stride = align(Width * 2, 256)
755
-
* Y_Scanlines = align(Height, 16)
756
-
* UV_Scanlines = align(Height/2, 16)
757
-
* Y_UBWC_Plane_Size = align(Y_Stride * Y_Scanlines, 4096)
758
-
* UV_UBWC_Plane_Size = align(UV_Stride * UV_Scanlines, 4096)
759
-
* Y_Meta_Stride = align(roundup(Width, Y_TileWidth), 64)
760
-
* Y_Meta_Scanlines = align(roundup(Height, Y_TileHeight), 16)
761
-
* Y_Meta_Plane_size = align(Y_Meta_Stride * Y_Meta_Scanlines, 4096)
762
-
* UV_Meta_Stride = align(roundup(Width, UV_TileWidth), 64)
763
-
* UV_Meta_Scanlines = align(roundup(Height, UV_TileHeight), 16)
764
-
* UV_Meta_Plane_size = align(UV_Meta_Stride * UV_Meta_Scanlines, 4096)
765
-
* Extradata = 8k
766
-
*
767
-
* Total size = align(Y_UBWC_Plane_size + UV_UBWC_Plane_size +
768
-
* Y_Meta_Plane_size + UV_Meta_Plane_size
769
-
* + max(Extradata, Y_Stride * 48), 4096)
770
-
*/
771
-
COLOR_FMT_P010_UBWC,
772
-
/* Venus P010:
773
-
* YUV 4:2:0 image with a plane of 10 bit Y samples followed
774
-
* by an interleaved U/V plane containing 10 bit 2x2 subsampled
775
-
* colour difference samples.
776
-
*
777
-
* <-------- Y/UV_Stride -------->
778
-
* <------- Width ------->
779
-
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . ^ ^
780
-
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | |
781
-
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . Height |
782
-
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | Y_Scanlines
783
-
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | |
784
-
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | |
785
-
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . | |
786
-
* Y Y Y Y Y Y Y Y Y Y Y Y . . . . V |
787
-
* . . . . . . . . . . . . . . . . |
788
-
* . . . . . . . . . . . . . . . . |
789
-
* . . . . . . . . . . . . . . . . |
790
-
* . . . . . . . . . . . . . . . . V
791
-
* U V U V U V U V U V U V . . . . ^
792
-
* U V U V U V U V U V U V . . . . |
793
-
* U V U V U V U V U V U V . . . . |
794
-
* U V U V U V U V U V U V . . . . UV_Scanlines
795
-
* . . . . . . . . . . . . . . . . |
796
-
* . . . . . . . . . . . . . . . . V
797
-
* . . . . . . . . . . . . . . . . --> Buffer size alignment
798
-
*
799
-
* Y_Stride : Width * 2 aligned to 128
800
-
* UV_Stride : Width * 2 aligned to 128
801
-
* Y_Scanlines: Height aligned to 32
802
-
* UV_Scanlines: Height/2 aligned to 16
803
-
* Extradata: Arbitrary (software-imposed) padding
804
-
* Total size = align((Y_Stride * Y_Scanlines
805
-
* + UV_Stride * UV_Scanlines
806
-
* + max(Extradata, Y_Stride * 8), 4096)
807
-
*/
808
-
COLOR_FMT_P010,
809
-
};
810
-
811
-
#define COLOR_FMT_RGBA1010102_UBWC COLOR_FMT_RGBA1010102_UBWC
812
-
#define COLOR_FMT_RGB565_UBWC COLOR_FMT_RGB565_UBWC
813
-
#define COLOR_FMT_P010_UBWC COLOR_FMT_P010_UBWC
814
-
#define COLOR_FMT_P010 COLOR_FMT_P010
815
-
816
-
/*
817
-
* Function arguments:
818
-
* @color_fmt
819
-
* @width
820
-
* Progressive: width
821
-
* Interlaced: width
822
-
*/
823
-
static unsigned int VENUS_Y_STRIDE(int color_fmt, int width)
824
-
{
825
-
unsigned int stride = 0;
826
-
827
-
if (!width)
828
-
return 0;
829
-
830
-
switch (color_fmt) {
831
-
case COLOR_FMT_NV21:
832
-
case COLOR_FMT_NV12:
833
-
case COLOR_FMT_NV12_MVTB:
834
-
case COLOR_FMT_NV12_UBWC:
835
-
stride = MSM_MEDIA_ALIGN(width, 128);
836
-
break;
837
-
case COLOR_FMT_NV12_BPP10_UBWC:
838
-
stride = MSM_MEDIA_ALIGN(width, 192);
839
-
stride = MSM_MEDIA_ALIGN(stride * 4 / 3, 256);
840
-
break;
841
-
case COLOR_FMT_P010_UBWC:
842
-
stride = MSM_MEDIA_ALIGN(width * 2, 256);
843
-
break;
844
-
case COLOR_FMT_P010:
845
-
stride = MSM_MEDIA_ALIGN(width * 2, 128);
846
-
break;
847
-
}
848
-
849
-
return stride;
850
-
}
851
-
852
-
/*
853
-
* Function arguments:
854
-
* @color_fmt
855
-
* @width
856
-
* Progressive: width
857
-
* Interlaced: width
858
-
*/
859
-
static unsigned int VENUS_UV_STRIDE(int color_fmt, int width)
860
-
{
861
-
unsigned int stride = 0;
862
-
863
-
if (!width)
864
-
return 0;
865
-
866
-
switch (color_fmt) {
867
-
case COLOR_FMT_NV21:
868
-
case COLOR_FMT_NV12:
869
-
case COLOR_FMT_NV12_MVTB:
870
-
case COLOR_FMT_NV12_UBWC:
871
-
stride = MSM_MEDIA_ALIGN(width, 128);
872
-
break;
873
-
case COLOR_FMT_NV12_BPP10_UBWC:
874
-
stride = MSM_MEDIA_ALIGN(width, 192);
875
-
stride = MSM_MEDIA_ALIGN(stride * 4 / 3, 256);
876
-
break;
877
-
case COLOR_FMT_P010_UBWC:
878
-
stride = MSM_MEDIA_ALIGN(width * 2, 256);
879
-
break;
880
-
case COLOR_FMT_P010:
881
-
stride = MSM_MEDIA_ALIGN(width * 2, 128);
882
-
break;
883
-
}
884
-
885
-
return stride;
886
-
}
887
-
888
-
/*
889
-
* Function arguments:
890
-
* @color_fmt
891
-
* @height
892
-
* Progressive: height
893
-
* Interlaced: (height+1)>>1
894
-
*/
895
-
static unsigned int VENUS_Y_SCANLINES(int color_fmt, int height)
896
-
{
897
-
unsigned int sclines = 0;
898
-
899
-
if (!height)
900
-
return 0;
901
-
902
-
switch (color_fmt) {
903
-
case COLOR_FMT_NV21:
904
-
case COLOR_FMT_NV12:
905
-
case COLOR_FMT_NV12_MVTB:
906
-
case COLOR_FMT_NV12_UBWC:
907
-
case COLOR_FMT_P010:
908
-
sclines = MSM_MEDIA_ALIGN(height, 32);
909
-
break;
910
-
case COLOR_FMT_NV12_BPP10_UBWC:
911
-
case COLOR_FMT_P010_UBWC:
912
-
sclines = MSM_MEDIA_ALIGN(height, 16);
913
-
break;
914
-
}
915
-
916
-
return sclines;
917
-
}
918
-
919
-
/*
920
-
* Function arguments:
921
-
* @color_fmt
922
-
* @height
923
-
* Progressive: height
924
-
* Interlaced: (height+1)>>1
925
-
*/
926
-
static unsigned int VENUS_UV_SCANLINES(int color_fmt, int height)
927
-
{
928
-
unsigned int sclines = 0;
929
-
930
-
if (!height)
931
-
return 0;
932
-
933
-
switch (color_fmt) {
934
-
case COLOR_FMT_NV21:
935
-
case COLOR_FMT_NV12:
936
-
case COLOR_FMT_NV12_MVTB:
937
-
case COLOR_FMT_NV12_BPP10_UBWC:
938
-
case COLOR_FMT_P010_UBWC:
939
-
case COLOR_FMT_P010:
940
-
sclines = MSM_MEDIA_ALIGN((height + 1) >> 1, 16);
941
-
break;
942
-
case COLOR_FMT_NV12_UBWC:
943
-
sclines = MSM_MEDIA_ALIGN((height + 1) >> 1, 32);
944
-
break;
945
-
}
946
-
947
-
return sclines;
948
-
}
949
-
950
-
/*
951
-
* Function arguments:
952
-
* @color_fmt
953
-
* @width
954
-
* Progressive: width
955
-
* Interlaced: width
956
-
*/
957
-
static unsigned int VENUS_Y_META_STRIDE(int color_fmt, int width)
958
-
{
959
-
int y_tile_width = 0, y_meta_stride;
960
-
961
-
if (!width)
962
-
return 0;
963
-
964
-
switch (color_fmt) {
965
-
case COLOR_FMT_NV12_UBWC:
966
-
case COLOR_FMT_P010_UBWC:
967
-
y_tile_width = 32;
968
-
break;
969
-
case COLOR_FMT_NV12_BPP10_UBWC:
970
-
y_tile_width = 48;
971
-
break;
972
-
default:
973
-
return 0;
974
-
}
975
-
976
-
y_meta_stride = MSM_MEDIA_ROUNDUP(width, y_tile_width);
977
-
return MSM_MEDIA_ALIGN(y_meta_stride, 64);
978
-
}
979
-
980
-
/*
981
-
* Function arguments:
982
-
* @color_fmt
983
-
* @height
984
-
* Progressive: height
985
-
* Interlaced: (height+1)>>1
986
-
*/
987
-
static unsigned int VENUS_Y_META_SCANLINES(int color_fmt, int height)
988
-
{
989
-
int y_tile_height = 0, y_meta_scanlines;
990
-
991
-
if (!height)
992
-
return 0;
993
-
994
-
switch (color_fmt) {
995
-
case COLOR_FMT_NV12_UBWC:
996
-
y_tile_height = 8;
997
-
break;
998
-
case COLOR_FMT_NV12_BPP10_UBWC:
999
-
case COLOR_FMT_P010_UBWC:
1000
-
y_tile_height = 4;
1001
-
break;
1002
-
default:
1003
-
return 0;
1004
-
}
1005
-
1006
-
y_meta_scanlines = MSM_MEDIA_ROUNDUP(height, y_tile_height);
1007
-
return MSM_MEDIA_ALIGN(y_meta_scanlines, 16);
1008
-
}
1009
-
1010
-
/*
1011
-
* Function arguments:
1012
-
* @color_fmt
1013
-
* @width
1014
-
* Progressive: width
1015
-
* Interlaced: width
1016
-
*/
1017
-
static unsigned int VENUS_UV_META_STRIDE(int color_fmt, int width)
1018
-
{
1019
-
int uv_tile_width = 0, uv_meta_stride;
1020
-
1021
-
if (!width)
1022
-
return 0;
1023
-
1024
-
switch (color_fmt) {
1025
-
case COLOR_FMT_NV12_UBWC:
1026
-
case COLOR_FMT_P010_UBWC:
1027
-
uv_tile_width = 16;
1028
-
break;
1029
-
case COLOR_FMT_NV12_BPP10_UBWC:
1030
-
uv_tile_width = 24;
1031
-
break;
1032
-
default:
1033
-
return 0;
1034
-
}
1035
-
1036
-
uv_meta_stride = MSM_MEDIA_ROUNDUP((width+1)>>1, uv_tile_width);
1037
-
return MSM_MEDIA_ALIGN(uv_meta_stride, 64);
1038
-
}
1039
-
1040
-
/*
1041
-
* Function arguments:
1042
-
* @color_fmt
1043
-
* @height
1044
-
* Progressive: height
1045
-
* Interlaced: (height+1)>>1
1046
-
*/
1047
-
static unsigned int VENUS_UV_META_SCANLINES(int color_fmt, int height)
1048
-
{
1049
-
int uv_tile_height = 0, uv_meta_scanlines;
1050
-
1051
-
if (!height)
1052
-
return 0;
1053
-
1054
-
switch (color_fmt) {
1055
-
case COLOR_FMT_NV12_UBWC:
1056
-
uv_tile_height = 8;
1057
-
break;
1058
-
case COLOR_FMT_NV12_BPP10_UBWC:
1059
-
case COLOR_FMT_P010_UBWC:
1060
-
uv_tile_height = 4;
1061
-
break;
1062
-
default:
1063
-
return 0;
1064
-
}
1065
-
1066
-
uv_meta_scanlines = MSM_MEDIA_ROUNDUP((height+1)>>1, uv_tile_height);
1067
-
return MSM_MEDIA_ALIGN(uv_meta_scanlines, 16);
1068
-
}
1069
-
1070
-
static unsigned int VENUS_RGB_STRIDE(int color_fmt, int width)
1071
-
{
1072
-
unsigned int alignment = 0, bpp = 4;
1073
-
1074
-
if (!width)
1075
-
return 0;
1076
-
1077
-
switch (color_fmt) {
1078
-
case COLOR_FMT_RGBA8888:
1079
-
alignment = 128;
1080
-
break;
1081
-
case COLOR_FMT_RGB565_UBWC:
1082
-
alignment = 256;
1083
-
bpp = 2;
1084
-
break;
1085
-
case COLOR_FMT_RGBA8888_UBWC:
1086
-
case COLOR_FMT_RGBA1010102_UBWC:
1087
-
alignment = 256;
1088
-
break;
1089
-
default:
1090
-
return 0;
1091
-
}
1092
-
1093
-
return MSM_MEDIA_ALIGN(width * bpp, alignment);
1094
-
}
1095
-
1096
-
static unsigned int VENUS_RGB_SCANLINES(int color_fmt, int height)
1097
-
{
1098
-
unsigned int alignment = 0;
1099
-
1100
-
if (!height)
1101
-
return 0;
1102
-
1103
-
switch (color_fmt) {
1104
-
case COLOR_FMT_RGBA8888:
1105
-
alignment = 32;
1106
-
break;
1107
-
case COLOR_FMT_RGBA8888_UBWC:
1108
-
case COLOR_FMT_RGBA1010102_UBWC:
1109
-
case COLOR_FMT_RGB565_UBWC:
1110
-
alignment = 16;
1111
-
break;
1112
-
default:
1113
-
return 0;
1114
-
}
1115
-
1116
-
return MSM_MEDIA_ALIGN(height, alignment);
1117
-
}
1118
-
1119
-
static unsigned int VENUS_RGB_META_STRIDE(int color_fmt, int width)
1120
-
{
1121
-
int rgb_meta_stride;
1122
-
1123
-
if (!width)
1124
-
return 0;
1125
-
1126
-
switch (color_fmt) {
1127
-
case COLOR_FMT_RGBA8888_UBWC:
1128
-
case COLOR_FMT_RGBA1010102_UBWC:
1129
-
case COLOR_FMT_RGB565_UBWC:
1130
-
rgb_meta_stride = MSM_MEDIA_ROUNDUP(width, 16);
1131
-
return MSM_MEDIA_ALIGN(rgb_meta_stride, 64);
1132
-
}
1133
-
1134
-
return 0;
1135
-
}
1136
-
1137
-
static unsigned int VENUS_RGB_META_SCANLINES(int color_fmt, int height)
1138
-
{
1139
-
int rgb_meta_scanlines;
1140
-
1141
-
if (!height)
1142
-
return 0;
1143
-
1144
-
switch (color_fmt) {
1145
-
case COLOR_FMT_RGBA8888_UBWC:
1146
-
case COLOR_FMT_RGBA1010102_UBWC:
1147
-
case COLOR_FMT_RGB565_UBWC:
1148
-
rgb_meta_scanlines = MSM_MEDIA_ROUNDUP(height, 4);
1149
-
return MSM_MEDIA_ALIGN(rgb_meta_scanlines, 16);
1150
-
}
1151
-
1152
-
return 0;
1153
-
}
1154
-
1155
-
#endif
-314
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
-314
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
···
1097
1097
.max_clk = 320000000,
1098
1098
};
1099
1099
1100
-
static const struct mdp5_cfg_hw msm8998_config = {
1101
-
.name = "msm8998",
1102
-
.mdp = {
1103
-
.count = 1,
1104
-
.caps = MDP_CAP_DSC |
1105
-
MDP_CAP_CDM |
1106
-
MDP_CAP_SRC_SPLIT |
1107
-
0,
1108
-
},
1109
-
.ctl = {
1110
-
.count = 5,
1111
-
.base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
1112
-
.flush_hw_mask = 0xf7ffffff,
1113
-
},
1114
-
.pipe_vig = {
1115
-
.count = 4,
1116
-
.base = { 0x04000, 0x06000, 0x08000, 0x0a000 },
1117
-
.caps = MDP_PIPE_CAP_HFLIP |
1118
-
MDP_PIPE_CAP_VFLIP |
1119
-
MDP_PIPE_CAP_SCALE |
1120
-
MDP_PIPE_CAP_CSC |
1121
-
MDP_PIPE_CAP_DECIMATION |
1122
-
MDP_PIPE_CAP_SW_PIX_EXT |
1123
-
0,
1124
-
},
1125
-
.pipe_rgb = {
1126
-
.count = 4,
1127
-
.base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
1128
-
.caps = MDP_PIPE_CAP_HFLIP |
1129
-
MDP_PIPE_CAP_VFLIP |
1130
-
MDP_PIPE_CAP_SCALE |
1131
-
MDP_PIPE_CAP_DECIMATION |
1132
-
MDP_PIPE_CAP_SW_PIX_EXT |
1133
-
0,
1134
-
},
1135
-
.pipe_dma = {
1136
-
.count = 2, /* driver supports max of 2 currently */
1137
-
.base = { 0x24000, 0x26000, 0x28000, 0x2a000 },
1138
-
.caps = MDP_PIPE_CAP_HFLIP |
1139
-
MDP_PIPE_CAP_VFLIP |
1140
-
MDP_PIPE_CAP_SW_PIX_EXT |
1141
-
0,
1142
-
},
1143
-
.pipe_cursor = {
1144
-
.count = 2,
1145
-
.base = { 0x34000, 0x36000 },
1146
-
.caps = MDP_PIPE_CAP_HFLIP |
1147
-
MDP_PIPE_CAP_VFLIP |
1148
-
MDP_PIPE_CAP_SW_PIX_EXT |
1149
-
MDP_PIPE_CAP_CURSOR |
1150
-
0,
1151
-
},
1152
-
1153
-
.lm = {
1154
-
.count = 6,
1155
-
.base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
1156
-
.instances = {
1157
-
{ .id = 0, .pp = 0, .dspp = 0,
1158
-
.caps = MDP_LM_CAP_DISPLAY |
1159
-
MDP_LM_CAP_PAIR, },
1160
-
{ .id = 1, .pp = 1, .dspp = 1,
1161
-
.caps = MDP_LM_CAP_DISPLAY, },
1162
-
{ .id = 2, .pp = 2, .dspp = -1,
1163
-
.caps = MDP_LM_CAP_DISPLAY |
1164
-
MDP_LM_CAP_PAIR, },
1165
-
{ .id = 3, .pp = -1, .dspp = -1,
1166
-
.caps = MDP_LM_CAP_WB, },
1167
-
{ .id = 4, .pp = -1, .dspp = -1,
1168
-
.caps = MDP_LM_CAP_WB, },
1169
-
{ .id = 5, .pp = 3, .dspp = -1,
1170
-
.caps = MDP_LM_CAP_DISPLAY, },
1171
-
},
1172
-
.nb_stages = 8,
1173
-
.max_width = 2560,
1174
-
.max_height = 0xFFFF,
1175
-
},
1176
-
.dspp = {
1177
-
.count = 2,
1178
-
.base = { 0x54000, 0x56000 },
1179
-
},
1180
-
.ad = {
1181
-
.count = 3,
1182
-
.base = { 0x78000, 0x78800, 0x79000 },
1183
-
},
1184
-
.pp = {
1185
-
.count = 4,
1186
-
.base = { 0x70000, 0x70800, 0x71000, 0x71800 },
1187
-
},
1188
-
.cdm = {
1189
-
.count = 1,
1190
-
.base = { 0x79200 },
1191
-
},
1192
-
.dsc = {
1193
-
.count = 2,
1194
-
.base = { 0x80000, 0x80400 },
1195
-
},
1196
-
.intf = {
1197
-
.base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 },
1198
-
.connect = {
1199
-
[0] = INTF_eDP,
1200
-
[1] = INTF_DSI,
1201
-
[2] = INTF_DSI,
1202
-
[3] = INTF_HDMI,
1203
-
},
1204
-
},
1205
-
.max_clk = 412500000,
1206
-
};
1207
-
1208
-
static const struct mdp5_cfg_hw sdm630_config = {
1209
-
.name = "sdm630",
1210
-
.mdp = {
1211
-
.count = 1,
1212
-
.caps = MDP_CAP_CDM |
1213
-
MDP_CAP_SRC_SPLIT |
1214
-
0,
1215
-
},
1216
-
.ctl = {
1217
-
.count = 5,
1218
-
.base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
1219
-
.flush_hw_mask = 0xf4ffffff,
1220
-
},
1221
-
.pipe_vig = {
1222
-
.count = 1,
1223
-
.base = { 0x04000 },
1224
-
.caps = MDP_PIPE_CAP_HFLIP |
1225
-
MDP_PIPE_CAP_VFLIP |
1226
-
MDP_PIPE_CAP_SCALE |
1227
-
MDP_PIPE_CAP_CSC |
1228
-
MDP_PIPE_CAP_DECIMATION |
1229
-
MDP_PIPE_CAP_SW_PIX_EXT |
1230
-
0,
1231
-
},
1232
-
.pipe_rgb = {
1233
-
.count = 4,
1234
-
.base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
1235
-
.caps = MDP_PIPE_CAP_HFLIP |
1236
-
MDP_PIPE_CAP_VFLIP |
1237
-
MDP_PIPE_CAP_SCALE |
1238
-
MDP_PIPE_CAP_DECIMATION |
1239
-
MDP_PIPE_CAP_SW_PIX_EXT |
1240
-
0,
1241
-
},
1242
-
.pipe_dma = {
1243
-
.count = 2, /* driver supports max of 2 currently */
1244
-
.base = { 0x24000, 0x26000, 0x28000 },
1245
-
.caps = MDP_PIPE_CAP_HFLIP |
1246
-
MDP_PIPE_CAP_VFLIP |
1247
-
MDP_PIPE_CAP_SW_PIX_EXT |
1248
-
0,
1249
-
},
1250
-
.pipe_cursor = {
1251
-
.count = 1,
1252
-
.base = { 0x34000 },
1253
-
.caps = MDP_PIPE_CAP_HFLIP |
1254
-
MDP_PIPE_CAP_VFLIP |
1255
-
MDP_PIPE_CAP_SW_PIX_EXT |
1256
-
MDP_PIPE_CAP_CURSOR |
1257
-
0,
1258
-
},
1259
-
1260
-
.lm = {
1261
-
.count = 2,
1262
-
.base = { 0x44000, 0x46000 },
1263
-
.instances = {
1264
-
{ .id = 0, .pp = 0, .dspp = 0,
1265
-
.caps = MDP_LM_CAP_DISPLAY |
1266
-
MDP_LM_CAP_PAIR, },
1267
-
{ .id = 1, .pp = 1, .dspp = -1,
1268
-
.caps = MDP_LM_CAP_WB, },
1269
-
},
1270
-
.nb_stages = 8,
1271
-
.max_width = 2048,
1272
-
.max_height = 0xFFFF,
1273
-
},
1274
-
.dspp = {
1275
-
.count = 1,
1276
-
.base = { 0x54000 },
1277
-
},
1278
-
.ad = {
1279
-
.count = 2,
1280
-
.base = { 0x78000, 0x78800 },
1281
-
},
1282
-
.pp = {
1283
-
.count = 3,
1284
-
.base = { 0x70000, 0x71000, 0x72000 },
1285
-
},
1286
-
.cdm = {
1287
-
.count = 1,
1288
-
.base = { 0x79200 },
1289
-
},
1290
-
.intf = {
1291
-
.base = { 0x6a000, 0x6a800 },
1292
-
.connect = {
1293
-
[0] = INTF_DISABLED,
1294
-
[1] = INTF_DSI,
1295
-
},
1296
-
},
1297
-
.max_clk = 412500000,
1298
-
};
1299
-
1300
-
static const struct mdp5_cfg_hw sdm660_config = {
1301
-
.name = "sdm660",
1302
-
.mdp = {
1303
-
.count = 1,
1304
-
.caps = MDP_CAP_DSC |
1305
-
MDP_CAP_CDM |
1306
-
MDP_CAP_SRC_SPLIT |
1307
-
0,
1308
-
},
1309
-
.ctl = {
1310
-
.count = 5,
1311
-
.base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
1312
-
.flush_hw_mask = 0xf4ffffff,
1313
-
},
1314
-
.pipe_vig = {
1315
-
.count = 2,
1316
-
.base = { 0x04000, 0x6000 },
1317
-
.caps = MDP_PIPE_CAP_HFLIP |
1318
-
MDP_PIPE_CAP_VFLIP |
1319
-
MDP_PIPE_CAP_SCALE |
1320
-
MDP_PIPE_CAP_CSC |
1321
-
MDP_PIPE_CAP_DECIMATION |
1322
-
MDP_PIPE_CAP_SW_PIX_EXT |
1323
-
0,
1324
-
},
1325
-
.pipe_rgb = {
1326
-
.count = 4,
1327
-
.base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
1328
-
.caps = MDP_PIPE_CAP_HFLIP |
1329
-
MDP_PIPE_CAP_VFLIP |
1330
-
MDP_PIPE_CAP_SCALE |
1331
-
MDP_PIPE_CAP_DECIMATION |
1332
-
MDP_PIPE_CAP_SW_PIX_EXT |
1333
-
0,
1334
-
},
1335
-
.pipe_dma = {
1336
-
.count = 2, /* driver supports max of 2 currently */
1337
-
.base = { 0x24000, 0x26000, 0x28000 },
1338
-
.caps = MDP_PIPE_CAP_HFLIP |
1339
-
MDP_PIPE_CAP_VFLIP |
1340
-
MDP_PIPE_CAP_SW_PIX_EXT |
1341
-
0,
1342
-
},
1343
-
.pipe_cursor = {
1344
-
.count = 1,
1345
-
.base = { 0x34000 },
1346
-
.caps = MDP_PIPE_CAP_HFLIP |
1347
-
MDP_PIPE_CAP_VFLIP |
1348
-
MDP_PIPE_CAP_SW_PIX_EXT |
1349
-
MDP_PIPE_CAP_CURSOR |
1350
-
0,
1351
-
},
1352
-
1353
-
.lm = {
1354
-
.count = 4,
1355
-
.base = { 0x44000, 0x45000, 0x46000, 0x49000 },
1356
-
.instances = {
1357
-
{ .id = 0, .pp = 0, .dspp = 0,
1358
-
.caps = MDP_LM_CAP_DISPLAY |
1359
-
MDP_LM_CAP_PAIR, },
1360
-
{ .id = 1, .pp = 1, .dspp = 1,
1361
-
.caps = MDP_LM_CAP_DISPLAY, },
1362
-
{ .id = 2, .pp = 2, .dspp = -1,
1363
-
.caps = MDP_LM_CAP_DISPLAY |
1364
-
MDP_LM_CAP_PAIR, },
1365
-
{ .id = 3, .pp = 3, .dspp = -1,
1366
-
.caps = MDP_LM_CAP_WB, },
1367
-
},
1368
-
.nb_stages = 8,
1369
-
.max_width = 2560,
1370
-
.max_height = 0xFFFF,
1371
-
},
1372
-
.dspp = {
1373
-
.count = 2,
1374
-
.base = { 0x54000, 0x56000 },
1375
-
},
1376
-
.ad = {
1377
-
.count = 2,
1378
-
.base = { 0x78000, 0x78800 },
1379
-
},
1380
-
.pp = {
1381
-
.count = 5,
1382
-
.base = { 0x70000, 0x70800, 0x71000, 0x71800, 0x72000 },
1383
-
},
1384
-
.cdm = {
1385
-
.count = 1,
1386
-
.base = { 0x79200 },
1387
-
},
1388
-
.dsc = {
1389
-
.count = 2,
1390
-
.base = { 0x80000, 0x80400 },
1391
-
},
1392
-
.intf = {
1393
-
.base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800 },
1394
-
.connect = {
1395
-
[0] = INTF_DISABLED,
1396
-
[1] = INTF_DSI,
1397
-
[2] = INTF_DSI,
1398
-
[3] = INTF_HDMI,
1399
-
},
1400
-
},
1401
-
.max_clk = 412500000,
1402
-
};
1403
-
1404
1100
static const struct mdp5_cfg_handler cfg_handlers_v1[] = {
1405
1101
{ .revision = 0, .config = { .hw = &msm8x74v1_config } },
1406
1102
{ .revision = 1, .config = { .hw = &msm8x26_config } },
···
1110
1414
{ .revision = 14, .config = { .hw = &msm8937_config } },
1111
1415
{ .revision = 15, .config = { .hw = &msm8917_config } },
1112
1416
{ .revision = 16, .config = { .hw = &msm8x53_config } },
1113
-
};
1114
-
1115
-
static const struct mdp5_cfg_handler cfg_handlers_v3[] = {
1116
-
{ .revision = 0, .config = { .hw = &msm8998_config } },
1117
-
{ .revision = 2, .config = { .hw = &sdm660_config } },
1118
-
{ .revision = 3, .config = { .hw = &sdm630_config } },
1119
1417
};
1120
1418
1121
1419
const struct mdp5_cfg_hw *mdp5_cfg_get_hw_config(struct mdp5_cfg_handler *cfg_handler)
···
1144
1454
case 1:
1145
1455
cfg_handlers = cfg_handlers_v1;
1146
1456
num_handlers = ARRAY_SIZE(cfg_handlers_v1);
1147
-
break;
1148
-
case 3:
1149
-
cfg_handlers = cfg_handlers_v3;
1150
-
num_handlers = ARRAY_SIZE(cfg_handlers_v3);
1151
1457
break;
1152
1458
default:
1153
1459
DRM_DEV_ERROR(dev->dev, "unexpected MDP major version: v%d.%d\n",
+395
-377
drivers/gpu/drm/msm/disp/mdp_format.c
+395
-377
drivers/gpu/drm/msm/disp/mdp_format.c
···
66
66
#define MDP_TILE_HEIGHT_UBWC 4
67
67
#define MDP_TILE_HEIGHT_NV12 8
68
68
69
-
#define INTERLEAVED_RGB_FMT(fmt, a, r, g, b, e0, e1, e2, e3, uc, alpha, \
70
-
bp, flg, fm, np) \
69
+
#define INTERLEAVED_RGB_FMT(fmt, bp, r, g, b, e0, e1, e2) \
71
70
{ \
72
71
.pixel_format = DRM_FORMAT_ ## fmt, \
73
72
.fetch_type = MDP_PLANE_INTERLEAVED, \
74
-
.alpha_enable = alpha, \
75
-
.element = { (e0), (e1), (e2), (e3) }, \
76
-
.bpc_g_y = g, \
77
-
.bpc_b_cb = b, \
78
-
.bpc_r_cr = r, \
79
-
.bpc_a = a, \
80
-
.chroma_sample = CHROMA_FULL, \
81
-
.unpack_count = uc, \
82
-
.bpp = bp, \
83
-
.fetch_mode = fm, \
84
-
.flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
85
-
.num_planes = np, \
86
-
.tile_height = MDP_TILE_HEIGHT_DEFAULT \
87
-
}
88
-
89
-
#define INTERLEAVED_RGB_FMT_TILED(fmt, a, r, g, b, e0, e1, e2, e3, uc, \
90
-
alpha, bp, flg, fm, np, th) \
91
-
{ \
92
-
.pixel_format = DRM_FORMAT_ ## fmt, \
93
-
.fetch_type = MDP_PLANE_INTERLEAVED, \
94
-
.alpha_enable = alpha, \
95
-
.element = { (e0), (e1), (e2), (e3) }, \
96
-
.bpc_g_y = g, \
97
-
.bpc_b_cb = b, \
98
-
.bpc_r_cr = r, \
99
-
.bpc_a = a, \
100
-
.chroma_sample = CHROMA_FULL, \
101
-
.unpack_count = uc, \
102
-
.bpp = bp, \
103
-
.fetch_mode = fm, \
104
-
.flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
105
-
.num_planes = np, \
106
-
.tile_height = th \
107
-
}
108
-
109
-
#define INTERLEAVED_YUV_FMT(fmt, a, r, g, b, e0, e1, e2, e3, \
110
-
alpha, chroma, count, bp, flg, fm, np) \
111
-
{ \
112
-
.pixel_format = DRM_FORMAT_ ## fmt, \
113
-
.fetch_type = MDP_PLANE_INTERLEAVED, \
114
-
.alpha_enable = alpha, \
115
-
.element = { (e0), (e1), (e2), (e3)}, \
116
-
.bpc_g_y = g, \
117
-
.bpc_b_cb = b, \
118
-
.bpc_r_cr = r, \
119
-
.bpc_a = a, \
120
-
.chroma_sample = chroma, \
121
-
.unpack_count = count, \
122
-
.bpp = bp, \
123
-
.fetch_mode = fm, \
124
-
.flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
125
-
.num_planes = np, \
126
-
.tile_height = MDP_TILE_HEIGHT_DEFAULT \
127
-
}
128
-
129
-
#define PSEUDO_YUV_FMT(fmt, a, r, g, b, e0, e1, chroma, flg, fm, np) \
130
-
{ \
131
-
.pixel_format = DRM_FORMAT_ ## fmt, \
132
-
.fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
133
-
.alpha_enable = 0, \
134
-
.element = { (e0), (e1), 0, 0 }, \
135
-
.bpc_g_y = g, \
136
-
.bpc_b_cb = b, \
137
-
.bpc_r_cr = r, \
138
-
.bpc_a = a, \
139
-
.chroma_sample = chroma, \
140
-
.unpack_count = 2, \
141
-
.bpp = 2, \
142
-
.fetch_mode = fm, \
143
-
.flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
144
-
.num_planes = np, \
145
-
.tile_height = MDP_TILE_HEIGHT_DEFAULT \
146
-
}
147
-
148
-
#define PSEUDO_YUV_FMT_TILED(fmt, a, r, g, b, e0, e1, chroma, \
149
-
flg, fm, np, th) \
150
-
{ \
151
-
.pixel_format = DRM_FORMAT_ ## fmt, \
152
-
.fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
153
-
.alpha_enable = 0, \
154
-
.element = { (e0), (e1), 0, 0 }, \
155
-
.bpc_g_y = g, \
156
-
.bpc_b_cb = b, \
157
-
.bpc_r_cr = r, \
158
-
.bpc_a = a, \
159
-
.chroma_sample = chroma, \
160
-
.unpack_count = 2, \
161
-
.bpp = 2, \
162
-
.fetch_mode = fm, \
163
-
.flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
164
-
.num_planes = np, \
165
-
.tile_height = th \
166
-
}
167
-
168
-
#define PSEUDO_YUV_FMT_LOOSE(fmt, a, r, g, b, e0, e1, chroma, flg, fm, np)\
169
-
{ \
170
-
.pixel_format = DRM_FORMAT_ ## fmt, \
171
-
.fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
172
-
.alpha_enable = 0, \
173
-
.element = { (e0), (e1), 0, 0 }, \
174
-
.bpc_g_y = g, \
175
-
.bpc_b_cb = b, \
176
-
.bpc_r_cr = r, \
177
-
.bpc_a = a, \
178
-
.chroma_sample = chroma, \
179
-
.unpack_count = 2, \
180
-
.bpp = 2, \
181
-
.fetch_mode = fm, \
182
-
.flags = MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB | flg, \
183
-
.num_planes = np, \
184
-
.tile_height = MDP_TILE_HEIGHT_DEFAULT \
185
-
}
186
-
187
-
#define PSEUDO_YUV_FMT_LOOSE_TILED(fmt, a, r, g, b, e0, e1, chroma, \
188
-
flg, fm, np, th) \
189
-
{ \
190
-
.pixel_format = DRM_FORMAT_ ## fmt, \
191
-
.fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
192
-
.alpha_enable = 0, \
193
-
.element = { (e0), (e1), 0, 0 }, \
194
-
.bpc_g_y = g, \
195
-
.bpc_b_cb = b, \
196
-
.bpc_r_cr = r, \
197
-
.bpc_a = a, \
198
-
.chroma_sample = chroma, \
199
-
.unpack_count = 2, \
200
-
.bpp = 2, \
201
-
.fetch_mode = fm, \
202
-
.flags = MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB | flg, \
203
-
.num_planes = np, \
204
-
.tile_height = th \
205
-
}
206
-
207
-
#define PLANAR_YUV_FMT(fmt, a, r, g, b, e0, e1, e2, alpha, chroma, bp, \
208
-
flg, fm, np) \
209
-
{ \
210
-
.pixel_format = DRM_FORMAT_ ## fmt, \
211
-
.fetch_type = MDP_PLANE_PLANAR, \
212
-
.alpha_enable = alpha, \
73
+
.alpha_enable = false, \
213
74
.element = { (e0), (e1), (e2), 0 }, \
214
75
.bpc_g_y = g, \
215
76
.bpc_b_cb = b, \
216
77
.bpc_r_cr = r, \
78
+
.bpc_a = 0, \
79
+
.chroma_sample = CHROMA_FULL, \
80
+
.unpack_count = 3, \
81
+
.bpp = bp, \
82
+
.fetch_mode = MDP_FETCH_LINEAR, \
83
+
.flags = MSM_FORMAT_FLAG_UNPACK_TIGHT, \
84
+
.num_planes = 1, \
85
+
.tile_height = MDP_TILE_HEIGHT_DEFAULT \
86
+
}
87
+
88
+
#define INTERLEAVED_RGBA_FMT(fmt, bp, a, r, g, b, e0, e1, e2, e3) \
89
+
{ \
90
+
.pixel_format = DRM_FORMAT_ ## fmt, \
91
+
.fetch_type = MDP_PLANE_INTERLEAVED, \
92
+
.alpha_enable = true, \
93
+
.element = { (e0), (e1), (e2), (e3) }, \
94
+
.bpc_g_y = g, \
95
+
.bpc_b_cb = b, \
96
+
.bpc_r_cr = r, \
217
97
.bpc_a = a, \
98
+
.chroma_sample = CHROMA_FULL, \
99
+
.unpack_count = 4, \
100
+
.bpp = bp, \
101
+
.fetch_mode = MDP_FETCH_LINEAR, \
102
+
.flags = MSM_FORMAT_FLAG_UNPACK_TIGHT, \
103
+
.num_planes = 1, \
104
+
.tile_height = MDP_TILE_HEIGHT_DEFAULT \
105
+
}
106
+
107
+
#define INTERLEAVED_RGBX_FMT(fmt, bp, a, r, g, b, e0, e1, e2, e3) \
108
+
{ \
109
+
.pixel_format = DRM_FORMAT_ ## fmt, \
110
+
.fetch_type = MDP_PLANE_INTERLEAVED, \
111
+
.alpha_enable = false, \
112
+
.element = { (e0), (e1), (e2), (e3) }, \
113
+
.bpc_g_y = g, \
114
+
.bpc_b_cb = b, \
115
+
.bpc_r_cr = r, \
116
+
.bpc_a = a, \
117
+
.chroma_sample = CHROMA_FULL, \
118
+
.unpack_count = 4, \
119
+
.bpp = bp, \
120
+
.fetch_mode = MDP_FETCH_LINEAR, \
121
+
.flags = MSM_FORMAT_FLAG_UNPACK_TIGHT, \
122
+
.num_planes = 1, \
123
+
.tile_height = MDP_TILE_HEIGHT_DEFAULT \
124
+
}
125
+
126
+
#define INTERLEAVED_RGBA_DX_FMT(fmt, bp, a, r, g, b, e0, e1, e2, e3) \
127
+
{ \
128
+
.pixel_format = DRM_FORMAT_ ## fmt, \
129
+
.fetch_type = MDP_PLANE_INTERLEAVED, \
130
+
.alpha_enable = true, \
131
+
.element = { (e0), (e1), (e2), (e3) }, \
132
+
.bpc_g_y = g, \
133
+
.bpc_b_cb = b, \
134
+
.bpc_r_cr = r, \
135
+
.bpc_a = a, \
136
+
.chroma_sample = CHROMA_FULL, \
137
+
.unpack_count = 4, \
138
+
.bpp = bp, \
139
+
.fetch_mode = MDP_FETCH_LINEAR, \
140
+
.flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | \
141
+
MSM_FORMAT_FLAG_DX, \
142
+
.num_planes = 1, \
143
+
.tile_height = MDP_TILE_HEIGHT_DEFAULT \
144
+
}
145
+
146
+
#define INTERLEAVED_RGBX_DX_FMT(fmt, bp, a, r, g, b, e0, e1, e2, e3) \
147
+
{ \
148
+
.pixel_format = DRM_FORMAT_ ## fmt, \
149
+
.fetch_type = MDP_PLANE_INTERLEAVED, \
150
+
.alpha_enable = false, \
151
+
.element = { (e0), (e1), (e2), (e3) }, \
152
+
.bpc_g_y = g, \
153
+
.bpc_b_cb = b, \
154
+
.bpc_r_cr = r, \
155
+
.bpc_a = a, \
156
+
.chroma_sample = CHROMA_FULL, \
157
+
.unpack_count = 4, \
158
+
.bpp = bp, \
159
+
.fetch_mode = MDP_FETCH_LINEAR, \
160
+
.flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | \
161
+
MSM_FORMAT_FLAG_DX, \
162
+
.num_planes = 1, \
163
+
.tile_height = MDP_TILE_HEIGHT_DEFAULT \
164
+
}
165
+
166
+
#define INTERLEAVED_RGB_FMT_TILED(fmt, bp, r, g, b, e0, e1, e2) \
167
+
{ \
168
+
.pixel_format = DRM_FORMAT_ ## fmt, \
169
+
.fetch_type = MDP_PLANE_INTERLEAVED, \
170
+
.alpha_enable = false, \
171
+
.element = { (e0), (e1), (e2), 0 }, \
172
+
.bpc_g_y = g, \
173
+
.bpc_b_cb = b, \
174
+
.bpc_r_cr = r, \
175
+
.bpc_a = 0, \
176
+
.chroma_sample = CHROMA_FULL, \
177
+
.unpack_count = 3, \
178
+
.bpp = bp, \
179
+
.fetch_mode = MDP_FETCH_UBWC, \
180
+
.flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | \
181
+
MSM_FORMAT_FLAG_COMPRESSED, \
182
+
.num_planes = 2, \
183
+
.tile_height = MDP_TILE_HEIGHT_UBWC, \
184
+
}
185
+
186
+
#define INTERLEAVED_RGBA_FMT_TILED(fmt, bp, a, r, g, b, e0, e1, e2, e3) \
187
+
{ \
188
+
.pixel_format = DRM_FORMAT_ ## fmt, \
189
+
.fetch_type = MDP_PLANE_INTERLEAVED, \
190
+
.alpha_enable = true, \
191
+
.element = { (e0), (e1), (e2), (e3) }, \
192
+
.bpc_g_y = g, \
193
+
.bpc_b_cb = b, \
194
+
.bpc_r_cr = r, \
195
+
.bpc_a = a, \
196
+
.chroma_sample = CHROMA_FULL, \
197
+
.unpack_count = 4, \
198
+
.bpp = bp, \
199
+
.fetch_mode = MDP_FETCH_UBWC, \
200
+
.flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | \
201
+
MSM_FORMAT_FLAG_COMPRESSED, \
202
+
.num_planes = 2, \
203
+
.tile_height = MDP_TILE_HEIGHT_UBWC, \
204
+
}
205
+
206
+
#define INTERLEAVED_RGBX_FMT_TILED(fmt, bp, a, r, g, b, e0, e1, e2, e3) \
207
+
{ \
208
+
.pixel_format = DRM_FORMAT_ ## fmt, \
209
+
.fetch_type = MDP_PLANE_INTERLEAVED, \
210
+
.alpha_enable = false, \
211
+
.element = { (e0), (e1), (e2), (e3) }, \
212
+
.bpc_g_y = g, \
213
+
.bpc_b_cb = b, \
214
+
.bpc_r_cr = r, \
215
+
.bpc_a = a, \
216
+
.chroma_sample = CHROMA_FULL, \
217
+
.unpack_count = 4, \
218
+
.bpp = bp, \
219
+
.fetch_mode = MDP_FETCH_UBWC, \
220
+
.flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | \
221
+
MSM_FORMAT_FLAG_COMPRESSED, \
222
+
.num_planes = 2, \
223
+
.tile_height = MDP_TILE_HEIGHT_UBWC, \
224
+
}
225
+
226
+
#define INTERLEAVED_RGBA_DX_FMT_TILED(fmt, bp, a, r, g, b, e0, e1, e2, e3) \
227
+
{ \
228
+
.pixel_format = DRM_FORMAT_ ## fmt, \
229
+
.fetch_type = MDP_PLANE_INTERLEAVED, \
230
+
.alpha_enable = true, \
231
+
.element = { (e0), (e1), (e2), (e3) }, \
232
+
.bpc_g_y = g, \
233
+
.bpc_b_cb = b, \
234
+
.bpc_r_cr = r, \
235
+
.bpc_a = a, \
236
+
.chroma_sample = CHROMA_FULL, \
237
+
.unpack_count = 4, \
238
+
.bpp = bp, \
239
+
.fetch_mode = MDP_FETCH_UBWC, \
240
+
.flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | \
241
+
MSM_FORMAT_FLAG_DX | \
242
+
MSM_FORMAT_FLAG_COMPRESSED, \
243
+
.num_planes = 2, \
244
+
.tile_height = MDP_TILE_HEIGHT_UBWC, \
245
+
}
246
+
247
+
#define INTERLEAVED_YUV_FMT(fmt, bp, r, g, b, e0, e1, e2, e3, chroma) \
248
+
{ \
249
+
.pixel_format = DRM_FORMAT_ ## fmt, \
250
+
.fetch_type = MDP_PLANE_INTERLEAVED, \
251
+
.alpha_enable = false, \
252
+
.element = { (e0), (e1), (e2), (e3)}, \
253
+
.bpc_g_y = g, \
254
+
.bpc_b_cb = b, \
255
+
.bpc_r_cr = r, \
256
+
.bpc_a = 0, \
257
+
.chroma_sample = chroma, \
258
+
.unpack_count = 4, \
259
+
.bpp = bp, \
260
+
.fetch_mode = MDP_FETCH_LINEAR, \
261
+
.flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | \
262
+
MSM_FORMAT_FLAG_YUV, \
263
+
.num_planes = 1, \
264
+
.tile_height = MDP_TILE_HEIGHT_DEFAULT \
265
+
}
266
+
267
+
#define PSEUDO_YUV_FMT(fmt, r, g, b, e0, e1, chroma) \
268
+
{ \
269
+
.pixel_format = DRM_FORMAT_ ## fmt, \
270
+
.fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
271
+
.alpha_enable = 0, \
272
+
.element = { (e0), (e1), 0, 0 }, \
273
+
.bpc_g_y = g, \
274
+
.bpc_b_cb = b, \
275
+
.bpc_r_cr = r, \
276
+
.bpc_a = 0, \
277
+
.chroma_sample = chroma, \
278
+
.unpack_count = 2, \
279
+
.bpp = 2, \
280
+
.fetch_mode = MDP_FETCH_LINEAR, \
281
+
.flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | \
282
+
MSM_FORMAT_FLAG_YUV, \
283
+
.num_planes = 2, \
284
+
.tile_height = MDP_TILE_HEIGHT_DEFAULT \
285
+
}
286
+
287
+
#define PSEUDO_YUV_FMT_TILED(fmt, r, g, b, e0, e1, chroma, flg, th) \
288
+
{ \
289
+
.pixel_format = DRM_FORMAT_ ## fmt, \
290
+
.fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
291
+
.alpha_enable = 0, \
292
+
.element = { (e0), (e1), 0, 0 }, \
293
+
.bpc_g_y = g, \
294
+
.bpc_b_cb = b, \
295
+
.bpc_r_cr = r, \
296
+
.bpc_a = 0, \
297
+
.chroma_sample = chroma, \
298
+
.unpack_count = 2, \
299
+
.bpp = 2, \
300
+
.fetch_mode = MDP_FETCH_UBWC, \
301
+
.flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | \
302
+
MSM_FORMAT_FLAG_YUV | \
303
+
MSM_FORMAT_FLAG_COMPRESSED | flg, \
304
+
.num_planes = 4, \
305
+
.tile_height = th \
306
+
}
307
+
308
+
#define PSEUDO_YUV_FMT_LOOSE(fmt, r, g, b, e0, e1, chroma) \
309
+
{ \
310
+
.pixel_format = DRM_FORMAT_ ## fmt, \
311
+
.fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
312
+
.alpha_enable = 0, \
313
+
.element = { (e0), (e1), 0, 0 }, \
314
+
.bpc_g_y = g, \
315
+
.bpc_b_cb = b, \
316
+
.bpc_r_cr = r, \
317
+
.bpc_a = 0, \
318
+
.chroma_sample = chroma, \
319
+
.unpack_count = 2, \
320
+
.bpp = 2, \
321
+
.fetch_mode = MDP_FETCH_LINEAR, \
322
+
.flags = MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB | \
323
+
MSM_FORMAT_FLAG_DX | \
324
+
MSM_FORMAT_FLAG_YUV, \
325
+
.num_planes = 2, \
326
+
.tile_height = MDP_TILE_HEIGHT_DEFAULT \
327
+
}
328
+
329
+
#define PLANAR_YUV_FMT(fmt, bp, r, g, b, e0, e1, e2, chroma) \
330
+
{ \
331
+
.pixel_format = DRM_FORMAT_ ## fmt, \
332
+
.fetch_type = MDP_PLANE_PLANAR, \
333
+
.alpha_enable = false, \
334
+
.element = { (e0), (e1), (e2), 0 }, \
335
+
.bpc_g_y = g, \
336
+
.bpc_b_cb = b, \
337
+
.bpc_r_cr = r, \
338
+
.bpc_a = 0, \
218
339
.chroma_sample = chroma, \
219
340
.unpack_count = 1, \
220
341
.bpp = bp, \
221
-
.fetch_mode = fm, \
222
-
.flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
223
-
.num_planes = np, \
342
+
.fetch_mode = MDP_FETCH_LINEAR, \
343
+
.flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | \
344
+
MSM_FORMAT_FLAG_YUV, \
345
+
.num_planes = 3, \
224
346
.tile_height = MDP_TILE_HEIGHT_DEFAULT \
225
347
}
226
348
227
349
static const struct msm_format mdp_formats[] = {
228
-
INTERLEAVED_RGB_FMT(ARGB8888,
350
+
INTERLEAVED_RGBA_FMT(ARGB8888, 4,
229
351
BPC8A, BPC8, BPC8, BPC8,
230
-
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
231
-
true, 4, 0,
232
-
MDP_FETCH_LINEAR, 1),
352
+
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA),
233
353
234
-
INTERLEAVED_RGB_FMT(ABGR8888,
354
+
INTERLEAVED_RGBA_FMT(ABGR8888, 4,
235
355
BPC8A, BPC8, BPC8, BPC8,
236
-
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
237
-
true, 4, 0,
238
-
MDP_FETCH_LINEAR, 1),
356
+
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA),
239
357
240
-
INTERLEAVED_RGB_FMT(XBGR8888,
358
+
INTERLEAVED_RGBX_FMT(XBGR8888, 4,
241
359
BPC8A, BPC8, BPC8, BPC8,
242
-
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
243
-
false, 4, 0,
244
-
MDP_FETCH_LINEAR, 1),
360
+
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA),
245
361
246
-
INTERLEAVED_RGB_FMT(RGBA8888,
362
+
INTERLEAVED_RGBA_FMT(RGBA8888, 4,
247
363
BPC8A, BPC8, BPC8, BPC8,
248
-
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
249
-
true, 4, 0,
250
-
MDP_FETCH_LINEAR, 1),
364
+
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr),
251
365
252
-
INTERLEAVED_RGB_FMT(BGRA8888,
366
+
INTERLEAVED_RGBA_FMT(BGRA8888, 4,
253
367
BPC8A, BPC8, BPC8, BPC8,
254
-
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
255
-
true, 4, 0,
256
-
MDP_FETCH_LINEAR, 1),
368
+
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb),
257
369
258
-
INTERLEAVED_RGB_FMT(BGRX8888,
370
+
INTERLEAVED_RGBX_FMT(BGRX8888, 4,
259
371
BPC8A, BPC8, BPC8, BPC8,
260
-
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
261
-
false, 4, 0,
262
-
MDP_FETCH_LINEAR, 1),
372
+
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb),
263
373
264
-
INTERLEAVED_RGB_FMT(XRGB8888,
374
+
INTERLEAVED_RGBX_FMT(XRGB8888, 4,
265
375
BPC8A, BPC8, BPC8, BPC8,
266
-
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
267
-
false, 4, 0,
268
-
MDP_FETCH_LINEAR, 1),
376
+
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA),
269
377
270
-
INTERLEAVED_RGB_FMT(RGBX8888,
378
+
INTERLEAVED_RGBX_FMT(RGBX8888, 4,
271
379
BPC8A, BPC8, BPC8, BPC8,
272
-
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
273
-
false, 4, 0,
274
-
MDP_FETCH_LINEAR, 1),
380
+
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr),
275
381
276
-
INTERLEAVED_RGB_FMT(RGB888,
277
-
0, BPC8, BPC8, BPC8,
278
-
C1_B_Cb, C0_G_Y, C2_R_Cr, 0, 3,
279
-
false, 3, 0,
280
-
MDP_FETCH_LINEAR, 1),
382
+
INTERLEAVED_RGB_FMT(RGB888, 3,
383
+
BPC8, BPC8, BPC8,
384
+
C1_B_Cb, C0_G_Y, C2_R_Cr),
281
385
282
-
INTERLEAVED_RGB_FMT(BGR888,
283
-
0, BPC8, BPC8, BPC8,
284
-
C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
285
-
false, 3, 0,
286
-
MDP_FETCH_LINEAR, 1),
386
+
INTERLEAVED_RGB_FMT(BGR888, 3,
387
+
BPC8, BPC8, BPC8,
388
+
C2_R_Cr, C0_G_Y, C1_B_Cb),
287
389
288
-
INTERLEAVED_RGB_FMT(RGB565,
289
-
0, BPC5, BPC6, BPC5,
290
-
C1_B_Cb, C0_G_Y, C2_R_Cr, 0, 3,
291
-
false, 2, 0,
292
-
MDP_FETCH_LINEAR, 1),
390
+
INTERLEAVED_RGB_FMT(RGB565, 2,
391
+
BPC5, BPC6, BPC5,
392
+
C1_B_Cb, C0_G_Y, C2_R_Cr),
293
393
294
-
INTERLEAVED_RGB_FMT(BGR565,
295
-
0, BPC5, BPC6, BPC5,
296
-
C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
297
-
false, 2, 0,
298
-
MDP_FETCH_LINEAR, 1),
394
+
INTERLEAVED_RGB_FMT(BGR565, 2,
395
+
BPC5, BPC6, BPC5,
396
+
C2_R_Cr, C0_G_Y, C1_B_Cb),
299
397
300
-
INTERLEAVED_RGB_FMT(ARGB1555,
398
+
INTERLEAVED_RGBA_FMT(ARGB1555, 2,
301
399
BPC1A, BPC5, BPC5, BPC5,
302
-
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
303
-
true, 2, 0,
304
-
MDP_FETCH_LINEAR, 1),
400
+
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA),
305
401
306
-
INTERLEAVED_RGB_FMT(ABGR1555,
402
+
INTERLEAVED_RGBA_FMT(ABGR1555, 2,
307
403
BPC1A, BPC5, BPC5, BPC5,
308
-
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
309
-
true, 2, 0,
310
-
MDP_FETCH_LINEAR, 1),
404
+
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA),
311
405
312
-
INTERLEAVED_RGB_FMT(RGBA5551,
406
+
INTERLEAVED_RGBA_FMT(RGBA5551, 2,
313
407
BPC1A, BPC5, BPC5, BPC5,
314
-
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
315
-
true, 2, 0,
316
-
MDP_FETCH_LINEAR, 1),
408
+
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr),
317
409
318
-
INTERLEAVED_RGB_FMT(BGRA5551,
410
+
INTERLEAVED_RGBA_FMT(BGRA5551, 2,
319
411
BPC1A, BPC5, BPC5, BPC5,
320
-
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
321
-
true, 2, 0,
322
-
MDP_FETCH_LINEAR, 1),
412
+
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb),
323
413
324
-
INTERLEAVED_RGB_FMT(XRGB1555,
414
+
INTERLEAVED_RGBX_FMT(XRGB1555, 2,
325
415
BPC1A, BPC5, BPC5, BPC5,
326
-
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
327
-
false, 2, 0,
328
-
MDP_FETCH_LINEAR, 1),
416
+
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA),
329
417
330
-
INTERLEAVED_RGB_FMT(XBGR1555,
418
+
INTERLEAVED_RGBX_FMT(XBGR1555, 2,
331
419
BPC1A, BPC5, BPC5, BPC5,
332
-
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
333
-
false, 2, 0,
334
-
MDP_FETCH_LINEAR, 1),
420
+
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA),
335
421
336
-
INTERLEAVED_RGB_FMT(RGBX5551,
422
+
INTERLEAVED_RGBX_FMT(RGBX5551, 2,
337
423
BPC1A, BPC5, BPC5, BPC5,
338
-
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
339
-
false, 2, 0,
340
-
MDP_FETCH_LINEAR, 1),
424
+
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr),
341
425
342
-
INTERLEAVED_RGB_FMT(BGRX5551,
426
+
INTERLEAVED_RGBX_FMT(BGRX5551, 2,
343
427
BPC1A, BPC5, BPC5, BPC5,
344
-
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
345
-
false, 2, 0,
346
-
MDP_FETCH_LINEAR, 1),
428
+
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb),
347
429
348
-
INTERLEAVED_RGB_FMT(ARGB4444,
430
+
INTERLEAVED_RGBA_FMT(ARGB4444, 2,
349
431
BPC4A, BPC4, BPC4, BPC4,
350
-
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
351
-
true, 2, 0,
352
-
MDP_FETCH_LINEAR, 1),
432
+
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA),
353
433
354
-
INTERLEAVED_RGB_FMT(ABGR4444,
434
+
INTERLEAVED_RGBA_FMT(ABGR4444, 2,
355
435
BPC4A, BPC4, BPC4, BPC4,
356
-
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
357
-
true, 2, 0,
358
-
MDP_FETCH_LINEAR, 1),
436
+
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA),
359
437
360
-
INTERLEAVED_RGB_FMT(RGBA4444,
438
+
INTERLEAVED_RGBA_FMT(RGBA4444, 2,
361
439
BPC4A, BPC4, BPC4, BPC4,
362
-
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
363
-
true, 2, 0,
364
-
MDP_FETCH_LINEAR, 1),
440
+
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr),
365
441
366
-
INTERLEAVED_RGB_FMT(BGRA4444,
442
+
INTERLEAVED_RGBA_FMT(BGRA4444, 2,
367
443
BPC4A, BPC4, BPC4, BPC4,
368
-
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
369
-
true, 2, 0,
370
-
MDP_FETCH_LINEAR, 1),
444
+
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb),
371
445
372
-
INTERLEAVED_RGB_FMT(XRGB4444,
446
+
INTERLEAVED_RGBX_FMT(XRGB4444, 2,
373
447
BPC4A, BPC4, BPC4, BPC4,
374
-
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
375
-
false, 2, 0,
376
-
MDP_FETCH_LINEAR, 1),
448
+
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA),
377
449
378
-
INTERLEAVED_RGB_FMT(XBGR4444,
450
+
INTERLEAVED_RGBX_FMT(XBGR4444, 2,
379
451
BPC4A, BPC4, BPC4, BPC4,
380
-
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
381
-
false, 2, 0,
382
-
MDP_FETCH_LINEAR, 1),
452
+
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA),
383
453
384
-
INTERLEAVED_RGB_FMT(RGBX4444,
454
+
INTERLEAVED_RGBX_FMT(RGBX4444, 2,
385
455
BPC4A, BPC4, BPC4, BPC4,
386
-
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
387
-
false, 2, 0,
388
-
MDP_FETCH_LINEAR, 1),
456
+
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr),
389
457
390
-
INTERLEAVED_RGB_FMT(BGRX4444,
458
+
INTERLEAVED_RGBX_FMT(BGRX4444, 2,
391
459
BPC4A, BPC4, BPC4, BPC4,
392
-
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
393
-
false, 2, 0,
394
-
MDP_FETCH_LINEAR, 1),
460
+
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb),
395
461
396
-
INTERLEAVED_RGB_FMT(BGRA1010102,
462
+
INTERLEAVED_RGBA_DX_FMT(BGRA1010102, 4,
397
463
BPC8A, BPC8, BPC8, BPC8,
398
-
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
399
-
true, 4, MSM_FORMAT_FLAG_DX,
400
-
MDP_FETCH_LINEAR, 1),
464
+
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb),
401
465
402
-
INTERLEAVED_RGB_FMT(RGBA1010102,
466
+
INTERLEAVED_RGBA_DX_FMT(RGBA1010102, 4,
403
467
BPC8A, BPC8, BPC8, BPC8,
404
-
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
405
-
true, 4, MSM_FORMAT_FLAG_DX,
406
-
MDP_FETCH_LINEAR, 1),
468
+
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr),
407
469
408
-
INTERLEAVED_RGB_FMT(ABGR2101010,
470
+
INTERLEAVED_RGBA_DX_FMT(ABGR2101010, 4,
409
471
BPC8A, BPC8, BPC8, BPC8,
410
-
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
411
-
true, 4, MSM_FORMAT_FLAG_DX,
412
-
MDP_FETCH_LINEAR, 1),
472
+
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA),
413
473
414
-
INTERLEAVED_RGB_FMT(ARGB2101010,
474
+
INTERLEAVED_RGBA_DX_FMT(ARGB2101010, 4,
415
475
BPC8A, BPC8, BPC8, BPC8,
416
-
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
417
-
true, 4, MSM_FORMAT_FLAG_DX,
418
-
MDP_FETCH_LINEAR, 1),
476
+
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA),
419
477
420
-
INTERLEAVED_RGB_FMT(XRGB2101010,
478
+
INTERLEAVED_RGBX_DX_FMT(XRGB2101010, 4,
421
479
BPC8A, BPC8, BPC8, BPC8,
422
-
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
423
-
false, 4, MSM_FORMAT_FLAG_DX,
424
-
MDP_FETCH_LINEAR, 1),
480
+
C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA),
425
481
426
-
INTERLEAVED_RGB_FMT(BGRX1010102,
482
+
INTERLEAVED_RGBX_DX_FMT(BGRX1010102, 4,
427
483
BPC8A, BPC8, BPC8, BPC8,
428
-
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
429
-
false, 4, MSM_FORMAT_FLAG_DX,
430
-
MDP_FETCH_LINEAR, 1),
484
+
C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb),
431
485
432
-
INTERLEAVED_RGB_FMT(XBGR2101010,
486
+
INTERLEAVED_RGBX_DX_FMT(XBGR2101010, 4,
433
487
BPC8A, BPC8, BPC8, BPC8,
434
-
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
435
-
false, 4, MSM_FORMAT_FLAG_DX,
436
-
MDP_FETCH_LINEAR, 1),
488
+
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA),
437
489
438
-
INTERLEAVED_RGB_FMT(RGBX1010102,
490
+
INTERLEAVED_RGBX_DX_FMT(RGBX1010102, 4,
439
491
BPC8A, BPC8, BPC8, BPC8,
440
-
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
441
-
false, 4, MSM_FORMAT_FLAG_DX,
442
-
MDP_FETCH_LINEAR, 1),
492
+
C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr),
443
493
444
494
/* --- RGB formats above / YUV formats below this line --- */
445
495
446
496
/* 2 plane YUV */
447
497
PSEUDO_YUV_FMT(NV12,
448
-
0, BPC8, BPC8, BPC8,
498
+
BPC8, BPC8, BPC8,
449
499
C1_B_Cb, C2_R_Cr,
450
-
CHROMA_420, MSM_FORMAT_FLAG_YUV,
451
-
MDP_FETCH_LINEAR, 2),
500
+
CHROMA_420),
452
501
453
502
PSEUDO_YUV_FMT(NV21,
454
-
0, BPC8, BPC8, BPC8,
503
+
BPC8, BPC8, BPC8,
455
504
C2_R_Cr, C1_B_Cb,
456
-
CHROMA_420, MSM_FORMAT_FLAG_YUV,
457
-
MDP_FETCH_LINEAR, 2),
505
+
CHROMA_420),
458
506
459
507
PSEUDO_YUV_FMT(NV16,
460
-
0, BPC8, BPC8, BPC8,
508
+
BPC8, BPC8, BPC8,
461
509
C1_B_Cb, C2_R_Cr,
462
-
CHROMA_H2V1, MSM_FORMAT_FLAG_YUV,
463
-
MDP_FETCH_LINEAR, 2),
510
+
CHROMA_H2V1),
464
511
465
512
PSEUDO_YUV_FMT(NV61,
466
-
0, BPC8, BPC8, BPC8,
513
+
BPC8, BPC8, BPC8,
467
514
C2_R_Cr, C1_B_Cb,
468
-
CHROMA_H2V1, MSM_FORMAT_FLAG_YUV,
469
-
MDP_FETCH_LINEAR, 2),
515
+
CHROMA_H2V1),
470
516
471
517
PSEUDO_YUV_FMT_LOOSE(P010,
472
-
0, BPC8, BPC8, BPC8,
518
+
BPC8, BPC8, BPC8,
473
519
C1_B_Cb, C2_R_Cr,
474
-
CHROMA_420, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_YUV,
475
-
MDP_FETCH_LINEAR, 2),
520
+
CHROMA_420),
476
521
477
522
/* 1 plane YUV */
478
-
INTERLEAVED_YUV_FMT(VYUY,
479
-
0, BPC8, BPC8, BPC8,
523
+
INTERLEAVED_YUV_FMT(VYUY, 2,
524
+
BPC8, BPC8, BPC8,
480
525
C2_R_Cr, C0_G_Y, C1_B_Cb, C0_G_Y,
481
-
false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
482
-
MDP_FETCH_LINEAR, 2),
526
+
CHROMA_H2V1),
483
527
484
-
INTERLEAVED_YUV_FMT(UYVY,
485
-
0, BPC8, BPC8, BPC8,
528
+
INTERLEAVED_YUV_FMT(UYVY, 2,
529
+
BPC8, BPC8, BPC8,
486
530
C1_B_Cb, C0_G_Y, C2_R_Cr, C0_G_Y,
487
-
false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
488
-
MDP_FETCH_LINEAR, 2),
531
+
CHROMA_H2V1),
489
532
490
-
INTERLEAVED_YUV_FMT(YUYV,
491
-
0, BPC8, BPC8, BPC8,
533
+
INTERLEAVED_YUV_FMT(YUYV, 2,
534
+
BPC8, BPC8, BPC8,
492
535
C0_G_Y, C1_B_Cb, C0_G_Y, C2_R_Cr,
493
-
false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
494
-
MDP_FETCH_LINEAR, 2),
536
+
CHROMA_H2V1),
495
537
496
-
INTERLEAVED_YUV_FMT(YVYU,
497
-
0, BPC8, BPC8, BPC8,
538
+
INTERLEAVED_YUV_FMT(YVYU, 2,
539
+
BPC8, BPC8, BPC8,
498
540
C0_G_Y, C2_R_Cr, C0_G_Y, C1_B_Cb,
499
-
false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
500
-
MDP_FETCH_LINEAR, 2),
541
+
CHROMA_H2V1),
501
542
502
543
/* 3 plane YUV */
503
-
PLANAR_YUV_FMT(YUV420,
504
-
0, BPC8, BPC8, BPC8,
544
+
PLANAR_YUV_FMT(YUV420, 1,
545
+
BPC8, BPC8, BPC8,
505
546
C2_R_Cr, C1_B_Cb, C0_G_Y,
506
-
false, CHROMA_420, 1, MSM_FORMAT_FLAG_YUV,
507
-
MDP_FETCH_LINEAR, 3),
547
+
CHROMA_420),
508
548
509
-
PLANAR_YUV_FMT(YVU420,
510
-
0, BPC8, BPC8, BPC8,
549
+
PLANAR_YUV_FMT(YVU420, 1,
550
+
BPC8, BPC8, BPC8,
511
551
C1_B_Cb, C2_R_Cr, C0_G_Y,
512
-
false, CHROMA_420, 1, MSM_FORMAT_FLAG_YUV,
513
-
MDP_FETCH_LINEAR, 3),
552
+
CHROMA_420),
514
553
};
515
554
516
555
/*
···
559
520
* the data will be passed by user-space.
560
521
*/
561
522
static const struct msm_format mdp_formats_ubwc[] = {
562
-
INTERLEAVED_RGB_FMT_TILED(BGR565,
563
-
0, BPC5, BPC6, BPC5,
564
-
C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
565
-
false, 2, MSM_FORMAT_FLAG_COMPRESSED,
566
-
MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
523
+
INTERLEAVED_RGB_FMT_TILED(BGR565, 2,
524
+
BPC5, BPC6, BPC5,
525
+
C2_R_Cr, C0_G_Y, C1_B_Cb),
567
526
568
-
INTERLEAVED_RGB_FMT_TILED(ABGR8888,
527
+
INTERLEAVED_RGBA_FMT_TILED(ABGR8888, 4,
569
528
BPC8A, BPC8, BPC8, BPC8,
570
-
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
571
-
true, 4, MSM_FORMAT_FLAG_COMPRESSED,
572
-
MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
529
+
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA),
573
530
574
531
/* ARGB8888 and ABGR8888 purposely have the same color
575
532
* ordering. The hardware only supports ABGR8888 UBWC
576
533
* natively.
577
534
*/
578
-
INTERLEAVED_RGB_FMT_TILED(ARGB8888,
535
+
INTERLEAVED_RGBA_FMT_TILED(ARGB8888, 4,
579
536
BPC8A, BPC8, BPC8, BPC8,
580
-
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
581
-
true, 4, MSM_FORMAT_FLAG_COMPRESSED,
582
-
MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
537
+
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA),
583
538
584
-
INTERLEAVED_RGB_FMT_TILED(XBGR8888,
539
+
INTERLEAVED_RGBX_FMT_TILED(XBGR8888, 4,
585
540
BPC8A, BPC8, BPC8, BPC8,
586
-
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
587
-
false, 4, MSM_FORMAT_FLAG_COMPRESSED,
588
-
MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
541
+
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA),
589
542
590
-
INTERLEAVED_RGB_FMT_TILED(XRGB8888,
543
+
INTERLEAVED_RGBX_FMT_TILED(XRGB8888, 4,
591
544
BPC8A, BPC8, BPC8, BPC8,
592
-
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
593
-
false, 4, MSM_FORMAT_FLAG_COMPRESSED,
594
-
MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
545
+
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA),
595
546
596
-
INTERLEAVED_RGB_FMT_TILED(ABGR2101010,
547
+
INTERLEAVED_RGBA_DX_FMT_TILED(ABGR2101010, 4,
597
548
BPC8A, BPC8, BPC8, BPC8,
598
-
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
599
-
true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
600
-
MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
549
+
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA),
601
550
602
-
INTERLEAVED_RGB_FMT_TILED(XBGR2101010,
551
+
INTERLEAVED_RGBA_DX_FMT_TILED(XBGR2101010, 4,
603
552
BPC8A, BPC8, BPC8, BPC8,
604
-
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
605
-
true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
606
-
MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
553
+
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA),
607
554
608
-
INTERLEAVED_RGB_FMT_TILED(XRGB2101010,
555
+
INTERLEAVED_RGBA_DX_FMT_TILED(XRGB2101010, 4,
609
556
BPC8A, BPC8, BPC8, BPC8,
610
-
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
611
-
true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
612
-
MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
557
+
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA),
613
558
614
559
/* XRGB2101010 and ARGB2101010 purposely have the same color
615
560
* ordering. The hardware only supports ARGB2101010 UBWC
616
561
* natively.
617
562
*/
618
-
INTERLEAVED_RGB_FMT_TILED(ARGB2101010,
563
+
INTERLEAVED_RGBA_DX_FMT_TILED(ARGB2101010, 4,
619
564
BPC8A, BPC8, BPC8, BPC8,
620
-
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
621
-
true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
622
-
MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
565
+
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA),
623
566
624
567
PSEUDO_YUV_FMT_TILED(NV12,
625
-
0, BPC8, BPC8, BPC8,
568
+
BPC8, BPC8, BPC8,
626
569
C1_B_Cb, C2_R_Cr,
627
-
CHROMA_420, MSM_FORMAT_FLAG_YUV |
628
-
MSM_FORMAT_FLAG_COMPRESSED,
629
-
MDP_FETCH_UBWC, 4, MDP_TILE_HEIGHT_NV12),
570
+
CHROMA_420, 0,
571
+
MDP_TILE_HEIGHT_NV12),
630
572
631
573
PSEUDO_YUV_FMT_TILED(P010,
632
-
0, BPC8, BPC8, BPC8,
574
+
BPC8, BPC8, BPC8,
633
575
C1_B_Cb, C2_R_Cr,
634
-
CHROMA_420, MSM_FORMAT_FLAG_DX |
635
-
MSM_FORMAT_FLAG_YUV |
636
-
MSM_FORMAT_FLAG_COMPRESSED,
637
-
MDP_FETCH_UBWC, 4, MDP_TILE_HEIGHT_UBWC),
576
+
CHROMA_420, MSM_FORMAT_FLAG_DX,
577
+
MDP_TILE_HEIGHT_UBWC),
638
578
};
639
579
640
580
const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format,
+53
-27
drivers/gpu/drm/msm/dp/dp_ctrl.c
+53
-27
drivers/gpu/drm/msm/dp/dp_ctrl.c
···
175
175
static int msm_dp_aux_link_configure(struct drm_dp_aux *aux,
176
176
struct msm_dp_link_info *link)
177
177
{
178
-
u8 values[2];
178
+
u8 lane_count, bw_code;
179
179
int err;
180
180
181
-
values[0] = drm_dp_link_rate_to_bw_code(link->rate);
182
-
values[1] = link->num_lanes;
181
+
lane_count = link->num_lanes;
183
182
184
183
if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
185
-
values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
184
+
lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
186
185
187
-
err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values));
186
+
err = drm_dp_dpcd_writeb(aux, DP_LANE_COUNT_SET, lane_count);
188
187
if (err < 0)
189
188
return err;
190
189
191
-
return 0;
190
+
if (link->use_rate_set) {
191
+
DRM_DEBUG_DP("using LINK_RATE_SET: 0x%02x", link->rate_set);
192
+
err = drm_dp_dpcd_writeb(aux, DP_LINK_RATE_SET, link->rate_set);
193
+
} else {
194
+
bw_code = drm_dp_link_rate_to_bw_code(link->rate);
195
+
DRM_DEBUG_DP("using LINK_BW_SET: 0x%02x", bw_code);
196
+
err = drm_dp_dpcd_writeb(aux, DP_LINK_BW_SET, bw_code);
197
+
}
198
+
199
+
return err;
192
200
}
193
201
194
202
/*
···
1482
1474
static int msm_dp_ctrl_link_rate_down_shift(struct msm_dp_ctrl_private *ctrl)
1483
1475
{
1484
1476
int ret = 0;
1477
+
struct msm_dp_link_info *link_params = &ctrl->link->link_params;
1485
1478
1486
-
switch (ctrl->link->link_params.rate) {
1487
-
case 810000:
1488
-
ctrl->link->link_params.rate = 540000;
1489
-
break;
1490
-
case 540000:
1491
-
ctrl->link->link_params.rate = 270000;
1492
-
break;
1493
-
case 270000:
1494
-
ctrl->link->link_params.rate = 162000;
1495
-
break;
1496
-
case 162000:
1497
-
default:
1498
-
ret = -EINVAL;
1499
-
break;
1479
+
if (link_params->rate_set) {
1480
+
--link_params->rate_set;
1481
+
link_params->rate = link_params->supported_rates[link_params->rate_set];
1482
+
} else {
1483
+
switch (link_params->rate) {
1484
+
case 810000:
1485
+
link_params->rate = 540000;
1486
+
break;
1487
+
case 540000:
1488
+
link_params->rate = 270000;
1489
+
break;
1490
+
case 270000:
1491
+
link_params->rate = 162000;
1492
+
break;
1493
+
case 162000:
1494
+
default:
1495
+
ret = -EINVAL;
1496
+
break;
1497
+
}
1500
1498
}
1501
1499
1502
1500
if (!ret) {
1503
1501
drm_dbg_dp(ctrl->drm_dev, "new rate=0x%x\n",
1504
-
ctrl->link->link_params.rate);
1502
+
link_params->rate);
1505
1503
}
1506
1504
1507
1505
return ret;
···
2409
2395
bool is_ycbcr_420)
2410
2396
{
2411
2397
u32 pixel_m, pixel_n;
2412
-
u32 mvid, nvid, pixel_div = 0, dispcc_input_rate;
2398
+
u32 mvid, nvid, pixel_div, dispcc_input_rate;
2413
2399
u32 const nvid_fixed = DP_LINK_CONSTANT_N_VALUE;
2414
2400
u32 const link_rate_hbr2 = 540000;
2415
2401
u32 const link_rate_hbr3 = 810000;
2416
2402
unsigned long den, num;
2417
2403
2418
-
if (rate == link_rate_hbr3)
2404
+
switch (rate) {
2405
+
case link_rate_hbr3:
2419
2406
pixel_div = 6;
2420
-
else if (rate == 162000 || rate == 270000)
2421
-
pixel_div = 2;
2422
-
else if (rate == link_rate_hbr2)
2407
+
break;
2408
+
case link_rate_hbr2:
2423
2409
pixel_div = 4;
2424
-
else
2410
+
break;
2411
+
case 162000:
2412
+
case 270000:
2413
+
pixel_div = 2;
2414
+
break;
2415
+
default:
2416
+
/*
2417
+
* This cannot be reached but the compiler is not able to know
2418
+
* that statically so return early to avoid a possibly invalid
2419
+
* division.
2420
+
*/
2425
2421
DRM_ERROR("Invalid pixel mux divider\n");
2422
+
return;
2423
+
}
2426
2424
2427
2425
dispcc_input_rate = (rate * 10) / pixel_div;
2428
2426
+2
-2
drivers/gpu/drm/msm/dp/dp_display.c
+2
-2
drivers/gpu/drm/msm/dp/dp_display.c
···
141
141
static const struct msm_dp_desc msm_dp_desc_sa8775p[] = {
142
142
{ .io_start = 0x0af54000, .id = MSM_DP_CONTROLLER_0, .wide_bus_supported = true },
143
143
{ .io_start = 0x0af5c000, .id = MSM_DP_CONTROLLER_1, .wide_bus_supported = true },
144
-
{ .io_start = 0x22154000, .id = MSM_DP_CONTROLLER_2, .wide_bus_supported = true },
145
-
{ .io_start = 0x2215c000, .id = MSM_DP_CONTROLLER_3, .wide_bus_supported = true },
144
+
{ .io_start = 0x22154000, .id = MSM_DP_CONTROLLER_0, .wide_bus_supported = true },
145
+
{ .io_start = 0x2215c000, .id = MSM_DP_CONTROLLER_1, .wide_bus_supported = true },
146
146
{}
147
147
};
148
148
+3
drivers/gpu/drm/msm/dp/dp_link.h
+3
drivers/gpu/drm/msm/dp/dp_link.h
+82
-11
drivers/gpu/drm/msm/dp/dp_panel.c
+82
-11
drivers/gpu/drm/msm/dp/dp_panel.c
···
13
13
#include <drm/drm_print.h>
14
14
15
15
#include <linux/io.h>
16
+
#include <linux/types.h>
17
+
#include <asm/byteorder.h>
16
18
17
19
#define DP_INTF_CONFIG_DATABUS_WIDEN BIT(4)
18
20
···
109
107
drm_dbg_dp(panel->drm_dev, "max_lanes=%d max_link_rate=%d\n",
110
108
link->max_dp_lanes, link->max_dp_link_rate);
111
109
112
-
link_info->rate = drm_dp_max_link_rate(dpcd);
110
+
max_lttpr_lanes = drm_dp_lttpr_max_lane_count(link->lttpr_common_caps);
111
+
max_lttpr_rate = drm_dp_lttpr_max_link_rate(link->lttpr_common_caps);
112
+
113
+
/* eDP sink */
114
+
if (msm_dp_panel->dpcd[DP_EDP_CONFIGURATION_CAP]) {
115
+
u8 edp_rev;
116
+
117
+
rc = drm_dp_dpcd_read_byte(panel->aux, DP_EDP_DPCD_REV, &edp_rev);
118
+
if (rc)
119
+
return rc;
120
+
121
+
drm_dbg_dp(panel->drm_dev, "edp_rev=0x%x\n", edp_rev);
122
+
123
+
/* For eDP v1.4+, parse the SUPPORTED_LINK_RATES table */
124
+
if (edp_rev >= DP_EDP_14) {
125
+
__le16 rates[DP_MAX_SUPPORTED_RATES];
126
+
u8 bw_set;
127
+
int i;
128
+
129
+
rc = drm_dp_dpcd_read_data(panel->aux, DP_SUPPORTED_LINK_RATES,
130
+
rates, sizeof(rates));
131
+
if (rc)
132
+
return rc;
133
+
134
+
rc = drm_dp_dpcd_read_byte(panel->aux, DP_LINK_BW_SET, &bw_set);
135
+
if (rc)
136
+
return rc;
137
+
138
+
/* Find index of max supported link rate that does not exceed dtsi limits */
139
+
for (i = 0; i < ARRAY_SIZE(rates); i++) {
140
+
/*
141
+
* The value from the DPCD multiplied by 200 gives
142
+
* the link rate in kHz. Divide by 10 to convert to
143
+
* symbol rate, accounting for 8b/10b encoding.
144
+
*/
145
+
u32 rate = (le16_to_cpu(rates[i]) * 200) / 10;
146
+
147
+
if (!rate)
148
+
break;
149
+
150
+
drm_dbg_dp(panel->drm_dev,
151
+
"SUPPORTED_LINK_RATES[%d]: %d\n", i, rate);
152
+
153
+
/*
154
+
* Limit link rate from link-frequencies of endpoint
155
+
* property of dtsi
156
+
*/
157
+
if (rate > link->max_dp_link_rate)
158
+
break;
159
+
160
+
/* Limit link rate from LTTPR capabilities, if any */
161
+
if (max_lttpr_rate && rate > max_lttpr_rate)
162
+
break;
163
+
164
+
link_info->rate = rate;
165
+
link_info->supported_rates[i] = rate;
166
+
link_info->rate_set = i;
167
+
}
168
+
169
+
/* Only use LINK_RATE_SET if LINK_BW_SET hasn't already been written to */
170
+
if (!bw_set && link_info->rate)
171
+
link_info->use_rate_set = true;
172
+
}
173
+
}
174
+
175
+
/* Fall back on MAX_LINK_RATE/LINK_BW_SET (DP, eDP <= v1.3) */
176
+
if (!link_info->rate) {
177
+
link_info->rate = drm_dp_max_link_rate(dpcd);
178
+
179
+
/* Limit link rate from link-frequencies of endpoint property of dtsi */
180
+
if (link_info->rate > link->max_dp_link_rate)
181
+
link_info->rate = link->max_dp_link_rate;
182
+
183
+
/* Limit link rate from LTTPR capabilities, if any */
184
+
if (max_lttpr_rate && max_lttpr_rate < link_info->rate)
185
+
link_info->rate = max_lttpr_rate;
186
+
}
187
+
113
188
link_info->num_lanes = drm_dp_max_lane_count(dpcd);
114
189
115
190
/* Limit data lanes from data-lanes of endpoint property of dtsi */
116
191
if (link_info->num_lanes > link->max_dp_lanes)
117
192
link_info->num_lanes = link->max_dp_lanes;
118
193
119
-
/* Limit link rate from link-frequencies of endpoint property of dtsi */
120
-
if (link_info->rate > link->max_dp_link_rate)
121
-
link_info->rate = link->max_dp_link_rate;
122
-
123
194
/* Limit data lanes from LTTPR capabilities, if any */
124
-
max_lttpr_lanes = drm_dp_lttpr_max_lane_count(panel->link->lttpr_common_caps);
125
195
if (max_lttpr_lanes && max_lttpr_lanes < link_info->num_lanes)
126
196
link_info->num_lanes = max_lttpr_lanes;
127
197
128
-
/* Limit link rate from LTTPR capabilities, if any */
129
-
max_lttpr_rate = drm_dp_lttpr_max_link_rate(panel->link->lttpr_common_caps);
130
-
if (max_lttpr_rate && max_lttpr_rate < link_info->rate)
131
-
link_info->rate = max_lttpr_rate;
132
-
133
198
drm_dbg_dp(panel->drm_dev, "version: %d.%d\n", major, minor);
134
199
drm_dbg_dp(panel->drm_dev, "link_rate=%d\n", link_info->rate);
200
+
drm_dbg_dp(panel->drm_dev, "link_rate_set=%d\n", link_info->rate_set);
201
+
drm_dbg_dp(panel->drm_dev, "use_rate_set=%d\n", link_info->use_rate_set);
135
202
drm_dbg_dp(panel->drm_dev, "lane_count=%d\n", link_info->num_lanes);
136
203
137
204
if (drm_dp_enhanced_frame_cap(dpcd))
+13
drivers/gpu/drm/msm/dsi/dsi_cfg.c
+13
drivers/gpu/drm/msm/dsi/dsi_cfg.c
···
205
205
},
206
206
};
207
207
208
+
static const struct msm_dsi_config kaanapali_dsi_cfg = {
209
+
.io_offset = DSI_6G_REG_SHIFT,
210
+
.regulator_data = sm8650_dsi_regulators,
211
+
.num_regulators = ARRAY_SIZE(sm8650_dsi_regulators),
212
+
.bus_clk_names = dsi_v2_4_clk_names,
213
+
.num_bus_clks = ARRAY_SIZE(dsi_v2_4_clk_names),
214
+
.io_start = {
215
+
{ 0x9ac0000, 0x9ac3000 },
216
+
},
217
+
};
218
+
208
219
static const struct regulator_bulk_data sc7280_dsi_regulators[] = {
209
220
{ .supply = "vdda", .init_load_uA = 8350 }, /* 1.2 V */
210
221
{ .supply = "refgen" },
···
343
332
&sm8650_dsi_cfg, &msm_dsi_6g_v2_host_ops},
344
333
{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_9_0,
345
334
&sm8650_dsi_cfg, &msm_dsi_6g_v2_9_host_ops},
335
+
{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_10_0,
336
+
&kaanapali_dsi_cfg, &msm_dsi_6g_v2_9_host_ops},
346
337
};
347
338
348
339
const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor)
+1
drivers/gpu/drm/msm/dsi/dsi_cfg.h
+1
drivers/gpu/drm/msm/dsi/dsi_cfg.h
+2
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+2
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+1
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+1
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
···
64
64
extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs;
65
65
extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs;
66
66
extern const struct msm_dsi_phy_cfg dsi_phy_3nm_8750_cfgs;
67
+
extern const struct msm_dsi_phy_cfg dsi_phy_3nm_kaanapali_cfgs;
67
68
68
69
struct msm_dsi_dphy_timing {
69
70
u32 clk_zero;
+1
-6
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
+1
-6
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
···
628
628
629
629
DBG("DSI%d PLL parent rate=%lu", pll_14nm->phy->id, req->rate);
630
630
631
-
req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate,
632
-
NULL,
633
-
postdiv->width,
634
-
postdiv->flags);
635
-
636
-
return 0;
631
+
return divider_determine_rate(hw, req, NULL, postdiv->width, postdiv->flags);
637
632
}
638
633
639
634
static int dsi_pll_14nm_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
+23
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+23
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
···
1504
1504
.num_dsi_phy = 2,
1505
1505
.quirks = DSI_PHY_7NM_QUIRK_V7_0,
1506
1506
};
1507
+
1508
+
const struct msm_dsi_phy_cfg dsi_phy_3nm_kaanapali_cfgs = {
1509
+
.has_phy_lane = true,
1510
+
.regulator_data = dsi_phy_7nm_98000uA_regulators,
1511
+
.num_regulators = ARRAY_SIZE(dsi_phy_7nm_98000uA_regulators),
1512
+
.ops = {
1513
+
.enable = dsi_7nm_phy_enable,
1514
+
.disable = dsi_7nm_phy_disable,
1515
+
.pll_init = dsi_pll_7nm_init,
1516
+
.save_pll_state = dsi_7nm_pll_save_state,
1517
+
.restore_pll_state = dsi_7nm_pll_restore_state,
1518
+
.set_continuous_clock = dsi_7nm_set_continuous_clock,
1519
+
},
1520
+
.min_pll_rate = 600000000UL,
1521
+
#ifdef CONFIG_64BIT
1522
+
.max_pll_rate = 5000000000UL,
1523
+
#else
1524
+
.max_pll_rate = ULONG_MAX,
1525
+
#endif
1526
+
.io_start = { 0x9ac1000, 0x9ac4000 },
1527
+
.num_dsi_phy = 2,
1528
+
.quirks = DSI_PHY_7NM_QUIRK_V7_0,
1529
+
};
+18
-6
drivers/gpu/drm/msm/msm_drv.c
+18
-6
drivers/gpu/drm/msm/msm_drv.c
···
588
588
589
589
switch (args->info) {
590
590
case MSM_INFO_GET_OFFSET:
591
-
args->value = msm_gem_mmap_offset(obj);
591
+
ret = drm_gem_create_mmap_offset(obj);
592
+
if (ret == 0)
593
+
args->value = drm_vma_node_offset_addr(&obj->vma_node);
592
594
break;
593
595
case MSM_INFO_GET_IOVA:
594
596
ret = msm_ioctl_gem_info_iova(dev, file, obj, &args->value);
···
838
836
.open = msm_open,
839
837
.postclose = msm_postclose,
840
838
.dumb_create = msm_gem_dumb_create,
841
-
.dumb_map_offset = msm_gem_dumb_map_offset,
839
+
.dumb_map_offset = drm_gem_dumb_map_offset,
842
840
.gem_prime_import = msm_gem_prime_import,
843
841
.gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
844
842
#ifdef CONFIG_DEBUG_FS
···
861
859
.open = msm_open,
862
860
.postclose = msm_postclose,
863
861
.dumb_create = msm_gem_dumb_create,
864
-
.dumb_map_offset = msm_gem_dumb_map_offset,
862
+
.dumb_map_offset = drm_gem_dumb_map_offset,
865
863
.gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
866
864
#ifdef CONFIG_DEBUG_FS
867
865
.debugfs_init = msm_debugfs_init,
···
962
960
MODULE_PARM_DESC(prefer_mdp5, "Select whether MDP5 or DPU driver should be preferred");
963
961
module_param(prefer_mdp5, bool, 0444);
964
962
963
+
/* list all platforms that have been migrated from mdp5 to dpu driver */
964
+
static const char *const msm_mdp5_dpu_migrated[] = {
965
+
/* there never was qcom,msm8998-mdp5 */
966
+
"qcom,sdm630-mdp5",
967
+
"qcom,sdm660-mdp5",
968
+
NULL
969
+
};
970
+
965
971
/* list all platforms supported by both mdp5 and dpu drivers */
966
972
static const char *const msm_mdp5_dpu_migration[] = {
967
973
"qcom,msm8917-mdp5",
968
974
"qcom,msm8937-mdp5",
969
975
"qcom,msm8953-mdp5",
970
976
"qcom,msm8996-mdp5",
971
-
"qcom,sdm630-mdp5",
972
-
"qcom,sdm660-mdp5",
973
977
NULL,
974
978
};
975
979
976
980
bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver)
977
981
{
978
-
/* If it is not an MDP5 device, do not try MDP5 driver */
982
+
/* If it is not an MDP5 device, use DPU */
979
983
if (!of_device_is_compatible(dev->of_node, "qcom,mdp5"))
984
+
return dpu_driver;
985
+
986
+
/* If it is no longer supported by MDP5, use DPU */
987
+
if (of_device_compatible_match(dev->of_node, msm_mdp5_dpu_migrated))
980
988
return dpu_driver;
981
989
982
990
/* If it is not in the migration list, use MDP5 */
-49
drivers/gpu/drm/msm/msm_gem.c
-49
drivers/gpu/drm/msm/msm_gem.c
···
375
375
return ret;
376
376
}
377
377
378
-
/** get mmap offset */
379
-
static uint64_t mmap_offset(struct drm_gem_object *obj)
380
-
{
381
-
struct drm_device *dev = obj->dev;
382
-
int ret;
383
-
384
-
msm_gem_assert_locked(obj);
385
-
386
-
/* Make it mmapable */
387
-
ret = drm_gem_create_mmap_offset(obj);
388
-
389
-
if (ret) {
390
-
DRM_DEV_ERROR(dev->dev, "could not allocate mmap offset\n");
391
-
return 0;
392
-
}
393
-
394
-
return drm_vma_node_offset_addr(&obj->vma_node);
395
-
}
396
-
397
-
uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj)
398
-
{
399
-
uint64_t offset;
400
-
401
-
msm_gem_lock(obj);
402
-
offset = mmap_offset(obj);
403
-
msm_gem_unlock(obj);
404
-
return offset;
405
-
}
406
378
407
379
static struct drm_gpuva *lookup_vma(struct drm_gem_object *obj,
408
380
struct drm_gpuvm *vm)
···
700
728
701
729
return msm_gem_new_handle(dev, file, args->size,
702
730
MSM_BO_SCANOUT | MSM_BO_WC, &args->handle, "dumb");
703
-
}
704
-
705
-
int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
706
-
uint32_t handle, uint64_t *offset)
707
-
{
708
-
struct drm_gem_object *obj;
709
-
int ret = 0;
710
-
711
-
/* GEM does all our handle to object mapping */
712
-
obj = drm_gem_object_lookup(file, handle);
713
-
if (obj == NULL) {
714
-
ret = -ENOENT;
715
-
goto fail;
716
-
}
717
-
718
-
*offset = msm_gem_mmap_offset(obj);
719
-
720
-
drm_gem_object_put(obj);
721
-
722
-
fail:
723
-
return ret;
724
731
}
725
732
726
733
static void *get_vaddr(struct drm_gem_object *obj, unsigned madv)
-3
drivers/gpu/drm/msm/msm_gem.h
-3
drivers/gpu/drm/msm/msm_gem.h
···
262
262
void msm_gem_vma_get(struct drm_gem_object *obj);
263
263
void msm_gem_vma_put(struct drm_gem_object *obj);
264
264
265
-
uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
266
265
int msm_gem_prot(struct drm_gem_object *obj);
267
266
int msm_gem_pin_vma_locked(struct drm_gem_object *obj, struct drm_gpuva *vma);
268
267
void msm_gem_unpin_locked(struct drm_gem_object *obj);
···
284
285
void msm_gem_unpin_pages_locked(struct drm_gem_object *obj);
285
286
int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
286
287
struct drm_mode_create_dumb *args);
287
-
int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
288
-
uint32_t handle, uint64_t *offset);
289
288
void *msm_gem_get_vaddr_locked(struct drm_gem_object *obj);
290
289
void *msm_gem_get_vaddr(struct drm_gem_object *obj);
291
290
void *msm_gem_get_vaddr_active(struct drm_gem_object *obj);
+1
-7
drivers/gpu/drm/msm/msm_gem_vma.c
+1
-7
drivers/gpu/drm/msm/msm_gem_vma.c
···
950
950
struct msm_gpu_submitqueue *queue, uint32_t nr_ops)
951
951
{
952
952
struct msm_vm_bind_job *job;
953
-
uint64_t sz;
954
953
int ret;
955
954
956
-
sz = struct_size(job, ops, nr_ops);
957
-
958
-
if (sz > SIZE_MAX)
959
-
return ERR_PTR(-ENOMEM);
960
-
961
-
job = kzalloc(sz, GFP_KERNEL | __GFP_NOWARN);
955
+
job = kzalloc(struct_size(job, ops, nr_ops), GFP_KERNEL | __GFP_NOWARN);
962
956
if (!job)
963
957
return ERR_PTR(-ENOMEM);
964
958
+10
-2
drivers/gpu/drm/msm/msm_mdss.c
+10
-2
drivers/gpu/drm/msm/msm_mdss.c
···
229
229
{
230
230
const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data;
231
231
u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) |
232
-
MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit);
232
+
MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13);
233
233
234
234
if (data->ubwc_bank_spread)
235
235
value |= MDSS_UBWC_STATIC_UBWC_BANK_SPREAD;
···
239
239
240
240
writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC);
241
241
242
-
writel_relaxed(4, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2);
242
+
if (data->ubwc_dec_version == UBWC_6_0)
243
+
writel_relaxed(5, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2);
244
+
else
245
+
writel_relaxed(4, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2);
246
+
243
247
writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE);
244
248
}
245
249
···
298
294
msm_mdss_setup_ubwc_dec_40(msm_mdss);
299
295
break;
300
296
case UBWC_5_0:
297
+
msm_mdss_setup_ubwc_dec_50(msm_mdss);
298
+
break;
299
+
case UBWC_6_0:
301
300
msm_mdss_setup_ubwc_dec_50(msm_mdss);
302
301
break;
303
302
default:
···
561
554
static const struct of_device_id mdss_dt_match[] = {
562
555
{ .compatible = "qcom,mdss", .data = &data_153k6 },
563
556
{ .compatible = "qcom,glymur-mdss", .data = &data_57k },
557
+
{ .compatible = "qcom,kaanapali-mdss", .data = &data_57k },
564
558
{ .compatible = "qcom,msm8998-mdss", .data = &data_76k8 },
565
559
{ .compatible = "qcom,qcm2290-mdss", .data = &data_76k8 },
566
560
{ .compatible = "qcom,qcs8300-mdss", .data = &data_74k },