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fpga: dfl-pci: rectify ReST formatting

Commit fa41d10589be ("fpga: dfl-pci: locate DFLs by PCIe vendor specific
capability") provides documentation to the FPGA Device Feature List (DFL)
Framework Overview, but introduced new documentation warnings:

./Documentation/fpga/dfl.rst:
505: WARNING: Title underline too short.
523: WARNING: Unexpected indentation.
523: WARNING: Blank line required after table.
524: WARNING: Block quote ends without a blank line; unexpected unindent.

Rectify ReST formatting in ./Documentation/fpga/dfl.rst.

Tested-by: Tom Rix <trix@redhat.com>
Acked-by: Moritz Fischer <mdf@kernel.org>
Acked-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com>
Link: https://lore.kernel.org/r/20210111112113.27242-1-lukas.bulwahn@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Lukas Bulwahn and committed by
Greg Kroah-Hartman 20612d24 4540b9fb

+2 -1
+2 -1
Documentation/fpga/dfl.rst
··· 502 502 could be a reference. 503 503 504 504 Location of DFLs on a PCI Device 505 - =========================== 505 + ================================ 506 506 The original method for finding a DFL on a PCI device assumed the start of the 507 507 first DFL to offset 0 of bar 0. If the first node of the DFL is an FME, 508 508 then further DFLs in the port(s) are specified in FME header registers. ··· 514 514 Offset/BIR vendor specific registers for each DFL. Bits 2:0 of Offset/BIR register 515 515 indicates the BAR, and bits 31:3 form the 8 byte aligned offset where bits 2:0 are 516 516 zero. 517 + :: 517 518 518 519 +----------------------------+ 519 520 |31 Number of DFLS 0|