Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 fixes from Thomas Gleixner:
- a bugfix which prevents a divide by 0 panic when the newly introduced
try_msr_calibrate_tsc() fails
- enablement of the Baytrail platform to utilize the newfangled msr
based calibration
* 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86: tsc: Add missing Baytrail frequency to the table
x86, tsc: Fallback to normal calibration if fast MSR calibration fails
+18
-21
+1
-1
arch/x86/include/asm/tsc.h
+1
-1
arch/x86/include/asm/tsc.h
+2
-5
arch/x86/kernel/tsc.c
+2
-5
arch/x86/kernel/tsc.c
···
653
653
654
654
/* Calibrate TSC using MSR for Intel Atom SoCs */
655
655
local_irq_save(flags);
656
-
i = try_msr_calibrate_tsc(&fast_calibrate);
656
+
fast_calibrate = try_msr_calibrate_tsc();
657
657
local_irq_restore(flags);
658
-
if (i >= 0) {
659
-
if (i == 0)
660
-
pr_warn("Fast TSC calibration using MSR failed\n");
658
+
if (fast_calibrate)
661
659
return fast_calibrate;
662
-
}
663
660
664
661
local_irq_save(flags);
665
662
fast_calibrate = quick_pit_calibrate();
+15
-15
arch/x86/kernel/tsc_msr.c
+15
-15
arch/x86/kernel/tsc_msr.c
···
53
53
/* TNG */
54
54
{ 6, 0x4a, 1, { 0, FREQ_100, FREQ_133, 0, 0, 0, 0, 0 } },
55
55
/* VLV2 */
56
-
{ 6, 0x37, 1, { 0, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } },
56
+
{ 6, 0x37, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } },
57
57
/* ANN */
58
58
{ 6, 0x5a, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_100, 0, 0, 0, 0 } },
59
59
};
···
77
77
78
78
/*
79
79
* Do MSR calibration only for known/supported CPUs.
80
-
* Return values:
81
-
* -1: CPU is unknown/unsupported for MSR based calibration
82
-
* 0: CPU is known/supported, but calibration failed
83
-
* 1: CPU is known/supported, and calibration succeeded
80
+
*
81
+
* Returns the calibration value or 0 if MSR calibration failed.
84
82
*/
85
-
int try_msr_calibrate_tsc(unsigned long *fast_calibrate)
83
+
unsigned long try_msr_calibrate_tsc(void)
86
84
{
87
-
int cpu_index;
88
85
u32 lo, hi, ratio, freq_id, freq;
86
+
unsigned long res;
87
+
int cpu_index;
89
88
90
89
cpu_index = match_cpu(boot_cpu_data.x86, boot_cpu_data.x86_model);
91
90
if (cpu_index < 0)
92
-
return -1;
93
-
94
-
*fast_calibrate = 0;
91
+
return 0;
95
92
96
93
if (freq_desc_tables[cpu_index].msr_plat) {
97
94
rdmsr(MSR_PLATFORM_INFO, lo, hi);
···
100
103
pr_info("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio);
101
104
102
105
if (!ratio)
103
-
return 0;
106
+
goto fail;
104
107
105
108
/* Get FSB FREQ ID */
106
109
rdmsr(MSR_FSB_FREQ, lo, hi);
···
109
112
pr_info("Resolved frequency ID: %u, frequency: %u KHz\n",
110
113
freq_id, freq);
111
114
if (!freq)
112
-
return 0;
115
+
goto fail;
113
116
114
117
/* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
115
-
*fast_calibrate = freq * ratio;
116
-
pr_info("TSC runs at %lu KHz\n", *fast_calibrate);
118
+
res = freq * ratio;
119
+
pr_info("TSC runs at %lu KHz\n", res);
117
120
118
121
#ifdef CONFIG_X86_LOCAL_APIC
119
122
lapic_timer_frequency = (freq * 1000) / HZ;
120
123
pr_info("lapic_timer_frequency = %d\n", lapic_timer_frequency);
121
124
#endif
125
+
return res;
122
126
123
-
return 1;
127
+
fail:
128
+
pr_warn("Fast TSC calibration using MSR failed\n");
129
+
return 0;
124
130
}