Merge branch 'pci/virtualization' · tjh.dev/kernel@2095b9d

+8

drivers/pci/pci-driver.c

··· 1650 1650 ret = acpi_dma_configure(dev, acpi_get_dma_attr(adev)); 1651 1651 } 1652 1652 1653 + /* 1654 + * Attempt to enable ACS regardless of capability because some Root 1655 + * Ports (e.g. those quirked with *_intel_pch_acs_*) do not have 1656 + * the standard ACS capability but still support ACS via those 1657 + * quirks. 1658 + */ 1659 + pci_enable_acs(to_pci_dev(dev)); 1660 + 1653 1661 pci_put_host_bridge_device(bridge); 1654 1662 1655 1663 /* @drv may not be valid when we're called from the IOMMU layer */

+48 -31

drivers/pci/pci.c

··· 13 13 #include <linux/delay.h> 14 14 #include <linux/dmi.h> 15 15 #include <linux/init.h> 16 + #include <linux/lockdep.h> 16 17 #include <linux/msi.h> 17 18 #include <linux/of.h> 18 19 #include <linux/pci.h> ··· 887 886 static const char *config_acs_param; 888 887 889 888 struct pci_acs { 890 - u16 cap; 891 889 u16 ctrl; 892 890 u16 fw_ctrl; 893 891 }; ··· 989 989 static void pci_std_enable_acs(struct pci_dev *dev, struct pci_acs *caps) 990 990 { 991 991 /* Source Validation */ 992 - caps->ctrl |= (caps->cap & PCI_ACS_SV); 992 + caps->ctrl |= (dev->acs_capabilities & PCI_ACS_SV); 993 993 994 994 /* P2P Request Redirect */ 995 - caps->ctrl |= (caps->cap & PCI_ACS_RR); 995 + caps->ctrl |= (dev->acs_capabilities & PCI_ACS_RR); 996 996 997 997 /* P2P Completion Redirect */ 998 - caps->ctrl |= (caps->cap & PCI_ACS_CR); 998 + caps->ctrl |= (dev->acs_capabilities & PCI_ACS_CR); 999 999 1000 1000 /* Upstream Forwarding */ 1001 - caps->ctrl |= (caps->cap & PCI_ACS_UF); 1001 + caps->ctrl |= (dev->acs_capabilities & PCI_ACS_UF); 1002 1002 1003 1003 /* Enable Translation Blocking for external devices and noats */ 1004 1004 if (pci_ats_disabled() || dev->external_facing || dev->untrusted) 1005 - caps->ctrl |= (caps->cap & PCI_ACS_TB); 1005 + caps->ctrl |= (dev->acs_capabilities & PCI_ACS_TB); 1006 1006 } 1007 1007 1008 1008 /** 1009 1009 * pci_enable_acs - enable ACS if hardware support it 1010 1010 * @dev: the PCI device 1011 1011 */ 1012 - static void pci_enable_acs(struct pci_dev *dev) 1012 + void pci_enable_acs(struct pci_dev *dev) 1013 1013 { 1014 1014 struct pci_acs caps; 1015 1015 bool enable_acs = false; ··· 1025 1025 if (!pos) 1026 1026 return; 1027 1027 1028 - pci_read_config_word(dev, pos + PCI_ACS_CAP, &caps.cap); 1029 1028 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &caps.ctrl); 1030 1029 caps.fw_ctrl = caps.ctrl; 1031 1030 ··· 3516 3517 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags) 3517 3518 { 3518 3519 int pos; 3519 - u16 cap, ctrl; 3520 + u16 ctrl; 3520 3521 3521 3522 pos = pdev->acs_cap; 3522 3523 if (!pos) ··· 3527 3528 * or only required if controllable. Features missing from the 3528 3529 * capability field can therefore be assumed as hard-wired enabled. 3529 3530 */ 3530 - pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap); 3531 - acs_flags &= (cap | PCI_ACS_EC); 3531 + acs_flags &= (pdev->acs_capabilities | PCI_ACS_EC); 3532 3532 3533 3533 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl); 3534 3534 return (ctrl & acs_flags) == acs_flags; ··· 3648 3650 */ 3649 3651 void pci_acs_init(struct pci_dev *dev) 3650 3652 { 3651 - dev->acs_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); 3653 + int pos; 3652 3654 3653 - /* 3654 - * Attempt to enable ACS regardless of capability because some Root 3655 - * Ports (e.g. those quirked with *_intel_pch_acs_*) do not have 3656 - * the standard ACS capability but still support ACS via those 3657 - * quirks. 3658 - */ 3659 - pci_enable_acs(dev); 3655 + dev->acs_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); 3656 + pos = dev->acs_cap; 3657 + if (!pos) 3658 + return; 3659 + 3660 + pci_read_config_word(dev, pos + PCI_ACS_CAP, &dev->acs_capabilities); 3661 + pci_disable_broken_acs_cap(dev); 3660 3662 } 3661 3663 3662 3664 /** ··· 4623 4625 * spec says 100 ms, but firmware can lower it and we allow drivers to 4624 4626 * increase it as well. 4625 4627 * 4626 - * Called with @pci_bus_sem locked for reading. 4628 + * Context: Called with @pci_bus_sem locked for reading. 4627 4629 */ 4628 4630 static int pci_bus_max_d3cold_delay(const struct pci_bus *bus) 4629 4631 { 4630 4632 const struct pci_dev *pdev; 4631 4633 int min_delay = 100; 4632 4634 int max_delay = 0; 4635 + 4636 + lockdep_assert_held(&pci_bus_sem); 4633 4637 4634 4638 list_for_each_entry(pdev, &bus->devices, bus_list) { 4635 4639 if (pdev->d3cold_delay < min_delay) ··· 4970 4970 * races with ->remove() by the device lock, which must be held by 4971 4971 * the caller. 4972 4972 */ 4973 + device_lock_assert(&dev->dev); 4973 4974 if (err_handler && err_handler->reset_prepare) 4974 4975 err_handler->reset_prepare(dev); 4975 4976 else if (dev->driver) ··· 5041 5040 * device including MSI, bus mastering, BARs, decoding IO and memory spaces, 5042 5041 * etc. 5043 5042 * 5044 - * Returns 0 if the device function was successfully reset or negative if the 5043 + * Context: The caller must hold the device lock. 5044 + * 5045 + * Return: 0 if the device function was successfully reset or negative if the 5045 5046 * device doesn't support resetting a single function. 5046 5047 */ 5047 5048 int __pci_reset_function_locked(struct pci_dev *dev) ··· 5052 5049 const struct pci_reset_fn_method *method; 5053 5050 5054 5051 might_sleep(); 5052 + device_lock_assert(&dev->dev); 5055 5053 5056 5054 /* 5057 5055 * A reset method returns -ENOTTY if it doesn't support this device and ··· 5175 5171 * over the reset. It also differs from pci_reset_function() in that it 5176 5172 * requires the PCI device lock to be held. 5177 5173 * 5178 - * Returns 0 if the device function was successfully reset or negative if the 5174 + * Context: The caller must hold the device lock. 5175 + * 5176 + * Return: 0 if the device function was successfully reset or negative if the 5179 5177 * device doesn't support resetting a single function. 5180 5178 */ 5181 5179 int pci_reset_function_locked(struct pci_dev *dev) 5182 5180 { 5183 5181 int rc; 5182 + 5183 + device_lock_assert(&dev->dev); 5184 5184 5185 5185 if (!pci_reset_supported(dev)) 5186 5186 return -ENOTTY; ··· 5301 5293 /* Do any devices on or below this slot prevent a bus reset? */ 5302 5294 static bool pci_slot_resettable(struct pci_slot *slot) 5303 5295 { 5304 - struct pci_dev *dev; 5296 + struct pci_dev *dev, *bridge = slot->bus->self; 5305 5297 5306 - if (slot->bus->self && 5307 - (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)) 5298 + if (bridge && (bridge->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)) 5308 5299 return false; 5309 5300 5310 5301 list_for_each_entry(dev, &slot->bus->devices, bus_list) { ··· 5320 5313 /* Lock devices from the top of the tree down */ 5321 5314 static void pci_slot_lock(struct pci_slot *slot) 5322 5315 { 5323 - struct pci_dev *dev; 5316 + struct pci_dev *dev, *bridge = slot->bus->self; 5317 + 5318 + if (bridge) 5319 + pci_dev_lock(bridge); 5324 5320 5325 5321 list_for_each_entry(dev, &slot->bus->devices, bus_list) { 5326 5322 if (!dev->slot || dev->slot != slot) ··· 5338 5328 /* Unlock devices from the bottom of the tree up */ 5339 5329 static void pci_slot_unlock(struct pci_slot *slot) 5340 5330 { 5341 - struct pci_dev *dev; 5331 + struct pci_dev *dev, *bridge = slot->bus->self; 5342 5332 5343 5333 list_for_each_entry(dev, &slot->bus->devices, bus_list) { 5344 5334 if (!dev->slot || dev->slot != slot) ··· 5348 5338 else 5349 5339 pci_dev_unlock(dev); 5350 5340 } 5341 + 5342 + if (bridge) 5343 + pci_dev_unlock(bridge); 5351 5344 } 5352 5345 5353 5346 /* Return 1 on successful lock, 0 on contention */ 5354 5347 static int pci_slot_trylock(struct pci_slot *slot) 5355 5348 { 5356 - struct pci_dev *dev; 5349 + struct pci_dev *dev, *bridge = slot->bus->self; 5350 + 5351 + if (bridge && !pci_dev_trylock(bridge)) 5352 + return 0; 5357 5353 5358 5354 list_for_each_entry(dev, &slot->bus->devices, bus_list) { 5359 5355 if (!dev->slot || dev->slot != slot) 5360 5356 continue; 5361 5357 if (dev->subordinate) { 5362 - if (!pci_bus_trylock(dev->subordinate)) { 5363 - pci_dev_unlock(dev); 5358 + if (!pci_bus_trylock(dev->subordinate)) 5364 5359 goto unlock; 5365 - } 5366 5360 } else if (!pci_dev_trylock(dev)) 5367 5361 goto unlock; 5368 5362 } ··· 5382 5368 else 5383 5369 pci_dev_unlock(dev); 5384 5370 } 5371 + 5372 + if (bridge) 5373 + pci_dev_unlock(bridge); 5385 5374 return 0; 5386 5375 } 5387 5376

+3 -1

drivers/pci/pci.h

··· 469 469 int rrs_timeout); 470 470 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 471 471 int rrs_timeout); 472 - int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int rrs_timeout); 473 472 474 473 int pci_setup_device(struct pci_dev *dev); 475 474 void __pci_size_stdbars(struct pci_dev *dev, int count, ··· 999 1000 } 1000 1001 1001 1002 void pci_acs_init(struct pci_dev *dev); 1003 + void pci_enable_acs(struct pci_dev *dev); 1002 1004 #ifdef CONFIG_PCI_QUIRKS 1003 1005 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 1004 1006 int pci_dev_specific_enable_acs(struct pci_dev *dev); 1005 1007 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev); 1008 + void pci_disable_broken_acs_cap(struct pci_dev *pdev); 1006 1009 int pcie_failed_link_retrain(struct pci_dev *dev); 1007 1010 #else 1008 1011 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, ··· 1020 1019 { 1021 1020 return -ENOTTY; 1022 1021 } 1022 + static inline void pci_disable_broken_acs_cap(struct pci_dev *dev) { } 1023 1023 static inline int pcie_failed_link_retrain(struct pci_dev *dev) 1024 1024 { 1025 1025 return -ENOTTY;

-12

drivers/pci/probe.c

··· 2549 2549 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, 2550 2550 int timeout) 2551 2551 { 2552 - #ifdef CONFIG_PCI_QUIRKS 2553 - struct pci_dev *bridge = bus->self; 2554 - 2555 - /* 2556 - * Certain IDT switches have an issue where they improperly trigger 2557 - * ACS Source Validation errors on completions for config reads. 2558 - */ 2559 - if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT && 2560 - bridge->device == 0x80b5) 2561 - return pci_idt_bus_quirk(bus, devfn, l, timeout); 2562 - #endif 2563 - 2564 2552 return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout); 2565 2553 } 2566 2554 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);

+36 -34

drivers/pci/quirks.c

··· 3759 3759 } 3760 3760 3761 3761 /* 3762 + * After asserting Secondary Bus Reset to downstream devices via a GB10 3763 + * Root Port, the link may not retrain correctly. 3764 + * https://lore.kernel.org/r/20251113084441.2124737-1-Johnny-CC.Chang@mediatek.com 3765 + */ 3766 + DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x22CE, quirk_no_bus_reset); 3767 + DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x22D0, quirk_no_bus_reset); 3768 + 3769 + /* 3762 3770 * Some NVIDIA GPU devices do not work with bus reset, SBR needs to be 3763 3771 * prevented for those affected devices. 3764 3772 */ ··· 3808 3800 * https://e2e.ti.com/support/processors/f/791/t/954382 3809 3801 */ 3810 3802 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset); 3803 + 3804 + /* 3805 + * Reports from users making use of PCI device assignment with ASM1164 3806 + * controllers indicate an issue with bus reset where the device fails to 3807 + * retrain. The issue appears more common in configurations with multiple 3808 + * controllers. The device does indicate PM reset support (NoSoftRst-), 3809 + * therefore this still leaves a viable reset method. 3810 + * https://forum.proxmox.com/threads/problems-with-pcie-passthrough-with-two-identical-devices.149003/ 3811 + */ 3812 + DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1164, quirk_no_bus_reset); 3811 3813 3812 3814 static void quirk_no_pm_reset(struct pci_dev *dev) 3813 3815 { ··· 5145 5127 { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs }, 5146 5128 /* QCOM SA8775P root port */ 5147 5129 { PCI_VENDOR_ID_QCOM, 0x0115, pci_quirk_qcom_rp_acs }, 5130 + /* QCOM Hamoa root port */ 5131 + { PCI_VENDOR_ID_QCOM, 0x0111, pci_quirk_qcom_rp_acs }, 5132 + /* QCOM Glymur root port */ 5133 + { PCI_VENDOR_ID_QCOM, 0x0120, pci_quirk_qcom_rp_acs }, 5148 5134 /* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */ 5149 5135 { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs }, 5150 5136 /* Intel PCH root ports */ ··· 5822 5800 5823 5801 /* 5824 5802 * Some IDT switches incorrectly flag an ACS Source Validation error on 5825 - * completions for config read requests even though PCIe r4.0, sec 5803 + * completions for config read requests even though PCIe r7.0, sec 5826 5804 * 6.12.1.1, says that completions are never affected by ACS Source 5827 5805 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36: 5828 5806 * ··· 5835 5813 * 5836 5814 * The workaround suggested by IDT is to issue a config write to the 5837 5815 * downstream device before issuing the first config read. This allows the 5838 - * downstream device to capture its bus and device numbers (see PCIe r4.0, 5839 - * sec 2.2.9), thus avoiding the ACS error on the completion. 5816 + * downstream device to capture its bus and device numbers (see PCIe r7.0, 5817 + * sec 2.2.9.1), thus avoiding the ACS error on the completion. 5840 5818 * 5841 5819 * However, we don't know when the device is ready to accept the config 5842 - * write, so we do config reads until we receive a non-Config Request Retry 5843 - * Status, then do the config write. 5844 - * 5845 - * To avoid hitting the erratum when doing the config reads, we disable ACS 5846 - * SV around this process. 5820 + * write, and the issue affects resets of the switch as well as enumeration, 5821 + * so disable use of ACS SV for these devices altogether. 5847 5822 */ 5848 - int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout) 5823 + void pci_disable_broken_acs_cap(struct pci_dev *pdev) 5849 5824 { 5850 - int pos; 5851 - u16 ctrl = 0; 5852 - bool found; 5853 - struct pci_dev *bridge = bus->self; 5854 - 5855 - pos = bridge->acs_cap; 5856 - 5857 - /* Disable ACS SV before initial config reads */ 5858 - if (pos) { 5859 - pci_read_config_word(bridge, pos + PCI_ACS_CTRL, &ctrl); 5860 - if (ctrl & PCI_ACS_SV) 5861 - pci_write_config_word(bridge, pos + PCI_ACS_CTRL, 5862 - ctrl & ~PCI_ACS_SV); 5825 + if (pdev->vendor == PCI_VENDOR_ID_IDT && 5826 + (pdev->device == 0x80b5 || pdev->device == 0x8090)) { 5827 + pci_info(pdev, "Disabling broken ACS SV; downstream device isolation reduced\n"); 5828 + pdev->acs_capabilities &= ~PCI_ACS_SV; 5863 5829 } 5864 - 5865 - found = pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout); 5866 - 5867 - /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */ 5868 - if (found) 5869 - pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0); 5870 - 5871 - /* Re-enable ACS_SV if it was previously enabled */ 5872 - if (ctrl & PCI_ACS_SV) 5873 - pci_write_config_word(bridge, pos + PCI_ACS_CTRL, ctrl); 5874 - 5875 - return found; 5876 5830 } 5877 5831 5878 5832 /* ··· 6206 6208 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2303, 6207 6209 pci_fixup_pericom_acs_store_forward); 6208 6210 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2303, 6211 + pci_fixup_pericom_acs_store_forward); 6212 + DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0xb404, 6213 + pci_fixup_pericom_acs_store_forward); 6214 + DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0xb404, 6209 6215 pci_fixup_pericom_acs_store_forward); 6210 6216 6211 6217 static void nvidia_ion_ahci_fixup(struct pci_dev *pdev)

+1

include/linux/pci.h

··· 564 564 struct pci_tsm *tsm; /* TSM operation state */ 565 565 #endif 566 566 u16 acs_cap; /* ACS Capability offset */ 567 + u16 acs_capabilities; /* ACS Capabilities */ 567 568 u8 supported_speeds; /* Supported Link Speeds Vector */ 568 569 phys_addr_t rom; /* Physical address if not from BAR */ 569 570 size_t romlen; /* Length if not from BAR */

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