tjh.dev / kernel
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drm/amdgpu: Fix core reset sequence for JPEG4_0_3

For cores 1 through 7 repair the core reset sequence by
adjusting offsets to access the expected registers.

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Sathishkumar S and committed by
Alex Deucher 20c34e5c a91d91b6

+5 -9
+5 -9
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
··· 1104 1104 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 1105 1105 regUVD_JMI0_UVD_JMI_CLIENT_STALL, 1106 1106 reg_offset, 0x1F); 1107 - SOC15_WAIT_ON_RREG(JPEG, jpeg_inst, 1108 - regUVD_JMI0_UVD_JMI_CLIENT_CLEAN_STATUS, 1109 - 0x1F, 0x1F); 1107 + SOC15_WAIT_ON_RREG_OFFSET(JPEG, jpeg_inst, 1108 + regUVD_JMI0_UVD_JMI_CLIENT_CLEAN_STATUS, 1109 + reg_offset, 0x1F, 0x1F); 1110 1110 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 1111 1111 regUVD_JMI0_JPEG_LMI_DROP, 1112 1112 reg_offset, 0x1F); 1113 - WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 1114 - regJPEG_CORE_RST_CTRL, 1115 - reg_offset, 1 << ring->pipe); 1113 + WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CORE_RST_CTRL, 1 << ring->pipe); 1116 1114 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 1117 1115 regUVD_JMI0_UVD_JMI_CLIENT_STALL, 1118 1116 reg_offset, 0x00); 1119 1117 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 1120 1118 regUVD_JMI0_JPEG_LMI_DROP, 1121 1119 reg_offset, 0x00); 1122 - WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 1123 - regJPEG_CORE_RST_CTRL, 1124 - reg_offset, 0x00); 1120 + WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CORE_RST_CTRL, 0x00); 1125 1121 } 1126 1122 1127 1123 static int jpeg_v4_0_3_ring_reset(struct amdgpu_ring *ring, unsigned int vmid)