Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2018-11-11' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie:
"drm: i915, amdgpu, sun4i, exynos and etnaviv fixes:
- amdgpu has some display fixes, KFD ioctl fixes and a Vega20 bios
interaction fix.
- sun4i has some NULL checks added
- i915 has a 32-bit system fix, LPE audio oops, and HDMI2.0 clock
fixes.
- Exynos has a 3 regression fixes (one frame counter, fbdev missing,
dsi->panel check)
- Etnaviv has a single fencing fix for GPU recovery"
* tag 'drm-fixes-2018-11-11' of git://anongit.freedesktop.org/drm/drm: (39 commits)
drm/amd/amdgpu/dm: Fix dm_dp_create_fake_mst_encoder()
drm/amd/display: Drop reusing drm connector for MST
drm/amd/display: Cleanup MST non-atomic code workaround
drm/amd/powerplay: always use fast UCLK switching when UCLK DPM enabled
drm/amd/powerplay: set a default fclk/gfxclk ratio
drm/amdgpu/display/dce11: only enable FBC when selected
drm/amdgpu/display/dm: handle FBC dc feature parameter
drm/amdgpu/display/dc: add FBC to dc_config
drm/amdgpu: add DC feature mask module parameter
drm/amdgpu/display: check if fbc is available in set_static_screen_control (v2)
drm/amdgpu/vega20: add CLK base offset
drm/amd/display: Stop leaking planes
drm/amd/display: Fix misleading buffer information
Revert "drm/amd/display: set backlight level limit to 1"
drm/amd: Update atom_smu_info_v3_3 structure
drm/i915: Fix ilk+ watermarks when disabling pipes
drm/sun4i: tcon: prevent tcon->panel dereference if NULL
drm/sun4i: tcon: fix check of tcon->panel null pointer
drm/i915: Don't oops during modeset shutdown after lpe audio deinit
drm/i915: Mark pin flags as u64
...
+252
-291
+1
drivers/gpu/drm/amd/amdgpu/amdgpu.h
+1
drivers/gpu/drm/amd/amdgpu/amdgpu.h
+11
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+11
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
···
127
127
int amdgpu_gpu_recovery = -1; /* auto */
128
128
int amdgpu_emu_mode = 0;
129
129
uint amdgpu_smu_memory_pool_size = 0;
130
+
/* FBC (bit 0) disabled by default*/
131
+
uint amdgpu_dc_feature_mask = 0;
132
+
130
133
struct amdgpu_mgpu_info mgpu_info = {
131
134
.mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
132
135
};
···
633
630
module_param(halt_if_hws_hang, int, 0644);
634
631
MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)");
635
632
#endif
633
+
634
+
/**
635
+
* DOC: dcfeaturemask (uint)
636
+
* Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
637
+
* The default is the current set of stable display features.
638
+
*/
639
+
MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))");
640
+
module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444);
636
641
637
642
static const struct pci_device_id pciidlist[] = {
638
643
#ifdef CONFIG_DRM_AMDGPU_SI
+1
drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
+1
drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
···
49
49
adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
50
50
adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
51
51
adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
52
+
adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));
52
53
}
53
54
return 0;
54
55
}
+8
-19
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+8
-19
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
···
429
429
adev->asic_type < CHIP_RAVEN)
430
430
init_data.flags.gpu_vm_support = true;
431
431
432
+
if (amdgpu_dc_feature_mask & DC_FBC_MASK)
433
+
init_data.flags.fbc_support = true;
434
+
432
435
/* Display Core create. */
433
436
adev->dm.dc = dc_create(&init_data);
434
437
···
1527
1524
{
1528
1525
struct amdgpu_display_manager *dm = bl_get_data(bd);
1529
1526
1530
-
/*
1531
-
* PWM interperts 0 as 100% rather than 0% because of HW
1532
-
* limitation for level 0.So limiting minimum brightness level
1533
-
* to 1.
1534
-
*/
1535
-
if (bd->props.brightness < 1)
1536
-
return 1;
1537
1527
if (dc_link_set_backlight_level(dm->backlight_link,
1538
1528
bd->props.brightness, 0, 0))
1539
1529
return 0;
···
2703
2707
drm_connector = &aconnector->base;
2704
2708
2705
2709
if (!aconnector->dc_sink) {
2706
-
/*
2707
-
* Create dc_sink when necessary to MST
2708
-
* Don't apply fake_sink to MST
2709
-
*/
2710
-
if (aconnector->mst_port) {
2711
-
dm_dp_mst_dc_sink_create(drm_connector);
2712
-
return stream;
2710
+
if (!aconnector->mst_port) {
2711
+
sink = create_fake_sink(aconnector);
2712
+
if (!sink)
2713
+
return stream;
2713
2714
}
2714
-
2715
-
sink = create_fake_sink(aconnector);
2716
-
if (!sink)
2717
-
return stream;
2718
2715
} else {
2719
2716
sink = aconnector->dc_sink;
2720
2717
}
···
3297
3308
static const struct drm_plane_funcs dm_plane_funcs = {
3298
3309
.update_plane = drm_atomic_helper_update_plane,
3299
3310
.disable_plane = drm_atomic_helper_disable_plane,
3300
-
.destroy = drm_plane_cleanup,
3311
+
.destroy = drm_primary_helper_destroy,
3301
3312
.reset = dm_drm_plane_reset,
3302
3313
.atomic_duplicate_state = dm_drm_plane_duplicate_state,
3303
3314
.atomic_destroy_state = dm_drm_plane_destroy_state,
-2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
-2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+7
-72
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+7
-72
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
···
205
205
.atomic_get_property = amdgpu_dm_connector_atomic_get_property
206
206
};
207
207
208
-
void dm_dp_mst_dc_sink_create(struct drm_connector *connector)
209
-
{
210
-
struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
211
-
struct dc_sink *dc_sink;
212
-
struct dc_sink_init_data init_params = {
213
-
.link = aconnector->dc_link,
214
-
.sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
215
-
216
-
/* FIXME none of this is safe. we shouldn't touch aconnector here in
217
-
* atomic_check
218
-
*/
219
-
220
-
/*
221
-
* TODO: Need to further figure out why ddc.algo is NULL while MST port exists
222
-
*/
223
-
if (!aconnector->port || !aconnector->port->aux.ddc.algo)
224
-
return;
225
-
226
-
ASSERT(aconnector->edid);
227
-
228
-
dc_sink = dc_link_add_remote_sink(
229
-
aconnector->dc_link,
230
-
(uint8_t *)aconnector->edid,
231
-
(aconnector->edid->extensions + 1) * EDID_LENGTH,
232
-
&init_params);
233
-
234
-
dc_sink->priv = aconnector;
235
-
aconnector->dc_sink = dc_sink;
236
-
237
-
if (aconnector->dc_sink)
238
-
amdgpu_dm_update_freesync_caps(
239
-
connector, aconnector->edid);
240
-
}
241
-
242
208
static int dm_dp_mst_get_modes(struct drm_connector *connector)
243
209
{
244
210
struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
···
285
319
struct amdgpu_device *adev = dev->dev_private;
286
320
struct amdgpu_encoder *amdgpu_encoder;
287
321
struct drm_encoder *encoder;
288
-
const struct drm_connector_helper_funcs *connector_funcs =
289
-
connector->base.helper_private;
290
-
struct drm_encoder *enc_master =
291
-
connector_funcs->best_encoder(&connector->base);
292
322
293
-
DRM_DEBUG_KMS("enc master is %p\n", enc_master);
294
323
amdgpu_encoder = kzalloc(sizeof(*amdgpu_encoder), GFP_KERNEL);
295
324
if (!amdgpu_encoder)
296
325
return NULL;
···
315
354
struct amdgpu_device *adev = dev->dev_private;
316
355
struct amdgpu_dm_connector *aconnector;
317
356
struct drm_connector *connector;
318
-
struct drm_connector_list_iter conn_iter;
319
-
320
-
drm_connector_list_iter_begin(dev, &conn_iter);
321
-
drm_for_each_connector_iter(connector, &conn_iter) {
322
-
aconnector = to_amdgpu_dm_connector(connector);
323
-
if (aconnector->mst_port == master
324
-
&& !aconnector->port) {
325
-
DRM_INFO("DM_MST: reusing connector: %p [id: %d] [master: %p]\n",
326
-
aconnector, connector->base.id, aconnector->mst_port);
327
-
328
-
aconnector->port = port;
329
-
drm_connector_set_path_property(connector, pathprop);
330
-
331
-
drm_connector_list_iter_end(&conn_iter);
332
-
aconnector->mst_connected = true;
333
-
return &aconnector->base;
334
-
}
335
-
}
336
-
drm_connector_list_iter_end(&conn_iter);
337
357
338
358
aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
339
359
if (!aconnector)
···
363
421
*/
364
422
amdgpu_dm_connector_funcs_reset(connector);
365
423
366
-
aconnector->mst_connected = true;
367
-
368
424
DRM_INFO("DM_MST: added connector: %p [id: %d] [master: %p]\n",
369
425
aconnector, connector->base.id, aconnector->mst_port);
370
426
···
374
434
static void dm_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
375
435
struct drm_connector *connector)
376
436
{
437
+
struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
438
+
struct drm_device *dev = master->base.dev;
439
+
struct amdgpu_device *adev = dev->dev_private;
377
440
struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
378
441
379
442
DRM_INFO("DM_MST: Disabling connector: %p [id: %d] [master: %p]\n",
···
390
447
aconnector->dc_sink = NULL;
391
448
}
392
449
393
-
aconnector->mst_connected = false;
450
+
drm_connector_unregister(connector);
451
+
if (adev->mode_info.rfbdev)
452
+
drm_fb_helper_remove_one_connector(&adev->mode_info.rfbdev->helper, connector);
453
+
drm_connector_put(connector);
394
454
}
395
455
396
456
static void dm_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr)
···
404
458
drm_kms_helper_hotplug_event(dev);
405
459
}
406
460
407
-
static void dm_dp_mst_link_status_reset(struct drm_connector *connector)
408
-
{
409
-
mutex_lock(&connector->dev->mode_config.mutex);
410
-
drm_connector_set_link_status_property(connector, DRM_MODE_LINK_STATUS_BAD);
411
-
mutex_unlock(&connector->dev->mode_config.mutex);
412
-
}
413
-
414
461
static void dm_dp_mst_register_connector(struct drm_connector *connector)
415
462
{
416
463
struct drm_device *dev = connector->dev;
417
464
struct amdgpu_device *adev = dev->dev_private;
418
-
struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
419
465
420
466
if (adev->mode_info.rfbdev)
421
467
drm_fb_helper_add_one_connector(&adev->mode_info.rfbdev->helper, connector);
···
415
477
DRM_ERROR("adev->mode_info.rfbdev is NULL\n");
416
478
417
479
drm_connector_register(connector);
418
-
419
-
if (aconnector->mst_connected)
420
-
dm_dp_mst_link_status_reset(connector);
421
480
}
422
481
423
482
static const struct drm_dp_mst_topology_cbs dm_mst_cbs = {
-1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
-1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
+2
-2
drivers/gpu/drm/amd/display/dc/core/dc_link.c
+2
-2
drivers/gpu/drm/amd/display/dc/core/dc_link.c
···
1722
1722
i2c_success = i2c_write(pipe_ctx, slave_address,
1723
1723
buffer, sizeof(buffer));
1724
1724
RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1725
-
offset = 0x%d, reg_val = 0x%d, i2c_success = %d\n",
1725
+
offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1726
1726
slave_address, buffer[0], buffer[1], i2c_success?1:0);
1727
1727
if (!i2c_success)
1728
1728
/* Write failure */
···
1734
1734
i2c_success = i2c_write(pipe_ctx, slave_address,
1735
1735
buffer, sizeof(buffer));
1736
1736
RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1737
-
offset = 0x%d, reg_val = 0x%d, i2c_success = %d\n",
1737
+
offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1738
1738
slave_address, buffer[0], buffer[1], i2c_success?1:0);
1739
1739
if (!i2c_success)
1740
1740
/* Write failure */
+1
drivers/gpu/drm/amd/display/dc/dc.h
+1
drivers/gpu/drm/amd/display/dc/dc.h
+6
-1
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+6
-1
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
···
1736
1736
if (events->force_trigger)
1737
1737
value |= 0x1;
1738
1738
1739
-
value |= 0x84;
1739
+
if (num_pipes) {
1740
+
struct dc *dc = pipe_ctx[0]->stream->ctx->dc;
1741
+
1742
+
if (dc->fbc_compressor)
1743
+
value |= 0x84;
1744
+
}
1740
1745
1741
1746
for (i = 0; i < num_pipes; i++)
1742
1747
pipe_ctx[i]->stream_res.tg->funcs->
+2
-1
drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+2
-1
drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
···
1362
1362
pool->base.sw_i2cs[i] = NULL;
1363
1363
}
1364
1364
1365
-
dc->fbc_compressor = dce110_compressor_create(ctx);
1365
+
if (dc->config.fbc_support)
1366
+
dc->fbc_compressor = dce110_compressor_create(ctx);
1366
1367
1367
1368
if (!underlay_create(ctx, &pool->base))
1368
1369
goto res_create_fail;
+5
-2
drivers/gpu/drm/amd/include/atomfirmware.h
+5
-2
drivers/gpu/drm/amd/include/atomfirmware.h
···
1325
1325
struct atom_common_table_header table_header;
1326
1326
uint8_t smuip_min_ver;
1327
1327
uint8_t smuip_max_ver;
1328
-
uint8_t smu_rsd1;
1328
+
uint8_t waflclk_ss_mode;
1329
1329
uint8_t gpuclk_ss_mode;
1330
1330
uint16_t sclk_ss_percentage;
1331
1331
uint16_t sclk_ss_rate_10hz;
···
1355
1355
uint32_t syspll3_1_vco_freq_10khz;
1356
1356
uint32_t bootup_fclk_10khz;
1357
1357
uint32_t bootup_waflclk_10khz;
1358
-
uint32_t reserved[3];
1358
+
uint32_t smu_info_caps;
1359
+
uint16_t waflclk_ss_percentage; // in unit of 0.001%
1360
+
uint16_t smuinitoffset;
1361
+
uint32_t reserved;
1359
1362
};
1360
1363
1361
1364
/*
+33
-20
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+33
-20
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
···
120
120
data->registry_data.disable_auto_wattman = 1;
121
121
data->registry_data.auto_wattman_debug = 0;
122
122
data->registry_data.auto_wattman_sample_period = 100;
123
+
data->registry_data.fclk_gfxclk_ratio = 0x3F6CCCCD;
123
124
data->registry_data.auto_wattman_threshold = 50;
124
125
data->registry_data.gfxoff_controlled_by_driver = 1;
125
126
data->gfxoff_allowed = false;
···
830
829
return 0;
831
830
}
832
831
832
+
static int vega20_notify_smc_display_change(struct pp_hwmgr *hwmgr)
833
+
{
834
+
struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
835
+
836
+
if (data->smu_features[GNLD_DPM_UCLK].enabled)
837
+
return smum_send_msg_to_smc_with_parameter(hwmgr,
838
+
PPSMC_MSG_SetUclkFastSwitch,
839
+
1);
840
+
841
+
return 0;
842
+
}
843
+
844
+
static int vega20_send_clock_ratio(struct pp_hwmgr *hwmgr)
845
+
{
846
+
struct vega20_hwmgr *data =
847
+
(struct vega20_hwmgr *)(hwmgr->backend);
848
+
849
+
return smum_send_msg_to_smc_with_parameter(hwmgr,
850
+
PPSMC_MSG_SetFclkGfxClkRatio,
851
+
data->registry_data.fclk_gfxclk_ratio);
852
+
}
853
+
833
854
static int vega20_disable_all_smu_features(struct pp_hwmgr *hwmgr)
834
855
{
835
856
struct vega20_hwmgr *data =
···
1555
1532
"[EnableDPMTasks] Failed to enable all smu features!",
1556
1533
return result);
1557
1534
1535
+
result = vega20_notify_smc_display_change(hwmgr);
1536
+
PP_ASSERT_WITH_CODE(!result,
1537
+
"[EnableDPMTasks] Failed to notify smc display change!",
1538
+
return result);
1539
+
1540
+
result = vega20_send_clock_ratio(hwmgr);
1541
+
PP_ASSERT_WITH_CODE(!result,
1542
+
"[EnableDPMTasks] Failed to send clock ratio!",
1543
+
return result);
1544
+
1558
1545
/* Initialize UVD/VCE powergating state */
1559
1546
vega20_init_powergate_state(hwmgr);
1560
1547
···
2005
1972
return ret;
2006
1973
}
2007
1974
2008
-
static int vega20_notify_smc_display_change(struct pp_hwmgr *hwmgr,
2009
-
bool has_disp)
2010
-
{
2011
-
struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2012
-
2013
-
if (data->smu_features[GNLD_DPM_UCLK].enabled)
2014
-
return smum_send_msg_to_smc_with_parameter(hwmgr,
2015
-
PPSMC_MSG_SetUclkFastSwitch,
2016
-
has_disp ? 1 : 0);
2017
-
2018
-
return 0;
2019
-
}
2020
-
2021
1975
int vega20_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
2022
1976
struct pp_display_clock_request *clock_req)
2023
1977
{
···
2063
2043
struct PP_Clocks min_clocks = {0};
2064
2044
struct pp_display_clock_request clock_req;
2065
2045
int ret = 0;
2066
-
2067
-
if ((hwmgr->display_config->num_display > 1) &&
2068
-
!hwmgr->display_config->multi_monitor_in_sync &&
2069
-
!hwmgr->display_config->nb_pstate_switch_disable)
2070
-
vega20_notify_smc_display_change(hwmgr, false);
2071
-
else
2072
-
vega20_notify_smc_display_change(hwmgr, true);
2073
2046
2074
2047
min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
2075
2048
min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
+1
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h
+1
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h
+2
-1
drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
+2
-1
drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
···
105
105
#define PPSMC_MSG_SetSystemVirtualDramAddrHigh 0x4B
106
106
#define PPSMC_MSG_SetSystemVirtualDramAddrLow 0x4C
107
107
#define PPSMC_MSG_WaflTest 0x4D
108
-
// Unused ID 0x4E to 0x50
108
+
#define PPSMC_MSG_SetFclkGfxClkRatio 0x4E
109
+
// Unused ID 0x4F to 0x50
109
110
#define PPSMC_MSG_AllowGfxOff 0x51
110
111
#define PPSMC_MSG_DisallowGfxOff 0x52
111
112
#define PPSMC_MSG_GetPptLimit 0x53
-9
drivers/gpu/drm/exynos/exynos5433_drm_decon.c
-9
drivers/gpu/drm/exynos/exynos5433_drm_decon.c
···
164
164
return frm;
165
165
}
166
166
167
-
static u32 decon_get_vblank_counter(struct exynos_drm_crtc *crtc)
168
-
{
169
-
struct decon_context *ctx = crtc->ctx;
170
-
171
-
return decon_get_frame_count(ctx, false);
172
-
}
173
-
174
167
static void decon_setup_trigger(struct decon_context *ctx)
175
168
{
176
169
if (!ctx->crtc->i80_mode && !(ctx->out_type & I80_HW_TRG))
···
529
536
.disable = decon_disable,
530
537
.enable_vblank = decon_enable_vblank,
531
538
.disable_vblank = decon_disable_vblank,
532
-
.get_vblank_counter = decon_get_vblank_counter,
533
539
.atomic_begin = decon_atomic_begin,
534
540
.update_plane = decon_update_plane,
535
541
.disable_plane = decon_disable_plane,
···
546
554
int ret;
547
555
548
556
ctx->drm_dev = drm_dev;
549
-
drm_dev->max_vblank_count = 0xffffffff;
550
557
551
558
for (win = ctx->first_win; win < WINDOWS_NR; win++) {
552
559
ctx->configs[win].pixel_formats = decon_formats;
-11
drivers/gpu/drm/exynos/exynos_drm_crtc.c
-11
drivers/gpu/drm/exynos/exynos_drm_crtc.c
···
162
162
exynos_crtc->ops->disable_vblank(exynos_crtc);
163
163
}
164
164
165
-
static u32 exynos_drm_crtc_get_vblank_counter(struct drm_crtc *crtc)
166
-
{
167
-
struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc);
168
-
169
-
if (exynos_crtc->ops->get_vblank_counter)
170
-
return exynos_crtc->ops->get_vblank_counter(exynos_crtc);
171
-
172
-
return 0;
173
-
}
174
-
175
165
static const struct drm_crtc_funcs exynos_crtc_funcs = {
176
166
.set_config = drm_atomic_helper_set_config,
177
167
.page_flip = drm_atomic_helper_page_flip,
···
171
181
.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
172
182
.enable_vblank = exynos_drm_crtc_enable_vblank,
173
183
.disable_vblank = exynos_drm_crtc_disable_vblank,
174
-
.get_vblank_counter = exynos_drm_crtc_get_vblank_counter,
175
184
};
176
185
177
186
struct exynos_drm_crtc *exynos_drm_crtc_create(struct drm_device *drm_dev,
-1
drivers/gpu/drm/exynos/exynos_drm_drv.h
-1
drivers/gpu/drm/exynos/exynos_drm_drv.h
···
135
135
void (*disable)(struct exynos_drm_crtc *crtc);
136
136
int (*enable_vblank)(struct exynos_drm_crtc *crtc);
137
137
void (*disable_vblank)(struct exynos_drm_crtc *crtc);
138
-
u32 (*get_vblank_counter)(struct exynos_drm_crtc *crtc);
139
138
enum drm_mode_status (*mode_valid)(struct exynos_drm_crtc *crtc,
140
139
const struct drm_display_mode *mode);
141
140
bool (*mode_fixup)(struct exynos_drm_crtc *crtc,
+11
-3
drivers/gpu/drm/exynos/exynos_drm_dsi.c
+11
-3
drivers/gpu/drm/exynos/exynos_drm_dsi.c
···
14
14
15
15
#include <drm/drmP.h>
16
16
#include <drm/drm_crtc_helper.h>
17
+
#include <drm/drm_fb_helper.h>
17
18
#include <drm/drm_mipi_dsi.h>
18
19
#include <drm/drm_panel.h>
19
20
#include <drm/drm_atomic_helper.h>
···
1475
1474
{
1476
1475
struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1477
1476
struct drm_connector *connector = &dsi->connector;
1477
+
struct drm_device *drm = encoder->dev;
1478
1478
int ret;
1479
1479
1480
1480
connector->polled = DRM_CONNECTOR_POLL_HPD;
1481
1481
1482
-
ret = drm_connector_init(encoder->dev, connector,
1483
-
&exynos_dsi_connector_funcs,
1482
+
ret = drm_connector_init(drm, connector, &exynos_dsi_connector_funcs,
1484
1483
DRM_MODE_CONNECTOR_DSI);
1485
1484
if (ret) {
1486
1485
DRM_ERROR("Failed to initialize connector with drm\n");
···
1490
1489
connector->status = connector_status_disconnected;
1491
1490
drm_connector_helper_add(connector, &exynos_dsi_connector_helper_funcs);
1492
1491
drm_connector_attach_encoder(connector, encoder);
1492
+
if (!drm->registered)
1493
+
return 0;
1493
1494
1495
+
connector->funcs->reset(connector);
1496
+
drm_fb_helper_add_one_connector(drm->fb_helper, connector);
1497
+
drm_connector_register(connector);
1494
1498
return 0;
1495
1499
}
1496
1500
···
1533
1527
}
1534
1528
1535
1529
dsi->panel = of_drm_find_panel(device->dev.of_node);
1536
-
if (dsi->panel) {
1530
+
if (IS_ERR(dsi->panel)) {
1531
+
dsi->panel = NULL;
1532
+
} else {
1537
1533
drm_panel_attach(dsi->panel, &dsi->connector);
1538
1534
dsi->connector.status = connector_status_connected;
1539
1535
}
+1
-1
drivers/gpu/drm/exynos/exynos_drm_fbdev.c
+1
-1
drivers/gpu/drm/exynos/exynos_drm_fbdev.c
+54
-53
drivers/gpu/drm/i915/gvt/gtt.c
+54
-53
drivers/gpu/drm/i915/gvt/gtt.c
···
1905
1905
vgpu_free_mm(mm);
1906
1906
return ERR_PTR(-ENOMEM);
1907
1907
}
1908
-
mm->ggtt_mm.last_partial_off = -1UL;
1909
1908
1910
1909
return mm;
1911
1910
}
···
1929
1930
invalidate_ppgtt_mm(mm);
1930
1931
} else {
1931
1932
vfree(mm->ggtt_mm.virtual_ggtt);
1932
-
mm->ggtt_mm.last_partial_off = -1UL;
1933
1933
}
1934
1934
1935
1935
vgpu_free_mm(mm);
···
2166
2168
struct intel_gvt_gtt_entry e, m;
2167
2169
dma_addr_t dma_addr;
2168
2170
int ret;
2171
+
struct intel_gvt_partial_pte *partial_pte, *pos, *n;
2172
+
bool partial_update = false;
2169
2173
2170
2174
if (bytes != 4 && bytes != 8)
2171
2175
return -EINVAL;
···
2178
2178
if (!vgpu_gmadr_is_valid(vgpu, gma))
2179
2179
return 0;
2180
2180
2181
-
ggtt_get_guest_entry(ggtt_mm, &e, g_gtt_index);
2182
-
2181
+
e.type = GTT_TYPE_GGTT_PTE;
2183
2182
memcpy((void *)&e.val64 + (off & (info->gtt_entry_size - 1)), p_data,
2184
2183
bytes);
2185
2184
2186
2185
/* If ggtt entry size is 8 bytes, and it's split into two 4 bytes
2187
-
* write, we assume the two 4 bytes writes are consecutive.
2188
-
* Otherwise, we abort and report error
2186
+
* write, save the first 4 bytes in a list and update virtual
2187
+
* PTE. Only update shadow PTE when the second 4 bytes comes.
2189
2188
*/
2190
2189
if (bytes < info->gtt_entry_size) {
2191
-
if (ggtt_mm->ggtt_mm.last_partial_off == -1UL) {
2192
-
/* the first partial part*/
2193
-
ggtt_mm->ggtt_mm.last_partial_off = off;
2194
-
ggtt_mm->ggtt_mm.last_partial_data = e.val64;
2195
-
return 0;
2196
-
} else if ((g_gtt_index ==
2197
-
(ggtt_mm->ggtt_mm.last_partial_off >>
2198
-
info->gtt_entry_size_shift)) &&
2199
-
(off != ggtt_mm->ggtt_mm.last_partial_off)) {
2200
-
/* the second partial part */
2190
+
bool found = false;
2201
2191
2202
-
int last_off = ggtt_mm->ggtt_mm.last_partial_off &
2203
-
(info->gtt_entry_size - 1);
2192
+
list_for_each_entry_safe(pos, n,
2193
+
&ggtt_mm->ggtt_mm.partial_pte_list, list) {
2194
+
if (g_gtt_index == pos->offset >>
2195
+
info->gtt_entry_size_shift) {
2196
+
if (off != pos->offset) {
2197
+
/* the second partial part*/
2198
+
int last_off = pos->offset &
2199
+
(info->gtt_entry_size - 1);
2204
2200
2205
-
memcpy((void *)&e.val64 + last_off,
2206
-
(void *)&ggtt_mm->ggtt_mm.last_partial_data +
2207
-
last_off, bytes);
2201
+
memcpy((void *)&e.val64 + last_off,
2202
+
(void *)&pos->data + last_off,
2203
+
bytes);
2208
2204
2209
-
ggtt_mm->ggtt_mm.last_partial_off = -1UL;
2210
-
} else {
2211
-
int last_offset;
2205
+
list_del(&pos->list);
2206
+
kfree(pos);
2207
+
found = true;
2208
+
break;
2209
+
}
2212
2210
2213
-
gvt_vgpu_err("failed to populate guest ggtt entry: abnormal ggtt entry write sequence, last_partial_off=%lx, offset=%x, bytes=%d, ggtt entry size=%d\n",
2214
-
ggtt_mm->ggtt_mm.last_partial_off, off,
2215
-
bytes, info->gtt_entry_size);
2211
+
/* update of the first partial part */
2212
+
pos->data = e.val64;
2213
+
ggtt_set_guest_entry(ggtt_mm, &e, g_gtt_index);
2214
+
return 0;
2215
+
}
2216
+
}
2216
2217
2217
-
/* set host ggtt entry to scratch page and clear
2218
-
* virtual ggtt entry as not present for last
2219
-
* partially write offset
2220
-
*/
2221
-
last_offset = ggtt_mm->ggtt_mm.last_partial_off &
2222
-
(~(info->gtt_entry_size - 1));
2223
-
2224
-
ggtt_get_host_entry(ggtt_mm, &m, last_offset);
2225
-
ggtt_invalidate_pte(vgpu, &m);
2226
-
ops->set_pfn(&m, gvt->gtt.scratch_mfn);
2227
-
ops->clear_present(&m);
2228
-
ggtt_set_host_entry(ggtt_mm, &m, last_offset);
2229
-
ggtt_invalidate(gvt->dev_priv);
2230
-
2231
-
ggtt_get_guest_entry(ggtt_mm, &e, last_offset);
2232
-
ops->clear_present(&e);
2233
-
ggtt_set_guest_entry(ggtt_mm, &e, last_offset);
2234
-
2235
-
ggtt_mm->ggtt_mm.last_partial_off = off;
2236
-
ggtt_mm->ggtt_mm.last_partial_data = e.val64;
2237
-
2238
-
return 0;
2218
+
if (!found) {
2219
+
/* the first partial part */
2220
+
partial_pte = kzalloc(sizeof(*partial_pte), GFP_KERNEL);
2221
+
if (!partial_pte)
2222
+
return -ENOMEM;
2223
+
partial_pte->offset = off;
2224
+
partial_pte->data = e.val64;
2225
+
list_add_tail(&partial_pte->list,
2226
+
&ggtt_mm->ggtt_mm.partial_pte_list);
2227
+
partial_update = true;
2239
2228
}
2240
2229
}
2241
2230
2242
-
if (ops->test_present(&e)) {
2231
+
if (!partial_update && (ops->test_present(&e))) {
2243
2232
gfn = ops->get_pfn(&e);
2244
2233
m = e;
2245
2234
···
2252
2263
} else
2253
2264
ops->set_pfn(&m, dma_addr >> PAGE_SHIFT);
2254
2265
} else {
2255
-
ggtt_get_host_entry(ggtt_mm, &m, g_gtt_index);
2256
-
ggtt_invalidate_pte(vgpu, &m);
2257
2266
ops->set_pfn(&m, gvt->gtt.scratch_mfn);
2258
2267
ops->clear_present(&m);
2259
2268
}
2260
2269
2261
2270
out:
2271
+
ggtt_set_guest_entry(ggtt_mm, &e, g_gtt_index);
2272
+
2273
+
ggtt_get_host_entry(ggtt_mm, &e, g_gtt_index);
2274
+
ggtt_invalidate_pte(vgpu, &e);
2275
+
2262
2276
ggtt_set_host_entry(ggtt_mm, &m, g_gtt_index);
2263
2277
ggtt_invalidate(gvt->dev_priv);
2264
-
ggtt_set_guest_entry(ggtt_mm, &e, g_gtt_index);
2265
2278
return 0;
2266
2279
}
2267
2280
···
2421
2430
2422
2431
intel_vgpu_reset_ggtt(vgpu, false);
2423
2432
2433
+
INIT_LIST_HEAD(>t->ggtt_mm->ggtt_mm.partial_pte_list);
2434
+
2424
2435
return create_scratch_page_tree(vgpu);
2425
2436
}
2426
2437
···
2447
2454
2448
2455
static void intel_vgpu_destroy_ggtt_mm(struct intel_vgpu *vgpu)
2449
2456
{
2457
+
struct intel_gvt_partial_pte *pos;
2458
+
2459
+
list_for_each_entry(pos,
2460
+
&vgpu->gtt.ggtt_mm->ggtt_mm.partial_pte_list, list) {
2461
+
gvt_dbg_mm("partial PTE update on hold 0x%lx : 0x%llx\n",
2462
+
pos->offset, pos->data);
2463
+
kfree(pos);
2464
+
}
2450
2465
intel_vgpu_destroy_mm(vgpu->gtt.ggtt_mm);
2451
2466
vgpu->gtt.ggtt_mm = NULL;
2452
2467
}
+7
-3
drivers/gpu/drm/i915/gvt/gtt.h
+7
-3
drivers/gpu/drm/i915/gvt/gtt.h
···
35
35
#define _GVT_GTT_H_
36
36
37
37
#define I915_GTT_PAGE_SHIFT 12
38
-
#define I915_GTT_PAGE_MASK (~(I915_GTT_PAGE_SIZE - 1))
39
38
40
39
struct intel_vgpu_mm;
41
40
···
132
133
133
134
#define GVT_RING_CTX_NR_PDPS GEN8_3LVL_PDPES
134
135
136
+
struct intel_gvt_partial_pte {
137
+
unsigned long offset;
138
+
u64 data;
139
+
struct list_head list;
140
+
};
141
+
135
142
struct intel_vgpu_mm {
136
143
enum intel_gvt_mm_type type;
137
144
struct intel_vgpu *vgpu;
···
162
157
} ppgtt_mm;
163
158
struct {
164
159
void *virtual_ggtt;
165
-
unsigned long last_partial_off;
166
-
u64 last_partial_data;
160
+
struct list_head partial_pte_list;
167
161
} ggtt_mm;
168
162
};
169
163
};
+4
-4
drivers/gpu/drm/i915/gvt/handlers.c
+4
-4
drivers/gpu/drm/i915/gvt/handlers.c
···
1609
1609
return 0;
1610
1610
}
1611
1611
1612
-
static int bxt_edp_psr_imr_iir_write(struct intel_vgpu *vgpu,
1612
+
static int edp_psr_imr_iir_write(struct intel_vgpu *vgpu,
1613
1613
unsigned int offset, void *p_data, unsigned int bytes)
1614
1614
{
1615
1615
vgpu_vreg(vgpu, offset) = 0;
···
2607
2607
MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2608
2608
MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2609
2609
MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2610
+
2611
+
MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
2612
+
MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
2610
2613
return 0;
2611
2614
}
2612
2615
···
3207
3204
MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
3208
3205
MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
3209
3206
MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
3210
-
3211
-
MMIO_DH(EDP_PSR_IMR, D_BXT, NULL, bxt_edp_psr_imr_iir_write);
3212
-
MMIO_DH(EDP_PSR_IIR, D_BXT, NULL, bxt_edp_psr_imr_iir_write);
3213
3207
3214
3208
MMIO_D(RC6_CTX_BASE, D_BXT);
3215
3209
+1
-1
drivers/gpu/drm/i915/gvt/mmio_context.c
+1
-1
drivers/gpu/drm/i915/gvt/mmio_context.c
···
131
131
{RCS, GAMT_CHKN_BIT_REG, 0x0, false}, /* 0x4ab8 */
132
132
133
133
{RCS, GEN9_GAMT_ECO_REG_RW_IA, 0x0, false}, /* 0x4ab0 */
134
-
{RCS, GEN9_CSFE_CHICKEN1_RCS, 0x0, false}, /* 0x20d4 */
134
+
{RCS, GEN9_CSFE_CHICKEN1_RCS, 0xffff, false}, /* 0x20d4 */
135
135
136
136
{RCS, GEN8_GARBCNTL, 0x0, false}, /* 0xb004 */
137
137
{RCS, GEN7_FF_THREAD_MODE, 0x0, false}, /* 0x20a0 */
+8
-7
drivers/gpu/drm/i915/i915_drv.c
+8
-7
drivers/gpu/drm/i915/i915_drv.c
···
1175
1175
return -EINVAL;
1176
1176
}
1177
1177
1178
-
dram_info->valid_dimm = true;
1179
-
1180
1178
/*
1181
1179
* If any of the channel is single rank channel, worst case output
1182
1180
* will be same as if single rank memory, so consider single rank
···
1191
1193
return -EINVAL;
1192
1194
}
1193
1195
1194
-
if (ch0.is_16gb_dimm || ch1.is_16gb_dimm)
1195
-
dram_info->is_16gb_dimm = true;
1196
+
dram_info->is_16gb_dimm = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
1196
1197
1197
1198
dev_priv->dram_info.symmetric_memory = intel_is_dram_symmetric(val_ch0,
1198
1199
val_ch1,
···
1311
1314
return -EINVAL;
1312
1315
}
1313
1316
1314
-
dram_info->valid_dimm = true;
1315
1317
dram_info->valid = true;
1316
1318
return 0;
1317
1319
}
···
1323
1327
int ret;
1324
1328
1325
1329
dram_info->valid = false;
1326
-
dram_info->valid_dimm = false;
1327
-
dram_info->is_16gb_dimm = false;
1328
1330
dram_info->rank = I915_DRAM_RANK_INVALID;
1329
1331
dram_info->bandwidth_kbps = 0;
1330
1332
dram_info->num_channels = 0;
1333
+
1334
+
/*
1335
+
* Assume 16Gb DIMMs are present until proven otherwise.
1336
+
* This is only used for the level 0 watermark latency
1337
+
* w/a which does not apply to bxt/glk.
1338
+
*/
1339
+
dram_info->is_16gb_dimm = !IS_GEN9_LP(dev_priv);
1331
1340
1332
1341
if (INTEL_GEN(dev_priv) < 9 || IS_GEMINILAKE(dev_priv))
1333
1342
return;
-1
drivers/gpu/drm/i915/i915_drv.h
-1
drivers/gpu/drm/i915/i915_drv.h
+1
-1
drivers/gpu/drm/i915/i915_gem_execbuffer.c
+1
-1
drivers/gpu/drm/i915/i915_gem_execbuffer.c
···
460
460
* any non-page-aligned or non-canonical addresses.
461
461
*/
462
462
if (unlikely(entry->flags & EXEC_OBJECT_PINNED &&
463
-
entry->offset != gen8_canonical_addr(entry->offset & PAGE_MASK)))
463
+
entry->offset != gen8_canonical_addr(entry->offset & I915_GTT_PAGE_MASK)))
464
464
return -EINVAL;
465
465
466
466
/* pad_to_size was once a reserved field, so sanitize it */
+1
-1
drivers/gpu/drm/i915/i915_gem_gtt.c
+1
-1
drivers/gpu/drm/i915/i915_gem_gtt.c
+17
-15
drivers/gpu/drm/i915/i915_gem_gtt.h
+17
-15
drivers/gpu/drm/i915/i915_gem_gtt.h
···
42
42
#include "i915_selftest.h"
43
43
#include "i915_timeline.h"
44
44
45
-
#define I915_GTT_PAGE_SIZE_4K BIT(12)
46
-
#define I915_GTT_PAGE_SIZE_64K BIT(16)
47
-
#define I915_GTT_PAGE_SIZE_2M BIT(21)
45
+
#define I915_GTT_PAGE_SIZE_4K BIT_ULL(12)
46
+
#define I915_GTT_PAGE_SIZE_64K BIT_ULL(16)
47
+
#define I915_GTT_PAGE_SIZE_2M BIT_ULL(21)
48
48
49
49
#define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K
50
50
#define I915_GTT_MAX_PAGE_SIZE I915_GTT_PAGE_SIZE_2M
51
+
52
+
#define I915_GTT_PAGE_MASK -I915_GTT_PAGE_SIZE
51
53
52
54
#define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE
53
55
···
661
659
u64 start, u64 end, unsigned int flags);
662
660
663
661
/* Flags used by pin/bind&friends. */
664
-
#define PIN_NONBLOCK BIT(0)
665
-
#define PIN_MAPPABLE BIT(1)
666
-
#define PIN_ZONE_4G BIT(2)
667
-
#define PIN_NONFAULT BIT(3)
668
-
#define PIN_NOEVICT BIT(4)
662
+
#define PIN_NONBLOCK BIT_ULL(0)
663
+
#define PIN_MAPPABLE BIT_ULL(1)
664
+
#define PIN_ZONE_4G BIT_ULL(2)
665
+
#define PIN_NONFAULT BIT_ULL(3)
666
+
#define PIN_NOEVICT BIT_ULL(4)
669
667
670
-
#define PIN_MBZ BIT(5) /* I915_VMA_PIN_OVERFLOW */
671
-
#define PIN_GLOBAL BIT(6) /* I915_VMA_GLOBAL_BIND */
672
-
#define PIN_USER BIT(7) /* I915_VMA_LOCAL_BIND */
673
-
#define PIN_UPDATE BIT(8)
668
+
#define PIN_MBZ BIT_ULL(5) /* I915_VMA_PIN_OVERFLOW */
669
+
#define PIN_GLOBAL BIT_ULL(6) /* I915_VMA_GLOBAL_BIND */
670
+
#define PIN_USER BIT_ULL(7) /* I915_VMA_LOCAL_BIND */
671
+
#define PIN_UPDATE BIT_ULL(8)
674
672
675
-
#define PIN_HIGH BIT(9)
676
-
#define PIN_OFFSET_BIAS BIT(10)
677
-
#define PIN_OFFSET_FIXED BIT(11)
673
+
#define PIN_HIGH BIT_ULL(9)
674
+
#define PIN_OFFSET_BIAS BIT_ULL(10)
675
+
#define PIN_OFFSET_FIXED BIT_ULL(11)
678
676
#define PIN_OFFSET_MASK (-I915_GTT_PAGE_SIZE)
679
677
680
678
#endif
+12
-8
drivers/gpu/drm/i915/i915_reg.h
+12
-8
drivers/gpu/drm/i915/i915_reg.h
···
2095
2095
2096
2096
/* ICL PHY DFLEX registers */
2097
2097
#define PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0)
2098
-
#define DFLEXDPMLE1_DPMLETC_MASK(n) (0xf << (4 * (n)))
2099
-
#define DFLEXDPMLE1_DPMLETC(n, x) ((x) << (4 * (n)))
2098
+
#define DFLEXDPMLE1_DPMLETC_MASK(tc_port) (0xf << (4 * (tc_port)))
2099
+
#define DFLEXDPMLE1_DPMLETC_ML0(tc_port) (1 << (4 * (tc_port)))
2100
+
#define DFLEXDPMLE1_DPMLETC_ML1_0(tc_port) (3 << (4 * (tc_port)))
2101
+
#define DFLEXDPMLE1_DPMLETC_ML3(tc_port) (8 << (4 * (tc_port)))
2102
+
#define DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) (12 << (4 * (tc_port)))
2103
+
#define DFLEXDPMLE1_DPMLETC_ML3_0(tc_port) (15 << (4 * (tc_port)))
2100
2104
2101
2105
/* BXT PHY Ref registers */
2102
2106
#define _PORT_REF_DW3_A 0x16218C
···
4597
4593
4598
4594
#define DRM_DIP_ENABLE (1 << 28)
4599
4595
#define PSR_VSC_BIT_7_SET (1 << 27)
4600
-
#define VSC_SELECT_MASK (0x3 << 26)
4601
-
#define VSC_SELECT_SHIFT 26
4602
-
#define VSC_DIP_HW_HEA_DATA (0 << 26)
4603
-
#define VSC_DIP_HW_HEA_SW_DATA (1 << 26)
4604
-
#define VSC_DIP_HW_DATA_SW_HEA (2 << 26)
4605
-
#define VSC_DIP_SW_HEA_DATA (3 << 26)
4596
+
#define VSC_SELECT_MASK (0x3 << 25)
4597
+
#define VSC_SELECT_SHIFT 25
4598
+
#define VSC_DIP_HW_HEA_DATA (0 << 25)
4599
+
#define VSC_DIP_HW_HEA_SW_DATA (1 << 25)
4600
+
#define VSC_DIP_HW_DATA_SW_HEA (2 << 25)
4601
+
#define VSC_DIP_SW_HEA_DATA (3 << 25)
4606
4602
#define VDIP_ENABLE_PPS (1 << 24)
4607
4603
4608
4604
/* Panel power sequencing */
+17
drivers/gpu/drm/i915/intel_audio.c
+17
drivers/gpu/drm/i915/intel_audio.c
···
144
144
/* HDMI N/CTS table */
145
145
#define TMDS_297M 297000
146
146
#define TMDS_296M 296703
147
+
#define TMDS_594M 594000
148
+
#define TMDS_593M 593407
149
+
147
150
static const struct {
148
151
int sample_rate;
149
152
int clock;
···
167
164
{ 176400, TMDS_297M, 18816, 247500 },
168
165
{ 192000, TMDS_296M, 23296, 281250 },
169
166
{ 192000, TMDS_297M, 20480, 247500 },
167
+
{ 44100, TMDS_593M, 8918, 937500 },
168
+
{ 44100, TMDS_594M, 9408, 990000 },
169
+
{ 48000, TMDS_593M, 5824, 562500 },
170
+
{ 48000, TMDS_594M, 6144, 594000 },
171
+
{ 32000, TMDS_593M, 5824, 843750 },
172
+
{ 32000, TMDS_594M, 3072, 445500 },
173
+
{ 88200, TMDS_593M, 17836, 937500 },
174
+
{ 88200, TMDS_594M, 18816, 990000 },
175
+
{ 96000, TMDS_593M, 11648, 562500 },
176
+
{ 96000, TMDS_594M, 12288, 594000 },
177
+
{ 176400, TMDS_593M, 35672, 937500 },
178
+
{ 176400, TMDS_594M, 37632, 990000 },
179
+
{ 192000, TMDS_593M, 23296, 562500 },
180
+
{ 192000, TMDS_594M, 24576, 594000 },
170
181
};
171
182
172
183
/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
+2
-16
drivers/gpu/drm/i915/intel_cdclk.c
+2
-16
drivers/gpu/drm/i915/intel_cdclk.c
···
2138
2138
static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv,
2139
2139
int pixel_rate)
2140
2140
{
2141
-
if (INTEL_GEN(dev_priv) >= 10)
2141
+
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2142
2142
return DIV_ROUND_UP(pixel_rate, 2);
2143
-
else if (IS_GEMINILAKE(dev_priv))
2144
-
/*
2145
-
* FIXME: Avoid using a pixel clock that is more than 99% of the cdclk
2146
-
* as a temporary workaround. Use a higher cdclk instead. (Note that
2147
-
* intel_compute_max_dotclk() limits the max pixel clock to 99% of max
2148
-
* cdclk.)
2149
-
*/
2150
-
return DIV_ROUND_UP(pixel_rate * 100, 2 * 99);
2151
2143
else if (IS_GEN9(dev_priv) ||
2152
2144
IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2153
2145
return pixel_rate;
···
2535
2543
{
2536
2544
int max_cdclk_freq = dev_priv->max_cdclk_freq;
2537
2545
2538
-
if (INTEL_GEN(dev_priv) >= 10)
2546
+
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2539
2547
return 2 * max_cdclk_freq;
2540
-
else if (IS_GEMINILAKE(dev_priv))
2541
-
/*
2542
-
* FIXME: Limiting to 99% as a temporary workaround. See
2543
-
* intel_min_cdclk() for details.
2544
-
*/
2545
-
return 2 * max_cdclk_freq * 99 / 100;
2546
2548
else if (IS_GEN9(dev_priv) ||
2547
2549
IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2548
2550
return max_cdclk_freq;
+7
-12
drivers/gpu/drm/i915/intel_display.c
+7
-12
drivers/gpu/drm/i915/intel_display.c
···
12768
12768
intel_check_cpu_fifo_underruns(dev_priv);
12769
12769
intel_check_pch_fifo_underruns(dev_priv);
12770
12770
12771
-
if (!new_crtc_state->active) {
12772
-
/*
12773
-
* Make sure we don't call initial_watermarks
12774
-
* for ILK-style watermark updates.
12775
-
*
12776
-
* No clue what this is supposed to achieve.
12777
-
*/
12778
-
if (INTEL_GEN(dev_priv) >= 9)
12779
-
dev_priv->display.initial_watermarks(intel_state,
12780
-
to_intel_crtc_state(new_crtc_state));
12781
-
}
12771
+
/* FIXME unify this for all platforms */
12772
+
if (!new_crtc_state->active &&
12773
+
!HAS_GMCH_DISPLAY(dev_priv) &&
12774
+
dev_priv->display.initial_watermarks)
12775
+
dev_priv->display.initial_watermarks(intel_state,
12776
+
to_intel_crtc_state(new_crtc_state));
12782
12777
}
12783
12778
}
12784
12779
···
14641
14646
fb->height < SKL_MIN_YUV_420_SRC_H ||
14642
14647
(fb->width % 4) != 0 || (fb->height % 4) != 0)) {
14643
14648
DRM_DEBUG_KMS("src dimensions not correct for NV12\n");
14644
-
return -EINVAL;
14649
+
goto err;
14645
14650
}
14646
14651
14647
14652
for (i = 0; i < fb->format->num_planes; i++) {
+3
-1
drivers/gpu/drm/i915/intel_lpe_audio.c
+3
-1
drivers/gpu/drm/i915/intel_lpe_audio.c
+1
-2
drivers/gpu/drm/i915/intel_pm.c
+1
-2
drivers/gpu/drm/i915/intel_pm.c
···
2881
2881
* any underrun. If not able to get Dimm info assume 16GB dimm
2882
2882
* to avoid any underrun.
2883
2883
*/
2884
-
if (!dev_priv->dram_info.valid_dimm ||
2885
-
dev_priv->dram_info.is_16gb_dimm)
2884
+
if (dev_priv->dram_info.is_16gb_dimm)
2886
2885
wm[0] += 1;
2887
2886
2888
2887
} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
+1
-1
drivers/gpu/drm/i915/selftests/huge_pages.c
+1
-1
drivers/gpu/drm/i915/selftests/huge_pages.c
+3
-3
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+3
-3
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
···
1337
1337
GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
1338
1338
if (vma->node.start != total ||
1339
1339
vma->node.size != 2*I915_GTT_PAGE_SIZE) {
1340
-
pr_err("i915_gem_gtt_reserve (pass 1) placement failed, found (%llx + %llx), expected (%llx + %lx)\n",
1340
+
pr_err("i915_gem_gtt_reserve (pass 1) placement failed, found (%llx + %llx), expected (%llx + %llx)\n",
1341
1341
vma->node.start, vma->node.size,
1342
1342
total, 2*I915_GTT_PAGE_SIZE);
1343
1343
err = -EINVAL;
···
1386
1386
GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
1387
1387
if (vma->node.start != total ||
1388
1388
vma->node.size != 2*I915_GTT_PAGE_SIZE) {
1389
-
pr_err("i915_gem_gtt_reserve (pass 2) placement failed, found (%llx + %llx), expected (%llx + %lx)\n",
1389
+
pr_err("i915_gem_gtt_reserve (pass 2) placement failed, found (%llx + %llx), expected (%llx + %llx)\n",
1390
1390
vma->node.start, vma->node.size,
1391
1391
total, 2*I915_GTT_PAGE_SIZE);
1392
1392
err = -EINVAL;
···
1430
1430
GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
1431
1431
if (vma->node.start != offset ||
1432
1432
vma->node.size != 2*I915_GTT_PAGE_SIZE) {
1433
-
pr_err("i915_gem_gtt_reserve (pass 3) placement failed, found (%llx + %llx), expected (%llx + %lx)\n",
1433
+
pr_err("i915_gem_gtt_reserve (pass 3) placement failed, found (%llx + %llx), expected (%llx + %llx)\n",
1434
1434
vma->node.start, vma->node.size,
1435
1435
offset, 2*I915_GTT_PAGE_SIZE);
1436
1436
err = -EINVAL;
+2
-2
drivers/gpu/drm/sun4i/sun4i_lvds.c
+2
-2
drivers/gpu/drm/sun4i/sun4i_lvds.c
···
75
75
76
76
DRM_DEBUG_DRIVER("Enabling LVDS output\n");
77
77
78
-
if (!IS_ERR(tcon->panel)) {
78
+
if (tcon->panel) {
79
79
drm_panel_prepare(tcon->panel);
80
80
drm_panel_enable(tcon->panel);
81
81
}
···
88
88
89
89
DRM_DEBUG_DRIVER("Disabling LVDS output\n");
90
90
91
-
if (!IS_ERR(tcon->panel)) {
91
+
if (tcon->panel) {
92
92
drm_panel_disable(tcon->panel);
93
93
drm_panel_unprepare(tcon->panel);
94
94
}
+2
-2
drivers/gpu/drm/sun4i/sun4i_rgb.c
+2
-2
drivers/gpu/drm/sun4i/sun4i_rgb.c
···
135
135
136
136
DRM_DEBUG_DRIVER("Enabling RGB output\n");
137
137
138
-
if (!IS_ERR(tcon->panel)) {
138
+
if (tcon->panel) {
139
139
drm_panel_prepare(tcon->panel);
140
140
drm_panel_enable(tcon->panel);
141
141
}
···
148
148
149
149
DRM_DEBUG_DRIVER("Disabling RGB output\n");
150
150
151
-
if (!IS_ERR(tcon->panel)) {
151
+
if (tcon->panel) {
152
152
drm_panel_disable(tcon->panel);
153
153
drm_panel_unprepare(tcon->panel);
154
154
}
+3
-2
drivers/gpu/drm/sun4i/sun4i_tcon.c
+3
-2
drivers/gpu/drm/sun4i/sun4i_tcon.c
···
491
491
sun4i_tcon0_mode_set_common(tcon, mode);
492
492
493
493
/* Set dithering if needed */
494
-
sun4i_tcon0_mode_set_dithering(tcon, tcon->panel->connector);
494
+
if (tcon->panel)
495
+
sun4i_tcon0_mode_set_dithering(tcon, tcon->panel->connector);
495
496
496
497
/* Adjust clock delay */
497
498
clk_delay = sun4i_tcon_get_clk_delay(mode, 0);
···
556
555
* Following code is a way to avoid quirks all around TCON
557
556
* and DOTCLOCK drivers.
558
557
*/
559
-
if (!IS_ERR(tcon->panel)) {
558
+
if (tcon->panel) {
560
559
struct drm_panel *panel = tcon->panel;
561
560
struct drm_connector *connector = panel->connector;
562
561
struct drm_display_info display_info = connector->display_info;
+9
-9
include/uapi/linux/kfd_ioctl.h
+9
-9
include/uapi/linux/kfd_ioctl.h
···
83
83
};
84
84
85
85
struct kfd_ioctl_get_queue_wave_state_args {
86
-
uint64_t ctl_stack_address; /* to KFD */
87
-
uint32_t ctl_stack_used_size; /* from KFD */
88
-
uint32_t save_area_used_size; /* from KFD */
89
-
uint32_t queue_id; /* to KFD */
90
-
uint32_t pad;
86
+
__u64 ctl_stack_address; /* to KFD */
87
+
__u32 ctl_stack_used_size; /* from KFD */
88
+
__u32 save_area_used_size; /* from KFD */
89
+
__u32 queue_id; /* to KFD */
90
+
__u32 pad;
91
91
};
92
92
93
93
/* For kfd_ioctl_set_memory_policy_args.default_policy and alternate_policy */
···
255
255
256
256
/* hw exception data */
257
257
struct kfd_hsa_hw_exception_data {
258
-
uint32_t reset_type;
259
-
uint32_t reset_cause;
260
-
uint32_t memory_lost;
261
-
uint32_t gpu_id;
258
+
__u32 reset_type;
259
+
__u32 reset_cause;
260
+
__u32 memory_lost;
261
+
__u32 gpu_id;
262
262
};
263
263
264
264
/* Event data */