mfd: rk8xx: Add rk806 support · tjh.dev/kernel@210f418

+14

drivers/mfd/Kconfig

··· 1201 1201 through I2C interface. The device supports multiple sub-devices 1202 1202 including interrupts, RTC, LDO & DCDC regulators, and onkey. 1203 1203 1204 + config MFD_RK8XX_SPI 1205 + tristate "Rockchip RK806 Power Management Chip" 1206 + depends on SPI && OF 1207 + select MFD_CORE 1208 + select REGMAP_SPI 1209 + select REGMAP_IRQ 1210 + select MFD_RK8XX 1211 + help 1212 + If you say yes here you get support for the RK806 Power Management 1213 + chip. 1214 + This driver provides common support for accessing the device 1215 + through an SPI interface. The device supports multiple sub-devices 1216 + including interrupts, LDO & DCDC regulators, and power on-key. 1217 + 1204 1218 config MFD_RN5T618 1205 1219 tristate "Ricoh RN5T567/618 PMIC" 1206 1220 depends on I2C

+1

drivers/mfd/Makefile

··· 216 216 obj-$(CONFIG_MFD_RC5T583) += rc5t583.o rc5t583-irq.o 217 217 obj-$(CONFIG_MFD_RK8XX) += rk8xx-core.o 218 218 obj-$(CONFIG_MFD_RK8XX_I2C) += rk8xx-i2c.o 219 + obj-$(CONFIG_MFD_RK8XX_SPI) += rk8xx-spi.o 219 220 obj-$(CONFIG_MFD_RN5T618) += rn5t618.o 220 221 obj-$(CONFIG_MFD_SEC_CORE) += sec-core.o sec-irq.o 221 222 obj-$(CONFIG_MFD_SYSCON) += syscon.o

+66 -3

drivers/mfd/rk8xx-core.c

··· 37 37 DEFINE_RES_IRQ(RK805_IRQ_PWRON_FALL), 38 38 }; 39 39 40 + static struct resource rk806_pwrkey_resources[] = { 41 + DEFINE_RES_IRQ(RK806_IRQ_PWRON_FALL), 42 + DEFINE_RES_IRQ(RK806_IRQ_PWRON_RISE), 43 + }; 44 + 40 45 static const struct resource rk817_pwrkey_resources[] = { 41 46 DEFINE_RES_IRQ(RK817_IRQ_PWRON_RISE), 42 47 DEFINE_RES_IRQ(RK817_IRQ_PWRON_FALL), ··· 66 61 .num_resources = ARRAY_SIZE(rk805_key_resources), 67 62 .resources = &rk805_key_resources[0], 68 63 .id = PLATFORM_DEVID_NONE, 64 + }, 65 + }; 66 + 67 + static const struct mfd_cell rk806s[] = { 68 + { .name = "rk805-pinctrl", .id = PLATFORM_DEVID_AUTO, }, 69 + { .name = "rk808-regulator", .id = PLATFORM_DEVID_AUTO, }, 70 + { 71 + .name = "rk805-pwrkey", 72 + .resources = rk806_pwrkey_resources, 73 + .num_resources = ARRAY_SIZE(rk806_pwrkey_resources), 74 + .id = PLATFORM_DEVID_AUTO, 69 75 }, 70 76 }; 71 77 ··· 137 121 RK805_BUCK4_ILMAX_3500MA}, 138 122 {RK805_BUCK4_CONFIG_REG, BUCK_ILMIN_MASK, BUCK_ILMIN_400MA}, 139 123 {RK805_THERMAL_REG, TEMP_HOTDIE_MSK, TEMP115C}, 124 + }; 125 + 126 + static const struct rk808_reg_data rk806_pre_init_reg[] = { 127 + { RK806_GPIO_INT_CONFIG, RK806_INT_POL_MSK, RK806_INT_POL_L }, 128 + { RK806_SYS_CFG3, RK806_SLAVE_RESTART_FUN_MSK, RK806_SLAVE_RESTART_FUN_EN }, 129 + { RK806_SYS_OPTION, RK806_SYS_ENB2_2M_MSK, RK806_SYS_ENB2_2M_EN }, 140 130 }; 141 131 142 132 static const struct rk808_reg_data rk808_pre_init_reg[] = { ··· 295 273 }, 296 274 }; 297 275 276 + static const struct regmap_irq rk806_irqs[] = { 277 + /* INT_STS0 IRQs */ 278 + REGMAP_IRQ_REG(RK806_IRQ_PWRON_FALL, 0, RK806_INT_STS_PWRON_FALL), 279 + REGMAP_IRQ_REG(RK806_IRQ_PWRON_RISE, 0, RK806_INT_STS_PWRON_RISE), 280 + REGMAP_IRQ_REG(RK806_IRQ_PWRON, 0, RK806_INT_STS_PWRON), 281 + REGMAP_IRQ_REG(RK806_IRQ_PWRON_LP, 0, RK806_INT_STS_PWRON_LP), 282 + REGMAP_IRQ_REG(RK806_IRQ_HOTDIE, 0, RK806_INT_STS_HOTDIE), 283 + REGMAP_IRQ_REG(RK806_IRQ_VDC_RISE, 0, RK806_INT_STS_VDC_RISE), 284 + REGMAP_IRQ_REG(RK806_IRQ_VDC_FALL, 0, RK806_INT_STS_VDC_FALL), 285 + REGMAP_IRQ_REG(RK806_IRQ_VB_LO, 0, RK806_INT_STS_VB_LO), 286 + /* INT_STS1 IRQs */ 287 + REGMAP_IRQ_REG(RK806_IRQ_REV0, 1, RK806_INT_STS_REV0), 288 + REGMAP_IRQ_REG(RK806_IRQ_REV1, 1, RK806_INT_STS_REV1), 289 + REGMAP_IRQ_REG(RK806_IRQ_REV2, 1, RK806_INT_STS_REV2), 290 + REGMAP_IRQ_REG(RK806_IRQ_CRC_ERROR, 1, RK806_INT_STS_CRC_ERROR), 291 + REGMAP_IRQ_REG(RK806_IRQ_SLP3_GPIO, 1, RK806_INT_STS_SLP3_GPIO), 292 + REGMAP_IRQ_REG(RK806_IRQ_SLP2_GPIO, 1, RK806_INT_STS_SLP2_GPIO), 293 + REGMAP_IRQ_REG(RK806_IRQ_SLP1_GPIO, 1, RK806_INT_STS_SLP1_GPIO), 294 + REGMAP_IRQ_REG(RK806_IRQ_WDT, 1, RK806_INT_STS_WDT), 295 + }; 296 + 298 297 static const struct regmap_irq rk808_irqs[] = { 299 298 /* INT_STS */ 300 299 [RK808_IRQ_VOUT_LO] = { ··· 466 423 .init_ack_masked = true, 467 424 }; 468 425 426 + static struct regmap_irq_chip rk806_irq_chip = { 427 + .name = "rk806", 428 + .irqs = rk806_irqs, 429 + .num_irqs = ARRAY_SIZE(rk806_irqs), 430 + .num_regs = 2, 431 + .irq_reg_stride = 2, 432 + .mask_base = RK806_INT_MSK0, 433 + .status_base = RK806_INT_STS0, 434 + .ack_base = RK806_INT_STS0, 435 + .init_ack_masked = true, 436 + }; 437 + 469 438 static const struct regmap_irq_chip rk808_irq_chip = { 470 439 .name = "rk808", 471 440 .irqs = rk808_irqs, ··· 604 549 struct rk808 *rk808; 605 550 const struct rk808_reg_data *pre_init_reg; 606 551 const struct mfd_cell *cells; 552 + int dual_support = 0; 607 553 int nr_pre_init_regs; 608 554 int nr_cells; 609 555 int ret; ··· 625 569 nr_pre_init_regs = ARRAY_SIZE(rk805_pre_init_reg); 626 570 cells = rk805s; 627 571 nr_cells = ARRAY_SIZE(rk805s); 572 + break; 573 + case RK806_ID: 574 + rk808->regmap_irq_chip = &rk806_irq_chip; 575 + pre_init_reg = rk806_pre_init_reg; 576 + nr_pre_init_regs = ARRAY_SIZE(rk806_pre_init_reg); 577 + cells = rk806s; 578 + nr_cells = ARRAY_SIZE(rk806s); 579 + dual_support = IRQF_SHARED; 628 580 break; 629 581 case RK808_ID: 630 582 rk808->regmap_irq_chip = &rk808_irq_chip; ··· 665 601 return dev_err_probe(dev, -EINVAL, "No interrupt support, no core IRQ\n"); 666 602 667 603 ret = devm_regmap_add_irq_chip(dev, rk808->regmap, irq, 668 - IRQF_ONESHOT, -1, 604 + IRQF_ONESHOT | dual_support, -1, 669 605 rk808->regmap_irq_chip, &rk808->irq_data); 670 606 if (ret) 671 607 return dev_err_probe(dev, ret, "Failed to add irq_chip\n"); ··· 680 616 pre_init_reg[i].addr); 681 617 } 682 618 683 - ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, 684 - cells, nr_cells, NULL, 0, 619 + ret = devm_mfd_add_devices(dev, 0, cells, nr_cells, NULL, 0, 685 620 regmap_irq_get_domain(rk808->irq_data)); 686 621 if (ret) 687 622 return dev_err_probe(dev, ret, "failed to add MFD devices\n");

+124

drivers/mfd/rk8xx-spi.c

··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * Rockchip RK806 Core (SPI) driver 4 + * 5 + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 6 + * Copyright (c) 2023 Collabora Ltd. 7 + * 8 + * Author: Xu Shengfei <xsf@rock-chips.com> 9 + * Author: Sebastian Reichel <sebastian.reichel@collabora.com> 10 + */ 11 + 12 + #include <linux/interrupt.h> 13 + #include <linux/mfd/core.h> 14 + #include <linux/mfd/rk808.h> 15 + #include <linux/module.h> 16 + #include <linux/regmap.h> 17 + #include <linux/spi/spi.h> 18 + 19 + #define RK806_ADDR_SIZE 2 20 + #define RK806_CMD_WITH_SIZE(CMD, VALUE_BYTES) \ 21 + (RK806_CMD_##CMD | RK806_CMD_CRC_DIS | (VALUE_BYTES - 1)) 22 + 23 + static const struct regmap_range rk806_volatile_ranges[] = { 24 + regmap_reg_range(RK806_POWER_EN0, RK806_POWER_EN5), 25 + regmap_reg_range(RK806_DVS_START_CTRL, RK806_INT_MSK1), 26 + }; 27 + 28 + static const struct regmap_access_table rk806_volatile_table = { 29 + .yes_ranges = rk806_volatile_ranges, 30 + .n_yes_ranges = ARRAY_SIZE(rk806_volatile_ranges), 31 + }; 32 + 33 + static const struct regmap_config rk806_regmap_config_spi = { 34 + .reg_bits = 16, 35 + .val_bits = 8, 36 + .max_register = RK806_BUCK_RSERVE_REG5, 37 + .cache_type = REGCACHE_RBTREE, 38 + .volatile_table = &rk806_volatile_table, 39 + }; 40 + 41 + static int rk806_spi_bus_write(void *context, const void *vdata, size_t count) 42 + { 43 + struct device *dev = context; 44 + struct spi_device *spi = to_spi_device(dev); 45 + struct spi_transfer xfer[2] = { 0 }; 46 + /* data and thus count includes the register address */ 47 + size_t val_size = count - RK806_ADDR_SIZE; 48 + char cmd; 49 + 50 + if (val_size < 1 || val_size > (RK806_CMD_LEN_MSK + 1)) 51 + return -EINVAL; 52 + 53 + cmd = RK806_CMD_WITH_SIZE(WRITE, val_size); 54 + 55 + xfer[0].tx_buf = &cmd; 56 + xfer[0].len = sizeof(cmd); 57 + xfer[1].tx_buf = vdata; 58 + xfer[1].len = count; 59 + 60 + return spi_sync_transfer(spi, xfer, ARRAY_SIZE(xfer)); 61 + } 62 + 63 + static int rk806_spi_bus_read(void *context, const void *vreg, size_t reg_size, 64 + void *val, size_t val_size) 65 + { 66 + struct device *dev = context; 67 + struct spi_device *spi = to_spi_device(dev); 68 + char txbuf[3] = { 0 }; 69 + 70 + if (reg_size != RK806_ADDR_SIZE || 71 + val_size < 1 || val_size > (RK806_CMD_LEN_MSK + 1)) 72 + return -EINVAL; 73 + 74 + /* TX buffer contains command byte followed by two address bytes */ 75 + txbuf[0] = RK806_CMD_WITH_SIZE(READ, val_size); 76 + memcpy(txbuf+1, vreg, reg_size); 77 + 78 + return spi_write_then_read(spi, txbuf, sizeof(txbuf), val, val_size); 79 + } 80 + 81 + static const struct regmap_bus rk806_regmap_bus_spi = { 82 + .write = rk806_spi_bus_write, 83 + .read = rk806_spi_bus_read, 84 + .reg_format_endian_default = REGMAP_ENDIAN_LITTLE, 85 + }; 86 + 87 + static int rk8xx_spi_probe(struct spi_device *spi) 88 + { 89 + struct regmap *regmap; 90 + 91 + regmap = devm_regmap_init(&spi->dev, &rk806_regmap_bus_spi, 92 + &spi->dev, &rk806_regmap_config_spi); 93 + if (IS_ERR(regmap)) 94 + return dev_err_probe(&spi->dev, PTR_ERR(regmap), 95 + "Failed to init regmap\n"); 96 + 97 + return rk8xx_probe(&spi->dev, RK806_ID, spi->irq, regmap); 98 + } 99 + 100 + static const struct of_device_id rk8xx_spi_of_match[] = { 101 + { .compatible = "rockchip,rk806", }, 102 + { } 103 + }; 104 + MODULE_DEVICE_TABLE(of, rk8xx_spi_of_match); 105 + 106 + static const struct spi_device_id rk8xx_spi_id_table[] = { 107 + { "rk806", 0 }, 108 + { } 109 + }; 110 + MODULE_DEVICE_TABLE(spi, rk8xx_spi_id_table); 111 + 112 + static struct spi_driver rk8xx_spi_driver = { 113 + .driver = { 114 + .name = "rk8xx-spi", 115 + .of_match_table = rk8xx_spi_of_match, 116 + }, 117 + .probe = rk8xx_spi_probe, 118 + .id_table = rk8xx_spi_id_table, 119 + }; 120 + module_spi_driver(rk8xx_spi_driver); 121 + 122 + MODULE_AUTHOR("Xu Shengfei <xsf@rock-chips.com>"); 123 + MODULE_DESCRIPTION("RK8xx SPI PMIC driver"); 124 + MODULE_LICENSE("GPL");

+409

include/linux/mfd/rk808.h

··· 289 289 #define RK805_INT_ALARM_EN (1 << 3) 290 290 #define RK805_INT_TIMER_EN (1 << 2) 291 291 292 + /* RK806 */ 293 + #define RK806_POWER_EN0 0x0 294 + #define RK806_POWER_EN1 0x1 295 + #define RK806_POWER_EN2 0x2 296 + #define RK806_POWER_EN3 0x3 297 + #define RK806_POWER_EN4 0x4 298 + #define RK806_POWER_EN5 0x5 299 + #define RK806_POWER_SLP_EN0 0x6 300 + #define RK806_POWER_SLP_EN1 0x7 301 + #define RK806_POWER_SLP_EN2 0x8 302 + #define RK806_POWER_DISCHRG_EN0 0x9 303 + #define RK806_POWER_DISCHRG_EN1 0xA 304 + #define RK806_POWER_DISCHRG_EN2 0xB 305 + #define RK806_BUCK_FB_CONFIG 0xC 306 + #define RK806_SLP_LP_CONFIG 0xD 307 + #define RK806_POWER_FPWM_EN0 0xE 308 + #define RK806_POWER_FPWM_EN1 0xF 309 + #define RK806_BUCK1_CONFIG 0x10 310 + #define RK806_BUCK2_CONFIG 0x11 311 + #define RK806_BUCK3_CONFIG 0x12 312 + #define RK806_BUCK4_CONFIG 0x13 313 + #define RK806_BUCK5_CONFIG 0x14 314 + #define RK806_BUCK6_CONFIG 0x15 315 + #define RK806_BUCK7_CONFIG 0x16 316 + #define RK806_BUCK8_CONFIG 0x17 317 + #define RK806_BUCK9_CONFIG 0x18 318 + #define RK806_BUCK10_CONFIG 0x19 319 + #define RK806_BUCK1_ON_VSEL 0x1A 320 + #define RK806_BUCK2_ON_VSEL 0x1B 321 + #define RK806_BUCK3_ON_VSEL 0x1C 322 + #define RK806_BUCK4_ON_VSEL 0x1D 323 + #define RK806_BUCK5_ON_VSEL 0x1E 324 + #define RK806_BUCK6_ON_VSEL 0x1F 325 + #define RK806_BUCK7_ON_VSEL 0x20 326 + #define RK806_BUCK8_ON_VSEL 0x21 327 + #define RK806_BUCK9_ON_VSEL 0x22 328 + #define RK806_BUCK10_ON_VSEL 0x23 329 + #define RK806_BUCK1_SLP_VSEL 0x24 330 + #define RK806_BUCK2_SLP_VSEL 0x25 331 + #define RK806_BUCK3_SLP_VSEL 0x26 332 + #define RK806_BUCK4_SLP_VSEL 0x27 333 + #define RK806_BUCK5_SLP_VSEL 0x28 334 + #define RK806_BUCK6_SLP_VSEL 0x29 335 + #define RK806_BUCK7_SLP_VSEL 0x2A 336 + #define RK806_BUCK8_SLP_VSEL 0x2B 337 + #define RK806_BUCK9_SLP_VSEL 0x2D 338 + #define RK806_BUCK10_SLP_VSEL 0x2E 339 + #define RK806_BUCK_DEBUG1 0x30 340 + #define RK806_BUCK_DEBUG2 0x31 341 + #define RK806_BUCK_DEBUG3 0x32 342 + #define RK806_BUCK_DEBUG4 0x33 343 + #define RK806_BUCK_DEBUG5 0x34 344 + #define RK806_BUCK_DEBUG6 0x35 345 + #define RK806_BUCK_DEBUG7 0x36 346 + #define RK806_BUCK_DEBUG8 0x37 347 + #define RK806_BUCK_DEBUG9 0x38 348 + #define RK806_BUCK_DEBUG10 0x39 349 + #define RK806_BUCK_DEBUG11 0x3A 350 + #define RK806_BUCK_DEBUG12 0x3B 351 + #define RK806_BUCK_DEBUG13 0x3C 352 + #define RK806_BUCK_DEBUG14 0x3D 353 + #define RK806_BUCK_DEBUG15 0x3E 354 + #define RK806_BUCK_DEBUG16 0x3F 355 + #define RK806_BUCK_DEBUG17 0x40 356 + #define RK806_BUCK_DEBUG18 0x41 357 + #define RK806_NLDO_IMAX 0x42 358 + #define RK806_NLDO1_ON_VSEL 0x43 359 + #define RK806_NLDO2_ON_VSEL 0x44 360 + #define RK806_NLDO3_ON_VSEL 0x45 361 + #define RK806_NLDO4_ON_VSEL 0x46 362 + #define RK806_NLDO5_ON_VSEL 0x47 363 + #define RK806_NLDO1_SLP_VSEL 0x48 364 + #define RK806_NLDO2_SLP_VSEL 0x49 365 + #define RK806_NLDO3_SLP_VSEL 0x4A 366 + #define RK806_NLDO4_SLP_VSEL 0x4B 367 + #define RK806_NLDO5_SLP_VSEL 0x4C 368 + #define RK806_PLDO_IMAX 0x4D 369 + #define RK806_PLDO1_ON_VSEL 0x4E 370 + #define RK806_PLDO2_ON_VSEL 0x4F 371 + #define RK806_PLDO3_ON_VSEL 0x50 372 + #define RK806_PLDO4_ON_VSEL 0x51 373 + #define RK806_PLDO5_ON_VSEL 0x52 374 + #define RK806_PLDO6_ON_VSEL 0x53 375 + #define RK806_PLDO1_SLP_VSEL 0x54 376 + #define RK806_PLDO2_SLP_VSEL 0x55 377 + #define RK806_PLDO3_SLP_VSEL 0x56 378 + #define RK806_PLDO4_SLP_VSEL 0x57 379 + #define RK806_PLDO5_SLP_VSEL 0x58 380 + #define RK806_PLDO6_SLP_VSEL 0x59 381 + #define RK806_CHIP_NAME 0x5A 382 + #define RK806_CHIP_VER 0x5B 383 + #define RK806_OTP_VER 0x5C 384 + #define RK806_SYS_STS 0x5D 385 + #define RK806_SYS_CFG0 0x5E 386 + #define RK806_SYS_CFG1 0x5F 387 + #define RK806_SYS_OPTION 0x61 388 + #define RK806_SLEEP_CONFIG0 0x62 389 + #define RK806_SLEEP_CONFIG1 0x63 390 + #define RK806_SLEEP_CTR_SEL0 0x64 391 + #define RK806_SLEEP_CTR_SEL1 0x65 392 + #define RK806_SLEEP_CTR_SEL2 0x66 393 + #define RK806_SLEEP_CTR_SEL3 0x67 394 + #define RK806_SLEEP_CTR_SEL4 0x68 395 + #define RK806_SLEEP_CTR_SEL5 0x69 396 + #define RK806_DVS_CTRL_SEL0 0x6A 397 + #define RK806_DVS_CTRL_SEL1 0x6B 398 + #define RK806_DVS_CTRL_SEL2 0x6C 399 + #define RK806_DVS_CTRL_SEL3 0x6D 400 + #define RK806_DVS_CTRL_SEL4 0x6E 401 + #define RK806_DVS_CTRL_SEL5 0x6F 402 + #define RK806_DVS_START_CTRL 0x70 403 + #define RK806_SLEEP_GPIO 0x71 404 + #define RK806_SYS_CFG3 0x72 405 + #define RK806_ON_SOURCE 0x74 406 + #define RK806_OFF_SOURCE 0x75 407 + #define RK806_PWRON_KEY 0x76 408 + #define RK806_INT_STS0 0x77 409 + #define RK806_INT_MSK0 0x78 410 + #define RK806_INT_STS1 0x79 411 + #define RK806_INT_MSK1 0x7A 412 + #define RK806_GPIO_INT_CONFIG 0x7B 413 + #define RK806_DATA_REG0 0x7C 414 + #define RK806_DATA_REG1 0x7D 415 + #define RK806_DATA_REG2 0x7E 416 + #define RK806_DATA_REG3 0x7F 417 + #define RK806_DATA_REG4 0x80 418 + #define RK806_DATA_REG5 0x81 419 + #define RK806_DATA_REG6 0x82 420 + #define RK806_DATA_REG7 0x83 421 + #define RK806_DATA_REG8 0x84 422 + #define RK806_DATA_REG9 0x85 423 + #define RK806_DATA_REG10 0x86 424 + #define RK806_DATA_REG11 0x87 425 + #define RK806_DATA_REG12 0x88 426 + #define RK806_DATA_REG13 0x89 427 + #define RK806_DATA_REG14 0x8A 428 + #define RK806_DATA_REG15 0x8B 429 + #define RK806_TM_REG 0x8C 430 + #define RK806_OTP_EN_REG 0x8D 431 + #define RK806_FUNC_OTP_EN_REG 0x8E 432 + #define RK806_TEST_REG1 0x8F 433 + #define RK806_TEST_REG2 0x90 434 + #define RK806_TEST_REG3 0x91 435 + #define RK806_TEST_REG4 0x92 436 + #define RK806_TEST_REG5 0x93 437 + #define RK806_BUCK_VSEL_OTP_REG0 0x94 438 + #define RK806_BUCK_VSEL_OTP_REG1 0x95 439 + #define RK806_BUCK_VSEL_OTP_REG2 0x96 440 + #define RK806_BUCK_VSEL_OTP_REG3 0x97 441 + #define RK806_BUCK_VSEL_OTP_REG4 0x98 442 + #define RK806_BUCK_VSEL_OTP_REG5 0x99 443 + #define RK806_BUCK_VSEL_OTP_REG6 0x9A 444 + #define RK806_BUCK_VSEL_OTP_REG7 0x9B 445 + #define RK806_BUCK_VSEL_OTP_REG8 0x9C 446 + #define RK806_BUCK_VSEL_OTP_REG9 0x9D 447 + #define RK806_NLDO1_VSEL_OTP_REG0 0x9E 448 + #define RK806_NLDO1_VSEL_OTP_REG1 0x9F 449 + #define RK806_NLDO1_VSEL_OTP_REG2 0xA0 450 + #define RK806_NLDO1_VSEL_OTP_REG3 0xA1 451 + #define RK806_NLDO1_VSEL_OTP_REG4 0xA2 452 + #define RK806_PLDO_VSEL_OTP_REG0 0xA3 453 + #define RK806_PLDO_VSEL_OTP_REG1 0xA4 454 + #define RK806_PLDO_VSEL_OTP_REG2 0xA5 455 + #define RK806_PLDO_VSEL_OTP_REG3 0xA6 456 + #define RK806_PLDO_VSEL_OTP_REG4 0xA7 457 + #define RK806_PLDO_VSEL_OTP_REG5 0xA8 458 + #define RK806_BUCK_EN_OTP_REG1 0xA9 459 + #define RK806_NLDO_EN_OTP_REG1 0xAA 460 + #define RK806_PLDO_EN_OTP_REG1 0xAB 461 + #define RK806_BUCK_FB_RES_OTP_REG1 0xAC 462 + #define RK806_OTP_RESEV_REG0 0xAD 463 + #define RK806_OTP_RESEV_REG1 0xAE 464 + #define RK806_OTP_RESEV_REG2 0xAF 465 + #define RK806_OTP_RESEV_REG3 0xB0 466 + #define RK806_OTP_RESEV_REG4 0xB1 467 + #define RK806_BUCK_SEQ_REG0 0xB2 468 + #define RK806_BUCK_SEQ_REG1 0xB3 469 + #define RK806_BUCK_SEQ_REG2 0xB4 470 + #define RK806_BUCK_SEQ_REG3 0xB5 471 + #define RK806_BUCK_SEQ_REG4 0xB6 472 + #define RK806_BUCK_SEQ_REG5 0xB7 473 + #define RK806_BUCK_SEQ_REG6 0xB8 474 + #define RK806_BUCK_SEQ_REG7 0xB9 475 + #define RK806_BUCK_SEQ_REG8 0xBA 476 + #define RK806_BUCK_SEQ_REG9 0xBB 477 + #define RK806_BUCK_SEQ_REG10 0xBC 478 + #define RK806_BUCK_SEQ_REG11 0xBD 479 + #define RK806_BUCK_SEQ_REG12 0xBE 480 + #define RK806_BUCK_SEQ_REG13 0xBF 481 + #define RK806_BUCK_SEQ_REG14 0xC0 482 + #define RK806_BUCK_SEQ_REG15 0xC1 483 + #define RK806_BUCK_SEQ_REG16 0xC2 484 + #define RK806_BUCK_SEQ_REG17 0xC3 485 + #define RK806_HK_TRIM_REG1 0xC4 486 + #define RK806_HK_TRIM_REG2 0xC5 487 + #define RK806_BUCK_REF_TRIM_REG1 0xC6 488 + #define RK806_BUCK_REF_TRIM_REG2 0xC7 489 + #define RK806_BUCK_REF_TRIM_REG3 0xC8 490 + #define RK806_BUCK_REF_TRIM_REG4 0xC9 491 + #define RK806_BUCK_REF_TRIM_REG5 0xCA 492 + #define RK806_BUCK_OSC_TRIM_REG1 0xCB 493 + #define RK806_BUCK_OSC_TRIM_REG2 0xCC 494 + #define RK806_BUCK_OSC_TRIM_REG3 0xCD 495 + #define RK806_BUCK_OSC_TRIM_REG4 0xCE 496 + #define RK806_BUCK_OSC_TRIM_REG5 0xCF 497 + #define RK806_BUCK_TRIM_ZCDIOS_REG1 0xD0 498 + #define RK806_BUCK_TRIM_ZCDIOS_REG2 0xD1 499 + #define RK806_NLDO_TRIM_REG1 0xD2 500 + #define RK806_NLDO_TRIM_REG2 0xD3 501 + #define RK806_NLDO_TRIM_REG3 0xD4 502 + #define RK806_PLDO_TRIM_REG1 0xD5 503 + #define RK806_PLDO_TRIM_REG2 0xD6 504 + #define RK806_PLDO_TRIM_REG3 0xD7 505 + #define RK806_TRIM_ICOMP_REG1 0xD8 506 + #define RK806_TRIM_ICOMP_REG2 0xD9 507 + #define RK806_EFUSE_CONTROL_REGH 0xDA 508 + #define RK806_FUSE_PROG_REG 0xDB 509 + #define RK806_MAIN_FSM_STS_REG 0xDD 510 + #define RK806_FSM_REG 0xDE 511 + #define RK806_TOP_RESEV_OFFR 0xEC 512 + #define RK806_TOP_RESEV_POR 0xED 513 + #define RK806_BUCK_VRSN_REG1 0xEE 514 + #define RK806_BUCK_VRSN_REG2 0xEF 515 + #define RK806_NLDO_RLOAD_SEL_REG1 0xF0 516 + #define RK806_PLDO_RLOAD_SEL_REG1 0xF1 517 + #define RK806_PLDO_RLOAD_SEL_REG2 0xF2 518 + #define RK806_BUCK_CMIN_MX_REG1 0xF3 519 + #define RK806_BUCK_CMIN_MX_REG2 0xF4 520 + #define RK806_BUCK_FREQ_SET_REG1 0xF5 521 + #define RK806_BUCK_FREQ_SET_REG2 0xF6 522 + #define RK806_BUCK_RS_MEABS_REG1 0xF7 523 + #define RK806_BUCK_RS_MEABS_REG2 0xF8 524 + #define RK806_BUCK_RS_ZDLEB_REG1 0xF9 525 + #define RK806_BUCK_RS_ZDLEB_REG2 0xFA 526 + #define RK806_BUCK_RSERVE_REG1 0xFB 527 + #define RK806_BUCK_RSERVE_REG2 0xFC 528 + #define RK806_BUCK_RSERVE_REG3 0xFD 529 + #define RK806_BUCK_RSERVE_REG4 0xFE 530 + #define RK806_BUCK_RSERVE_REG5 0xFF 531 + 532 + /* INT_STS Register field definitions */ 533 + #define RK806_INT_STS_PWRON_FALL BIT(0) 534 + #define RK806_INT_STS_PWRON_RISE BIT(1) 535 + #define RK806_INT_STS_PWRON BIT(2) 536 + #define RK806_INT_STS_PWRON_LP BIT(3) 537 + #define RK806_INT_STS_HOTDIE BIT(4) 538 + #define RK806_INT_STS_VDC_RISE BIT(5) 539 + #define RK806_INT_STS_VDC_FALL BIT(6) 540 + #define RK806_INT_STS_VB_LO BIT(7) 541 + #define RK806_INT_STS_REV0 BIT(0) 542 + #define RK806_INT_STS_REV1 BIT(1) 543 + #define RK806_INT_STS_REV2 BIT(2) 544 + #define RK806_INT_STS_CRC_ERROR BIT(3) 545 + #define RK806_INT_STS_SLP3_GPIO BIT(4) 546 + #define RK806_INT_STS_SLP2_GPIO BIT(5) 547 + #define RK806_INT_STS_SLP1_GPIO BIT(6) 548 + #define RK806_INT_STS_WDT BIT(7) 549 + 550 + /* SPI command */ 551 + #define RK806_CMD_READ 0 552 + #define RK806_CMD_WRITE BIT(7) 553 + #define RK806_CMD_CRC_EN BIT(6) 554 + #define RK806_CMD_CRC_DIS 0 555 + #define RK806_CMD_LEN_MSK 0x0f 556 + #define RK806_REG_H 0x00 557 + 558 + #define VERSION_AB 0x01 559 + 560 + enum rk806_reg_id { 561 + RK806_ID_DCDC1 = 0, 562 + RK806_ID_DCDC2, 563 + RK806_ID_DCDC3, 564 + RK806_ID_DCDC4, 565 + RK806_ID_DCDC5, 566 + RK806_ID_DCDC6, 567 + RK806_ID_DCDC7, 568 + RK806_ID_DCDC8, 569 + RK806_ID_DCDC9, 570 + RK806_ID_DCDC10, 571 + 572 + RK806_ID_NLDO1, 573 + RK806_ID_NLDO2, 574 + RK806_ID_NLDO3, 575 + RK806_ID_NLDO4, 576 + RK806_ID_NLDO5, 577 + 578 + RK806_ID_PLDO1, 579 + RK806_ID_PLDO2, 580 + RK806_ID_PLDO3, 581 + RK806_ID_PLDO4, 582 + RK806_ID_PLDO5, 583 + RK806_ID_PLDO6, 584 + RK806_ID_END, 585 + }; 586 + 587 + /* Define the RK806 IRQ numbers */ 588 + enum rk806_irqs { 589 + /* INT_STS0 registers */ 590 + RK806_IRQ_PWRON_FALL, 591 + RK806_IRQ_PWRON_RISE, 592 + RK806_IRQ_PWRON, 593 + RK806_IRQ_PWRON_LP, 594 + RK806_IRQ_HOTDIE, 595 + RK806_IRQ_VDC_RISE, 596 + RK806_IRQ_VDC_FALL, 597 + RK806_IRQ_VB_LO, 598 + 599 + /* INT_STS0 registers */ 600 + RK806_IRQ_REV0, 601 + RK806_IRQ_REV1, 602 + RK806_IRQ_REV2, 603 + RK806_IRQ_CRC_ERROR, 604 + RK806_IRQ_SLP3_GPIO, 605 + RK806_IRQ_SLP2_GPIO, 606 + RK806_IRQ_SLP1_GPIO, 607 + RK806_IRQ_WDT, 608 + }; 609 + 610 + /* VCC1 Low Voltage Threshold */ 611 + enum rk806_lv_sel { 612 + VB_LO_SEL_2800, 613 + VB_LO_SEL_2900, 614 + VB_LO_SEL_3000, 615 + VB_LO_SEL_3100, 616 + VB_LO_SEL_3200, 617 + VB_LO_SEL_3300, 618 + VB_LO_SEL_3400, 619 + VB_LO_SEL_3500, 620 + }; 621 + 622 + /* System Shutdown Voltage Select */ 623 + enum rk806_uv_sel { 624 + VB_UV_SEL_2700, 625 + VB_UV_SEL_2800, 626 + VB_UV_SEL_2900, 627 + VB_UV_SEL_3000, 628 + VB_UV_SEL_3100, 629 + VB_UV_SEL_3200, 630 + VB_UV_SEL_3300, 631 + VB_UV_SEL_3400, 632 + }; 633 + 634 + /* Pin Function */ 635 + enum rk806_pwrctrl_fun { 636 + PWRCTRL_NULL_FUN, 637 + PWRCTRL_SLP_FUN, 638 + PWRCTRL_POWOFF_FUN, 639 + PWRCTRL_RST_FUN, 640 + PWRCTRL_DVS_FUN, 641 + PWRCTRL_GPIO_FUN, 642 + }; 643 + 644 + /* Pin Polarity */ 645 + enum rk806_pin_level { 646 + POL_LOW, 647 + POL_HIGH, 648 + }; 649 + 650 + enum rk806_vsel_ctr_sel { 651 + CTR_BY_NO_EFFECT, 652 + CTR_BY_PWRCTRL1, 653 + CTR_BY_PWRCTRL2, 654 + CTR_BY_PWRCTRL3, 655 + }; 656 + 657 + enum rk806_dvs_ctr_sel { 658 + CTR_SEL_NO_EFFECT, 659 + CTR_SEL_DVS_START1, 660 + CTR_SEL_DVS_START2, 661 + CTR_SEL_DVS_START3, 662 + }; 663 + 664 + enum rk806_pin_dr_sel { 665 + RK806_PIN_INPUT, 666 + RK806_PIN_OUTPUT, 667 + }; 668 + 669 + #define RK806_INT_POL_MSK BIT(1) 670 + #define RK806_INT_POL_H BIT(1) 671 + #define RK806_INT_POL_L 0 672 + 673 + #define RK806_SLAVE_RESTART_FUN_MSK BIT(1) 674 + #define RK806_SLAVE_RESTART_FUN_EN BIT(1) 675 + #define RK806_SLAVE_RESTART_FUN_OFF 0 676 + 677 + #define RK806_SYS_ENB2_2M_MSK BIT(1) 678 + #define RK806_SYS_ENB2_2M_EN BIT(1) 679 + #define RK806_SYS_ENB2_2M_OFF 0 680 + 681 + enum rk806_int_fun { 682 + RK806_INT_ONLY, 683 + RK806_INT_ADN_WKUP, 684 + }; 685 + 686 + enum rk806_dvs_mode { 687 + RK806_DVS_NOT_SUPPORT, 688 + RK806_DVS_START1, 689 + RK806_DVS_START2, 690 + RK806_DVS_START3, 691 + RK806_DVS_PWRCTRL1, 692 + RK806_DVS_PWRCTRL2, 693 + RK806_DVS_PWRCTRL3, 694 + RK806_DVS_START_PWRCTR1, 695 + RK806_DVS_START_PWRCTR2, 696 + RK806_DVS_START_PWRCTR3, 697 + RK806_DVS_END, 698 + }; 699 + 292 700 /* RK808 IRQ Definitions */ 293 701 #define RK808_IRQ_VOUT_LO 0 294 702 #define RK808_IRQ_VB_LO 1 ··· 1188 780 1189 781 enum { 1190 782 RK805_ID = 0x8050, 783 + RK806_ID = 0x8060, 1191 784 RK808_ID = 0x0000, 1192 785 RK809_ID = 0x8090, 1193 786 RK817_ID = 0x8170,

Configure Feed

Configure Feed