Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'arc-4.15-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc
Pull ARC fixes from Vineet Gupta:
- MCIP aka ARconnect fixes for SMP builds [Euginey]
- preventive fix for SLC (L2 cache) flushing [Euginey]
- Kconfig default fix [Ulf Magnusson]
- trailing semicolon fixes [Luis de Bethencourt]
- other assorted minor fixes
* tag 'arc-4.15-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
ARC: setup cpu possible mask according to possible-cpus dts property
ARC: mcip: update MCIP debug mask when the new cpu came online
ARC: mcip: halt GFRC counter when ARC cores halt
ARCv2: boot log: fix HS48 release number
arc: dts: use 'atmel' as manufacturer for at24 in axs10x_mb
ARC: Fix malformed ARC_EMUL_UNALIGNED default
ARC: boot log: Fix trailing semicolon
ARC: dw2 unwind: Fix trailing semicolon
ARC: Enable fatal signals on boot for dev platforms
ARCv2: Don't pretend we may set L-bit in STATUS32 with kflag instruction
ARCv2: cache: fix slc_entire_op: flush only instead of flush-n-inv
+130
-29
-1
arch/arc/Kconfig
-1
arch/arc/Kconfig
+1
-1
arch/arc/boot/dts/axs101.dts
+1
-1
arch/arc/boot/dts/axs101.dts
···
17
17
compatible = "snps,axs101", "snps,arc-sdp";
18
18
19
19
chosen {
20
-
bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=tty0 console=ttyS3,115200n8 consoleblank=0 video=1280x720@60";
20
+
bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=tty0 console=ttyS3,115200n8 consoleblank=0 video=1280x720@60 print-fatal-signals=1";
21
21
};
22
22
};
+2
-2
arch/arc/boot/dts/axs10x_mb.dtsi
+2
-2
arch/arc/boot/dts/axs10x_mb.dtsi
···
214
214
};
215
215
216
216
eeprom@0x54{
217
-
compatible = "24c01";
217
+
compatible = "atmel,24c01";
218
218
reg = <0x54>;
219
219
pagesize = <0x8>;
220
220
};
221
221
222
222
eeprom@0x57{
223
-
compatible = "24c04";
223
+
compatible = "atmel,24c04";
224
224
reg = <0x57>;
225
225
pagesize = <0x8>;
226
226
};
+1
-1
arch/arc/boot/dts/haps_hs_idu.dts
+1
-1
arch/arc/boot/dts/haps_hs_idu.dts
+1
-1
arch/arc/boot/dts/nsim_700.dts
+1
-1
arch/arc/boot/dts/nsim_700.dts
+1
-1
arch/arc/boot/dts/nsim_hs.dts
+1
-1
arch/arc/boot/dts/nsim_hs.dts
+1
-1
arch/arc/boot/dts/nsim_hs_idu.dts
+1
-1
arch/arc/boot/dts/nsim_hs_idu.dts
+1
-1
arch/arc/boot/dts/nsimosci.dts
+1
-1
arch/arc/boot/dts/nsimosci.dts
···
20
20
/* this is for console on PGU */
21
21
/* bootargs = "console=tty0 consoleblank=0"; */
22
22
/* this is for console on serial */
23
-
bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblank=0 debug video=640x480-24";
23
+
bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblank=0 debug video=640x480-24 print-fatal-signals=1";
24
24
};
25
25
26
26
aliases {
+1
-1
arch/arc/boot/dts/nsimosci_hs.dts
+1
-1
arch/arc/boot/dts/nsimosci_hs.dts
···
20
20
/* this is for console on PGU */
21
21
/* bootargs = "console=tty0 consoleblank=0"; */
22
22
/* this is for console on serial */
23
-
bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblank=0 debug video=640x480-24";
23
+
bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblank=0 debug video=640x480-24 print-fatal-signals=1";
24
24
};
25
25
26
26
aliases {
+1
-1
arch/arc/boot/dts/nsimosci_hs_idu.dts
+1
-1
arch/arc/boot/dts/nsimosci_hs_idu.dts
···
18
18
19
19
chosen {
20
20
/* this is for console on serial */
21
-
bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblan=0 debug video=640x480-24";
21
+
bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblan=0 debug video=640x480-24 print-fatal-signals=1";
22
22
};
23
23
24
24
aliases {
+1
-1
arch/arc/include/asm/entry-arcv2.h
+1
-1
arch/arc/include/asm/entry-arcv2.h
+69
-5
arch/arc/kernel/mcip.c
+69
-5
arch/arc/kernel/mcip.c
···
22
22
23
23
static char smp_cpuinfo_buf[128];
24
24
25
+
/*
26
+
* Set mask to halt GFRC if any online core in SMP cluster is halted.
27
+
* Only works for ARC HS v3.0+, on earlier versions has no effect.
28
+
*/
29
+
static void mcip_update_gfrc_halt_mask(int cpu)
30
+
{
31
+
struct bcr_generic gfrc;
32
+
unsigned long flags;
33
+
u32 gfrc_halt_mask;
34
+
35
+
READ_BCR(ARC_REG_GFRC_BUILD, gfrc);
36
+
37
+
/*
38
+
* CMD_GFRC_SET_CORE and CMD_GFRC_READ_CORE commands were added in
39
+
* GFRC 0x3 version.
40
+
*/
41
+
if (gfrc.ver < 0x3)
42
+
return;
43
+
44
+
raw_spin_lock_irqsave(&mcip_lock, flags);
45
+
46
+
__mcip_cmd(CMD_GFRC_READ_CORE, 0);
47
+
gfrc_halt_mask = read_aux_reg(ARC_REG_MCIP_READBACK);
48
+
gfrc_halt_mask |= BIT(cpu);
49
+
__mcip_cmd_data(CMD_GFRC_SET_CORE, 0, gfrc_halt_mask);
50
+
51
+
raw_spin_unlock_irqrestore(&mcip_lock, flags);
52
+
}
53
+
54
+
static void mcip_update_debug_halt_mask(int cpu)
55
+
{
56
+
u32 mcip_mask = 0;
57
+
unsigned long flags;
58
+
59
+
raw_spin_lock_irqsave(&mcip_lock, flags);
60
+
61
+
/*
62
+
* mcip_mask is same for CMD_DEBUG_SET_SELECT and CMD_DEBUG_SET_MASK
63
+
* commands. So read it once instead of reading both CMD_DEBUG_READ_MASK
64
+
* and CMD_DEBUG_READ_SELECT.
65
+
*/
66
+
__mcip_cmd(CMD_DEBUG_READ_SELECT, 0);
67
+
mcip_mask = read_aux_reg(ARC_REG_MCIP_READBACK);
68
+
69
+
mcip_mask |= BIT(cpu);
70
+
71
+
__mcip_cmd_data(CMD_DEBUG_SET_SELECT, 0, mcip_mask);
72
+
/*
73
+
* Parameter specified halt cause:
74
+
* STATUS32[H]/actionpoint/breakpoint/self-halt
75
+
* We choose all of them (0xF).
76
+
*/
77
+
__mcip_cmd_data(CMD_DEBUG_SET_MASK, 0xF, mcip_mask);
78
+
79
+
raw_spin_unlock_irqrestore(&mcip_lock, flags);
80
+
}
81
+
25
82
static void mcip_setup_per_cpu(int cpu)
26
83
{
84
+
struct mcip_bcr mp;
85
+
86
+
READ_BCR(ARC_REG_MCIP_BCR, mp);
87
+
27
88
smp_ipi_irq_setup(cpu, IPI_IRQ);
28
89
smp_ipi_irq_setup(cpu, SOFTIRQ_IRQ);
90
+
91
+
/* Update GFRC halt mask as new CPU came online */
92
+
if (mp.gfrc)
93
+
mcip_update_gfrc_halt_mask(cpu);
94
+
95
+
/* Update MCIP debug mask as new CPU came online */
96
+
if (mp.dbg)
97
+
mcip_update_debug_halt_mask(cpu);
29
98
}
30
99
31
100
static void mcip_ipi_send(int cpu)
···
170
101
IS_AVAIL1(mp.gfrc, "GFRC"));
171
102
172
103
cpuinfo_arc700[0].extn.gfrc = mp.gfrc;
173
-
174
-
if (mp.dbg) {
175
-
__mcip_cmd_data(CMD_DEBUG_SET_SELECT, 0, 0xf);
176
-
__mcip_cmd_data(CMD_DEBUG_SET_MASK, 0xf, 0xf);
177
-
}
178
104
}
179
105
180
106
struct plat_smp_ops plat_smp_ops = {
+1
-1
arch/arc/kernel/setup.c
+1
-1
arch/arc/kernel/setup.c
+40
-10
arch/arc/kernel/smp.c
+40
-10
arch/arc/kernel/smp.c
···
24
24
#include <linux/reboot.h>
25
25
#include <linux/irqdomain.h>
26
26
#include <linux/export.h>
27
+
#include <linux/of_fdt.h>
27
28
28
29
#include <asm/processor.h>
29
30
#include <asm/setup.h>
···
48
47
{
49
48
}
50
49
50
+
static int __init arc_get_cpu_map(const char *name, struct cpumask *cpumask)
51
+
{
52
+
unsigned long dt_root = of_get_flat_dt_root();
53
+
const char *buf;
54
+
55
+
buf = of_get_flat_dt_prop(dt_root, name, NULL);
56
+
if (!buf)
57
+
return -EINVAL;
58
+
59
+
if (cpulist_parse(buf, cpumask))
60
+
return -EINVAL;
61
+
62
+
return 0;
63
+
}
64
+
65
+
/*
66
+
* Read from DeviceTree and setup cpu possible mask. If there is no
67
+
* "possible-cpus" property in DeviceTree pretend all [0..NR_CPUS-1] exist.
68
+
*/
69
+
static void __init arc_init_cpu_possible(void)
70
+
{
71
+
struct cpumask cpumask;
72
+
73
+
if (arc_get_cpu_map("possible-cpus", &cpumask)) {
74
+
pr_warn("Failed to get possible-cpus from dtb, pretending all %u cpus exist\n",
75
+
NR_CPUS);
76
+
77
+
cpumask_setall(&cpumask);
78
+
}
79
+
80
+
if (!cpumask_test_cpu(0, &cpumask))
81
+
panic("Master cpu (cpu[0]) is missed in cpu possible mask!");
82
+
83
+
init_cpu_possible(&cpumask);
84
+
}
85
+
51
86
/*
52
87
* Called from setup_arch() before calling setup_processor()
53
88
*
···
95
58
*/
96
59
void __init smp_init_cpus(void)
97
60
{
98
-
unsigned int i;
99
-
100
-
for (i = 0; i < NR_CPUS; i++)
101
-
set_cpu_possible(i, true);
61
+
arc_init_cpu_possible();
102
62
103
63
if (plat_smp_ops.init_early_smp)
104
64
plat_smp_ops.init_early_smp();
···
104
70
/* called from init ( ) => process 1 */
105
71
void __init smp_prepare_cpus(unsigned int max_cpus)
106
72
{
107
-
int i;
108
-
109
73
/*
110
74
* if platform didn't set the present map already, do it now
111
75
* boot cpu is set to present already by init/main.c
112
76
*/
113
-
if (num_present_cpus() <= 1) {
114
-
for (i = 0; i < max_cpus; i++)
115
-
set_cpu_present(i, true);
116
-
}
77
+
if (num_present_cpus() <= 1)
78
+
init_cpu_present(cpu_possible_mask);
117
79
}
118
80
119
81
void __init smp_cpus_done(unsigned int max_cpus)
+4
-1
arch/arc/mm/cache.c
+4
-1
arch/arc/mm/cache.c
···
780
780
781
781
write_aux_reg(r, ctrl);
782
782
783
-
write_aux_reg(ARC_REG_SLC_INVALIDATE, 1);
783
+
if (op & OP_INV) /* Inv or flush-n-inv use same cmd reg */
784
+
write_aux_reg(ARC_REG_SLC_INVALIDATE, 0x1);
785
+
else
786
+
write_aux_reg(ARC_REG_SLC_FLUSH, 0x1);
784
787
785
788
/* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */
786
789
read_aux_reg(r);
+5
include/soc/arc/mcip.h
+5
include/soc/arc/mcip.h
···
15
15
16
16
#define ARC_REG_MCIP_BCR 0x0d0
17
17
#define ARC_REG_MCIP_IDU_BCR 0x0D5
18
+
#define ARC_REG_GFRC_BUILD 0x0D6
18
19
#define ARC_REG_MCIP_CMD 0x600
19
20
#define ARC_REG_MCIP_WDATA 0x601
20
21
#define ARC_REG_MCIP_READBACK 0x602
···
37
36
#define CMD_SEMA_RELEASE 0x12
38
37
39
38
#define CMD_DEBUG_SET_MASK 0x34
39
+
#define CMD_DEBUG_READ_MASK 0x35
40
40
#define CMD_DEBUG_SET_SELECT 0x36
41
+
#define CMD_DEBUG_READ_SELECT 0x37
41
42
42
43
#define CMD_GFRC_READ_LO 0x42
43
44
#define CMD_GFRC_READ_HI 0x43
45
+
#define CMD_GFRC_SET_CORE 0x47
46
+
#define CMD_GFRC_READ_CORE 0x48
44
47
45
48
#define CMD_IDU_ENABLE 0x71
46
49
#define CMD_IDU_DISABLE 0x72