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bitmap: introduce hardware-specific bitfield operations

Hardware of various vendors, but very notably Rockchip, often uses
32-bit registers where the upper 16-bit half of the register is a
write-enable mask for the lower half.

This type of hardware setup allows for more granular concurrent register
write access.

Over the years, many drivers have hand-rolled their own version of this
macro, usually without any checks, often called something like
HIWORD_UPDATE or FIELD_PREP_HIWORD, commonly with slightly different
semantics between them.

Clearly there is a demand for such a macro, and thus the demand should
be satisfied in a common header file. As this is a convention that spans
across multiple vendors, and similar conventions may also have
cross-vendor adoption, it's best if it lives in a vendor-agnostic header
file that can be expanded over time.

Add hw_bitfield.h with two macros: FIELD_PREP_WM16, and
FIELD_PREP_WM16_CONST. The latter is a version that can be used in
initializers, like FIELD_PREP_CONST.

Suggested-by: Yury Norov (NVIDIA) <yury.norov@gmail.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Acked-by: Jakub Kicinski <kuba@kernel.org>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Yury Norov (NVIDIA) <yury.norov@gmail.com>

authored by

Nicolas Frattaroli and committed by
Yury Norov 21368fcb a3fecb91

+63
+1
MAINTAINERS
··· 4275 4275 F: include/linux/cpumask.h 4276 4276 F: include/linux/cpumask_types.h 4277 4277 F: include/linux/find.h 4278 + F: include/linux/hw_bitfield.h 4278 4279 F: include/linux/nodemask.h 4279 4280 F: include/linux/nodemask_types.h 4280 4281 F: include/uapi/linux/bits.h
+62
include/linux/hw_bitfield.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 + /* 3 + * Copyright (C) 2025, Collabora Ltd. 4 + */ 5 + 6 + #ifndef _LINUX_HW_BITFIELD_H 7 + #define _LINUX_HW_BITFIELD_H 8 + 9 + #include <linux/bitfield.h> 10 + #include <linux/build_bug.h> 11 + #include <linux/limits.h> 12 + 13 + /** 14 + * FIELD_PREP_WM16() - prepare a bitfield element with a mask in the upper half 15 + * @_mask: shifted mask defining the field's length and position 16 + * @_val: value to put in the field 17 + * 18 + * FIELD_PREP_WM16() masks and shifts up the value, as well as bitwise ORs the 19 + * result with the mask shifted up by 16. 20 + * 21 + * This is useful for a common design of hardware registers where the upper 22 + * 16-bit half of a 32-bit register is used as a write-enable mask. In such a 23 + * register, a bit in the lower half is only updated if the corresponding bit 24 + * in the upper half is high. 25 + */ 26 + #define FIELD_PREP_WM16(_mask, _val) \ 27 + ({ \ 28 + typeof(_val) __val = _val; \ 29 + typeof(_mask) __mask = _mask; \ 30 + __BF_FIELD_CHECK(__mask, ((u16)0U), __val, \ 31 + "HWORD_UPDATE: "); \ 32 + (((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) | \ 33 + ((__mask) << 16); \ 34 + }) 35 + 36 + /** 37 + * FIELD_PREP_WM16_CONST() - prepare a constant bitfield element with a mask in 38 + * the upper half 39 + * @_mask: shifted mask defining the field's length and position 40 + * @_val: value to put in the field 41 + * 42 + * FIELD_PREP_WM16_CONST() masks and shifts up the value, as well as bitwise ORs 43 + * the result with the mask shifted up by 16. 44 + * 45 + * This is useful for a common design of hardware registers where the upper 46 + * 16-bit half of a 32-bit register is used as a write-enable mask. In such a 47 + * register, a bit in the lower half is only updated if the corresponding bit 48 + * in the upper half is high. 49 + * 50 + * Unlike FIELD_PREP_WM16(), this is a constant expression and can therefore 51 + * be used in initializers. Error checking is less comfortable for this 52 + * version. 53 + */ 54 + #define FIELD_PREP_WM16_CONST(_mask, _val) \ 55 + ( \ 56 + FIELD_PREP_CONST(_mask, _val) | \ 57 + (BUILD_BUG_ON_ZERO(const_true((u64)(_mask) > U16_MAX)) + \ 58 + ((_mask) << 16)) \ 59 + ) 60 + 61 + 62 + #endif /* _LINUX_HW_BITFIELD_H */