Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
dt-bindings: devfreq: rk3399_dmc: Convert to YAML
I want to add, deprecate, and bugfix some properties, as well as add the
first users. This is easier with a proper schema.
The transformation is mostly straightforward, plus a few notable tweaks:
* Renamed rockchip,dram_speed_bin to rockchip,ddr3_speed_bin. The
driver code and the example matched, but the description was
different. I went with the implementation. Note that this property is
also slated for deprecation/deletion in the subsequent patches.
* Drop upthreshold and downdifferential properties from the example.
These were undocumented (so, wouldn't pass validation), but were
representing software properties (governor tweaks). I drop them from
the driver in subsequent patches.
* Rename clock from pclk_ddr_mon to dmc_clk. The driver, DT example,
and all downstream users matched -- the binding definition was the
exception. Anyway, "dmc_clk" is a more appropriately generic name.
* Choose a better filename and location (this is a memory controller).
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
authored by
Brian Norris
and committed by
Chanwoo Choi
2142c27e
31231092
+306
-212
-212
Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
-212
Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
···
1
-
* Rockchip rk3399 DMC (Dynamic Memory Controller) device
2
-
3
-
Required properties:
4
-
- compatible: Must be "rockchip,rk3399-dmc".
5
-
- devfreq-events: Node to get DDR loading, Refer to
6
-
Documentation/devicetree/bindings/devfreq/event/
7
-
rockchip-dfi.txt
8
-
- clocks: Phandles for clock specified in "clock-names" property
9
-
- clock-names : The name of clock used by the DFI, must be
10
-
"pclk_ddr_mon";
11
-
- operating-points-v2: Refer to Documentation/devicetree/bindings/opp/opp-v2.yaml
12
-
for details.
13
-
- center-supply: DMC supply node.
14
-
- status: Marks the node enabled/disabled.
15
-
- rockchip,pmu: Phandle to the syscon managing the "PMU general register
16
-
files".
17
-
18
-
Optional properties:
19
-
- interrupts: The CPU interrupt number. The interrupt specifier
20
-
format depends on the interrupt controller.
21
-
It should be a DCF interrupt. When DDR DVFS finishes
22
-
a DCF interrupt is triggered.
23
-
- rockchip,pmu: Phandle to the syscon managing the "PMU general register
24
-
files".
25
-
26
-
Following properties relate to DDR timing:
27
-
28
-
- rockchip,dram_speed_bin : Value reference include/dt-bindings/clock/rk3399-ddr.h,
29
-
it selects the DDR3 cl-trp-trcd type. It must be
30
-
set according to "Speed Bin" in DDR3 datasheet,
31
-
DO NOT use a smaller "Speed Bin" than specified
32
-
for the DDR3 being used.
33
-
34
-
- rockchip,pd_idle : Configure the PD_IDLE value. Defines the
35
-
power-down idle period in which memories are
36
-
placed into power-down mode if bus is idle
37
-
for PD_IDLE DFI clock cycles.
38
-
39
-
- rockchip,sr_idle : Configure the SR_IDLE value. Defines the
40
-
self-refresh idle period in which memories are
41
-
placed into self-refresh mode if bus is idle
42
-
for SR_IDLE * 1024 DFI clock cycles (DFI
43
-
clocks freq is half of DRAM clock), default
44
-
value is "0".
45
-
46
-
- rockchip,sr_mc_gate_idle : Defines the memory self-refresh and controller
47
-
clock gating idle period. Memories are placed
48
-
into self-refresh mode and memory controller
49
-
clock arg gating started if bus is idle for
50
-
sr_mc_gate_idle*1024 DFI clock cycles.
51
-
52
-
- rockchip,srpd_lite_idle : Defines the self-refresh power down idle
53
-
period in which memories are placed into
54
-
self-refresh power down mode if bus is idle
55
-
for srpd_lite_idle * 1024 DFI clock cycles.
56
-
This parameter is for LPDDR4 only.
57
-
58
-
- rockchip,standby_idle : Defines the standby idle period in which
59
-
memories are placed into self-refresh mode.
60
-
The controller, pi, PHY and DRAM clock will
61
-
be gated if bus is idle for standby_idle * DFI
62
-
clock cycles.
63
-
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-
- rockchip,dram_dll_dis_freq : Defines the DDR3 DLL bypass frequency in MHz.
65
-
When DDR frequency is less than DRAM_DLL_DISB_FREQ,
66
-
DDR3 DLL will be bypassed. Note: if DLL was bypassed,
67
-
the odt will also stop working.
68
-
69
-
- rockchip,phy_dll_dis_freq : Defines the PHY dll bypass frequency in
70
-
MHz (Mega Hz). When DDR frequency is less than
71
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DRAM_DLL_DISB_FREQ, PHY DLL will be bypassed.
72
-
Note: PHY DLL and PHY ODT are independent.
73
-
74
-
- rockchip,ddr3_odt_dis_freq : When the DRAM type is DDR3, this parameter defines
75
-
the ODT disable frequency in MHz (Mega Hz).
76
-
when the DDR frequency is less then ddr3_odt_dis_freq,
77
-
the ODT on the DRAM side and controller side are
78
-
both disabled.
79
-
80
-
- rockchip,ddr3_drv : When the DRAM type is DDR3, this parameter defines
81
-
the DRAM side driver strength in ohms. Default
82
-
value is 40.
83
-
84
-
- rockchip,ddr3_odt : When the DRAM type is DDR3, this parameter defines
85
-
the DRAM side ODT strength in ohms. Default value
86
-
is 120.
87
-
88
-
- rockchip,phy_ddr3_ca_drv : When the DRAM type is DDR3, this parameter defines
89
-
the phy side CA line (incluing command line,
90
-
address line and clock line) driver strength.
91
-
Default value is 40.
92
-
93
-
- rockchip,phy_ddr3_dq_drv : When the DRAM type is DDR3, this parameter defines
94
-
the PHY side DQ line (including DQS/DQ/DM line)
95
-
driver strength. Default value is 40.
96
-
97
-
- rockchip,phy_ddr3_odt : When the DRAM type is DDR3, this parameter defines
98
-
the PHY side ODT strength. Default value is 240.
99
-
100
-
- rockchip,lpddr3_odt_dis_freq : When the DRAM type is LPDDR3, this parameter defines
101
-
then ODT disable frequency in MHz (Mega Hz).
102
-
When DDR frequency is less then ddr3_odt_dis_freq,
103
-
the ODT on the DRAM side and controller side are
104
-
both disabled.
105
-
106
-
- rockchip,lpddr3_drv : When the DRAM type is LPDDR3, this parameter defines
107
-
the DRAM side driver strength in ohms. Default
108
-
value is 34.
109
-
110
-
- rockchip,lpddr3_odt : When the DRAM type is LPDDR3, this parameter defines
111
-
the DRAM side ODT strength in ohms. Default value
112
-
is 240.
113
-
114
-
- rockchip,phy_lpddr3_ca_drv : When the DRAM type is LPDDR3, this parameter defines
115
-
the PHY side CA line (including command line,
116
-
address line and clock line) driver strength.
117
-
Default value is 40.
118
-
119
-
- rockchip,phy_lpddr3_dq_drv : When the DRAM type is LPDDR3, this parameter defines
120
-
the PHY side DQ line (including DQS/DQ/DM line)
121
-
driver strength. Default value is 40.
122
-
123
-
- rockchip,phy_lpddr3_odt : When dram type is LPDDR3, this parameter define
124
-
the phy side odt strength, default value is 240.
125
-
126
-
- rockchip,lpddr4_odt_dis_freq : When the DRAM type is LPDDR4, this parameter
127
-
defines the ODT disable frequency in
128
-
MHz (Mega Hz). When the DDR frequency is less then
129
-
ddr3_odt_dis_freq, the ODT on the DRAM side and
130
-
controller side are both disabled.
131
-
132
-
- rockchip,lpddr4_drv : When the DRAM type is LPDDR4, this parameter defines
133
-
the DRAM side driver strength in ohms. Default
134
-
value is 60.
135
-
136
-
- rockchip,lpddr4_dq_odt : When the DRAM type is LPDDR4, this parameter defines
137
-
the DRAM side ODT on DQS/DQ line strength in ohms.
138
-
Default value is 40.
139
-
140
-
- rockchip,lpddr4_ca_odt : When the DRAM type is LPDDR4, this parameter defines
141
-
the DRAM side ODT on CA line strength in ohms.
142
-
Default value is 40.
143
-
144
-
- rockchip,phy_lpddr4_ca_drv : When the DRAM type is LPDDR4, this parameter defines
145
-
the PHY side CA line (including command address
146
-
line) driver strength. Default value is 40.
147
-
148
-
- rockchip,phy_lpddr4_ck_cs_drv : When the DRAM type is LPDDR4, this parameter defines
149
-
the PHY side clock line and CS line driver
150
-
strength. Default value is 80.
151
-
152
-
- rockchip,phy_lpddr4_dq_drv : When the DRAM type is LPDDR4, this parameter defines
153
-
the PHY side DQ line (including DQS/DQ/DM line)
154
-
driver strength. Default value is 80.
155
-
156
-
- rockchip,phy_lpddr4_odt : When the DRAM type is LPDDR4, this parameter defines
157
-
the PHY side ODT strength. Default value is 60.
158
-
159
-
Example:
160
-
dmc_opp_table: dmc_opp_table {
161
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compatible = "operating-points-v2";
162
-
163
-
opp00 {
164
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opp-hz = /bits/ 64 <300000000>;
165
-
opp-microvolt = <900000>;
166
-
};
167
-
opp01 {
168
-
opp-hz = /bits/ 64 <666000000>;
169
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opp-microvolt = <900000>;
170
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};
171
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};
172
-
173
-
dmc: dmc {
174
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compatible = "rockchip,rk3399-dmc";
175
-
devfreq-events = <&dfi>;
176
-
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
177
-
clocks = <&cru SCLK_DDRC>;
178
-
clock-names = "dmc_clk";
179
-
operating-points-v2 = <&dmc_opp_table>;
180
-
center-supply = <&ppvar_centerlogic>;
181
-
upthreshold = <15>;
182
-
downdifferential = <10>;
183
-
rockchip,ddr3_speed_bin = <21>;
184
-
rockchip,pd_idle = <0x40>;
185
-
rockchip,sr_idle = <0x2>;
186
-
rockchip,sr_mc_gate_idle = <0x3>;
187
-
rockchip,srpd_lite_idle = <0x4>;
188
-
rockchip,standby_idle = <0x2000>;
189
-
rockchip,dram_dll_dis_freq = <300>;
190
-
rockchip,phy_dll_dis_freq = <125>;
191
-
rockchip,auto_pd_dis_freq = <666>;
192
-
rockchip,ddr3_odt_dis_freq = <333>;
193
-
rockchip,ddr3_drv = <40>;
194
-
rockchip,ddr3_odt = <120>;
195
-
rockchip,phy_ddr3_ca_drv = <40>;
196
-
rockchip,phy_ddr3_dq_drv = <40>;
197
-
rockchip,phy_ddr3_odt = <240>;
198
-
rockchip,lpddr3_odt_dis_freq = <333>;
199
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rockchip,lpddr3_drv = <34>;
200
-
rockchip,lpddr3_odt = <240>;
201
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rockchip,phy_lpddr3_ca_drv = <40>;
202
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rockchip,phy_lpddr3_dq_drv = <40>;
203
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rockchip,phy_lpddr3_odt = <240>;
204
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rockchip,lpddr4_odt_dis_freq = <333>;
205
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rockchip,lpddr4_drv = <60>;
206
-
rockchip,lpddr4_dq_odt = <40>;
207
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rockchip,lpddr4_ca_odt = <40>;
208
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rockchip,phy_lpddr4_ca_drv = <40>;
209
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rockchip,phy_lpddr4_ck_cs_drv = <80>;
210
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rockchip,phy_lpddr4_dq_drv = <80>;
211
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rockchip,phy_lpddr4_odt = <60>;
212
-
};
+306
Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-dmc.yaml
+306
Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-dmc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
# %YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Rockchip rk3399 DMC (Dynamic Memory Controller) device
8
+
9
+
maintainers:
10
+
- Brian Norris <briannorris@chromium.org>
11
+
12
+
properties:
13
+
compatible:
14
+
enum:
15
+
- rockchip,rk3399-dmc
16
+
17
+
devfreq-events:
18
+
$ref: /schemas/types.yaml#/definitions/phandle
19
+
description:
20
+
Node to get DDR loading. Refer to
21
+
Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt.
22
+
23
+
clocks:
24
+
maxItems: 1
25
+
26
+
clock-names:
27
+
items:
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+
- const: dmc_clk
29
+
30
+
operating-points-v2: true
31
+
32
+
center-supply:
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+
description:
34
+
DMC regulator supply.
35
+
36
+
rockchip,pmu:
37
+
$ref: /schemas/types.yaml#/definitions/phandle
38
+
description:
39
+
Phandle to the syscon managing the "PMU general register files".
40
+
41
+
interrupts:
42
+
maxItems: 1
43
+
description:
44
+
The CPU interrupt number. It should be a DCF interrupt. When DDR DVFS
45
+
finishes, a DCF interrupt is triggered.
46
+
47
+
rockchip,ddr3_speed_bin:
48
+
$ref: /schemas/types.yaml#/definitions/uint32
49
+
description:
50
+
For values, reference include/dt-bindings/clock/rk3399-ddr.h. Selects the
51
+
DDR3 cl-trp-trcd type. It must be set according to "Speed Bin" in DDR3
52
+
datasheet; DO NOT use a smaller "Speed Bin" than specified for the DDR3
53
+
being used.
54
+
55
+
rockchip,pd_idle:
56
+
$ref: /schemas/types.yaml#/definitions/uint32
57
+
description:
58
+
Configure the PD_IDLE value. Defines the power-down idle period in which
59
+
memories are placed into power-down mode if bus is idle for PD_IDLE DFI
60
+
clock cycles.
61
+
62
+
rockchip,sr_idle:
63
+
$ref: /schemas/types.yaml#/definitions/uint32
64
+
description:
65
+
Configure the SR_IDLE value. Defines the self-refresh idle period in
66
+
which memories are placed into self-refresh mode if bus is idle for
67
+
SR_IDLE * 1024 DFI clock cycles (DFI clocks freq is half of DRAM clock).
68
+
default: 0
69
+
70
+
rockchip,sr_mc_gate_idle:
71
+
$ref: /schemas/types.yaml#/definitions/uint32
72
+
description:
73
+
Defines the memory self-refresh and controller clock gating idle period.
74
+
Memories are placed into self-refresh mode and memory controller clock
75
+
arg gating started if bus is idle for sr_mc_gate_idle*1024 DFI clock
76
+
cycles.
77
+
78
+
rockchip,srpd_lite_idle:
79
+
$ref: /schemas/types.yaml#/definitions/uint32
80
+
description:
81
+
Defines the self-refresh power down idle period in which memories are
82
+
placed into self-refresh power down mode if bus is idle for
83
+
srpd_lite_idle * 1024 DFI clock cycles. This parameter is for LPDDR4
84
+
only.
85
+
86
+
rockchip,standby_idle:
87
+
$ref: /schemas/types.yaml#/definitions/uint32
88
+
description:
89
+
Defines the standby idle period in which memories are placed into
90
+
self-refresh mode. The controller, pi, PHY and DRAM clock will be gated
91
+
if bus is idle for standby_idle * DFI clock cycles.
92
+
93
+
rockchip,dram_dll_dis_freq:
94
+
$ref: /schemas/types.yaml#/definitions/uint32
95
+
description: |
96
+
Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less
97
+
than DRAM_DLL_DISB_FREQ, DDR3 DLL will be bypassed.
98
+
Note: if DLL was bypassed, the odt will also stop working.
99
+
100
+
rockchip,phy_dll_dis_freq:
101
+
$ref: /schemas/types.yaml#/definitions/uint32
102
+
description: |
103
+
Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR frequency
104
+
is less than DRAM_DLL_DISB_FREQ, PHY DLL will be bypassed.
105
+
Note: PHY DLL and PHY ODT are independent.
106
+
107
+
rockchip,auto_pd_dis_freq:
108
+
$ref: /schemas/types.yaml#/definitions/uint32
109
+
description:
110
+
Defines the auto PD disable frequency in MHz.
111
+
112
+
rockchip,ddr3_odt_dis_freq:
113
+
$ref: /schemas/types.yaml#/definitions/uint32
114
+
description:
115
+
When the DRAM type is DDR3, this parameter defines the ODT disable
116
+
frequency in MHz (Mega Hz). When the DDR frequency is less then
117
+
ddr3_odt_dis_freq, the ODT on the DRAM side and controller side are both
118
+
disabled.
119
+
120
+
rockchip,ddr3_drv:
121
+
$ref: /schemas/types.yaml#/definitions/uint32
122
+
description:
123
+
When the DRAM type is DDR3, this parameter defines the DRAM side drive
124
+
strength in ohms.
125
+
default: 40
126
+
127
+
rockchip,ddr3_odt:
128
+
$ref: /schemas/types.yaml#/definitions/uint32
129
+
description:
130
+
When the DRAM type is DDR3, this parameter defines the DRAM side ODT
131
+
strength in ohms.
132
+
default: 120
133
+
134
+
rockchip,phy_ddr3_ca_drv:
135
+
$ref: /schemas/types.yaml#/definitions/uint32
136
+
description:
137
+
When the DRAM type is DDR3, this parameter defines the phy side CA line
138
+
(incluing command line, address line and clock line) drive strength.
139
+
default: 40
140
+
141
+
rockchip,phy_ddr3_dq_drv:
142
+
$ref: /schemas/types.yaml#/definitions/uint32
143
+
description:
144
+
When the DRAM type is DDR3, this parameter defines the PHY side DQ line
145
+
(including DQS/DQ/DM line) drive strength.
146
+
default: 40
147
+
148
+
rockchip,phy_ddr3_odt:
149
+
$ref: /schemas/types.yaml#/definitions/uint32
150
+
description:
151
+
When the DRAM type is DDR3, this parameter defines the PHY side ODT
152
+
strength.
153
+
default: 240
154
+
155
+
rockchip,lpddr3_odt_dis_freq:
156
+
$ref: /schemas/types.yaml#/definitions/uint32
157
+
description:
158
+
When the DRAM type is LPDDR3, this parameter defines then ODT disable
159
+
frequency in MHz (Mega Hz). When DDR frequency is less then
160
+
ddr3_odt_dis_freq, the ODT on the DRAM side and controller side are both
161
+
disabled.
162
+
163
+
rockchip,lpddr3_drv:
164
+
$ref: /schemas/types.yaml#/definitions/uint32
165
+
description:
166
+
When the DRAM type is LPDDR3, this parameter defines the DRAM side drive
167
+
strength in ohms.
168
+
default: 34
169
+
170
+
rockchip,lpddr3_odt:
171
+
$ref: /schemas/types.yaml#/definitions/uint32
172
+
description:
173
+
When the DRAM type is LPDDR3, this parameter defines the DRAM side ODT
174
+
strength in ohms.
175
+
default: 240
176
+
177
+
rockchip,phy_lpddr3_ca_drv:
178
+
$ref: /schemas/types.yaml#/definitions/uint32
179
+
description:
180
+
When the DRAM type is LPDDR3, this parameter defines the PHY side CA line
181
+
(including command line, address line and clock line) drive strength.
182
+
default: 40
183
+
184
+
rockchip,phy_lpddr3_dq_drv:
185
+
$ref: /schemas/types.yaml#/definitions/uint32
186
+
description:
187
+
When the DRAM type is LPDDR3, this parameter defines the PHY side DQ line
188
+
(including DQS/DQ/DM line) drive strength.
189
+
default: 40
190
+
191
+
rockchip,phy_lpddr3_odt:
192
+
$ref: /schemas/types.yaml#/definitions/uint32
193
+
description:
194
+
When dram type is LPDDR3, this parameter define the phy side odt
195
+
strength, default value is 240.
196
+
197
+
rockchip,lpddr4_odt_dis_freq:
198
+
$ref: /schemas/types.yaml#/definitions/uint32
199
+
description:
200
+
When the DRAM type is LPDDR4, this parameter defines the ODT disable
201
+
frequency in MHz (Mega Hz). When the DDR frequency is less then
202
+
ddr3_odt_dis_freq, the ODT on the DRAM side and controller side are both
203
+
disabled.
204
+
205
+
rockchip,lpddr4_drv:
206
+
$ref: /schemas/types.yaml#/definitions/uint32
207
+
description:
208
+
When the DRAM type is LPDDR4, this parameter defines the DRAM side drive
209
+
strength in ohms.
210
+
default: 60
211
+
212
+
rockchip,lpddr4_dq_odt:
213
+
$ref: /schemas/types.yaml#/definitions/uint32
214
+
description:
215
+
When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on
216
+
DQS/DQ line strength in ohms.
217
+
default: 40
218
+
219
+
rockchip,lpddr4_ca_odt:
220
+
$ref: /schemas/types.yaml#/definitions/uint32
221
+
description:
222
+
When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on
223
+
CA line strength in ohms.
224
+
default: 40
225
+
226
+
rockchip,phy_lpddr4_ca_drv:
227
+
$ref: /schemas/types.yaml#/definitions/uint32
228
+
description:
229
+
When the DRAM type is LPDDR4, this parameter defines the PHY side CA line
230
+
(including command address line) drive strength.
231
+
default: 40
232
+
233
+
rockchip,phy_lpddr4_ck_cs_drv:
234
+
$ref: /schemas/types.yaml#/definitions/uint32
235
+
description:
236
+
When the DRAM type is LPDDR4, this parameter defines the PHY side clock
237
+
line and CS line drive strength.
238
+
default: 80
239
+
240
+
rockchip,phy_lpddr4_dq_drv:
241
+
$ref: /schemas/types.yaml#/definitions/uint32
242
+
description:
243
+
When the DRAM type is LPDDR4, this parameter defines the PHY side DQ line
244
+
(including DQS/DQ/DM line) drive strength.
245
+
default: 80
246
+
247
+
rockchip,phy_lpddr4_odt:
248
+
$ref: /schemas/types.yaml#/definitions/uint32
249
+
description:
250
+
When the DRAM type is LPDDR4, this parameter defines the PHY side ODT
251
+
strength.
252
+
default: 60
253
+
254
+
required:
255
+
- compatible
256
+
- devfreq-events
257
+
- clocks
258
+
- clock-names
259
+
- operating-points-v2
260
+
- center-supply
261
+
262
+
additionalProperties: false
263
+
264
+
examples:
265
+
- |
266
+
#include <dt-bindings/clock/rk3399-cru.h>
267
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
268
+
memory-controller {
269
+
compatible = "rockchip,rk3399-dmc";
270
+
devfreq-events = <&dfi>;
271
+
rockchip,pmu = <&pmu>;
272
+
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
273
+
clocks = <&cru SCLK_DDRC>;
274
+
clock-names = "dmc_clk";
275
+
operating-points-v2 = <&dmc_opp_table>;
276
+
center-supply = <&ppvar_centerlogic>;
277
+
rockchip,ddr3_speed_bin = <21>;
278
+
rockchip,pd_idle = <0x40>;
279
+
rockchip,sr_idle = <0x2>;
280
+
rockchip,sr_mc_gate_idle = <0x3>;
281
+
rockchip,srpd_lite_idle = <0x4>;
282
+
rockchip,standby_idle = <0x2000>;
283
+
rockchip,dram_dll_dis_freq = <300>;
284
+
rockchip,phy_dll_dis_freq = <125>;
285
+
rockchip,auto_pd_dis_freq = <666>;
286
+
rockchip,ddr3_odt_dis_freq = <333>;
287
+
rockchip,ddr3_drv = <40>;
288
+
rockchip,ddr3_odt = <120>;
289
+
rockchip,phy_ddr3_ca_drv = <40>;
290
+
rockchip,phy_ddr3_dq_drv = <40>;
291
+
rockchip,phy_ddr3_odt = <240>;
292
+
rockchip,lpddr3_odt_dis_freq = <333>;
293
+
rockchip,lpddr3_drv = <34>;
294
+
rockchip,lpddr3_odt = <240>;
295
+
rockchip,phy_lpddr3_ca_drv = <40>;
296
+
rockchip,phy_lpddr3_dq_drv = <40>;
297
+
rockchip,phy_lpddr3_odt = <240>;
298
+
rockchip,lpddr4_odt_dis_freq = <333>;
299
+
rockchip,lpddr4_drv = <60>;
300
+
rockchip,lpddr4_dq_odt = <40>;
301
+
rockchip,lpddr4_ca_odt = <40>;
302
+
rockchip,phy_lpddr4_ca_drv = <40>;
303
+
rockchip,phy_lpddr4_ck_cs_drv = <80>;
304
+
rockchip,phy_lpddr4_dq_drv = <80>;
305
+
rockchip,phy_lpddr4_odt = <60>;
306
+
};