Merge branch 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6

+1 -2

drivers/gpu/drm/radeon/evergreen.c

··· 2194 2194 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; 2195 2195 } 2196 2196 rdev->mc.visible_vram_size = rdev->mc.aper_size; 2197 - rdev->mc.active_vram_size = rdev->mc.visible_vram_size; 2198 2197 r700_vram_gtt_location(rdev, &rdev->mc); 2199 2198 radeon_update_bandwidth_info(rdev); 2200 2199 ··· 2933 2934 /* XXX: ontario has problems blitting to gart at the moment */ 2934 2935 if (rdev->family == CHIP_PALM) { 2935 2936 rdev->asic->copy = NULL; 2936 - rdev->mc.active_vram_size = rdev->mc.visible_vram_size; 2937 + radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 2937 2938 } 2938 2939 2939 2940 /* allocate wb buffer */

+2 -2

drivers/gpu/drm/radeon/evergreen_blit_kms.c

··· 623 623 dev_err(rdev->dev, "(%d) pin blit object failed\n", r); 624 624 return r; 625 625 } 626 - rdev->mc.active_vram_size = rdev->mc.real_vram_size; 626 + radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 627 627 return 0; 628 628 } 629 629 ··· 631 631 { 632 632 int r; 633 633 634 - rdev->mc.active_vram_size = rdev->mc.visible_vram_size; 634 + radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 635 635 if (rdev->r600_blit.shader_obj == NULL) 636 636 return; 637 637 /* If we can't reserve the bo, unref should be enough to destroy

+2 -3

drivers/gpu/drm/radeon/r100.c

··· 1024 1024 return r; 1025 1025 } 1026 1026 rdev->cp.ready = true; 1027 - rdev->mc.active_vram_size = rdev->mc.real_vram_size; 1027 + radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 1028 1028 return 0; 1029 1029 } 1030 1030 ··· 1042 1042 void r100_cp_disable(struct radeon_device *rdev) 1043 1043 { 1044 1044 /* Disable ring */ 1045 - rdev->mc.active_vram_size = rdev->mc.visible_vram_size; 1045 + radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 1046 1046 rdev->cp.ready = false; 1047 1047 WREG32(RADEON_CP_CSQ_MODE, 0); 1048 1048 WREG32(RADEON_CP_CSQ_CNTL, 0); ··· 2312 2312 /* FIXME we don't use the second aperture yet when we could use it */ 2313 2313 if (rdev->mc.visible_vram_size > rdev->mc.aper_size) 2314 2314 rdev->mc.visible_vram_size = rdev->mc.aper_size; 2315 - rdev->mc.active_vram_size = rdev->mc.visible_vram_size; 2316 2315 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 2317 2316 if (rdev->flags & RADEON_IS_IGP) { 2318 2317 uint32_t tom;

+1 -2

drivers/gpu/drm/radeon/r600.c

··· 1255 1255 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 1256 1256 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 1257 1257 rdev->mc.visible_vram_size = rdev->mc.aper_size; 1258 - rdev->mc.active_vram_size = rdev->mc.visible_vram_size; 1259 1258 r600_vram_gtt_location(rdev, &rdev->mc); 1260 1259 1261 1260 if (rdev->flags & RADEON_IS_IGP) { ··· 1936 1937 */ 1937 1938 void r600_cp_stop(struct radeon_device *rdev) 1938 1939 { 1939 - rdev->mc.active_vram_size = rdev->mc.visible_vram_size; 1940 + radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 1940 1941 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 1941 1942 WREG32(SCRATCH_UMSK, 0); 1942 1943 }

+2 -2

drivers/gpu/drm/radeon/r600_blit_kms.c

··· 558 558 dev_err(rdev->dev, "(%d) pin blit object failed\n", r); 559 559 return r; 560 560 } 561 - rdev->mc.active_vram_size = rdev->mc.real_vram_size; 561 + radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 562 562 return 0; 563 563 } 564 564 ··· 566 566 { 567 567 int r; 568 568 569 - rdev->mc.active_vram_size = rdev->mc.visible_vram_size; 569 + radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 570 570 if (rdev->r600_blit.shader_obj == NULL) 571 571 return; 572 572 /* If we can't reserve the bo, unref should be enough to destroy

+1 -1

drivers/gpu/drm/radeon/radeon.h

··· 345 345 * about vram size near mc fb location */ 346 346 u64 mc_vram_size; 347 347 u64 visible_vram_size; 348 - u64 active_vram_size; 349 348 u64 gtt_size; 350 349 u64 gtt_start; 351 350 u64 gtt_end; ··· 1447 1448 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 1448 1449 extern int radeon_resume_kms(struct drm_device *dev); 1449 1450 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); 1451 + extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 1450 1452 1451 1453 /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */ 1452 1454 extern bool r600_card_posted(struct radeon_device *rdev);

+4 -1

drivers/gpu/drm/radeon/radeon_gem.c

··· 156 156 { 157 157 struct radeon_device *rdev = dev->dev_private; 158 158 struct drm_radeon_gem_info *args = data; 159 + struct ttm_mem_type_manager *man; 160 + 161 + man = &rdev->mman.bdev.man[TTM_PL_VRAM]; 159 162 160 163 args->vram_size = rdev->mc.real_vram_size; 161 - args->vram_visible = rdev->mc.real_vram_size; 164 + args->vram_visible = (u64)man->size << PAGE_SHIFT; 162 165 if (rdev->stollen_vga_memory) 163 166 args->vram_visible -= radeon_bo_size(rdev->stollen_vga_memory); 164 167 args->vram_visible -= radeon_fbdev_total_size(rdev);

+14

drivers/gpu/drm/radeon/radeon_ttm.c

··· 589 589 DRM_INFO("radeon: ttm finalized\n"); 590 590 } 591 591 592 + /* this should only be called at bootup or when userspace 593 + * isn't running */ 594 + void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size) 595 + { 596 + struct ttm_mem_type_manager *man; 597 + 598 + if (!rdev->mman.initialized) 599 + return; 600 + 601 + man = &rdev->mman.bdev.man[TTM_PL_VRAM]; 602 + /* this just adjusts TTM size idea, which sets lpfn to the correct value */ 603 + man->size = size >> PAGE_SHIFT; 604 + } 605 + 592 606 static struct vm_operations_struct radeon_ttm_vm_ops; 593 607 static const struct vm_operations_struct *ttm_vm_ops = NULL; 594 608

-1

drivers/gpu/drm/radeon/rs600.c

··· 751 751 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 752 752 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 753 753 rdev->mc.visible_vram_size = rdev->mc.aper_size; 754 - rdev->mc.active_vram_size = rdev->mc.visible_vram_size; 755 754 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 756 755 base = RREG32_MC(R_000004_MC_FB_LOCATION); 757 756 base = G_000004_MC_FB_START(base) << 16;

-1

drivers/gpu/drm/radeon/rs690.c

··· 157 157 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 158 158 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 159 159 rdev->mc.visible_vram_size = rdev->mc.aper_size; 160 - rdev->mc.active_vram_size = rdev->mc.visible_vram_size; 161 160 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION); 162 161 base = G_000100_MC_FB_START(base) << 16; 163 162 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);

+1 -2

drivers/gpu/drm/radeon/rv770.c

··· 307 307 */ 308 308 void r700_cp_stop(struct radeon_device *rdev) 309 309 { 310 - rdev->mc.active_vram_size = rdev->mc.visible_vram_size; 310 + radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 311 311 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); 312 312 WREG32(SCRATCH_UMSK, 0); 313 313 } ··· 1123 1123 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 1124 1124 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 1125 1125 rdev->mc.visible_vram_size = rdev->mc.aper_size; 1126 - rdev->mc.active_vram_size = rdev->mc.visible_vram_size; 1127 1126 r700_vram_gtt_location(rdev, &rdev->mc); 1128 1127 radeon_update_bandwidth_info(rdev); 1129 1128

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