Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Pull arm64 fixes from Catalin Marinas:
- Errata workarounds for Cortex-A510: broken hardware dirty bit
management, detection code for the TRBE (tracing) bugs with the
actual fixes going in via the CoreSight tree.
- Cortex-X2 errata handling for TRBE (inheriting the workarounds from
Cortex-A710).
- Fix ex_handler_load_unaligned_zeropad() to use the correct struct
members.
- A couple of kselftest fixes for FPSIMD.
- Silence the vdso "no previous prototype" warning.
- Mark start_backtrace() notrace and NOKPROBE_SYMBOL.
* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
arm64: cpufeature: List early Cortex-A510 parts as having broken dbm
kselftest/arm64: Correct logging of FPSIMD register read via ptrace
kselftest/arm64: Skip VL_INHERIT tests for unsupported vector types
arm64: errata: Add detection for TRBE trace data corruption
arm64: errata: Add detection for TRBE invalid prohibited states
arm64: errata: Add detection for TRBE ignored system register writes
arm64: Add Cortex-A510 CPU part definition
arm64: extable: fix load_unaligned_zeropad() reg indices
arm64: Mark start_backtrace() notrace and NOKPROBE_SYMBOL
arm64: errata: Update ARM64_ERRATUM_[2119858|2224489] with Cortex-X2 ranges
arm64: Add Cortex-X2 CPU part definition
arm64: vdso: Fix "no previous prototype" warning
+144
-13
+12
Documentation/arm64/silicon-errata.rst
+12
Documentation/arm64/silicon-errata.rst
···
52
52
| Allwinner | A64/R18 | UNKNOWN1 | SUN50I_ERRATUM_UNKNOWN1 |
53
53
+----------------+-----------------+-----------------+-----------------------------+
54
54
+----------------+-----------------+-----------------+-----------------------------+
55
+
| ARM | Cortex-A510 | #2064142 | ARM64_ERRATUM_2064142 |
56
+
+----------------+-----------------+-----------------+-----------------------------+
57
+
| ARM | Cortex-A510 | #2038923 | ARM64_ERRATUM_2038923 |
58
+
+----------------+-----------------+-----------------+-----------------------------+
59
+
| ARM | Cortex-A510 | #1902691 | ARM64_ERRATUM_1902691 |
60
+
+----------------+-----------------+-----------------+-----------------------------+
55
61
| ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
56
62
+----------------+-----------------+-----------------+-----------------------------+
57
63
| ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
···
98
92
+----------------+-----------------+-----------------+-----------------------------+
99
93
| ARM | Cortex-A77 | #1508412 | ARM64_ERRATUM_1508412 |
100
94
+----------------+-----------------+-----------------+-----------------------------+
95
+
| ARM | Cortex-A510 | #2051678 | ARM64_ERRATUM_2051678 |
96
+
+----------------+-----------------+-----------------+-----------------------------+
101
97
| ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 |
102
98
+----------------+-----------------+-----------------+-----------------------------+
103
99
| ARM | Cortex-A710 | #2054223 | ARM64_ERRATUM_2054223 |
104
100
+----------------+-----------------+-----------------+-----------------------------+
105
101
| ARM | Cortex-A710 | #2224489 | ARM64_ERRATUM_2224489 |
102
+
+----------------+-----------------+-----------------+-----------------------------+
103
+
| ARM | Cortex-X2 | #2119858 | ARM64_ERRATUM_2119858 |
104
+
+----------------+-----------------+-----------------+-----------------------------+
105
+
| ARM | Cortex-X2 | #2224489 | ARM64_ERRATUM_2224489 |
106
106
+----------------+-----------------+-----------------+-----------------------------+
107
107
| ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 |
108
108
+----------------+-----------------+-----------------+-----------------------------+
+75
-6
arch/arm64/Kconfig
+75
-6
arch/arm64/Kconfig
···
670
670
config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
671
671
bool
672
672
673
+
config ARM64_ERRATUM_2051678
674
+
bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
675
+
help
676
+
This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
677
+
Affected Coretex-A510 might not respect the ordering rules for
678
+
hardware update of the page table's dirty bit. The workaround
679
+
is to not enable the feature on affected CPUs.
680
+
681
+
If unsure, say Y.
682
+
673
683
config ARM64_ERRATUM_2119858
674
-
bool "Cortex-A710: 2119858: workaround TRBE overwriting trace data in FILL mode"
684
+
bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
675
685
default y
676
686
depends on CORESIGHT_TRBE
677
687
select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
678
688
help
679
-
This option adds the workaround for ARM Cortex-A710 erratum 2119858.
689
+
This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
680
690
681
-
Affected Cortex-A710 cores could overwrite up to 3 cache lines of trace
691
+
Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
682
692
data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
683
693
the event of a WRAP event.
684
694
···
771
761
If unsure, say Y.
772
762
773
763
config ARM64_ERRATUM_2224489
774
-
bool "Cortex-A710: 2224489: workaround TRBE writing to address out-of-range"
764
+
bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
775
765
depends on CORESIGHT_TRBE
776
766
default y
777
767
select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
778
768
help
779
-
This option adds the workaround for ARM Cortex-A710 erratum 2224489.
769
+
This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
780
770
781
-
Affected Cortex-A710 cores might write to an out-of-range address, not reserved
771
+
Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
782
772
for TRBE. Under some conditions, the TRBE might generate a write to the next
783
773
virtually addressed page following the last page of the TRBE address space
784
774
(i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
785
775
786
776
Work around this in the driver by always making sure that there is a
787
777
page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
778
+
779
+
If unsure, say Y.
780
+
781
+
config ARM64_ERRATUM_2064142
782
+
bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
783
+
depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in
784
+
default y
785
+
help
786
+
This option adds the workaround for ARM Cortex-A510 erratum 2064142.
787
+
788
+
Affected Cortex-A510 core might fail to write into system registers after the
789
+
TRBE has been disabled. Under some conditions after the TRBE has been disabled
790
+
writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1,
791
+
and TRBTRG_EL1 will be ignored and will not be effected.
792
+
793
+
Work around this in the driver by executing TSB CSYNC and DSB after collection
794
+
is stopped and before performing a system register write to one of the affected
795
+
registers.
796
+
797
+
If unsure, say Y.
798
+
799
+
config ARM64_ERRATUM_2038923
800
+
bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
801
+
depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in
802
+
default y
803
+
help
804
+
This option adds the workaround for ARM Cortex-A510 erratum 2038923.
805
+
806
+
Affected Cortex-A510 core might cause an inconsistent view on whether trace is
807
+
prohibited within the CPU. As a result, the trace buffer or trace buffer state
808
+
might be corrupted. This happens after TRBE buffer has been enabled by setting
809
+
TRBLIMITR_EL1.E, followed by just a single context synchronization event before
810
+
execution changes from a context, in which trace is prohibited to one where it
811
+
isn't, or vice versa. In these mentioned conditions, the view of whether trace
812
+
is prohibited is inconsistent between parts of the CPU, and the trace buffer or
813
+
the trace buffer state might be corrupted.
814
+
815
+
Work around this in the driver by preventing an inconsistent view of whether the
816
+
trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a
817
+
change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or
818
+
two ISB instructions if no ERET is to take place.
819
+
820
+
If unsure, say Y.
821
+
822
+
config ARM64_ERRATUM_1902691
823
+
bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
824
+
depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in
825
+
default y
826
+
help
827
+
This option adds the workaround for ARM Cortex-A510 erratum 1902691.
828
+
829
+
Affected Cortex-A510 core might cause trace data corruption, when being written
830
+
into the memory. Effectively TRBE is broken and hence cannot be used to capture
831
+
trace data.
832
+
833
+
Work around this problem in the driver by just preventing TRBE initialization on
834
+
affected cpus. The firmware must have disabled the access to TRBE for the kernel
835
+
on such implementations. This will cover the kernel for any firmware that doesn't
836
+
do this already.
788
837
789
838
If unsure, say Y.
790
839
+4
arch/arm64/include/asm/cputype.h
+4
arch/arm64/include/asm/cputype.h
···
73
73
#define ARM_CPU_PART_CORTEX_A76 0xD0B
74
74
#define ARM_CPU_PART_NEOVERSE_N1 0xD0C
75
75
#define ARM_CPU_PART_CORTEX_A77 0xD0D
76
+
#define ARM_CPU_PART_CORTEX_A510 0xD46
76
77
#define ARM_CPU_PART_CORTEX_A710 0xD47
78
+
#define ARM_CPU_PART_CORTEX_X2 0xD48
77
79
#define ARM_CPU_PART_NEOVERSE_N2 0xD49
78
80
79
81
#define APM_CPU_PART_POTENZA 0x000
···
117
115
#define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76)
118
116
#define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1)
119
117
#define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77)
118
+
#define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510)
120
119
#define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710)
120
+
#define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)
121
121
#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)
122
122
#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
123
123
#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
+29
arch/arm64/kernel/cpu_errata.c
+29
arch/arm64/kernel/cpu_errata.c
···
347
347
#endif
348
348
#ifdef CONFIG_ARM64_ERRATUM_2119858
349
349
MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
350
+
MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0),
350
351
#endif
351
352
{},
352
353
};
···
372
371
#endif
373
372
#ifdef CONFIG_ARM64_ERRATUM_2224489
374
373
MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
374
+
MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0),
375
375
#endif
376
376
{},
377
377
};
···
598
596
.capability = ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE,
599
597
.type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
600
598
CAP_MIDR_RANGE_LIST(trbe_write_out_of_range_cpus),
599
+
},
600
+
#endif
601
+
#ifdef CONFIG_ARM64_ERRATUM_2064142
602
+
{
603
+
.desc = "ARM erratum 2064142",
604
+
.capability = ARM64_WORKAROUND_2064142,
605
+
606
+
/* Cortex-A510 r0p0 - r0p2 */
607
+
ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2)
608
+
},
609
+
#endif
610
+
#ifdef CONFIG_ARM64_ERRATUM_2038923
611
+
{
612
+
.desc = "ARM erratum 2038923",
613
+
.capability = ARM64_WORKAROUND_2038923,
614
+
615
+
/* Cortex-A510 r0p0 - r0p2 */
616
+
ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2)
617
+
},
618
+
#endif
619
+
#ifdef CONFIG_ARM64_ERRATUM_1902691
620
+
{
621
+
.desc = "ARM erratum 1902691",
622
+
.capability = ARM64_WORKAROUND_1902691,
623
+
624
+
/* Cortex-A510 r0p0 - r0p1 */
625
+
ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 1)
601
626
},
602
627
#endif
603
628
{
+3
arch/arm64/kernel/cpufeature.c
+3
arch/arm64/kernel/cpufeature.c
+3
-2
arch/arm64/kernel/stacktrace.c
+3
-2
arch/arm64/kernel/stacktrace.c
···
33
33
*/
34
34
35
35
36
-
static void start_backtrace(struct stackframe *frame, unsigned long fp,
37
-
unsigned long pc)
36
+
static notrace void start_backtrace(struct stackframe *frame, unsigned long fp,
37
+
unsigned long pc)
38
38
{
39
39
frame->fp = fp;
40
40
frame->pc = pc;
···
55
55
frame->prev_fp = 0;
56
56
frame->prev_type = STACK_TYPE_UNKNOWN;
57
57
}
58
+
NOKPROBE_SYMBOL(start_backtrace);
58
59
59
60
/*
60
61
* Unwind from one frame record (A) to the next frame record (B).
+4
-1
arch/arm64/kernel/vdso/Makefile
+4
-1
arch/arm64/kernel/vdso/Makefile
···
29
29
ccflags-y := -fno-common -fno-builtin -fno-stack-protector -ffixed-x18
30
30
ccflags-y += -DDISABLE_BRANCH_PROFILING -DBUILD_VDSO
31
31
32
+
# -Wmissing-prototypes and -Wmissing-declarations are removed from
33
+
# the CFLAGS of vgettimeofday.c to make possible to build the
34
+
# kernel with CONFIG_WERROR enabled.
32
35
CFLAGS_REMOVE_vgettimeofday.o = $(CC_FLAGS_FTRACE) -Os $(CC_FLAGS_SCS) $(GCC_PLUGINS_CFLAGS) \
33
-
$(CC_FLAGS_LTO)
36
+
$(CC_FLAGS_LTO) -Wmissing-prototypes -Wmissing-declarations
34
37
KASAN_SANITIZE := n
35
38
KCSAN_SANITIZE := n
36
39
UBSAN_SANITIZE := n
+2
-2
arch/arm64/mm/extable.c
+2
-2
arch/arm64/mm/extable.c
···
40
40
ex_handler_load_unaligned_zeropad(const struct exception_table_entry *ex,
41
41
struct pt_regs *regs)
42
42
{
43
-
int reg_data = FIELD_GET(EX_DATA_REG_DATA, ex->type);
44
-
int reg_addr = FIELD_GET(EX_DATA_REG_ADDR, ex->type);
43
+
int reg_data = FIELD_GET(EX_DATA_REG_DATA, ex->data);
44
+
int reg_addr = FIELD_GET(EX_DATA_REG_ADDR, ex->data);
45
45
unsigned long data, addr, offset;
46
46
47
47
addr = pt_regs_read_reg(regs, reg_addr);
+3
arch/arm64/tools/cpucaps
+3
arch/arm64/tools/cpucaps
+9
-2
tools/testing/selftests/arm64/fp/sve-ptrace.c
+9
-2
tools/testing/selftests/arm64/fp/sve-ptrace.c
···
261
261
}
262
262
263
263
ksft_test_result((sve->flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_FPSIMD,
264
-
"Set FPSIMD registers via %s\n", type->name);
264
+
"Got FPSIMD registers via %s\n", type->name);
265
265
if ((sve->flags & SVE_PT_REGS_MASK) != SVE_PT_REGS_FPSIMD)
266
266
goto out;
267
267
···
557
557
}
558
558
559
559
/* prctl() flags */
560
-
ptrace_set_get_inherit(child, &vec_types[i]);
560
+
if (getauxval(vec_types[i].hwcap_type) & vec_types[i].hwcap) {
561
+
ptrace_set_get_inherit(child, &vec_types[i]);
562
+
} else {
563
+
ksft_test_result_skip("%s SVE_PT_VL_INHERIT set\n",
564
+
vec_types[i].name);
565
+
ksft_test_result_skip("%s SVE_PT_VL_INHERIT cleared\n",
566
+
vec_types[i].name);
567
+
}
561
568
562
569
/* Step through every possible VQ */
563
570
for (vq = SVE_VQ_MIN; vq <= SVE_VQ_MAX; vq++) {