+3 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c

reviewed

··· 1186 1186 if (!dev_info) 1187 1187 ret = amdgpu_acpi_dev_init(&dev_info, xcc_info, sbdf); 1188 1188 1189 1189 - if (ret == -ENOMEM) 1189 1189 + if (ret == -ENOMEM) { 1190 1190 + kfree(xcc_info); 1190 1191 return ret; 1192 1192 + } 1191 1193 1192 1194 if (!dev_info) { 1193 1195 kfree(xcc_info);

+3 -5

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

reviewed

··· 317 317 void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev) 318 318 { 319 319 if (amdgpu_device_should_recover_gpu(adev)) 320 320 - amdgpu_reset_domain_schedule(adev->reset_domain, 321 321 - &adev->kfd.reset_work); 320 320 + (void)amdgpu_reset_domain_schedule(adev->reset_domain, &adev->kfd.reset_work); 322 321 } 323 322 324 323 int amdgpu_amdkfd_alloc_kernel_mem(struct amdgpu_device *adev, size_t size, ··· 719 720 if (gfx_block != NULL) 720 721 gfx_block->version->funcs->set_powergating_state((void *)gfx_block, state); 721 722 } 722 722 - amdgpu_dpm_switch_power_profile(adev, 723 723 - PP_SMC_POWER_PROFILE_COMPUTE, 724 724 - !idle); 723 723 + (void)amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_COMPUTE, !idle); 724 724 + 725 725 } 726 726 727 727 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)

+9 -9

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

reviewed

··· 1924 1924 1925 1925 /* Make sure restore workers don't access the BO any more */ 1926 1926 mutex_lock(&process_info->lock); 1927 1927 - list_del(&mem->validate_list); 1927 1927 + if (!list_empty(&mem->validate_list)) 1928 1928 + list_del_init(&mem->validate_list); 1928 1929 mutex_unlock(&process_info->lock); 1929 1929 - 1930 1930 - /* Cleanup user pages and MMU notifiers */ 1931 1931 - if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) { 1932 1932 - amdgpu_hmm_unregister(mem->bo); 1933 1933 - mutex_lock(&process_info->notifier_lock); 1934 1934 - amdgpu_hmm_range_free(mem->range); 1935 1935 - mutex_unlock(&process_info->notifier_lock); 1936 1936 - } 1937 1930 1938 1931 ret = reserve_bo_and_cond_vms(mem, NULL, BO_VM_ALL, &ctx); 1939 1932 if (unlikely(ret)) 1940 1933 return ret; 1934 1934 + 1935 1935 + /* Cleanup user pages and MMU notifiers */ 1936 1936 + if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) { 1937 1937 + amdgpu_hmm_unregister(mem->bo); 1938 1938 + amdgpu_hmm_range_free(mem->range); 1939 1939 + mem->range = NULL; 1940 1940 + } 1941 1941 1942 1942 amdgpu_amdkfd_remove_eviction_fence(mem->bo, 1943 1943 process_info->eviction_fence);

+4 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

reviewed

··· 892 892 struct amdgpu_bo *bo = e->bo; 893 893 894 894 e->range = amdgpu_hmm_range_alloc(NULL); 895 895 - if (unlikely(!e->range)) 896 896 - return -ENOMEM; 895 895 + if (unlikely(!e->range)) { 896 896 + r = -ENOMEM; 897 897 + goto out_free_user_pages; 898 898 + } 897 899 898 900 r = amdgpu_ttm_tt_get_user_pages(bo, e->range); 899 901 if (r)

+11 -5

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

reviewed

··· 3504 3504 } 3505 3505 } 3506 3506 3507 3507 - amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); 3508 3508 - amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); 3509 3509 - 3510 3507 amdgpu_amdkfd_suspend(adev, true); 3511 3508 amdgpu_amdkfd_teardown_processes(adev); 3512 3509 amdgpu_userq_suspend(adev); ··· 4899 4902 amdgpu_virt_fini_data_exchange(adev); 4900 4903 } 4901 4904 4905 4905 + amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); 4906 4906 + amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); 4907 4907 + 4902 4908 /* disable all interrupts */ 4903 4909 amdgpu_irq_disable_all(adev); 4904 4910 if (adev->mode_info.mode_config_initialized) { ··· 4924 4924 * before ip_fini_early to prevent kfd locking refcount issues by calling 4925 4925 * amdgpu_amdkfd_suspend() 4926 4926 */ 4927 4927 - if (drm_dev_is_unplugged(adev_to_drm(adev))) 4927 4927 + if (pci_dev_is_disconnected(adev->pdev)) 4928 4928 amdgpu_amdkfd_device_fini_sw(adev); 4929 4929 4930 4930 amdgpu_device_ip_fini_early(adev); ··· 4936 4936 4937 4937 amdgpu_gart_dummy_page_fini(adev); 4938 4938 4939 4939 - if (drm_dev_is_unplugged(adev_to_drm(adev))) 4939 4939 + if (pci_dev_is_disconnected(adev->pdev)) 4940 4940 amdgpu_device_unmap_mmio(adev); 4941 4941 4942 4942 } ··· 5732 5732 5733 5733 /* enable mmio access after mode 1 reset completed */ 5734 5734 adev->no_hw_access = false; 5735 5735 + 5736 5736 + /* ensure no_hw_access is updated before we access hw */ 5737 5737 + smp_mb(); 5735 5738 5736 5739 amdgpu_device_load_pci_state(adev->pdev); 5737 5740 ret = amdgpu_psp_wait_for_bootloader(adev); ··· 7359 7356 7360 7357 amdgpu_xcp_dev_unplug(adev); 7361 7358 drm_dev_unplug(ddev); 7359 7359 + 7360 7360 + amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); 7361 7361 + amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); 7362 7362 7363 7363 amdgpu_irq_disable_all(adev); 7364 7364

-3

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

reviewed

··· 2405 2405 return -ENODEV; 2406 2406 } 2407 2407 2408 2408 - if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2409 2409 - amdgpu_aspm = 0; 2410 2410 - 2411 2408 if (amdgpu_virtual_display || 2412 2409 amdgpu_device_asic_has_dc_support(pdev, flags & AMD_ASIC_MASK)) 2413 2410 supports_atomic = true;

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c

reviewed

··· 1436 1436 if (!*exp_ranges) 1437 1437 *exp_ranges = range_cnt; 1438 1438 err: 1439 1439 - kfree(ranges); 1439 1439 + kvfree(ranges); 1440 1440 1441 1441 return ret; 1442 1442 }

+8 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_job.c

reviewed

··· 92 92 struct drm_wedge_task_info *info = NULL; 93 93 struct amdgpu_task_info *ti = NULL; 94 94 struct amdgpu_device *adev = ring->adev; 95 95 + enum drm_gpu_sched_stat status = DRM_GPU_SCHED_STAT_RESET; 95 96 int idx, r; 96 97 97 98 if (!drm_dev_enter(adev_to_drm(adev), &idx)) { ··· 136 135 ring->funcs->reset) { 137 136 dev_err(adev->dev, "Starting %s ring reset\n", 138 137 s_job->sched->name); 138 138 + /* Stop the scheduler to prevent anybody else from touching the ring buffer. */ 139 139 + drm_sched_wqueue_stop(&ring->sched); 139 140 r = amdgpu_ring_reset(ring, job->vmid, job->hw_fence); 140 141 if (!r) { 142 142 + /* Start the scheduler again */ 143 143 + drm_sched_wqueue_start(&ring->sched); 141 144 atomic_inc(&ring->adev->gpu_reset_counter); 142 145 dev_err(adev->dev, "Ring %s reset succeeded\n", 143 146 ring->sched.name); 144 147 drm_dev_wedged_event(adev_to_drm(adev), 145 148 DRM_WEDGE_RECOVERY_NONE, info); 149 149 + /* This is needed to add the job back to the pending list */ 150 150 + status = DRM_GPU_SCHED_STAT_NO_HANG; 146 151 goto exit; 147 152 } 148 153 dev_err(adev->dev, "Ring %s reset failed\n", ring->sched.name); ··· 184 177 exit: 185 178 amdgpu_vm_put_task_info(ti); 186 179 drm_dev_exit(idx); 187 187 - return DRM_GPU_SCHED_STAT_RESET; 180 180 + return status; 188 181 } 189 182 190 183 int amdgpu_job_alloc(struct amdgpu_device *adev, struct amdgpu_vm *vm,

+3 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

reviewed

··· 4352 4352 * to handle fatal error */ 4353 4353 r = amdgpu_nbio_ras_sw_init(adev); 4354 4354 if (r) 4355 4355 - return r; 4355 4355 + goto release_con; 4356 4356 4357 4357 if (adev->nbio.ras && 4358 4358 adev->nbio.ras->init_ras_controller_interrupt) { ··· 4649 4649 } else 4650 4650 amdgpu_ras_block_late_init_default(adev, &obj->ras_comm); 4651 4651 } 4652 4652 + 4653 4653 + amdgpu_ras_check_bad_page_status(adev); 4652 4654 4653 4655 return 0; 4654 4656 }

+23 -4

drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c

reviewed

··· 1712 1712 dev_warn(adev->dev, "RAS records:%u exceeds 90%% of threshold:%d", 1713 1713 control->ras_num_bad_pages, 1714 1714 ras->bad_page_cnt_threshold); 1715 1715 - if (amdgpu_bad_page_threshold != 0 && 1716 1716 - control->ras_num_bad_pages >= ras->bad_page_cnt_threshold) 1717 1717 - amdgpu_dpm_send_rma_reason(adev); 1718 1718 - 1719 1715 } else if (hdr->header == RAS_TABLE_HDR_BAD && 1720 1716 amdgpu_bad_page_threshold != 0) { 1721 1717 if (hdr->version >= RAS_TABLE_VER_V2_1) { ··· 1927 1931 return smu_ras_drv->smu_eeprom_funcs->erase_ras_table(adev, 1928 1932 result); 1929 1933 return -EOPNOTSUPP; 1934 1934 + } 1935 1935 + 1936 1936 + void amdgpu_ras_check_bad_page_status(struct amdgpu_device *adev) 1937 1937 + { 1938 1938 + struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1939 1939 + struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; 1940 1940 + 1941 1941 + if (!control || amdgpu_bad_page_threshold == 0) 1942 1942 + return; 1943 1943 + 1944 1944 + if (control->ras_num_bad_pages >= ras->bad_page_cnt_threshold) { 1945 1945 + if (amdgpu_dpm_send_rma_reason(adev)) 1946 1946 + dev_warn(adev->dev, "Unable to send out-of-band RMA CPER"); 1947 1947 + else 1948 1948 + dev_dbg(adev->dev, "Sent out-of-band RMA CPER"); 1949 1949 + 1950 1950 + if (adev->cper.enabled && !amdgpu_uniras_enabled(adev)) { 1951 1951 + if (amdgpu_cper_generate_bp_threshold_record(adev)) 1952 1952 + dev_warn(adev->dev, "Unable to send in-band RMA CPER"); 1953 1953 + else 1954 1954 + dev_dbg(adev->dev, "Sent in-band RMA CPER"); 1955 1955 + } 1956 1956 + } 1930 1957 }

+2

drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h

reviewed

··· 193 193 194 194 int amdgpu_ras_eeprom_update_record_num(struct amdgpu_ras_eeprom_control *control); 195 195 196 196 + void amdgpu_ras_check_bad_page_status(struct amdgpu_device *adev); 197 197 + 196 198 extern const struct file_operations amdgpu_ras_debugfs_eeprom_size_ops; 197 199 extern const struct file_operations amdgpu_ras_debugfs_eeprom_table_ops; 198 200

-4

drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c

reviewed

··· 868 868 void amdgpu_ring_reset_helper_begin(struct amdgpu_ring *ring, 869 869 struct amdgpu_fence *guilty_fence) 870 870 { 871 871 - /* Stop the scheduler to prevent anybody else from touching the ring buffer. */ 872 872 - drm_sched_wqueue_stop(&ring->sched); 873 871 /* back up the non-guilty commands */ 874 872 amdgpu_ring_backup_unprocessed_commands(ring, guilty_fence); 875 873 } ··· 893 895 amdgpu_ring_write(ring, ring->ring_backup[i]); 894 896 amdgpu_ring_commit(ring); 895 897 } 896 896 - /* Start the scheduler again */ 897 897 - drm_sched_wqueue_start(&ring->sched); 898 898 return 0; 899 899 } 900 900

+3

drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c

reviewed

··· 558 558 struct amdgpu_ring *gfx_ring = &sdma_instance->ring; 559 559 struct amdgpu_ring *page_ring = &sdma_instance->page; 560 560 561 561 + if (amdgpu_sriov_vf(adev)) 562 562 + return -EOPNOTSUPP; 563 563 + 561 564 mutex_lock(&sdma_instance->engine_reset_mutex); 562 565 563 566 if (!caller_handles_kernel_queues) {

-17

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

reviewed

··· 2360 2360 unsigned max_bits) 2361 2361 { 2362 2362 unsigned int max_size = 1 << (max_bits - 30); 2363 2363 - bool sys_5level_pgtable = false; 2364 2363 unsigned int vm_size; 2365 2364 uint64_t tmp; 2366 2366 - 2367 2367 - #ifdef CONFIG_X86_64 2368 2368 - /* 2369 2369 - * Refer to function configure_5level_paging() for details. 2370 2370 - */ 2371 2371 - sys_5level_pgtable = (native_read_cr4() & X86_CR4_LA57); 2372 2372 - #endif 2373 2373 - 2374 2374 - /* 2375 2375 - * If GPU supports 5-level page table, but system uses 4-level page table, 2376 2376 - * then use 4-level page table on GPU 2377 2377 - */ 2378 2378 - if (max_level == 4 && !sys_5level_pgtable) { 2379 2379 - min_vm_size = 256 * 1024; 2380 2380 - max_level = 3; 2381 2381 - } 2382 2365 2383 2366 /* adjust vm size first */ 2384 2367 if (amdgpu_vm_size != -1) {

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c

reviewed

··· 1176 1176 1177 1177 switch (type) { 1178 1178 case ACA_SMU_TYPE_UE: 1179 1179 - if (ext_error_code != 0 && ext_error_code != 9) 1179 1179 + if (ext_error_code != 0 && ext_error_code != 1 && ext_error_code != 9) 1180 1180 count = 0ULL; 1181 1181 1182 1182 bank->aca_err_type = ACA_ERROR_TYPE_UE;

+1 -1

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

reviewed

··· 1673 1673 if (r) 1674 1674 goto failure; 1675 1675 1676 1676 - if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x50) { 1676 1676 + if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x52) { 1677 1677 r = mes_v11_0_set_hw_resources_1(&adev->mes); 1678 1678 if (r) { 1679 1679 DRM_ERROR("failed mes_v11_0_set_hw_resources_1, r=%d\n", r);

+21

drivers/gpu/drm/amd/amdgpu/psp_v15_0_8.c

reviewed

··· 187 187 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67, value); 188 188 } 189 189 190 190 + static bool psp_v15_0_8_get_ras_capability(struct psp_context *psp) 191 191 + { 192 192 + struct amdgpu_device *adev = psp->adev; 193 193 + struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 194 194 + u32 reg_data; 195 195 + 196 196 + /* query ras cap should be done from host side */ 197 197 + if (amdgpu_sriov_vf(adev)) 198 198 + return false; 199 199 + 200 200 + if (!con) 201 201 + return false; 202 202 + 203 203 + reg_data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_127); 204 204 + adev->ras_hw_enabled = (reg_data & GENMASK_ULL(23, 0)); 205 205 + con->poison_supported = ((reg_data & GENMASK_ULL(24, 24)) >> 24) ? true : false; 206 206 + 207 207 + return true; 208 208 + } 209 209 + 190 210 static int psp_v15_0_8_get_fw_type(struct amdgpu_firmware_info *ucode, 191 211 enum psp_gfx_fw_type *type) 192 212 { ··· 354 334 .ring_get_wptr = psp_v15_0_8_ring_get_wptr, 355 335 .ring_set_wptr = psp_v15_0_8_ring_set_wptr, 356 336 .get_fw_type = psp_v15_0_8_get_fw_type, 337 337 + .get_ras_capability = psp_v15_0_8_get_ras_capability, 357 338 }; 358 339 359 340 void psp_v15_0_8_set_psp_funcs(struct psp_context *psp)

+3 -12

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

reviewed

··· 1424 1424 1425 1425 adev->sdma.supported_reset = 1426 1426 amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring); 1427 1427 - switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1428 1428 - case IP_VERSION(5, 0, 0): 1429 1429 - case IP_VERSION(5, 0, 2): 1430 1430 - case IP_VERSION(5, 0, 5): 1431 1431 - if ((adev->sdma.instance[0].fw_version >= 35) && 1432 1432 - !amdgpu_sriov_vf(adev) && 1433 1433 - !adev->debug_disable_gpu_ring_reset) 1434 1434 - adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1435 1435 - break; 1436 1436 - default: 1437 1437 - break; 1438 1438 - } 1427 1427 + if (!amdgpu_sriov_vf(adev) && 1428 1428 + !adev->debug_disable_gpu_ring_reset) 1429 1429 + adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1439 1430 1440 1431 /* Allocate memory for SDMA IP Dump buffer */ 1441 1432 ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL);

+3 -19

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

reviewed

··· 1342 1342 1343 1343 adev->sdma.supported_reset = 1344 1344 amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring); 1345 1345 - switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1346 1346 - case IP_VERSION(5, 2, 0): 1347 1347 - case IP_VERSION(5, 2, 2): 1348 1348 - case IP_VERSION(5, 2, 3): 1349 1349 - case IP_VERSION(5, 2, 4): 1350 1350 - if ((adev->sdma.instance[0].fw_version >= 76) && 1351 1351 - !amdgpu_sriov_vf(adev) && 1352 1352 - !adev->debug_disable_gpu_ring_reset) 1353 1353 - adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1354 1354 - break; 1355 1355 - case IP_VERSION(5, 2, 5): 1356 1356 - if ((adev->sdma.instance[0].fw_version >= 34) && 1357 1357 - !amdgpu_sriov_vf(adev) && 1358 1358 - !adev->debug_disable_gpu_ring_reset) 1359 1359 - adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1360 1360 - break; 1361 1361 - default: 1362 1362 - break; 1363 1363 - } 1345 1345 + if (!amdgpu_sriov_vf(adev) && 1346 1346 + !adev->debug_disable_gpu_ring_reset) 1347 1347 + adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1364 1348 1365 1349 /* Allocate memory for SDMA IP Dump buffer */ 1366 1350 ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL);

+3 -12

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

reviewed

··· 1364 1364 1365 1365 adev->sdma.supported_reset = 1366 1366 amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring); 1367 1367 - switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 1368 1368 - case IP_VERSION(6, 0, 0): 1369 1369 - case IP_VERSION(6, 0, 2): 1370 1370 - case IP_VERSION(6, 0, 3): 1371 1371 - if ((adev->sdma.instance[0].fw_version >= 21) && 1372 1372 - !amdgpu_sriov_vf(adev) && 1373 1373 - !adev->debug_disable_gpu_ring_reset) 1374 1374 - adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1375 1375 - break; 1376 1376 - default: 1377 1377 - break; 1378 1378 - } 1367 1367 + if (!amdgpu_sriov_vf(adev) && 1368 1368 + !adev->debug_disable_gpu_ring_reset) 1369 1369 + adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1379 1370 1380 1371 if (amdgpu_sdma_ras_sw_init(adev)) { 1381 1372 dev_err(adev->dev, "Failed to initialize sdma ras block!\n");

+3 -1

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

reviewed

··· 521 521 RREG32_SOC15(VCN, i, mmUVD_STATUS))) 522 522 vinst->set_pg_state(vinst, AMD_PG_STATE_GATE); 523 523 524 524 - if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) 524 524 + /* VF doesn't enable interrupt operations for RAS */ 525 525 + if (!amdgpu_sriov_vf(adev) && 526 526 + amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) 525 527 amdgpu_irq_put(adev, &vinst->ras_poison_irq, 0); 526 528 } 527 529

+6 -2

drivers/gpu/drm/amd/amdkfd/kfd_chardev.c

reviewed

··· 2804 2804 * SET_SHADER_DEBUGGER clears any stale process context data 2805 2805 * saved in MES. 2806 2806 */ 2807 2807 - if (pdd->dev->kfd->shared_resources.enable_mes) 2808 2808 - kfd_dbg_set_mes_debug_mode(pdd, !kfd_dbg_has_cwsr_workaround(pdd->dev)); 2807 2807 + if (pdd->dev->kfd->shared_resources.enable_mes) { 2808 2808 + ret = kfd_dbg_set_mes_debug_mode( 2809 2809 + pdd, !kfd_dbg_has_cwsr_workaround(pdd->dev)); 2810 2810 + if (ret) 2811 2811 + return ret; 2812 2812 + } 2809 2813 } 2810 2814 2811 2815 p->runtime_info.runtime_state = DEBUG_RUNTIME_STATE_ENABLED;

+5 -4

drivers/gpu/drm/amd/amdkfd/kfd_debug.c

reviewed

··· 575 575 continue; 576 576 577 577 if (!pdd->dev->kfd->shared_resources.enable_mes) 578 578 - debug_refresh_runlist(pdd->dev->dqm); 578 578 + (void)debug_refresh_runlist(pdd->dev->dqm); 579 579 else 580 580 - kfd_dbg_set_mes_debug_mode(pdd, true); 580 580 + (void)kfd_dbg_set_mes_debug_mode(pdd, true); 581 581 } 582 582 } 583 583 ··· 637 637 pr_err("Failed to release debug vmid on [%i]\n", pdd->dev->id); 638 638 639 639 if (!pdd->dev->kfd->shared_resources.enable_mes) 640 640 - debug_refresh_runlist(pdd->dev->dqm); 640 640 + (void)debug_refresh_runlist(pdd->dev->dqm); 641 641 else 642 642 - kfd_dbg_set_mes_debug_mode(pdd, !kfd_dbg_has_cwsr_workaround(pdd->dev)); 642 642 + (void)kfd_dbg_set_mes_debug_mode(pdd, 643 643 + !kfd_dbg_has_cwsr_workaround(pdd->dev)); 643 644 } 644 645 645 646 kfd_dbg_set_workaround(target, false);

+6

drivers/gpu/drm/amd/amdkfd/kfd_events.c

reviewed

··· 331 331 if (p->signal_page) 332 332 return -EBUSY; 333 333 334 334 + if (size < KFD_SIGNAL_EVENT_LIMIT * 8) { 335 335 + pr_err("Event page size %llu is too small, need at least %lu bytes\n", 336 336 + size, (unsigned long)(KFD_SIGNAL_EVENT_LIMIT * 8)); 337 337 + return -EINVAL; 338 338 + } 339 339 + 334 340 page = kzalloc(sizeof(*page), GFP_KERNEL); 335 341 if (!page) 336 342 return -ENOMEM;

+25 -15

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

reviewed

··· 1244 1244 struct dmub_srv *dmub_srv = adev->dm.dmub_srv; 1245 1245 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 1246 1246 const struct firmware *dmub_fw = adev->dm.dmub_fw; 1247 1247 + struct dc *dc = adev->dm.dc; 1247 1248 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu; 1248 1249 struct abm *abm = adev->dm.dc->res_pool->abm; 1249 1250 struct dc_context *ctx = adev->dm.dc->ctx; ··· 1350 1349 for (i = 0; i < fb_info->num_fb; ++i) 1351 1350 hw_params.fb[i] = &fb_info->fb[i]; 1352 1351 1353 1353 - switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1354 1354 - case IP_VERSION(3, 1, 3): 1355 1355 - case IP_VERSION(3, 1, 4): 1356 1356 - case IP_VERSION(3, 5, 0): 1357 1357 - case IP_VERSION(3, 5, 1): 1358 1358 - case IP_VERSION(3, 6, 0): 1359 1359 - case IP_VERSION(4, 0, 1): 1352 1352 + /* Enable usb4 dpia in the FW APU */ 1353 1353 + if (dc->caps.is_apu && 1354 1354 + dc->res_pool->usb4_dpia_count != 0 && 1355 1355 + !dc->debug.dpia_debug.bits.disable_dpia) { 1360 1356 hw_params.dpia_supported = true; 1361 1361 - hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia; 1362 1362 - break; 1363 1363 - default: 1364 1364 - break; 1357 1357 + hw_params.disable_dpia = dc->debug.dpia_debug.bits.disable_dpia; 1358 1358 + hw_params.dpia_hpd_int_enable_supported = false; 1359 1359 + hw_params.enable_non_transparent_setconfig = dc->config.consolidated_dpia_dp_lt; 1360 1360 + hw_params.disable_dpia_bw_allocation = !dc->config.usb4_bw_alloc_support; 1365 1361 } 1366 1362 1367 1363 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { ··· 8030 8032 dc_plane_state->plane_size.chroma_size.height = stream->src.height; 8031 8033 dc_plane_state->plane_size.chroma_size.width = stream->src.width; 8032 8034 dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 8035 8035 + dc_plane_state->tiling_info.gfxversion = DcGfxVersion9; 8033 8036 dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN; 8034 8037 dc_plane_state->rotation = ROTATION_ANGLE_0; 8035 8038 dc_plane_state->is_tiling_rotated = false; ··· 10661 10662 10662 10663 wb_info->dwb_params.capture_rate = dwb_capture_rate_0; 10663 10664 10664 10664 - wb_info->dwb_params.scaler_taps.h_taps = 4; 10665 10665 - wb_info->dwb_params.scaler_taps.v_taps = 4; 10666 10666 - wb_info->dwb_params.scaler_taps.h_taps_c = 2; 10667 10667 - wb_info->dwb_params.scaler_taps.v_taps_c = 2; 10665 10665 + wb_info->dwb_params.scaler_taps.h_taps = 1; 10666 10666 + wb_info->dwb_params.scaler_taps.v_taps = 1; 10667 10667 + wb_info->dwb_params.scaler_taps.h_taps_c = 1; 10668 10668 + wb_info->dwb_params.scaler_taps.v_taps_c = 1; 10668 10669 wb_info->dwb_params.subsample_position = DWB_INTERSTITIAL_SUBSAMPLING; 10669 10670 10670 10671 wb_info->mcif_buf_params.luma_pitch = afb->base.pitches[0]; ··· 11680 11681 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 11681 11682 struct dm_crtc_state *old_dm_crtc_state, *new_dm_crtc_state; 11682 11683 struct amdgpu_device *adev = drm_to_adev(plane->dev); 11684 11684 + struct drm_connector_state *new_con_state; 11685 11685 + struct drm_connector *connector; 11683 11686 int i; 11684 11687 11685 11688 /* ··· 11691 11690 if (amdgpu_ip_version(adev, DCE_HWIP, 0) < IP_VERSION(3, 2, 0) && 11692 11691 state->allow_modeset) 11693 11692 return true; 11693 11693 + 11694 11694 + /* Check for writeback commit */ 11695 11695 + for_each_new_connector_in_state(state, connector, new_con_state, i) { 11696 11696 + if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 11697 11697 + continue; 11698 11698 + 11699 11699 + if (new_con_state->writeback_job) 11700 11700 + return true; 11701 11701 + } 11694 11702 11695 11703 if (amdgpu_in_reset(adev) && state->allow_modeset) 11696 11704 return true;

+12 -3

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

reviewed

··· 506 506 struct amdgpu_dm_connector *aconnector = NULL; 507 507 bool enable = amdgpu_dm_is_valid_crc_source(source); 508 508 int ret = 0; 509 509 + enum crc_poly_mode crc_poly_mode = CRC_POLY_MODE_16; 509 510 510 511 /* Configuration will be deferred to stream enable. */ 511 512 if (!stream_state) ··· 529 528 amdgpu_dm_replay_disable(stream_state); 530 529 } 531 530 531 531 + /* CRC polynomial selection only support for DCN3.6+ except DCN4.0.1 */ 532 532 + if ((amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 6, 0)) && 533 533 + (amdgpu_ip_version(adev, DCE_HWIP, 0) != IP_VERSION(4, 0, 1))) { 534 534 + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 535 535 + 536 536 + crc_poly_mode = acrtc->dm_irq_params.crc_poly_mode; 537 537 + } 538 538 + 532 539 /* Enable or disable CRTC CRC generation */ 533 540 if (dm_is_crc_source_crtc(source) || source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE) { 534 541 if (!dc_stream_configure_crc(stream_state->ctx->dc, 535 535 - stream_state, NULL, enable, enable, 0, true)) { 542 542 + stream_state, NULL, enable, enable, 0, true, crc_poly_mode)) { 536 543 ret = -EINVAL; 537 544 goto unlock; 538 545 } ··· 886 877 else if (adev->dm.secure_display_ctx.op_mode == DISPLAY_CRC_MODE) 887 878 /* update ROI via dm*/ 888 879 dc_stream_configure_crc(stream_state->ctx->dc, stream_state, 889 889 - &crc_window, true, true, i, false); 880 880 + &crc_window, true, true, i, false, (enum crc_poly_mode)acrtc->dm_irq_params.crc_poly_mode); 890 881 891 882 reset_crc_frame_count[i] = true; 892 883 ··· 910 901 else if (adev->dm.secure_display_ctx.op_mode == DISPLAY_CRC_MODE) 911 902 /* Avoid ROI window get changed, keep overwriting. */ 912 903 dc_stream_configure_crc(stream_state->ctx->dc, stream_state, 913 913 - &crc_window, true, true, i, false); 904 904 + &crc_window, true, true, i, false, (enum crc_poly_mode)acrtc->dm_irq_params.crc_poly_mode); 914 905 915 906 /* crc ready for psp to read out */ 916 907 crtc_ctx->crc_info.crc[i].crc_ready = true;

+69 -1

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

reviewed

··· 46 46 #include "amdgpu_dm_psr.h" 47 47 #endif 48 48 49 49 + #define MULTIPLIER_TO_LR 270000 49 50 struct dmub_debugfs_trace_header { 50 51 uint32_t entry_count; 51 52 uint32_t reserved[3]; ··· 303 302 304 303 switch (param[1]) { 305 304 case LINK_RATE_LOW: 305 305 + case LINK_RATE_RATE_2: 306 306 + case LINK_RATE_RATE_3: 306 307 case LINK_RATE_HIGH: 307 308 case LINK_RATE_RBR2: 309 309 + case LINK_RATE_RATE_6: 308 310 case LINK_RATE_HIGH2: 309 311 case LINK_RATE_HIGH3: 310 312 case LINK_RATE_UHBR10: ··· 3508 3504 uint8_t param_nums = 0; 3509 3505 long param[2]; 3510 3506 bool valid_input = true; 3507 3507 + uint8_t supported_link_rates[16] = {0}; 3508 3508 + uint32_t entry = 0; 3509 3509 + uint32_t link_rate_in_khz = 0; 3510 3510 + uint8_t dpcd_rev = 0; 3511 3511 3512 3512 if (size == 0) 3513 3513 return -EINVAL; ··· 3556 3548 return size; 3557 3549 } 3558 3550 3551 3551 + if (!dm_helpers_dp_read_dpcd(link->ctx, link, DP_SUPPORTED_LINK_RATES, 3552 3552 + supported_link_rates, sizeof(supported_link_rates))) 3553 3553 + return -EINVAL; 3554 3554 + 3555 3555 + dpcd_rev = link->dpcd_caps.dpcd_rev.raw; 3556 3556 + if (dpcd_rev < DP_DPCD_REV_13 || 3557 3557 + (supported_link_rates[entry + 1] == 0 && supported_link_rates[entry] == 0)) { 3558 3558 + return size; 3559 3559 + } 3560 3560 + 3561 3561 + entry = param[1] * 2; 3562 3562 + link_rate_in_khz = (supported_link_rates[entry + 1] * 0x100 + 3563 3563 + supported_link_rates[entry]) * 200; 3564 3564 + 3559 3565 /* save user force lane_count, link_rate to preferred settings 3560 3566 * spread spectrum will not be changed 3561 3567 */ ··· 3577 3555 prefer_link_settings.lane_count = param[0]; 3578 3556 prefer_link_settings.use_link_rate_set = true; 3579 3557 prefer_link_settings.link_rate_set = param[1]; 3580 3580 - prefer_link_settings.link_rate = link->dpcd_caps.edp_supported_link_rates[param[1]]; 3558 3558 + prefer_link_settings.link_rate = link_rate_in_khz / MULTIPLIER_TO_LR; 3581 3559 3582 3560 mutex_lock(&adev->dm.dc_lock); 3583 3561 dc_link_set_preferred_training_settings(dc, &prefer_link_settings, ··· 3839 3817 3840 3818 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_update_fops, crc_win_update_get, 3841 3819 crc_win_update_set, "%llu\n"); 3820 3820 + 3821 3821 + /* 3822 3822 + * Trigger to set crc polynomial mode 3823 3823 + * 0: 16-bit CRC, 1: 32-bit CRC 3824 3824 + * only accepts 0 or 1 for supported hwip versions 3825 3825 + */ 3826 3826 + static int crc_poly_mode_set(void *data, u64 val) 3827 3827 + { 3828 3828 + struct drm_crtc *crtc = data; 3829 3829 + struct amdgpu_crtc *acrtc; 3830 3830 + struct amdgpu_device *adev = drm_to_adev(crtc->dev); 3831 3831 + 3832 3832 + if ((amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 6, 0)) && 3833 3833 + (amdgpu_ip_version(adev, DCE_HWIP, 0) != IP_VERSION(4, 0, 1)) && 3834 3834 + (val < 2)) { 3835 3835 + acrtc = to_amdgpu_crtc(crtc); 3836 3836 + mutex_lock(&adev->dm.dc_lock); 3837 3837 + spin_lock_irq(&adev_to_drm(adev)->event_lock); 3838 3838 + acrtc->dm_irq_params.crc_poly_mode = val; 3839 3839 + spin_unlock_irq(&adev_to_drm(adev)->event_lock); 3840 3840 + mutex_unlock(&adev->dm.dc_lock); 3841 3841 + } 3842 3842 + 3843 3843 + return 0; 3844 3844 + } 3845 3845 + 3846 3846 + /* 3847 3847 + * Get crc polynomial mode (0: 16-bit CRC, 1: 32-bit CRC) 3848 3848 + */ 3849 3849 + static int crc_poly_mode_get(void *data, u64 *val) 3850 3850 + { 3851 3851 + struct drm_crtc *crtc = data; 3852 3852 + struct drm_device *drm_dev = crtc->dev; 3853 3853 + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3854 3854 + 3855 3855 + spin_lock_irq(&drm_dev->event_lock); 3856 3856 + *val = acrtc->dm_irq_params.crc_poly_mode; 3857 3857 + spin_unlock_irq(&drm_dev->event_lock); 3858 3858 + 3859 3859 + return 0; 3860 3860 + } 3861 3861 + 3862 3862 + DEFINE_DEBUGFS_ATTRIBUTE(crc_poly_mode_fops, crc_poly_mode_get, 3863 3863 + crc_poly_mode_set, "%llu\n"); 3842 3864 #endif 3843 3865 void crtc_debugfs_init(struct drm_crtc *crtc) 3844 3866 { ··· 3902 3836 &crc_win_y_end_fops); 3903 3837 debugfs_create_file_unsafe("crc_win_update", 0644, dir, crtc, 3904 3838 &crc_win_update_fops); 3839 3839 + debugfs_create_file_unsafe("crc_poly_mode", 0644, dir, crtc, 3840 3840 + &crc_poly_mode_fops); 3905 3841 dput(dir); 3906 3842 #endif 3907 3843 debugfs_create_file("amdgpu_current_bpc", 0644, crtc->debugfs_entry,

+1

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq_params.h

reviewed

··· 39 39 40 40 #ifdef CONFIG_DEBUG_FS 41 41 enum amdgpu_dm_pipe_crc_source crc_src; 42 42 + int crc_poly_mode; /* enum crc_poly_mode from timing_generator.h */ 42 43 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 43 44 struct crc_window_param window_param[MAX_CRC_WINDOW_NUM]; 44 45 /* At least one CRC window is activated or not*/

+1 -1

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

reviewed

··· 1650 1650 MAX_COLOR_3DLUT_SIZE); 1651 1651 } 1652 1652 1653 1653 - if (dpp_color_caps.ogam_ram) { 1653 1653 + if (dpp_color_caps.ogam_ram || dm->dc->caps.color.mpc.preblend) { 1654 1654 drm_object_attach_property(&plane->base, 1655 1655 mode_info.plane_blend_lut_property, 0); 1656 1656 drm_object_attach_property(&plane->base,

+1 -1

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

reviewed

··· 186 186 187 187 return display_count; 188 188 } 189 189 - static void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, 189 189 + void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, 190 190 bool safe_to_lower, bool disable) 191 191 { 192 192 struct dc *dc = clk_mgr_base->ctx->dc;

+6

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.h

reviewed

··· 64 64 struct clk_mgr_dcn35 *clk_mgr, 65 65 struct pp_smu_funcs *pp_smu, 66 66 struct dccg *dccg); 67 67 + 68 68 + void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, 69 69 + struct dc_state *context, 70 70 + bool safe_to_lower, 71 71 + bool disable); 72 72 + 67 73 #endif //__DCN35_CLK_MGR_H__

+19 -5

drivers/gpu/drm/amd/display/dc/core/dc.c

reviewed

··· 701 701 * once. 702 702 * @idx: Capture CRC on which CRC engine instance 703 703 * @reset: Reset CRC engine before the configuration 704 704 + * @crc_poly_mode: CRC polynomial mode 704 705 * 705 706 * By default, the entire frame is used to calculate the CRC. 706 707 * ··· 710 709 */ 711 710 bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream, 712 711 struct crc_params *crc_window, bool enable, bool continuous, 713 713 - uint8_t idx, bool reset) 712 712 + uint8_t idx, bool reset, enum crc_poly_mode crc_poly_mode) 714 713 { 715 714 struct pipe_ctx *pipe; 716 715 struct crc_params param; ··· 734 733 param.windowb_y_start = 0; 735 734 param.windowb_x_end = pipe->stream->timing.h_addressable; 736 735 param.windowb_y_end = pipe->stream->timing.v_addressable; 736 736 + param.crc_poly_mode = crc_poly_mode; 737 737 738 738 if (crc_window) { 739 739 param.windowa_x_start = crc_window->windowa_x_start; ··· 2770 2768 case DcGfxVersion7: 2771 2769 case DcGfxVersion8: 2772 2770 case DcGfxVersionUnknown: 2771 2771 + case DcGfxBase: 2773 2772 default: 2774 2773 break; 2775 2774 } ··· 3863 3860 if (!dc_dmub_should_send_dirty_rect_cmd(dc, stream)) 3864 3861 return; 3865 3862 3866 3866 - if (!dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst)) 3863 3863 + if (!dc->config.frame_update_cmd_version2 && !dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst)) 3867 3864 return; 3868 3865 3869 3866 memset(&cmd, 0x0, sizeof(cmd)); ··· 3883 3880 if (srf_updates[i].surface->flip_immediate) 3884 3881 continue; 3885 3882 3886 3886 - update_dirty_rect->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; 3883 3883 + if (dc->config.frame_update_cmd_version2) 3884 3884 + update_dirty_rect->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_2; 3885 3885 + else 3886 3886 + update_dirty_rect->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_1; 3887 3887 + 3887 3888 update_dirty_rect->dirty_rect_count = flip_addr->dirty_rect_count; 3888 3889 memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects, 3889 3890 sizeof(flip_addr->dirty_rects)); ··· 3901 3894 3902 3895 update_dirty_rect->panel_inst = panel_inst; 3903 3896 update_dirty_rect->pipe_idx = j; 3897 3897 + update_dirty_rect->otg_inst = pipe_ctx->stream_res.tg->inst; 3904 3898 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT); 3905 3899 } 3906 3900 } ··· 3924 3916 if (!dc_dmub_should_send_dirty_rect_cmd(dc, stream)) 3925 3917 return; 3926 3918 3927 3927 - if (!dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst)) 3919 3919 + if (!dc->config.frame_update_cmd_version2 && !dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst)) 3928 3920 return; 3929 3921 3930 3922 memset(&cmd, 0x0, sizeof(cmd)); ··· 3943 3935 /* Do not send in immediate flip mode */ 3944 3936 if (srf_updates[i].surface->flip_immediate) 3945 3937 continue; 3946 3946 - update_dirty_rect->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; 3938 3938 + 3939 3939 + if (dc->config.frame_update_cmd_version2) 3940 3940 + update_dirty_rect->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_2; 3941 3941 + else 3942 3942 + update_dirty_rect->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_1; 3943 3943 + 3947 3944 update_dirty_rect->dirty_rect_count = flip_addr->dirty_rect_count; 3948 3945 memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects, 3949 3946 sizeof(flip_addr->dirty_rects)); ··· 3961 3948 continue; 3962 3949 update_dirty_rect->panel_inst = panel_inst; 3963 3950 update_dirty_rect->pipe_idx = j; 3951 3951 + update_dirty_rect->otg_inst = pipe_ctx->stream_res.tg->inst; 3964 3952 dc_dmub_cmd[*dmub_cmd_count].dmub_cmd = cmd; 3965 3953 dc_dmub_cmd[*dmub_cmd_count].wait_type = DM_DMUB_WAIT_TYPE_NO_WAIT; 3966 3954 (*dmub_cmd_count)++;

+7

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

reviewed

··· 2065 2065 while (bottom_pipe_ctx->bottom_pipe != NULL) 2066 2066 bottom_pipe_ctx = bottom_pipe_ctx->bottom_pipe; 2067 2067 2068 2068 + if (bottom_pipe_ctx->plane_state->tiling_info.gfxversion == DcGfxBase) { 2069 2069 + /* LINEAR Surface - set border color to red */ 2070 2070 + color->color_r_cr = color_value; 2071 2071 + return; 2072 2072 + } 2073 2073 + 2074 2074 + ASSERT(bottom_pipe_ctx->plane_state->tiling_info.gfxversion == DcGfxVersion9); 2068 2075 switch (bottom_pipe_ctx->plane_state->tiling_info.gfx9.swizzle) { 2069 2076 case DC_SW_LINEAR: 2070 2077 /* LINEAR Surface - set border color to red */

+1

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

reviewed

··· 4434 4434 4435 4435 if (dc->res_pool->funcs->patch_unknown_plane_state && 4436 4436 pipe_ctx->plane_state && 4437 4437 + pipe_ctx->plane_state->tiling_info.gfxversion == DcGfxVersion9 && 4437 4438 pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) { 4438 4439 result = dc->res_pool->funcs->patch_unknown_plane_state(pipe_ctx->plane_state); 4439 4440 if (result != DC_OK)

+2 -1

drivers/gpu/drm/amd/display/dc/dc.h

reviewed

··· 63 63 struct dcn_optc_reg_state; 64 64 struct dcn_dccg_reg_state; 65 65 66 66 - #define DC_VER "3.2.367" 66 66 + #define DC_VER "3.2.368" 67 67 68 68 /** 69 69 * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC ··· 560 560 bool enable_dpia_pre_training; 561 561 bool unify_link_enc_assignment; 562 562 bool enable_cursor_offload; 563 563 + bool frame_update_cmd_version2; 563 564 struct spl_sharpness_range dcn_sharpness_range; 564 565 struct spl_sharpness_range dcn_override_sharpness_range; 565 566 };

+11 -4

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

reviewed

··· 1034 1034 struct pipe_ctx *pipe_ctx, uint8_t p_idx, 1035 1035 struct dmub_cmd_update_cursor_payload0 *payload) 1036 1036 { 1037 1037 + struct dc *dc = pipe_ctx->stream->ctx->dc; 1037 1038 struct hubp *hubp = pipe_ctx->plane_res.hubp; 1038 1039 unsigned int panel_inst = 0; 1039 1040 1040 1040 - if (!dc_get_edp_link_panel_inst(hubp->ctx->dc, 1041 1041 - pipe_ctx->stream->link, &panel_inst)) 1042 1042 - return; 1041 1041 + if (dc->config.frame_update_cmd_version2 == true) { 1042 1042 + /* Don't need panel_inst for command version2 */ 1043 1043 + payload->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_2; 1044 1044 + } else { 1045 1045 + if (!dc_get_edp_link_panel_inst(hubp->ctx->dc, 1046 1046 + pipe_ctx->stream->link, &panel_inst)) 1047 1047 + return; 1048 1048 + payload->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_1; 1049 1049 + } 1043 1050 1044 1051 /* Payload: Cursor Rect is built from position & attribute 1045 1052 * x & y are obtained from postion ··· 1059 1052 1060 1053 payload->enable = hubp->pos.cur_ctl.bits.cur_enable; 1061 1054 payload->pipe_idx = p_idx; 1062 1062 - payload->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; 1063 1055 payload->panel_inst = panel_inst; 1056 1056 + payload->otg_inst = pipe_ctx->stream_res.tg->inst; 1064 1057 } 1065 1058 1066 1059 static void dc_build_cursor_position_update_payload0(

+2 -1

drivers/gpu/drm/amd/display/dc/dc_hw_types.h

reviewed

··· 342 342 }; 343 343 344 344 enum dc_gfxversion { 345 345 - DcGfxVersion7 = 0, 345 345 + DcGfxBase = 0, 346 346 + DcGfxVersion7, 346 347 DcGfxVersion8, 347 348 DcGfxVersion9, 348 349 DcGfxVersion10,

+2 -1

drivers/gpu/drm/amd/display/dc/dc_stream.h

reviewed

··· 584 584 bool enable, 585 585 bool continuous, 586 586 uint8_t idx, 587 587 - bool reset); 587 587 + bool reset, 588 588 + enum crc_poly_mode crc_poly_mode); 588 589 589 590 bool dc_stream_get_crc(struct dc *dc, 590 591 struct dc_stream_state *stream,

+25 -2

drivers/gpu/drm/amd/display/dc/dc_types.h

reviewed

··· 1230 1230 uint32_t replay_desync_error_fail_count; 1231 1231 /* The frame skip number dal send to DMUB */ 1232 1232 uint16_t frame_skip_number; 1233 1233 - /* Current Panel Replay event */ 1233 1233 + /* Current Panel Replay events */ 1234 1234 uint32_t replay_events; 1235 1235 }; 1236 1236 ··· 1256 1256 unsigned int max_nonboost_brightness_millinits; 1257 1257 unsigned int min_brightness_millinits; 1258 1258 } nits_brightness; 1259 1259 - /* PSR */ 1259 1259 + /* PSR/Replay */ 1260 1260 struct psr { 1261 1261 bool disable_psr; 1262 1262 bool disallow_psrsu; ··· 1266 1266 bool rc_allow_fullscreen_VPB; 1267 1267 bool read_psrcap_again; 1268 1268 unsigned int replay_enable_option; 1269 1269 + bool enable_frame_skipping; 1270 1270 + bool enable_teams_optimization; 1269 1271 } psr; 1270 1272 /* ABM */ 1271 1273 struct varib { ··· 1284 1282 struct ilr { 1285 1283 bool optimize_edp_link_rate; /* eDP ILR */ 1286 1284 } ilr; 1285 1285 + /* Adaptive VariBright*/ 1286 1286 + struct adaptive_vb { 1287 1287 + bool disable_adaptive_vb; 1288 1288 + unsigned int default_abm_vb_levels; // default value = 0xDCAA6414 1289 1289 + unsigned int default_cacp_vb_levels; 1290 1290 + unsigned int default_abm_vb_hdr_levels; // default value = 0xB4805A40 1291 1291 + unsigned int default_cacp_vb_hdr_levels; 1292 1292 + unsigned int abm_scaling_factors; // default value = 0x23210012 1293 1293 + unsigned int cacp_scaling_factors; 1294 1294 + unsigned int battery_life_configures; // default value = 0x0A141E 1295 1295 + unsigned int abm_backlight_adaptive_pwl_1; // default value = 0x6A4F7244 1296 1296 + unsigned int abm_backlight_adaptive_pwl_2; // default value = 0x4C615659 1297 1297 + unsigned int abm_backlight_adaptive_pwl_3; // default value = 0x0064 1298 1298 + unsigned int cacp_backlight_adaptive_pwl_1; 1299 1299 + unsigned int cacp_backlight_adaptive_pwl_2; 1300 1300 + unsigned int cacp_backlight_adaptive_pwl_3; 1301 1301 + } adaptive_vb; 1302 1302 + /* Ramless Idle Opt*/ 1303 1303 + struct rio { 1304 1304 + bool disable_rio; 1305 1305 + } rio; 1287 1306 }; 1288 1307 1289 1308 #define MAX_SINKS_PER_LINK 4

+53 -1

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

reviewed

··· 131 131 132 132 void dccg2_init(struct dccg *dccg) 133 133 { 134 134 + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 135 135 + 136 136 + /* Hardcoded register values for DCN20 137 137 + * These are specific to 100Mhz refclk 138 138 + * Different ASICs with different refclk may override this in their own init 139 139 + */ 140 140 + REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x00120264); 141 141 + REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x001186a0); 142 142 + REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x0e01003c); 143 143 + 144 144 + if (REG(REFCLK_CNTL)) 145 145 + REG_WRITE(REFCLK_CNTL, 0); 146 146 + } 147 147 + 148 148 + void dccg2_refclk_setup(struct dccg *dccg) 149 149 + { 150 150 + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 151 151 + 152 152 + /* REFCLK programming that must occur after hubbub initialization */ 153 153 + if (REG(REFCLK_CNTL)) 154 154 + REG_WRITE(REFCLK_CNTL, 0); 155 155 + } 156 156 + 157 157 + bool dccg2_is_s0i3_golden_init_wa_done(struct dccg *dccg) 158 158 + { 159 159 + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 160 160 + 161 161 + return REG_READ(MICROSECOND_TIME_BASE_DIV) == 0x00120464; 162 162 + } 163 163 + 164 164 + void dccg2_allow_clock_gating(struct dccg *dccg, bool allow) 165 165 + { 166 166 + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 167 167 + 168 168 + if (allow) { 169 169 + REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 170 170 + REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 171 171 + } else { 172 172 + REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0xFFFFFFFF); 173 173 + REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0xFFFFFFFF); 174 174 + } 175 175 + } 176 176 + 177 177 + void dccg2_enable_memory_low_power(struct dccg *dccg, bool enable) 178 178 + { 179 179 + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 180 180 + 181 181 + REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, enable ? 0 : 1); 134 182 } 135 183 136 184 static const struct dccg_funcs dccg2_funcs = { ··· 187 139 .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, 188 140 .otg_add_pixel = dccg2_otg_add_pixel, 189 141 .otg_drop_pixel = dccg2_otg_drop_pixel, 190 190 - .dccg_init = dccg2_init 142 142 + .dccg_init = dccg2_init, 143 143 + .refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */ 144 144 + .allow_clock_gating = dccg2_allow_clock_gating, 145 145 + .enable_memory_low_power = dccg2_enable_memory_low_power, 146 146 + .is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done 191 147 }; 192 148 193 149 struct dccg *dccg2_create(

+15 -3

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

reviewed

··· 46 46 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\ 47 47 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\ 48 48 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 4),\ 49 49 - DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5) 49 49 + DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5),\ 50 50 + SR(DCCG_GATE_DISABLE_CNTL),\ 51 51 + SR(DCCG_GATE_DISABLE_CNTL2) 50 52 51 53 #define DCCG_SF(reg_name, field_name, post_fix)\ 52 54 .field_name = reg_name ## __ ## field_name ## post_fix ··· 83 81 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\ 84 82 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\ 85 83 DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\ 86 86 - DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh) 84 84 + DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh),\ 85 85 + DCCG_SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh) 87 86 88 87 89 88 ··· 133 130 type DISPCLK_CHG_FWD_CORR_DISABLE;\ 134 131 type DISPCLK_FREQ_CHANGE_CNTL;\ 135 132 type OTG_ADD_PIXEL[MAX_PIPES];\ 136 136 - type OTG_DROP_PIXEL[MAX_PIPES]; 133 133 + type OTG_DROP_PIXEL[MAX_PIPES];\ 134 134 + type DC_MEM_GLOBAL_PWR_REQ_DIS; 137 135 138 136 #define DCCG3_REG_FIELD_LIST(type) \ 139 137 type HDMICHARCLK0_EN;\ ··· 518 514 519 515 520 516 void dccg2_init(struct dccg *dccg); 517 517 + 518 518 + void dccg2_refclk_setup(struct dccg *dccg); 519 519 + 520 520 + bool dccg2_is_s0i3_golden_init_wa_done(struct dccg *dccg); 521 521 + 522 522 + void dccg2_allow_clock_gating(struct dccg *dccg, bool allow); 523 523 + 524 524 + void dccg2_enable_memory_low_power(struct dccg *dccg, bool enable); 521 525 522 526 struct dccg *dccg2_create( 523 527 struct dc_context *ctx,

+10 -20

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

reviewed

··· 1105 1105 dccg35_set_dpstreamclk_src_new(dccg, src, inst); 1106 1106 } 1107 1107 1108 1108 - static void dccg35_trigger_dio_fifo_resync(struct dccg *dccg) 1108 1108 + void dccg35_trigger_dio_fifo_resync(struct dccg *dccg) 1109 1109 { 1110 1110 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 1111 1111 uint32_t dispclk_rdivider_value = 0; ··· 1114 1114 if (dispclk_rdivider_value != 0) 1115 1115 REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, dispclk_rdivider_value); 1116 1116 } 1117 1117 + 1117 1118 static void dccg35_wait_for_dentist_change_done( 1118 1119 struct dccg *dccg) 1119 1120 { ··· 1152 1151 1153 1152 } 1154 1153 1155 1155 - static void dccg35_update_dpp_dto(struct dccg *dccg, int dpp_inst, 1156 1156 - int req_dppclk) 1154 1154 + void dccg35_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) 1157 1155 { 1158 1156 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 1159 1157 ··· 1498 1498 __func__, dp_hpo_inst, (src == REFCLK) ? 0 : 1, otg_inst); 1499 1499 } 1500 1500 1501 1501 - 1502 1502 - static void dccg35_set_dpstreamclk_root_clock_gating( 1503 1503 - struct dccg *dccg, 1504 1504 - int dp_hpo_inst, 1505 1505 - bool enable) 1501 1501 + void dccg35_set_dpstreamclk_root_clock_gating(struct dccg *dccg, int dp_hpo_inst, bool enable) 1506 1502 { 1507 1503 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 1508 1504 ··· 1665 1669 dccg35_set_dtbclk_dto(dccg, &dto_params); 1666 1670 } 1667 1671 1668 1668 - static void dccg35_dpp_root_clock_control( 1669 1669 - struct dccg *dccg, 1670 1670 - unsigned int dpp_inst, 1671 1671 - bool clock_on) 1672 1672 + void dccg35_dpp_root_clock_control(struct dccg *dccg, unsigned int dpp_inst, bool clock_on) 1672 1673 { 1673 1674 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 1674 1675 ··· 1697 1704 DC_LOG_DEBUG("%s: dpp_inst(%d) clock_on = %d\n", __func__, dpp_inst, clock_on); 1698 1705 } 1699 1706 1700 1700 - static void dccg35_disable_symclk32_se( 1701 1701 - struct dccg *dccg, 1702 1702 - int hpo_se_inst) 1707 1707 + void dccg35_disable_symclk32_se(struct dccg *dccg, int hpo_se_inst) 1703 1708 { 1704 1709 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 1705 1710 ··· 1804 1813 REG_UPDATE(DCCG_GLOBAL_FGCG_REP_CNTL, DCCG_GLOBAL_FGCG_REP_DIS, !value); 1805 1814 } 1806 1815 1807 1807 - static void dccg35_enable_dscclk(struct dccg *dccg, int inst) 1816 1816 + void dccg35_enable_dscclk(struct dccg *dccg, int inst) 1808 1817 { 1809 1818 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 1810 1819 ··· 1851 1860 udelay(10); 1852 1861 } 1853 1862 1854 1854 - static void dccg35_disable_dscclk(struct dccg *dccg, 1855 1855 - int inst) 1863 1863 + void dccg35_disable_dscclk(struct dccg *dccg, int inst) 1856 1864 { 1857 1865 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 1858 1866 ··· 1896 1906 udelay(10); 1897 1907 } 1898 1908 1899 1899 - static void dccg35_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst) 1909 1909 + void dccg35_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst) 1900 1910 { 1901 1911 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 1902 1912 ··· 2003 2013 return num_enabled_symclk_fe; 2004 2014 } 2005 2015 2006 2006 - static void dccg35_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst) 2016 2016 + void dccg35_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst) 2007 2017 { 2008 2018 uint8_t num_enabled_symclk_fe = 0; 2009 2019 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

+17

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

reviewed

··· 249 249 250 250 void dccg35_init(struct dccg *dccg); 251 251 252 252 + void dccg35_trigger_dio_fifo_resync(struct dccg *dccg); 253 253 + 254 254 + void dccg35_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk); 255 255 + 252 256 void dccg35_enable_global_fgcg_rep(struct dccg *dccg, bool value); 253 257 void dccg35_root_gate_disable_control(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating); 254 258 259 259 + void dccg35_set_dpstreamclk_root_clock_gating(struct dccg *dccg, int dp_hpo_inst, bool enable); 260 260 + 261 261 + void dccg35_set_hdmistreamclk_root_clock_gating(struct dccg *dccg, bool enable); 262 262 + 263 263 + void dccg35_dpp_root_clock_control(struct dccg *dccg, unsigned int dpp_inst, bool clock_on); 264 264 + 265 265 + void dccg35_disable_symclk32_se(struct dccg *dccg, int hpo_se_inst); 266 266 + 267 267 + void dccg35_enable_dscclk(struct dccg *dccg, int inst); 268 268 + void dccg35_disable_dscclk(struct dccg *dccg, int inst); 269 269 + 270 270 + void dccg35_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst); 271 271 + void dccg35_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst); 255 272 256 273 #endif //__DCN35_DCCG_H__

+3

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

reviewed

··· 100 100 static enum mi_tiling_format get_mi_tiling( 101 101 struct dc_tiling_info *tiling_info) 102 102 { 103 103 + ASSERT(tiling_info->gfxversion == DcGfxVersion8); 103 104 switch (tiling_info->gfx8.array_mode) { 104 105 case DC_ARRAY_1D_TILED_THIN1: 105 106 case DC_ARRAY_1D_TILED_THICK: ··· 434 433 struct dce_mem_input *dce_mi, const struct dc_tiling_info *info) 435 434 { 436 435 if (dce_mi->masks->GRPH_SW_MODE) { /* GFX9 */ 436 436 + ASSERT(info->gfxversion == DcGfxVersion9); 437 437 REG_UPDATE_6(GRPH_CONTROL, 438 438 GRPH_SW_MODE, info->gfx9.swizzle, 439 439 GRPH_NUM_BANKS, log_2(info->gfx9.num_banks), ··· 449 447 } 450 448 451 449 if (dce_mi->masks->GRPH_MICRO_TILE_MODE) { /* GFX8 */ 450 450 + ASSERT(info->gfxversion == DcGfxVersion8); 452 451 REG_UPDATE_9(GRPH_CONTROL, 453 452 GRPH_NUM_BANKS, info->gfx8.num_banks, 454 453 GRPH_BANK_WIDTH, info->gfx8.bank_width,

+3

drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c

reviewed

··· 165 165 const struct dc_tiling_info *info, 166 166 const enum surface_pixel_format pixel_format) 167 167 { 168 168 + ASSERT(info->gfxversion == DcGfxVersion8); 169 169 + 168 170 uint32_t value = 0; 169 171 170 172 set_reg_field_value(value, info->gfx8.num_banks, ··· 543 541 else 544 542 bpp = bpp_8; 545 543 544 544 + ASSERT(tiling_info->gfxversion == DcGfxVersion8); 546 545 switch (tiling_info->gfx8.array_mode) { 547 546 case DC_ARRAY_1D_TILED_THIN1: 548 547 case DC_ARRAY_1D_TILED_THICK:

+29 -8

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c

reviewed

··· 105 105 #define NUMBER_REGIONS 32 106 106 #define NUMBER_SW_SEGMENTS 16 107 107 108 108 - bool cm3_helper_translate_curve_to_hw_format( 109 109 - const struct dc_transfer_func *output_tf, 110 110 - struct pwl_params *lut_params, bool fixpoint) 108 108 + #define DC_LOGGER \ 109 109 + ctx->logger 110 110 + 111 111 + bool cm3_helper_translate_curve_to_hw_format(struct dc_context *ctx, 112 112 + const struct dc_transfer_func *output_tf, 113 113 + struct pwl_params *lut_params, bool fixpoint) 111 114 { 112 115 struct curve_points3 *corner_points; 113 116 struct pwl_result_data *rgb_resulted; ··· 165 162 if (seg_distr[k] != -1) 166 163 hw_points += (1 << seg_distr[k]); 167 164 } 165 165 + 166 166 + // DCN3+ have 257 pts in lieu of no separate slope registers 167 167 + // Prior HW had 256 base+slope pairs 168 168 + // Shaper LUT (i.e. fixpoint == true) is still 256 bases and 256 deltas 169 169 + hw_points = fixpoint ? (hw_points - 1) : hw_points; 168 170 169 171 j = 0; 170 172 for (k = 0; k < (region_end - region_start); k++) { ··· 231 223 corner_points[1].green.slope = dc_fixpt_zero; 232 224 corner_points[1].blue.slope = dc_fixpt_zero; 233 225 234 234 - // DCN3+ have 257 pts in lieu of no separate slope registers 235 235 - // Prior HW had 256 base+slope pairs 236 226 lut_params->hw_points_num = hw_points + 1; 237 227 238 228 k = 0; ··· 254 248 if (fixpoint == true) { 255 249 i = 1; 256 250 while (i != hw_points + 2) { 251 251 + uint32_t red_clamp; 252 252 + uint32_t green_clamp; 253 253 + uint32_t blue_clamp; 254 254 + 257 255 if (i >= hw_points) { 258 256 if (dc_fixpt_lt(rgb_plus_1->red, rgb->red)) 259 257 rgb_plus_1->red = dc_fixpt_add(rgb->red, ··· 270 260 rgb_minus_1->delta_blue); 271 261 } 272 262 273 273 - rgb->delta_red_reg = dc_fixpt_clamp_u0d10(rgb->delta_red); 274 274 - rgb->delta_green_reg = dc_fixpt_clamp_u0d10(rgb->delta_green); 275 275 - rgb->delta_blue_reg = dc_fixpt_clamp_u0d10(rgb->delta_blue); 263 263 + rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red); 264 264 + rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green); 265 265 + rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue); 266 266 + 267 267 + red_clamp = dc_fixpt_clamp_u0d14(rgb->delta_red); 268 268 + green_clamp = dc_fixpt_clamp_u0d14(rgb->delta_green); 269 269 + blue_clamp = dc_fixpt_clamp_u0d14(rgb->delta_blue); 270 270 + 271 271 + if (red_clamp >> 10 || green_clamp >> 10 || blue_clamp >> 10) 272 272 + DC_LOG_ERROR("Losing delta precision while programming shaper LUT."); 273 273 + 274 274 + rgb->delta_red_reg = red_clamp & 0x3ff; 275 275 + rgb->delta_green_reg = green_clamp & 0x3ff; 276 276 + rgb->delta_blue_reg = blue_clamp & 0x3ff; 276 277 rgb->red_reg = dc_fixpt_clamp_u0d14(rgb->red); 277 278 rgb->green_reg = dc_fixpt_clamp_u0d14(rgb->green); 278 279 rgb->blue_reg = dc_fixpt_clamp_u0d14(rgb->blue);

+1 -1

drivers/gpu/drm/amd/display/dc/dio/Makefile

reviewed

··· 27 27 ############################################################################### 28 28 # DCN10 29 29 ############################################################################### 30 30 - DIO_DCN10 = dcn10_link_encoder.o dcn10_stream_encoder.o 30 30 + DIO_DCN10 = dcn10_link_encoder.o dcn10_stream_encoder.o dcn10_dio.o 31 31 32 32 AMD_DAL_DIO_DCN10 = $(addprefix $(AMDDALPATH)/dc/dio/dcn10/,$(DIO_DCN10)) 33 33

+47

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_dio.c

reviewed

··· 1 1 + // SPDX-License-Identifier: MIT 2 2 + // 3 3 + // Copyright 2025 Advanced Micro Devices, Inc. 4 4 + 5 5 + #include "dc_hw_types.h" 6 6 + #include "dm_services.h" 7 7 + #include "reg_helper.h" 8 8 + #include "dcn10_dio.h" 9 9 + 10 10 + #define CTX \ 11 11 + dio10->base.ctx 12 12 + #define REG(reg)\ 13 13 + dio10->regs->reg 14 14 + 15 15 + #undef FN 16 16 + #define FN(reg_name, field_name) \ 17 17 + dio10->shifts->field_name, dio10->masks->field_name 18 18 + 19 19 + static void dcn10_dio_mem_pwr_ctrl(struct dio *dio, bool enable_i2c_light_sleep) 20 20 + { 21 21 + struct dcn10_dio *dio10 = TO_DCN10_DIO(dio); 22 22 + 23 23 + /* power AFMT HDMI memory */ 24 24 + REG_WRITE(DIO_MEM_PWR_CTRL, 0); 25 25 + 26 26 + if (enable_i2c_light_sleep) 27 27 + REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 1); 28 28 + } 29 29 + 30 30 + static const struct dio_funcs dcn10_dio_funcs = { 31 31 + .mem_pwr_ctrl = dcn10_dio_mem_pwr_ctrl, 32 32 + }; 33 33 + 34 34 + void dcn10_dio_construct( 35 35 + struct dcn10_dio *dio10, 36 36 + struct dc_context *ctx, 37 37 + const struct dcn_dio_registers *regs, 38 38 + const struct dcn_dio_shift *shifts, 39 39 + const struct dcn_dio_mask *masks) 40 40 + { 41 41 + dio10->base.ctx = ctx; 42 42 + dio10->base.funcs = &dcn10_dio_funcs; 43 43 + 44 44 + dio10->regs = regs; 45 45 + dio10->shifts = shifts; 46 46 + dio10->masks = masks; 47 47 + }

+42

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_dio.h

reviewed

··· 1 1 + // SPDX-License-Identifier: MIT 2 2 + // 3 3 + // Copyright 2025 Advanced Micro Devices, Inc. 4 4 + 5 5 + #ifndef __DCN10_DIO_H__ 6 6 + #define __DCN10_DIO_H__ 7 7 + 8 8 + #include "dio.h" 9 9 + 10 10 + #define TO_DCN10_DIO(dio_base) \ 11 11 + container_of(dio_base, struct dcn10_dio, base) 12 12 + 13 13 + #define DIO_REG_LIST_DCN10()\ 14 14 + SR(DIO_MEM_PWR_CTRL) 15 15 + 16 16 + struct dcn_dio_registers { 17 17 + uint32_t DIO_MEM_PWR_CTRL; 18 18 + }; 19 19 + 20 20 + struct dcn_dio_shift { 21 21 + uint8_t I2C_LIGHT_SLEEP_FORCE; 22 22 + }; 23 23 + 24 24 + struct dcn_dio_mask { 25 25 + uint32_t I2C_LIGHT_SLEEP_FORCE; 26 26 + }; 27 27 + 28 28 + struct dcn10_dio { 29 29 + struct dio base; 30 30 + const struct dcn_dio_registers *regs; 31 31 + const struct dcn_dio_shift *shifts; 32 32 + const struct dcn_dio_mask *masks; 33 33 + }; 34 34 + 35 35 + void dcn10_dio_construct( 36 36 + struct dcn10_dio *dio10, 37 37 + struct dc_context *ctx, 38 38 + const struct dcn_dio_registers *regs, 39 39 + const struct dcn_dio_shift *shifts, 40 40 + const struct dcn_dio_mask *masks); 41 41 + 42 42 + #endif /* __DCN10_DIO_H__ */

+1

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

reviewed

··· 1006 1006 1007 1007 v->source_pixel_format[input_idx] = tl_pixel_format_to_bw_defs( 1008 1008 pipe->plane_state->format); 1009 1009 + ASSERT(pipe->plane_state->tiling_info.gfxversion == DcGfxVersion9); 1009 1010 v->source_surface_mode[input_idx] = tl_sw_mode_to_bw_defs( 1010 1011 pipe->plane_state->tiling_info.gfx9.swizzle); 1011 1012 v->lb_bit_per_pixel[input_idx] = tl_lb_bpp_to_int(pipe->plane_res.scl_data.lb_params.depth);

+3

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

reviewed

··· 460 460 case DcGfxAddr3: 461 461 surface->tiling = gfx_addr3_to_dml2_swizzle_mode(plane_state->tiling_info.gfx_addr3.swizzle); 462 462 break; 463 463 + case DcGfxBase: 464 464 + surface->tiling = dml2_sw_linear; 465 465 + break; 463 466 } 464 467 } 465 468

+3

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h

reviewed

··· 115 115 unsigned int channel_width_bytes; 116 116 unsigned int channel_count; 117 117 unsigned int transactions_per_clock; 118 118 + bool alt_clock_bw_conversion; 118 119 }; 119 120 121 121 + #define ENABLE_WCK 120 122 struct dml2_soc_state_table { 123 123 + struct dml2_clk_table wck_ratio; 121 124 struct dml2_clk_table uclk; 122 125 struct dml2_clk_table fclk; 123 126 struct dml2_clk_table dcfclk;

+21 -5

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

reviewed

··· 7077 7077 } 7078 7078 } 7079 7079 7080 7080 - static double uclk_khz_to_dram_bw_mbps(unsigned long uclk_khz, const struct dml2_dram_params *dram_config) 7080 7080 + static double uclk_khz_to_dram_bw_mbps(unsigned long uclk_khz, const struct dml2_dram_params *dram_config, const struct dml2_mcg_dram_bw_to_min_clk_table *dram_bw_table) 7081 7081 { 7082 7082 double bw_mbps = 0; 7083 7083 - bw_mbps = ((double)uclk_khz * dram_config->channel_count * dram_config->channel_width_bytes * dram_config->transactions_per_clock) / 1000.0; 7083 7083 + unsigned int i; 7084 7084 + 7085 7085 + if (!dram_config->alt_clock_bw_conversion) 7086 7086 + bw_mbps = ((double)uclk_khz * dram_config->channel_count * dram_config->channel_width_bytes * dram_config->transactions_per_clock) / 1000.0; 7087 7087 + else 7088 7088 + for (i = 0; i < dram_bw_table->num_entries; i++) 7089 7089 + if (dram_bw_table->entries[i].min_uclk_khz >= uclk_khz) { 7090 7090 + bw_mbps = (double)dram_bw_table->entries[i].pre_derate_dram_bw_kbps / 1000.0; 7091 7091 + break; 7092 7092 + } 7093 7093 + 7094 7094 + DML_ASSERT(bw_mbps > 0); 7084 7095 7085 7096 return bw_mbps; 7086 7097 } ··· 7975 7964 mode_lib->ms.max_dispclk_freq_mhz = (double)min_clk_table->max_ss_clocks_khz.dispclk / 1000; 7976 7965 mode_lib->ms.max_dscclk_freq_mhz = (double)min_clk_table->max_clocks_khz.dscclk / 1000; 7977 7966 mode_lib->ms.max_dppclk_freq_mhz = (double)min_clk_table->max_ss_clocks_khz.dppclk / 1000; 7978 7978 - mode_lib->ms.uclk_freq_mhz = dram_bw_kbps_to_uclk_mhz(min_clk_table->dram_bw_table.entries[in_out_params->min_clk_index].pre_derate_dram_bw_kbps, &mode_lib->soc.clk_table.dram_config); 7967 7967 + mode_lib->ms.uclk_freq_mhz = (double)min_clk_table->dram_bw_table.entries[in_out_params->min_clk_index].min_uclk_khz / 1000.0; 7968 7968 + if (!mode_lib->ms.uclk_freq_mhz) 7969 7969 + mode_lib->ms.uclk_freq_mhz = dram_bw_kbps_to_uclk_mhz(min_clk_table->dram_bw_table.entries[in_out_params->min_clk_index].pre_derate_dram_bw_kbps, &mode_lib->soc.clk_table.dram_config); 7979 7970 mode_lib->ms.dram_bw_mbps = ((double)min_clk_table->dram_bw_table.entries[in_out_params->min_clk_index].pre_derate_dram_bw_kbps / 1000); 7980 7971 mode_lib->ms.max_dram_bw_mbps = ((double)min_clk_table->dram_bw_table.entries[min_clk_table->dram_bw_table.num_entries - 1].pre_derate_dram_bw_kbps / 1000); 7981 7972 mode_lib->ms.qos_param_index = get_qos_param_index((unsigned int) (mode_lib->ms.uclk_freq_mhz * 1000.0), mode_lib->soc.qos_parameters.qos_params.dcn4x.per_uclk_dpm_params); ··· 10420 10407 10421 10408 mode_lib->mp.Dcfclk = programming->min_clocks.dcn4x.active.dcfclk_khz / 1000.0; 10422 10409 mode_lib->mp.FabricClock = programming->min_clocks.dcn4x.active.fclk_khz / 1000.0; 10423 10423 - mode_lib->mp.dram_bw_mbps = uclk_khz_to_dram_bw_mbps(programming->min_clocks.dcn4x.active.uclk_khz, &mode_lib->soc.clk_table.dram_config); 10410 10410 + mode_lib->mp.dram_bw_mbps = uclk_khz_to_dram_bw_mbps(programming->min_clocks.dcn4x.active.uclk_khz, &mode_lib->soc.clk_table.dram_config, &min_clk_table->dram_bw_table); 10424 10411 mode_lib->mp.uclk_freq_mhz = programming->min_clocks.dcn4x.active.uclk_khz / 1000.0; 10425 10412 mode_lib->mp.GlobalDPPCLK = programming->min_clocks.dcn4x.dpprefclk_khz / 1000.0; 10426 10413 s->SOCCLK = (double)programming->min_clocks.dcn4x.socclk_khz / 1000; ··· 10498 10485 DML_LOG_VERBOSE("DML::%s: SOCCLK = %f\n", __func__, s->SOCCLK); 10499 10486 DML_LOG_VERBOSE("DML::%s: min_clk_index = %0d\n", __func__, in_out_params->min_clk_index); 10500 10487 DML_LOG_VERBOSE("DML::%s: min_clk_table min_fclk_khz = %ld\n", __func__, min_clk_table->dram_bw_table.entries[in_out_params->min_clk_index].min_fclk_khz); 10501 10501 - DML_LOG_VERBOSE("DML::%s: min_clk_table uclk_mhz = %f\n", __func__, dram_bw_kbps_to_uclk_mhz(min_clk_table->dram_bw_table.entries[in_out_params->min_clk_index].pre_derate_dram_bw_kbps, &mode_lib->soc.clk_table.dram_config)); 10488 10488 + if (min_clk_table->dram_bw_table.entries[in_out_params->min_clk_index].min_uclk_khz) 10489 10489 + DML_LOG_VERBOSE("DML::%s: min_clk_table uclk_mhz = %f\n", __func__, min_clk_table->dram_bw_table.entries[in_out_params->min_clk_index].min_uclk_khz / 1000.0); 10490 10490 + else 10491 10491 + DML_LOG_VERBOSE("DML::%s: min_clk_table uclk_mhz = %f\n", __func__, dram_bw_kbps_to_uclk_mhz(min_clk_table->dram_bw_table.entries[in_out_params->min_clk_index].pre_derate_dram_bw_kbps, &mode_lib->soc.clk_table.dram_config)); 10502 10492 for (k = 0; k < mode_lib->mp.num_active_pipes; ++k) { 10503 10493 DML_LOG_VERBOSE("DML::%s: pipe=%d is in plane=%d\n", __func__, k, mode_lib->mp.pipe_plane[k]); 10504 10494 DML_LOG_VERBOSE("DML::%s: Per-plane DPPPerSurface[%0d] = %d\n", __func__, k, mode_lib->mp.NoOfDPP[k]);

+39 -20

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c

reviewed

··· 7 7 #include "dml_top_types.h" 8 8 #include "lib_float_math.h" 9 9 10 10 - static double dram_bw_kbps_to_uclk_khz(unsigned long long bandwidth_kbps, const struct dml2_dram_params *dram_config) 10 10 + static double dram_bw_kbps_to_uclk_khz(unsigned long long bandwidth_kbps, const struct dml2_dram_params *dram_config, struct dml2_mcg_dram_bw_to_min_clk_table *dram_bw_table) 11 11 { 12 12 double uclk_khz = 0; 13 13 - unsigned long uclk_mbytes_per_tick = 0; 14 13 15 15 - uclk_mbytes_per_tick = dram_config->channel_count * dram_config->channel_width_bytes * dram_config->transactions_per_clock; 14 14 + if (!dram_config->alt_clock_bw_conversion) { 15 15 + unsigned long uclk_bytes_per_tick = 0; 16 16 17 17 - uclk_khz = (double)bandwidth_kbps / uclk_mbytes_per_tick; 17 17 + uclk_bytes_per_tick = dram_config->channel_count * dram_config->channel_width_bytes * dram_config->transactions_per_clock; 18 18 + uclk_khz = (double)bandwidth_kbps / uclk_bytes_per_tick; 19 19 + } else { 20 20 + unsigned int i; 21 21 + /* For lpddr5 bytes per tick changes with mpstate, use table to find uclk*/ 22 22 + for (i = 0; i < dram_bw_table->num_entries; i++) 23 23 + if (dram_bw_table->entries[i].pre_derate_dram_bw_kbps >= bandwidth_kbps) { 24 24 + uclk_khz = dram_bw_table->entries[i].min_uclk_khz; 25 25 + break; 26 26 + } 27 27 + } 18 28 19 29 return uclk_khz; 20 30 } ··· 44 34 *dcfclk = in_out->min_clk_table->dram_bw_table.entries[min_clock_index_for_latency].min_dcfclk_khz; 45 35 *fclk = in_out->min_clk_table->dram_bw_table.entries[min_clock_index_for_latency].min_fclk_khz; 46 36 *uclk = dram_bw_kbps_to_uclk_khz(in_out->min_clk_table->dram_bw_table.entries[min_clock_index_for_latency].pre_derate_dram_bw_kbps, 47 47 - &in_out->soc_bb->clk_table.dram_config); 37 37 + &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); 48 38 } 49 39 50 40 static unsigned long dml_round_up(double a) ··· 63 53 double min_uclk_latency, min_fclk_latency, min_dcfclk_latency; 64 54 const struct dml2_core_mode_support_result *mode_support_result = &in_out->display_cfg->mode_support_result; 65 55 66 66 - min_uclk_avg = dram_bw_kbps_to_uclk_khz(mode_support_result->global.active.average_bw_dram_kbps, &in_out->soc_bb->clk_table.dram_config); 67 67 - min_uclk_avg = (double)min_uclk_avg / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_average.dram_derate_percent_pixel / 100); 56 56 + min_uclk_avg = dram_bw_kbps_to_uclk_khz((unsigned long long)(mode_support_result->global.active.average_bw_dram_kbps 57 57 + / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_average.dram_derate_percent_pixel / 100)), 58 58 + &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); 68 59 69 69 - min_uclk_urgent = dram_bw_kbps_to_uclk_khz(mode_support_result->global.active.urgent_bw_dram_kbps, &in_out->soc_bb->clk_table.dram_config); 70 60 if (in_out->display_cfg->display_config.hostvm_enable) 71 71 - min_uclk_urgent = (double)min_uclk_urgent / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_urgent.dram_derate_percent_pixel_and_vm / 100); 61 61 + min_uclk_urgent = dram_bw_kbps_to_uclk_khz((unsigned long long)(mode_support_result->global.active.urgent_bw_dram_kbps 62 62 + / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_urgent.dram_derate_percent_pixel_and_vm / 100)), 63 63 + &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); 72 64 else 73 73 - min_uclk_urgent = (double)min_uclk_urgent / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_urgent.dram_derate_percent_pixel / 100); 65 65 + min_uclk_urgent = dram_bw_kbps_to_uclk_khz((unsigned long long)(mode_support_result->global.active.urgent_bw_dram_kbps 66 66 + / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_urgent.dram_derate_percent_pixel / 100)), 67 67 + &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); 74 68 75 69 min_uclk_bw = min_uclk_urgent > min_uclk_avg ? min_uclk_urgent : min_uclk_avg; 76 70 ··· 111 97 const struct dml2_core_mode_support_result *mode_support_result = &in_out->display_cfg->mode_support_result; 112 98 113 99 /* assumes DF throttling is enabled */ 114 114 - min_uclk_avg = dram_bw_kbps_to_uclk_khz(mode_support_result->global.svp_prefetch.average_bw_dram_kbps, &in_out->soc_bb->clk_table.dram_config); 115 115 - min_uclk_avg = (double)min_uclk_avg / ((double)in_out->soc_bb->qos_parameters.derate_table.dcn_mall_prefetch_average.dram_derate_percent_pixel / 100); 100 100 + min_uclk_avg = dram_bw_kbps_to_uclk_khz((unsigned long long)(mode_support_result->global.svp_prefetch.average_bw_dram_kbps 101 101 + / ((double)in_out->soc_bb->qos_parameters.derate_table.dcn_mall_prefetch_average.dram_derate_percent_pixel / 100)), 102 102 + &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); 116 103 117 117 - min_uclk_urgent = dram_bw_kbps_to_uclk_khz(mode_support_result->global.svp_prefetch.urgent_bw_dram_kbps, &in_out->soc_bb->clk_table.dram_config); 118 118 - min_uclk_urgent = (double)min_uclk_urgent / ((double)in_out->soc_bb->qos_parameters.derate_table.dcn_mall_prefetch_urgent.dram_derate_percent_pixel / 100); 104 104 + min_uclk_urgent = dram_bw_kbps_to_uclk_khz((unsigned long long)(mode_support_result->global.svp_prefetch.urgent_bw_dram_kbps 105 105 + / ((double)in_out->soc_bb->qos_parameters.derate_table.dcn_mall_prefetch_urgent.dram_derate_percent_pixel / 100)), 106 106 + &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); 119 107 120 108 min_uclk_bw = min_uclk_urgent > min_uclk_avg ? min_uclk_urgent : min_uclk_avg; 121 109 ··· 144 128 in_out->programming->min_clocks.dcn4x.svp_prefetch.dcfclk_khz = dml_round_up(min_dcfclk_bw > min_dcfclk_latency ? min_dcfclk_bw : min_dcfclk_latency); 145 129 146 130 /* assumes DF throttling is disabled */ 147 147 - min_uclk_avg = dram_bw_kbps_to_uclk_khz(mode_support_result->global.svp_prefetch.average_bw_dram_kbps, &in_out->soc_bb->clk_table.dram_config); 148 148 - min_uclk_avg = (double)min_uclk_avg / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_average.dram_derate_percent_pixel / 100); 131 131 + min_uclk_avg = dram_bw_kbps_to_uclk_khz((unsigned long long)(mode_support_result->global.svp_prefetch.average_bw_dram_kbps 132 132 + / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_average.dram_derate_percent_pixel / 100)), 133 133 + &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); 149 134 150 150 - min_uclk_urgent = dram_bw_kbps_to_uclk_khz(mode_support_result->global.svp_prefetch.urgent_bw_dram_kbps, &in_out->soc_bb->clk_table.dram_config); 151 151 - min_uclk_urgent = (double)min_uclk_urgent / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_urgent.dram_derate_percent_pixel / 100); 135 135 + min_uclk_urgent = dram_bw_kbps_to_uclk_khz((unsigned long long)(mode_support_result->global.svp_prefetch.urgent_bw_dram_kbps 136 136 + / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_urgent.dram_derate_percent_pixel / 100)), 137 137 + &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); 152 138 153 139 min_uclk_bw = min_uclk_urgent > min_uclk_avg ? min_uclk_urgent : min_uclk_avg; 154 140 ··· 185 167 double min_uclk_latency, min_fclk_latency, min_dcfclk_latency; 186 168 const struct dml2_core_mode_support_result *mode_support_result = &in_out->display_cfg->mode_support_result; 187 169 188 188 - min_uclk_avg = dram_bw_kbps_to_uclk_khz(mode_support_result->global.active.average_bw_dram_kbps, &in_out->soc_bb->clk_table.dram_config); 189 189 - min_uclk_avg = (double)min_uclk_avg / ((double)in_out->soc_bb->qos_parameters.derate_table.system_idle_average.dram_derate_percent_pixel / 100); 170 170 + min_uclk_avg = dram_bw_kbps_to_uclk_khz((unsigned long long)(mode_support_result->global.active.average_bw_dram_kbps 171 171 + / ((double)in_out->soc_bb->qos_parameters.derate_table.system_idle_average.dram_derate_percent_pixel / 100)), 172 172 + &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); 190 173 191 174 min_fclk_avg = (double)mode_support_result->global.active.average_bw_sdp_kbps / in_out->soc_bb->fabric_datapath_to_dcn_data_return_bytes; 192 175 min_fclk_avg = (double)min_fclk_avg / ((double)in_out->soc_bb->qos_parameters.derate_table.system_idle_average.fclk_derate_percent / 100);

+1

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_internal_shared_types.h

reviewed

··· 16 16 17 17 struct dram_bw_to_min_clk_table_entry { 18 18 unsigned long long pre_derate_dram_bw_kbps; 19 19 + unsigned long min_uclk_khz; 19 20 unsigned long min_fclk_khz; 20 21 unsigned long min_dcfclk_khz; 21 22 };

+1

drivers/gpu/drm/amd/display/dc/dsc/dsc.h

reviewed

··· 115 115 void (*dsc_disconnect)(struct display_stream_compressor *dsc); 116 116 void (*dsc_wait_disconnect_pending_clear)(struct display_stream_compressor *dsc); 117 117 void (*dsc_get_single_enc_caps)(struct dsc_enc_caps *dsc_enc_caps, unsigned int max_dscclk_khz); 118 118 + void (*set_fgcg)(struct display_stream_compressor *dsc, bool enable); 118 119 }; 119 120 120 121 #endif

+1 -1

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_cm_common.h

reviewed

··· 59 59 const struct pwl_params *params, 60 60 const struct dcn3_xfer_func_reg *reg); 61 61 62 62 - bool cm3_helper_translate_curve_to_hw_format( 62 62 + bool cm3_helper_translate_curve_to_hw_format(struct dc_context *ctx, 63 63 const struct dc_transfer_func *output_tf, 64 64 struct pwl_params *lut_params, bool fixpoint); 65 65

+2

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

reviewed

··· 145 145 { 146 146 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); 147 147 148 148 + ASSERT(info->gfxversion == DcGfxVersion9); 149 149 + 148 150 REG_UPDATE_6(DCSURF_ADDR_CONFIG, 149 151 NUM_PIPES, log_2(info->gfx9.num_pipes), 150 152 NUM_BANKS, log_2(info->gfx9.num_banks),

+2

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

reviewed

··· 313 313 const struct dc_tiling_info *info, 314 314 const enum surface_pixel_format pixel_format) 315 315 { 316 316 + ASSERT(info->gfxversion == DcGfxVersion9); 317 317 + 316 318 REG_UPDATE_3(DCSURF_ADDR_CONFIG, 317 319 NUM_PIPES, log_2(info->gfx9.num_pipes), 318 320 PIPE_INTERLEAVE, info->gfx9.pipe_interleave,

+2

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

reviewed

··· 321 321 const struct dc_tiling_info *info, 322 322 const enum surface_pixel_format pixel_format) 323 323 { 324 324 + ASSERT(info->gfxversion == DcGfxVersion9); 325 325 + 324 326 REG_UPDATE_4(DCSURF_ADDR_CONFIG, 325 327 NUM_PIPES, log_2(info->gfx9.num_pipes), 326 328 PIPE_INTERLEAVE, info->gfx9.pipe_interleave,

+6 -1

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

reviewed

··· 589 589 * 590 590 * DIM_TYPE field in DCSURF_TILING for Display is always 1 (2D dimension) which is HW default. 591 591 */ 592 592 - REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, info->gfx_addr3.swizzle); 592 592 + if (info->gfxversion == DcGfxAddr3) { 593 593 + REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, info->gfx_addr3.swizzle); 594 594 + } else { 595 595 + /* linear */ 596 596 + REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, 0); 597 597 + } 593 598 } 594 599 595 600 void hubp401_program_size(

+5 -4

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

reviewed

··· 50 50 #include "link_hwss.h" 51 51 #include "dpcd_defs.h" 52 52 #include "dsc.h" 53 53 + #include "dio/dcn10/dcn10_dio.h" 53 54 #include "dce/dmub_psr.h" 54 55 #include "dc_dmub_srv.h" 55 56 #include "dce/dmub_hw_lock_mgr.h" ··· 1882 1881 1883 1882 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ 1884 1883 if (!is_optimized_init_done) 1885 1885 - REG_WRITE(DIO_MEM_PWR_CTRL, 0); 1884 1884 + if (dc->res_pool->dio && dc->res_pool->dio->funcs->mem_pwr_ctrl) 1885 1885 + dc->res_pool->dio->funcs->mem_pwr_ctrl(dc->res_pool->dio, false); 1886 1886 1887 1887 if (!dc->debug.disable_clock_gate) { 1888 1888 /* enable all DCN clock gating */ 1889 1889 - REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 1890 1890 - 1891 1891 - REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 1889 1889 + if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating) 1890 1890 + dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true); 1892 1891 1893 1892 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 1894 1893 }

+9 -21

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

reviewed

··· 357 357 358 358 void dcn20_dccg_init(struct dce_hwseq *hws) 359 359 { 360 360 - /* 361 361 - * set MICROSECOND_TIME_BASE_DIV 362 362 - * 100Mhz refclk -> 0x120264 363 363 - * 27Mhz refclk -> 0x12021b 364 364 - * 48Mhz refclk -> 0x120230 365 365 - * 366 366 - */ 367 367 - REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264); 360 360 + struct dc *dc = hws->ctx->dc; 368 361 369 369 - /* 370 370 - * set MILLISECOND_TIME_BASE_DIV 371 371 - * 100Mhz refclk -> 0x1186a0 372 372 - * 27Mhz refclk -> 0x106978 373 373 - * 48Mhz refclk -> 0x10bb80 374 374 - * 375 375 - */ 376 376 - REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0); 377 377 - 378 378 - /* This value is dependent on the hardware pipeline delay so set once per SOC */ 379 379 - REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0xe01003c); 362 362 + if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->dccg_init) 363 363 + dc->res_pool->dccg->funcs->dccg_init(dc->res_pool->dccg); 380 364 } 381 365 382 366 void dcn20_disable_vga( ··· 3139 3155 REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF); 3140 3156 3141 3157 dcn10_hubbub_global_timer_enable(dc->res_pool->hubbub, true, 2); 3142 3142 - if (REG(REFCLK_CNTL)) 3143 3143 - REG_WRITE(REFCLK_CNTL, 0); 3158 3158 + 3159 3159 + if (hws->funcs.dccg_init) 3160 3160 + hws->funcs.dccg_init(hws); 3161 3161 + 3162 3162 + if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->refclk_setup) 3163 3163 + dc->res_pool->dccg->funcs->refclk_setup(dc->res_pool->dccg); 3144 3164 // 3145 3165 3146 3166

+6 -4

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

reviewed

··· 40 40 #include "clk_mgr.h" 41 41 #include "reg_helper.h" 42 42 #include "dcn10/dcn10_hubbub.h" 43 43 + #include "dio/dcn10/dcn10_dio.h" 44 44 + 43 45 44 46 #define CTX \ 45 47 hws->ctx ··· 362 360 } 363 361 364 362 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ 365 365 - REG_WRITE(DIO_MEM_PWR_CTRL, 0); 363 363 + if (dc->res_pool->dio && dc->res_pool->dio->funcs->mem_pwr_ctrl) 364 364 + dc->res_pool->dio->funcs->mem_pwr_ctrl(dc->res_pool->dio, false); 366 365 367 366 if (!dc->debug.disable_clock_gate) { 368 367 /* enable all DCN clock gating */ 369 369 - REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 370 370 - 371 371 - REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 368 368 + if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating) 369 369 + dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true); 372 370 373 371 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 374 372 }

+4 -5

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

reviewed

··· 33 33 #include "vmid.h" 34 34 #include "reg_helper.h" 35 35 #include "hw/clk_mgr.h" 36 36 + #include "hw/dccg.h" 36 37 #include "dc_dmub_srv.h" 37 38 #include "abm.h" 38 39 #include "link_service.h" ··· 88 87 89 88 bool dcn21_s0i3_golden_init_wa(struct dc *dc) 90 89 { 91 91 - struct dce_hwseq *hws = dc->hwseq; 92 92 - uint32_t value = 0; 90 90 + if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->is_s0i3_golden_init_wa_done) 91 91 + return !dc->res_pool->dccg->funcs->is_s0i3_golden_init_wa_done(dc->res_pool->dccg); 93 92 94 94 - value = REG_READ(MICROSECOND_TIME_BASE_DIV); 95 95 - 96 96 - return value != 0x00120464; 93 93 + return false; 97 94 } 98 95 99 96 void dcn21_exit_optimized_pwr_state(

+10 -8

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

reviewed

··· 53 53 #include "dcn30/dcn30_resource.h" 54 54 #include "link_service.h" 55 55 #include "dc_state_priv.h" 56 56 + #include "dio/dcn10/dcn10_dio.h" 56 57 57 58 #define TO_DCN_DCCG(dccg)\ 58 59 container_of(dccg, struct dcn_dccg, base) ··· 241 240 if (plane_state->blend_tf.type == TF_TYPE_HWPWL) 242 241 blend_lut = &plane_state->blend_tf.pwl; 243 242 else if (plane_state->blend_tf.type == TF_TYPE_DISTRIBUTED_POINTS) { 244 244 - result = cm3_helper_translate_curve_to_hw_format( 243 243 + result = cm3_helper_translate_curve_to_hw_format(plane_state->ctx, 245 244 &plane_state->blend_tf, &dpp_base->regamma_params, false); 246 245 if (!result) 247 246 return result; ··· 336 335 if (plane_state->in_transfer_func.type == TF_TYPE_HWPWL) 337 336 params = &plane_state->in_transfer_func.pwl; 338 337 else if (plane_state->in_transfer_func.type == TF_TYPE_DISTRIBUTED_POINTS && 339 339 - cm3_helper_translate_curve_to_hw_format(&plane_state->in_transfer_func, 340 340 - &dpp_base->degamma_params, false)) 338 338 + cm3_helper_translate_curve_to_hw_format(plane_state->ctx, 339 339 + &plane_state->in_transfer_func, 340 340 + &dpp_base->degamma_params, false)) 341 341 params = &dpp_base->degamma_params; 342 342 343 343 result = dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params); ··· 409 407 params = &stream->out_transfer_func.pwl; 410 408 else if (pipe_ctx->stream->out_transfer_func.type == 411 409 TF_TYPE_DISTRIBUTED_POINTS && 412 412 - cm3_helper_translate_curve_to_hw_format( 410 410 + cm3_helper_translate_curve_to_hw_format(stream->ctx, 413 411 &stream->out_transfer_func, 414 412 &mpc->blender_params, false)) 415 413 params = &mpc->blender_params; ··· 796 794 } 797 795 798 796 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ 799 799 - REG_WRITE(DIO_MEM_PWR_CTRL, 0); 797 797 + if (dc->res_pool->dio && dc->res_pool->dio->funcs->mem_pwr_ctrl) 798 798 + dc->res_pool->dio->funcs->mem_pwr_ctrl(dc->res_pool->dio, false); 800 799 801 800 if (!dc->debug.disable_clock_gate) { 802 801 /* enable all DCN clock gating */ 803 803 - REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 804 804 - 805 805 - REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 802 802 + if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating) 803 803 + dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true); 806 804 807 805 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 808 806 }

+6 -9

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

reviewed

··· 53 53 #include "dcn30/dcn30_vpg.h" 54 54 #include "dce/dce_i2c_hw.h" 55 55 #include "dce/dmub_abm_lcd.h" 56 56 + #include "dio/dcn10/dcn10_dio.h" 56 57 57 58 #define DC_LOGGER_INIT(logger) 58 59 ··· 238 237 abms[i]->funcs->abm_init(abms[i], backlight, user_level); 239 238 } 240 239 241 241 - /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ 242 242 - REG_WRITE(DIO_MEM_PWR_CTRL, 0); 243 243 - 244 244 - // Set i2c to light sleep until engine is setup 245 245 - if (dc->debug.enable_mem_low_power.bits.i2c) 246 246 - REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 1); 240 240 + /* Power on DIO memory (AFMT HDMI) and set I2C to light sleep */ 241 241 + if (dc->res_pool->dio && dc->res_pool->dio->funcs->mem_pwr_ctrl) 242 242 + dc->res_pool->dio->funcs->mem_pwr_ctrl(dc->res_pool->dio, dc->debug.enable_mem_low_power.bits.i2c); 247 243 248 244 if (hws->funcs.setup_hpo_hw_control) 249 245 hws->funcs.setup_hpo_hw_control(hws, false); 250 246 251 247 if (!dc->debug.disable_clock_gate) { 252 248 /* enable all DCN clock gating */ 253 253 - REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 254 254 - 255 255 - REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 249 249 + if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating) 250 250 + dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true); 256 251 257 252 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 258 253 }

+15 -12

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

reviewed

··· 52 52 #include "link_service.h" 53 53 #include "../dcn20/dcn20_hwseq.h" 54 54 #include "dc_state_priv.h" 55 55 + #include "dio/dcn10/dcn10_dio.h" 55 56 56 57 #define DC_LOGGER_INIT(logger) 57 58 ··· 493 492 if (plane_state->blend_tf.type == TF_TYPE_HWPWL) 494 493 lut_params = &plane_state->blend_tf.pwl; 495 494 else if (plane_state->blend_tf.type == TF_TYPE_DISTRIBUTED_POINTS) { 496 496 - result = cm3_helper_translate_curve_to_hw_format(&plane_state->blend_tf, 497 497 - &dpp_base->regamma_params, false); 495 495 + result = cm3_helper_translate_curve_to_hw_format(plane_state->ctx, 496 496 + &plane_state->blend_tf, 497 497 + &dpp_base->regamma_params, false); 498 498 if (!result) 499 499 return result; 500 500 ··· 509 507 lut_params = &plane_state->in_shaper_func.pwl; 510 508 else if (plane_state->in_shaper_func.type == TF_TYPE_DISTRIBUTED_POINTS) { 511 509 // TODO: dpp_base replace 512 512 - ASSERT(false); 513 513 - cm3_helper_translate_curve_to_hw_format(&plane_state->in_shaper_func, 514 514 - &dpp_base->shaper_params, true); 510 510 + cm3_helper_translate_curve_to_hw_format(plane_state->ctx, 511 511 + &plane_state->in_shaper_func, 512 512 + &dpp_base->shaper_params, true); 515 513 lut_params = &dpp_base->shaper_params; 516 514 } 517 515 ··· 551 549 if (plane_state->in_transfer_func.type == TF_TYPE_HWPWL) 552 550 params = &plane_state->in_transfer_func.pwl; 553 551 else if (plane_state->in_transfer_func.type == TF_TYPE_DISTRIBUTED_POINTS && 554 554 - cm3_helper_translate_curve_to_hw_format(&plane_state->in_transfer_func, 555 555 - &dpp_base->degamma_params, false)) 552 552 + cm3_helper_translate_curve_to_hw_format(plane_state->ctx, 553 553 + &plane_state->in_transfer_func, 554 554 + &dpp_base->degamma_params, false)) 556 555 params = &dpp_base->degamma_params; 557 556 558 557 dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params); ··· 584 581 params = &stream->out_transfer_func.pwl; 585 582 else if (pipe_ctx->stream->out_transfer_func.type == 586 583 TF_TYPE_DISTRIBUTED_POINTS && 587 587 - cm3_helper_translate_curve_to_hw_format( 584 584 + cm3_helper_translate_curve_to_hw_format(stream->ctx, 588 585 &stream->out_transfer_func, 589 586 &mpc->blender_params, false)) 590 587 params = &mpc->blender_params; ··· 958 955 } 959 956 960 957 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ 961 961 - REG_WRITE(DIO_MEM_PWR_CTRL, 0); 958 958 + if (dc->res_pool->dio && dc->res_pool->dio->funcs->mem_pwr_ctrl) 959 959 + dc->res_pool->dio->funcs->mem_pwr_ctrl(dc->res_pool->dio, false); 962 960 963 961 if (!dc->debug.disable_clock_gate) { 964 962 /* enable all DCN clock gating */ 965 965 - REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 966 966 - 967 967 - REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 963 963 + if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating) 964 964 + dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true); 968 965 969 966 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 970 967 }

+6 -7

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

reviewed

··· 53 53 #include "dcn30/dcn30_vpg.h" 54 54 #include "dce/dce_i2c_hw.h" 55 55 #include "dsc.h" 56 56 + #include "dio/dcn10/dcn10_dio.h" 56 57 #include "dcn20/dcn20_optc.h" 57 58 #include "dcn30/dcn30_cm_common.h" 58 59 #include "dcn31/dcn31_hwseq.h" ··· 273 272 } 274 273 } 275 274 276 276 - /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ 277 277 - REG_WRITE(DIO_MEM_PWR_CTRL, 0); 278 278 - 279 279 - // Set i2c to light sleep until engine is setup 280 280 - if (dc->debug.enable_mem_low_power.bits.i2c) 281 281 - REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 0); 275 275 + /* Power on DIO memory (AFMT HDMI) and optionally disable I2C light sleep */ 276 276 + if (dc->res_pool->dio && dc->res_pool->dio->funcs->mem_pwr_ctrl) 277 277 + dc->res_pool->dio->funcs->mem_pwr_ctrl(dc->res_pool->dio, !dc->debug.enable_mem_low_power.bits.i2c); 282 278 283 279 if (hws->funcs.setup_hpo_hw_control) 284 280 hws->funcs.setup_hpo_hw_control(hws, false); ··· 286 288 } 287 289 288 290 if (dc->debug.disable_mem_low_power) { 289 289 - REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, 1); 291 291 + if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->enable_memory_low_power) 292 292 + dc->res_pool->dccg->funcs->enable_memory_low_power(dc->res_pool->dccg, false); 290 293 } 291 294 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) 292 295 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);

+14 -11

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

reviewed

··· 39 39 #include "dc_state_priv.h" 40 40 #include "link_enc_cfg.h" 41 41 #include "../hw_sequencer.h" 42 42 + #include "dio/dcn10/dcn10_dio.h" 42 43 43 44 #define DC_LOGGER_INIT(logger) 44 45 ··· 321 320 } 322 321 323 322 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ 324 324 - REG_WRITE(DIO_MEM_PWR_CTRL, 0); 323 323 + if (dc->res_pool->dio && dc->res_pool->dio->funcs->mem_pwr_ctrl) 324 324 + dc->res_pool->dio->funcs->mem_pwr_ctrl(dc->res_pool->dio, false); 325 325 326 326 if (!dc->debug.disable_clock_gate) { 327 327 /* enable all DCN clock gating */ 328 328 - REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 329 329 - 330 330 - REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 328 328 + if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating) 329 329 + dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true); 331 330 332 331 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 333 332 } ··· 432 431 if (mcm_luts.lut1d_func->type == TF_TYPE_HWPWL) 433 432 m_lut_params.pwl = &mcm_luts.lut1d_func->pwl; 434 433 else if (mcm_luts.lut1d_func->type == TF_TYPE_DISTRIBUTED_POINTS) { 435 435 - rval = cm3_helper_translate_curve_to_hw_format( 434 434 + rval = cm3_helper_translate_curve_to_hw_format(mpc->ctx, 436 435 mcm_luts.lut1d_func, 437 436 &dpp_base->regamma_params, false); 438 437 m_lut_params.pwl = rval ? &dpp_base->regamma_params : NULL; ··· 452 451 m_lut_params.pwl = &mcm_luts.shaper->pwl; 453 452 else if (mcm_luts.shaper->type == TF_TYPE_DISTRIBUTED_POINTS) { 454 453 ASSERT(false); 455 455 - rval = cm3_helper_translate_curve_to_hw_format( 454 454 + rval = cm3_helper_translate_curve_to_hw_format(mpc->ctx, 456 455 mcm_luts.shaper, 457 456 &dpp_base->regamma_params, true); 458 457 m_lut_params.pwl = rval ? &dpp_base->regamma_params : NULL; ··· 629 628 if (plane_state->blend_tf.type == TF_TYPE_HWPWL) 630 629 lut_params = &plane_state->blend_tf.pwl; 631 630 else if (plane_state->blend_tf.type == TF_TYPE_DISTRIBUTED_POINTS) { 632 632 - rval = cm3_helper_translate_curve_to_hw_format(&plane_state->blend_tf, 633 633 - &dpp_base->regamma_params, false); 631 631 + rval = cm3_helper_translate_curve_to_hw_format(plane_state->ctx, 632 632 + &plane_state->blend_tf, 633 633 + &dpp_base->regamma_params, false); 634 634 lut_params = rval ? &dpp_base->regamma_params : NULL; 635 635 } 636 636 result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id); ··· 642 640 lut_params = &plane_state->in_shaper_func.pwl; 643 641 else if (plane_state->in_shaper_func.type == TF_TYPE_DISTRIBUTED_POINTS) { 644 642 // TODO: dpp_base replace 645 645 - rval = cm3_helper_translate_curve_to_hw_format(&plane_state->in_shaper_func, 646 646 - &dpp_base->shaper_params, true); 643 643 + rval = cm3_helper_translate_curve_to_hw_format(plane_state->ctx, 644 644 + &plane_state->in_shaper_func, 645 645 + &dpp_base->shaper_params, true); 647 646 lut_params = rval ? &dpp_base->shaper_params : NULL; 648 647 } 649 648 result &= mpc->funcs->program_shaper(mpc, lut_params, mpcc_id); ··· 678 675 params = &stream->out_transfer_func.pwl; 679 676 else if (pipe_ctx->stream->out_transfer_func.type == 680 677 TF_TYPE_DISTRIBUTED_POINTS && 681 681 - cm3_helper_translate_curve_to_hw_format( 678 678 + cm3_helper_translate_curve_to_hw_format(stream->ctx, 682 679 &stream->out_transfer_func, 683 680 &mpc->blender_params, false)) 684 681 params = &mpc->blender_params;

+2

drivers/gpu/drm/amd/display/dc/inc/core_types.h

reviewed

··· 35 35 #include "hubp.h" 36 36 #include "mpc.h" 37 37 #include "dwb.h" 38 38 + #include "hw/dio.h" 38 39 #include "mcif_wb.h" 39 40 #include "panel_cntl.h" 40 41 #include "dmub/inc/dmub_cmd.h" ··· 251 250 struct timing_generator *timing_generators[MAX_PIPES]; 252 251 struct stream_encoder *stream_enc[MAX_PIPES * 2]; 253 252 struct hubbub *hubbub; 253 253 + struct dio *dio; 254 254 struct mpc *mpc; 255 255 struct pp_smu_funcs *pp_smu; 256 256 struct dce_aux *engines[MAX_PIPES];

+4

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

reviewed

··· 224 224 void (*otg_drop_pixel)(struct dccg *dccg, 225 225 uint32_t otg_inst); 226 226 void (*dccg_init)(struct dccg *dccg); 227 227 + void (*refclk_setup)(struct dccg *dccg); /* Deprecated - for backward compatibility only */ 228 228 + void (*allow_clock_gating)(struct dccg *dccg, bool allow); 229 229 + void (*enable_memory_low_power)(struct dccg *dccg, bool enable); 227 230 void (*set_dpstreamclk_root_clock_gating)( 228 231 struct dccg *dccg, 229 232 int dp_hpo_inst, ··· 337 334 void (*dccg_root_gate_disable_control)(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating); 338 335 void (*dccg_read_reg_state)(struct dccg *dccg, struct dcn_dccg_reg_state *dccg_reg_state); 339 336 void (*dccg_enable_global_fgcg)(struct dccg *dccg, bool enable); 337 337 + bool (*is_s0i3_golden_init_wa_done)(struct dccg *dccg); 340 338 }; 341 339 342 340 #endif //__DAL_DCCG_H__

+22

drivers/gpu/drm/amd/display/dc/inc/hw/dio.h

reviewed

··· 1 1 + // SPDX-License-Identifier: MIT 2 2 + // 3 3 + // Copyright 2025 Advanced Micro Devices, Inc. 4 4 + 5 5 + #ifndef __DC_DIO_H__ 6 6 + #define __DC_DIO_H__ 7 7 + 8 8 + #include "dc_types.h" 9 9 + 10 10 + struct dc_context; 11 11 + struct dio; 12 12 + 13 13 + struct dio_funcs { 14 14 + void (*mem_pwr_ctrl)(struct dio *dio, bool enable_i2c_light_sleep); 15 15 + }; 16 16 + 17 17 + struct dio { 18 18 + const struct dio_funcs *funcs; 19 19 + struct dc_context *ctx; 20 20 + }; 21 21 + 22 22 + #endif /* __DC_DIO_H__ */

+7

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

reviewed

··· 122 122 VBLANK_SYNCHRONIZABLE 123 123 }; 124 124 125 125 + enum crc_poly_mode { 126 126 + CRC_POLY_MODE_16, 127 127 + CRC_POLY_MODE_32, 128 128 + CRC_POLY_MODE_MAX, 129 129 + }; 130 130 + 125 131 struct crc_params { 126 132 /* Regions used to calculate CRC*/ 127 133 uint16_t windowa_x_start; ··· 150 144 151 145 uint8_t crc_eng_inst; 152 146 bool reset; 147 147 + enum crc_poly_mode crc_poly_mode; 153 148 }; 154 149 155 150 struct dcn_otg_state {

+52

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

reviewed

··· 35 35 36 36 #define DP_SINK_PR_ENABLE_AND_CONFIGURATION 0x37B 37 37 38 38 + static unsigned int dp_pr_calc_num_static_frames(unsigned int vsync_rate_hz) 39 39 + { 40 40 + // at least 2 frames for static screen 41 41 + unsigned int num_frames = 2; 42 42 + 43 43 + // get number of frames for at least 50ms 44 44 + if (vsync_rate_hz > 40) 45 45 + num_frames = (vsync_rate_hz + 10) / 20; 46 46 + 47 47 + return num_frames; 48 48 + } 49 49 + 50 50 + static void dp_pr_set_static_screen_param(struct dc_link *link) 51 51 + { 52 52 + struct dc_static_screen_params params = {0}; 53 53 + struct dc *dc = link->ctx->dc; 54 54 + // only support DP sst for now 55 55 + if (!dc_is_dp_sst_signal(link->connector_signal)) 56 56 + return; 57 57 + 58 58 + for (int i = 0; i < MAX_PIPES; i++) { 59 59 + if (dc->current_state->res_ctx.pipe_ctx[i].stream && 60 60 + dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) { 61 61 + struct dc_stream_state *stream = dc->current_state->res_ctx.pipe_ctx[i].stream; 62 62 + unsigned int vsync_rate_hz = div64_u64(div64_u64( 63 63 + (stream->timing.pix_clk_100hz * (u64)100), 64 64 + stream->timing.v_total), 65 65 + stream->timing.h_total); 66 66 + 67 67 + params.triggers.cursor_update = true; 68 68 + params.triggers.overlay_update = true; 69 69 + params.triggers.surface_update = true; 70 70 + params.num_frames = dp_pr_calc_num_static_frames(vsync_rate_hz); 71 71 + 72 72 + dc_stream_set_static_screen_params(dc, &stream, 1, &params); 73 73 + break; 74 74 + } 75 75 + } 76 76 + } 77 77 + 38 78 static bool dp_setup_panel_replay(struct dc_link *link, const struct dc_stream_state *stream) 39 79 { 40 80 /* To-do: Setup Replay */ ··· 199 159 if (!dc || !link || !inst_out) 200 160 return false; 201 161 162 162 + if (dc->config.frame_update_cmd_version2 == false) 163 163 + return dc_get_edp_link_panel_inst(dc, link, inst_out); 164 164 + 202 165 if (!dc_is_dp_sst_signal(link->connector_signal)) /* only supoprt DP sst (eDP included) for now */ 203 166 return false; 204 167 ··· 241 198 242 199 if (!dp_pr_get_panel_inst(dc, link, &panel_inst)) 243 200 return false; 201 201 + 202 202 + if (enable && !dc_is_embedded_signal(link->connector_signal)) 203 203 + dp_pr_set_static_screen_param(link); 244 204 245 205 if (link->replay_settings.replay_allow_active != enable) { 246 206 //for sending PR enable commands to DMUB ··· 321 275 cmd.pr_copy_settings.data.dsc_slice_height = (pipe_ctx->stream->timing.v_addressable + 322 276 pipe_ctx->stream->timing.v_border_top + pipe_ctx->stream->timing.v_border_bottom) / 323 277 pipe_ctx->stream->timing.dsc_cfg.num_slices_v; 278 278 + 279 279 + if (dc_is_embedded_signal(link->connector_signal)) 280 280 + cmd.pr_copy_settings.data.main_link_activity_option = 0x03;//OPTION_1C; 281 281 + else 282 282 + // For external DP, use option 1-A 283 283 + cmd.pr_copy_settings.data.main_link_activity_option = 0x01;//OPTION_1A; 324 284 325 285 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 326 286 return true;

+18 -1

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h

reviewed

··· 244 244 uint32_t OTG_TRIGB_MANUAL_TRIG; \ 245 245 uint32_t OTG_UPDATE_LOCK; \ 246 246 uint32_t OTG_V_TOTAL_INT_STATUS; \ 247 247 - uint32_t OTG_VSYNC_NOM_INT_STATUS 247 247 + uint32_t OTG_VSYNC_NOM_INT_STATUS; \ 248 248 + uint32_t OTG_CRC0_DATA_R32; \ 249 249 + uint32_t OTG_CRC0_DATA_G32; \ 250 250 + uint32_t OTG_CRC0_DATA_B32; \ 251 251 + uint32_t OTG_CRC1_DATA_R32; \ 252 252 + uint32_t OTG_CRC1_DATA_G32; \ 253 253 + uint32_t OTG_CRC1_DATA_B32 248 254 249 255 250 256 struct dcn_optc_registers { ··· 663 657 type OTG_V_COUNT_STOP;\ 664 658 type OTG_V_COUNT_STOP_TIMER; 665 659 660 660 + #define TG_REG_FIELD_LIST_DCN3_6(type) \ 661 661 + type OTG_CRC_POLY_SEL; \ 662 662 + type CRC0_R_CR32; \ 663 663 + type CRC0_G_Y32; \ 664 664 + type CRC0_B_CB32; \ 665 665 + type CRC1_R_CR32; \ 666 666 + type CRC1_G_Y32; \ 667 667 + type CRC1_B_CB32; 668 668 + 666 669 #define TG_REG_FIELD_LIST_DCN401(type) \ 667 670 type OPTC_SEGMENT_WIDTH_LAST;\ 668 671 type OTG_PSTATE_KEEPOUT_START;\ ··· 685 670 TG_REG_FIELD_LIST_DCN2_0(uint8_t) 686 671 TG_REG_FIELD_LIST_DCN3_2(uint8_t) 687 672 TG_REG_FIELD_LIST_DCN3_5(uint8_t) 673 673 + TG_REG_FIELD_LIST_DCN3_6(uint8_t) 688 674 TG_REG_FIELD_LIST_DCN401(uint8_t) 689 675 }; 690 676 ··· 694 678 TG_REG_FIELD_LIST_DCN2_0(uint32_t) 695 679 TG_REG_FIELD_LIST_DCN3_2(uint32_t) 696 680 TG_REG_FIELD_LIST_DCN3_5(uint32_t) 681 681 + TG_REG_FIELD_LIST_DCN3_6(uint32_t) 697 682 TG_REG_FIELD_LIST_DCN401(uint32_t) 698 683 }; 699 684

+95 -1

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

reviewed

··· 180 180 REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000); 181 181 } 182 182 183 183 + /** 184 184 + * optc35_get_crc - Capture CRC result per component 185 185 + * 186 186 + * @optc: timing_generator instance. 187 187 + * @idx: index of crc engine to get CRC from 188 188 + * @r_cr: primary CRC signature for red data. 189 189 + * @g_y: primary CRC signature for green data. 190 190 + * @b_cb: primary CRC signature for blue data. 191 191 + * 192 192 + * This function reads the CRC signature from the OPTC registers. Notice that 193 193 + * we have three registers to keep the CRC result per color component (RGB). 194 194 + * 195 195 + * For different DCN versions: 196 196 + * - If CRC32 registers (OTG_CRC0_DATA_R32/G32/B32) are available, read from 197 197 + * 32-bit CRC registers. DCN 3.6+ supports both CRC-32 and CRC-16 polynomials 198 198 + * selectable via OTG_CRC_POLY_SEL. 199 199 + * - Otherwise, read from legacy 16-bit CRC registers (OTG_CRC0_DATA_RG/B) 200 200 + * which only support CRC-16 polynomial. 201 201 + * 202 202 + * Returns: 203 203 + * If CRC is disabled, return false; otherwise, return true, and the CRC 204 204 + * results in the parameters. 205 205 + */ 206 206 + static bool optc35_get_crc(struct timing_generator *optc, uint8_t idx, 207 207 + uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb) 208 208 + { 209 209 + uint32_t field = 0; 210 210 + struct optc *optc1 = DCN10TG_FROM_TG(optc); 211 211 + 212 212 + REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field); 213 213 + 214 214 + /* Early return if CRC is not enabled for this CRTC */ 215 215 + if (!field) 216 216 + return false; 217 217 + 218 218 + if (optc1->tg_mask->CRC0_R_CR32 != 0 && optc1->tg_mask->CRC1_R_CR32 != 0 && 219 219 + optc1->tg_mask->CRC0_G_Y32 != 0 && optc1->tg_mask->CRC1_G_Y32 != 0 && 220 220 + optc1->tg_mask->CRC0_B_CB32 != 0 && optc1->tg_mask->CRC1_B_CB32 != 0) { 221 221 + switch (idx) { 222 222 + case 0: 223 223 + /* OTG_CRC0_DATA_R32/G32/B32 has the CRC32 results */ 224 224 + REG_GET(OTG_CRC0_DATA_R32, 225 225 + CRC0_R_CR32, r_cr); 226 226 + REG_GET(OTG_CRC0_DATA_G32, 227 227 + CRC0_G_Y32, g_y); 228 228 + REG_GET(OTG_CRC0_DATA_B32, 229 229 + CRC0_B_CB32, b_cb); 230 230 + break; 231 231 + case 1: 232 232 + /* OTG_CRC1_DATA_R32/G32/B32 has the CRC32 results */ 233 233 + REG_GET(OTG_CRC1_DATA_R32, 234 234 + CRC1_R_CR32, r_cr); 235 235 + REG_GET(OTG_CRC1_DATA_G32, 236 236 + CRC1_G_Y32, g_y); 237 237 + REG_GET(OTG_CRC1_DATA_B32, 238 238 + CRC1_B_CB32, b_cb); 239 239 + break; 240 240 + default: 241 241 + return false; 242 242 + } 243 243 + } else { 244 244 + switch (idx) { 245 245 + case 0: 246 246 + /* OTG_CRC0_DATA_RG has the CRC16 results for the red and green component */ 247 247 + REG_GET_2(OTG_CRC0_DATA_RG, 248 248 + CRC0_R_CR, r_cr, 249 249 + CRC0_G_Y, g_y); 250 250 + 251 251 + /* OTG_CRC0_DATA_B has the CRC16 results for the blue component */ 252 252 + REG_GET(OTG_CRC0_DATA_B, 253 253 + CRC0_B_CB, b_cb); 254 254 + break; 255 255 + case 1: 256 256 + /* OTG_CRC1_DATA_RG has the CRC16 results for the red and green component */ 257 257 + REG_GET_2(OTG_CRC1_DATA_RG, 258 258 + CRC1_R_CR, r_cr, 259 259 + CRC1_G_Y, g_y); 260 260 + 261 261 + /* OTG_CRC1_DATA_B has the CRC16 results for the blue component */ 262 262 + REG_GET(OTG_CRC1_DATA_B, 263 263 + CRC1_B_CB, b_cb); 264 264 + break; 265 265 + default: 266 266 + return false; 267 267 + } 268 268 + } 269 269 + 270 270 + return true; 271 271 + } 272 272 + 183 273 static bool optc35_configure_crc(struct timing_generator *optc, 184 274 const struct crc_params *params) 185 275 { ··· 355 265 break; 356 266 default: 357 267 return false; 268 268 + } 269 269 + if (optc1->tg_mask->OTG_CRC_POLY_SEL != 0) { 270 270 + REG_UPDATE(OTG_CRC_CNTL, 271 271 + OTG_CRC_POLY_SEL, params->crc_poly_mode); 358 272 } 359 273 return true; 360 274 } ··· 582 488 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred, 583 489 .clear_optc_underflow = optc1_clear_optc_underflow, 584 490 .setup_global_swap_lock = NULL, 585 585 - .get_crc = optc1_get_crc, 491 491 + .get_crc = optc35_get_crc, 586 492 .configure_crc = optc35_configure_crc, 587 493 .set_dsc_config = optc3_set_dsc_config, 588 494 .get_dsc_status = optc2_get_dsc_status,

+10

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h

reviewed

··· 74 74 SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh),\ 75 75 SF(OTG0_INTERRUPT_DEST, OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST, mask_sh) 76 76 77 77 + #define OPTC_COMMON_MASK_SH_LIST_DCN3_6(mask_sh)\ 78 78 + OPTC_COMMON_MASK_SH_LIST_DCN3_5(mask_sh),\ 79 79 + SF(OTG0_OTG_CRC_CNTL, OTG_CRC_POLY_SEL, mask_sh),\ 80 80 + SF(OTG_CRC320_OTG_CRC0_DATA_R32, CRC0_R_CR32, mask_sh),\ 81 81 + SF(OTG_CRC320_OTG_CRC0_DATA_G32, CRC0_G_Y32, mask_sh),\ 82 82 + SF(OTG_CRC320_OTG_CRC0_DATA_B32, CRC0_B_CB32, mask_sh),\ 83 83 + SF(OTG_CRC320_OTG_CRC1_DATA_R32, CRC1_R_CR32, mask_sh),\ 84 84 + SF(OTG_CRC320_OTG_CRC1_DATA_G32, CRC1_G_Y32, mask_sh),\ 85 85 + SF(OTG_CRC320_OTG_CRC1_DATA_B32, CRC1_B_CB32, mask_sh) 86 86 + 77 87 void dcn35_timing_generator_init(struct optc *optc1); 78 88 79 89 void dcn35_timing_generator_set_fgcg(struct optc *optc1, bool enable);

+2 -1

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c

reviewed

··· 401 401 */ 402 402 if (pipe_cnt == 1) { 403 403 pipes[0].pipe.src.det_size_override = DCN3_2_MAX_DET_SIZE; 404 404 - if (pipe->plane_state && !disable_unbounded_requesting && pipe->plane_state->tiling_info.gfx9.swizzle != DC_SW_LINEAR) { 404 404 + if (pipe->plane_state && !disable_unbounded_requesting && pipe->plane_state->tiling_info.gfxversion != DcGfxBase && 405 405 + !(pipe->plane_state->tiling_info.gfxversion == DcGfxVersion9 && pipe->plane_state->tiling_info.gfx9.swizzle == DC_SW_LINEAR)) { 405 406 if (!is_dual_plane(pipe->plane_state->format)) { 406 407 pipes[0].pipe.src.det_size_override = DCN3_2_DEFAULT_DET_SIZE; 407 408 pipes[0].pipe.src.unbounded_req_mode = true;

+9 -3

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

reviewed

··· 460 460 }; 461 461 462 462 #define optc_regs_init(id)\ 463 463 - OPTC_COMMON_REG_LIST_DCN3_5_RI(id) 463 463 + OPTC_COMMON_REG_LIST_DCN3_5_RI(id),\ 464 464 + SRI_ARR(OTG_CRC0_DATA_R32, OTG_CRC32, id),\ 465 465 + SRI_ARR(OTG_CRC0_DATA_G32, OTG_CRC32, id),\ 466 466 + SRI_ARR(OTG_CRC0_DATA_B32, OTG_CRC32, id),\ 467 467 + SRI_ARR(OTG_CRC1_DATA_R32, OTG_CRC32, id),\ 468 468 + SRI_ARR(OTG_CRC1_DATA_G32, OTG_CRC32, id),\ 469 469 + SRI_ARR(OTG_CRC1_DATA_B32, OTG_CRC32, id) 464 470 465 471 static struct dcn_optc_registers optc_regs[4]; 466 472 467 473 static const struct dcn_optc_shift optc_shift = { 468 468 - OPTC_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT) 474 474 + OPTC_COMMON_MASK_SH_LIST_DCN3_6(__SHIFT) 469 475 }; 470 476 471 477 static const struct dcn_optc_mask optc_mask = { 472 472 - OPTC_COMMON_MASK_SH_LIST_DCN3_5(_MASK) 478 478 + OPTC_COMMON_MASK_SH_LIST_DCN3_6(_MASK) 473 479 }; 474 480 475 481 #define hubp_regs_init(id)\

+46

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

reviewed

··· 21 21 #include "dcn401/dcn401_hubbub.h" 22 22 #include "dcn401/dcn401_mpc.h" 23 23 #include "dcn401/dcn401_hubp.h" 24 24 + #include "dio/dcn10/dcn10_dio.h" 24 25 #include "irq/dcn401/irq_service_dcn401.h" 25 26 #include "dcn401/dcn401_dpp.h" 26 27 #include "dcn401/dcn401_optc.h" ··· 635 634 DCN20_VMID_MASK_SH_LIST(_MASK) 636 635 }; 637 636 637 637 + #define dio_regs_init() \ 638 638 + DIO_REG_LIST_DCN10() 639 639 + 640 640 + static struct dcn_dio_registers dio_regs; 641 641 + 642 642 + #define DIO_MASK_SH_LIST_DCN401(mask_sh)\ 643 643 + HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh) 644 644 + 645 645 + static const struct dcn_dio_shift dio_shift = { 646 646 + DIO_MASK_SH_LIST_DCN401(__SHIFT) 647 647 + }; 648 648 + 649 649 + static const struct dcn_dio_mask dio_mask = { 650 650 + DIO_MASK_SH_LIST_DCN401(_MASK) 651 651 + }; 652 652 + 638 653 static const struct resource_caps res_cap_dcn4_01 = { 639 654 .num_timing_generator = 4, 640 655 .num_opp = 4, ··· 896 879 } 897 880 898 881 return &hubbub2->base; 882 882 + } 883 883 + 884 884 + static struct dio *dcn401_dio_create(struct dc_context *ctx) 885 885 + { 886 886 + struct dcn10_dio *dio10 = kzalloc(sizeof(struct dcn10_dio), GFP_KERNEL); 887 887 + 888 888 + if (!dio10) 889 889 + return NULL; 890 890 + 891 891 + #undef REG_STRUCT 892 892 + #define REG_STRUCT dio_regs 893 893 + dio_regs_init(); 894 894 + 895 895 + dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask); 896 896 + 897 897 + return &dio10->base; 899 898 } 900 899 901 900 static struct hubp *dcn401_hubp_create( ··· 1532 1499 if (pool->base.dccg != NULL) 1533 1500 dcn_dccg_destroy(&pool->base.dccg); 1534 1501 1502 1502 + if (pool->base.dio != NULL) { 1503 1503 + kfree(TO_DCN10_DIO(pool->base.dio)); 1504 1504 + pool->base.dio = NULL; 1505 1505 + } 1506 1506 + 1535 1507 if (pool->base.oem_device != NULL) { 1536 1508 struct dc *dc = pool->base.oem_device->ctx->dc; 1537 1509 ··· 2106 2068 if (pool->base.hubbub == NULL) { 2107 2069 BREAK_TO_DEBUGGER(); 2108 2070 dm_error("DC: failed to create hubbub!\n"); 2071 2071 + goto create_fail; 2072 2072 + } 2073 2073 + 2074 2074 + /* DIO */ 2075 2075 + pool->base.dio = dcn401_dio_create(ctx); 2076 2076 + if (pool->base.dio == NULL) { 2077 2077 + BREAK_TO_DEBUGGER(); 2078 2078 + dm_error("DC: failed to create dio!\n"); 2109 2079 goto create_fail; 2110 2080 } 2111 2081

+10

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

reviewed

··· 736 736 uint32_t u32All; 737 737 }; 738 738 739 739 + /** 740 740 + * Definition of Panel Replay ML Activity Options 741 741 + */ 742 742 + enum pr_ml_activity_option { 743 743 + OPTION_DEFAULT = 0x00, // VESA Option Default (1C) 744 744 + OPTION_1A = 0x01, // VESA Option 1A 745 745 + OPTION_1B = 0x02, // VESA Option 1B 746 746 + OPTION_1C = 0x03, // VESA Option 1C 747 747 + }; 748 748 + 739 749 union fw_assisted_mclk_switch_version { 740 750 struct { 741 751 uint8_t minor : 5;

+14 -5

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

reviewed

··· 1355 1355 int i, ret; 1356 1356 1357 1357 smu->pool_size = adev->pm.smu_prv_buffer_size; 1358 1358 - smu_feature_init(smu, SMU_FEATURE_MAX); 1358 1358 + smu_feature_init(smu, SMU_FEATURE_NUM_DEFAULT); 1359 1359 1360 1360 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1361 1361 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); ··· 1646 1646 { 1647 1647 struct amdgpu_device *adev = smu->adev; 1648 1648 uint8_t pcie_gen = 0, pcie_width = 0; 1649 1649 - uint64_t features_supported; 1649 1649 + struct smu_feature_bits features_supported; 1650 1650 int ret = 0; 1651 1651 1652 1652 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { ··· 1807 1807 return ret; 1808 1808 } 1809 1809 smu_feature_list_set_bits(smu, SMU_FEATURE_LIST_SUPPORTED, 1810 1810 - (unsigned long *)&features_supported); 1810 1810 + features_supported.bits); 1811 1811 1812 1812 if (!smu_is_dpm_running(smu)) 1813 1813 dev_info(adev->dev, "dpm has been disabled\n"); ··· 3152 3152 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100; 3153 3153 *size = 4; 3154 3154 break; 3155 3155 - case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 3156 3156 - ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); 3155 3155 + case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: { 3156 3156 + struct smu_feature_bits feature_mask; 3157 3157 + uint32_t features[2]; 3158 3158 + 3159 3159 + /* TBD: need to handle for > 64 bits */ 3160 3160 + ret = smu_feature_get_enabled_mask(smu, &feature_mask); 3161 3161 + if (!ret) { 3162 3162 + smu_feature_bits_to_arr32(&feature_mask, features, 64); 3163 3163 + *(uint64_t *)data = *(uint64_t *)features; 3164 3164 + } 3157 3165 *size = 8; 3158 3166 break; 3167 3167 + } 3159 3168 case AMDGPU_PP_SENSOR_UVD_POWER: 3160 3169 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 3161 3170 *size = 4;

+27 -2

drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h

reviewed

··· 471 471 struct smu_power_gate power_gate; 472 472 }; 473 473 474 474 - #define SMU_FEATURE_MAX (64) 474 474 + #define SMU_FEATURE_NUM_DEFAULT (64) 475 475 + #define SMU_FEATURE_MAX (128) 475 476 476 477 struct smu_feature_bits { 477 478 DECLARE_BITMAP(bits, SMU_FEATURE_MAX); 478 479 }; 480 480 + 481 481 + /* 482 482 + * Helpers for initializing smu_feature_bits statically. 483 483 + * Use SMU_FEATURE_BIT_INIT() which automatically handles array indexing: 484 484 + * static const struct smu_feature_bits example = { 485 485 + * .bits = { 486 486 + * SMU_FEATURE_BIT_INIT(5), 487 487 + * SMU_FEATURE_BIT_INIT(10), 488 488 + * SMU_FEATURE_BIT_INIT(65), 489 489 + * SMU_FEATURE_BIT_INIT(100) 490 490 + * } 491 491 + * }; 492 492 + */ 493 493 + #define SMU_FEATURE_BITS_ELEM(bit) ((bit) / BITS_PER_LONG) 494 494 + #define SMU_FEATURE_BITS_POS(bit) ((bit) % BITS_PER_LONG) 495 495 + #define SMU_FEATURE_BIT_INIT(bit) \ 496 496 + [SMU_FEATURE_BITS_ELEM(bit)] = (1UL << SMU_FEATURE_BITS_POS(bit)) 479 497 480 498 enum smu_feature_list { 481 499 SMU_FEATURE_LIST_SUPPORTED, ··· 1230 1212 * on the SMU. 1231 1213 * &feature_mask: Enabled feature mask. 1232 1214 */ 1233 1233 - int (*get_enabled_mask)(struct smu_context *smu, uint64_t *feature_mask); 1215 1215 + int (*get_enabled_mask)(struct smu_context *smu, 1216 1216 + struct smu_feature_bits *feature_mask); 1234 1217 1235 1218 /** 1236 1219 * @feature_is_enabled: Test if a feature is enabled. ··· 2061 2042 unsigned int nbits) 2062 2043 { 2063 2044 return bitmap_empty(bits->bits, nbits); 2045 2045 + } 2046 2046 + 2047 2047 + static inline bool smu_feature_bits_full(const struct smu_feature_bits *bits, 2048 2048 + unsigned int nbits) 2049 2049 + { 2050 2050 + return bitmap_full(bits->bits, nbits); 2064 2051 } 2065 2052 2066 2053 static inline void smu_feature_bits_copy(struct smu_feature_bits *dst,

+12 -10

drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

reviewed

··· 65 65 #define SMU_FEATURES_HIGH_MASK 0xFFFFFFFF00000000 66 66 #define SMU_FEATURES_HIGH_SHIFT 32 67 67 68 68 - #define SMC_DPM_FEATURE ( \ 69 69 - FEATURE_DPM_PREFETCHER_MASK | \ 70 70 - FEATURE_DPM_GFXCLK_MASK | \ 71 71 - FEATURE_DPM_UCLK_MASK | \ 72 72 - FEATURE_DPM_SOCCLK_MASK | \ 73 73 - FEATURE_DPM_MP0CLK_MASK | \ 74 74 - FEATURE_DPM_FCLK_MASK | \ 75 75 - FEATURE_DPM_XGMI_MASK) 68 68 + static const struct smu_feature_bits arcturus_dpm_features = { 69 69 + .bits = { SMU_FEATURE_BIT_INIT(FEATURE_DPM_PREFETCHER_BIT), 70 70 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT), 71 71 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK_BIT), 72 72 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_SOCCLK_BIT), 73 73 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_MP0CLK_BIT), 74 74 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_FCLK_BIT), 75 75 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_XGMI_BIT) } 76 76 + }; 76 77 77 78 #define smnPCIE_ESM_CTRL 0x111003D0 78 79 ··· 1527 1526 static bool arcturus_is_dpm_running(struct smu_context *smu) 1528 1527 { 1529 1528 int ret = 0; 1530 1530 - uint64_t feature_enabled; 1529 1529 + struct smu_feature_bits feature_enabled; 1531 1530 1532 1531 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 1533 1532 if (ret) 1534 1533 return false; 1535 1534 1536 1536 - return !!(feature_enabled & SMC_DPM_FEATURE); 1535 1535 + return smu_feature_bits_test_mask(&feature_enabled, 1536 1536 + arcturus_dpm_features.bits); 1537 1537 } 1538 1538 1539 1539 static int arcturus_dpm_set_vcn_enable(struct smu_context *smu,

+14 -10

drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c

reviewed

··· 60 60 61 61 static uint32_t cyan_skillfish_sclk_default; 62 62 63 63 - #define FEATURE_MASK(feature) (1ULL << feature) 64 64 - #define SMC_DPM_FEATURE ( \ 65 65 - FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \ 66 66 - FEATURE_MASK(FEATURE_SOC_DPM_BIT) | \ 67 67 - FEATURE_MASK(FEATURE_GFX_DPM_BIT)) 63 63 + static const struct smu_feature_bits cyan_skillfish_dpm_features = { 64 64 + .bits = { 65 65 + SMU_FEATURE_BIT_INIT(FEATURE_FCLK_DPM_BIT), 66 66 + SMU_FEATURE_BIT_INIT(FEATURE_SOC_DPM_BIT), 67 67 + SMU_FEATURE_BIT_INIT(FEATURE_GFX_DPM_BIT) 68 68 + } 69 69 + }; 68 70 69 71 static struct cmn2asic_msg_mapping cyan_skillfish_message_map[SMU_MSG_MAX_COUNT] = { 70 72 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0), ··· 363 361 { 364 362 struct amdgpu_device *adev = smu->adev; 365 363 int ret = 0; 366 366 - uint64_t feature_enabled; 364 364 + struct smu_feature_bits feature_enabled; 367 365 368 366 /* we need to re-init after suspend so return false */ 369 367 if (adev->in_suspend) ··· 380 378 cyan_skillfish_get_smu_metrics_data(smu, METRICS_CURR_GFXCLK, 381 379 &cyan_skillfish_sclk_default); 382 380 383 383 - return !!(feature_enabled & SMC_DPM_FEATURE); 381 381 + return smu_feature_bits_test_mask(&feature_enabled, 382 382 + cyan_skillfish_dpm_features.bits); 384 383 } 385 384 386 385 static ssize_t cyan_skillfish_get_gpu_metrics(struct smu_context *smu, ··· 568 565 return 0; 569 566 } 570 567 571 571 - static int cyan_skillfish_get_enabled_mask(struct smu_context *smu, 572 572 - uint64_t *feature_mask) 568 568 + static int 569 569 + cyan_skillfish_get_enabled_mask(struct smu_context *smu, 570 570 + struct smu_feature_bits *feature_mask) 573 571 { 574 572 if (!feature_mask) 575 573 return -EINVAL; 576 576 - memset(feature_mask, 0xff, sizeof(*feature_mask)); 574 574 + smu_feature_bits_fill(feature_mask); 577 575 578 576 return 0; 579 577 }

+15 -12

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

reviewed

··· 58 58 #undef pr_info 59 59 #undef pr_debug 60 60 61 61 - #define FEATURE_MASK(feature) (1ULL << feature) 62 62 - #define SMC_DPM_FEATURE ( \ 63 63 - FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \ 64 64 - FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ 65 65 - FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT) | \ 66 66 - FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ 67 67 - FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ 68 68 - FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) | \ 69 69 - FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ 70 70 - FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)) 61 61 + static const struct smu_feature_bits navi10_dpm_features = { 62 62 + .bits = { 63 63 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_PREFETCHER_BIT), 64 64 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT), 65 65 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFX_PACE_BIT), 66 66 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK_BIT), 67 67 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_SOCCLK_BIT), 68 68 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_MP0CLK_BIT), 69 69 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_LINK_BIT), 70 70 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_DCEFCLK_BIT) 71 71 + } 72 72 + }; 71 73 72 74 #define SMU_11_0_GFX_BUSY_THRESHOLD 15 73 75 ··· 1621 1619 static bool navi10_is_dpm_running(struct smu_context *smu) 1622 1620 { 1623 1621 int ret = 0; 1624 1624 - uint64_t feature_enabled; 1622 1622 + struct smu_feature_bits feature_enabled; 1625 1623 1626 1624 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 1627 1625 if (ret) 1628 1626 return false; 1629 1627 1630 1630 - return !!(feature_enabled & SMC_DPM_FEATURE); 1628 1628 + return smu_feature_bits_test_mask(&feature_enabled, 1629 1629 + navi10_dpm_features.bits); 1631 1630 } 1632 1631 1633 1632 static int navi10_get_fan_speed_rpm(struct smu_context *smu,

+15 -12

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

reviewed

··· 60 60 #undef pr_info 61 61 #undef pr_debug 62 62 63 63 - #define FEATURE_MASK(feature) (1ULL << feature) 64 64 - #define SMC_DPM_FEATURE ( \ 65 65 - FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \ 66 66 - FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ 67 67 - FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ 68 68 - FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ 69 69 - FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ 70 70 - FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ 71 71 - FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) | \ 72 72 - FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)) 63 63 + static const struct smu_feature_bits sienna_cichlid_dpm_features = { 64 64 + .bits = { 65 65 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_PREFETCHER_BIT), 66 66 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT), 67 67 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK_BIT), 68 68 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_LINK_BIT), 69 69 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_SOCCLK_BIT), 70 70 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_FCLK_BIT), 71 71 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_DCEFCLK_BIT), 72 72 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_MP0CLK_BIT) 73 73 + } 74 74 + }; 73 75 74 76 #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15 75 77 ··· 1536 1534 static bool sienna_cichlid_is_dpm_running(struct smu_context *smu) 1537 1535 { 1538 1536 int ret = 0; 1539 1539 - uint64_t feature_enabled; 1537 1537 + struct smu_feature_bits feature_enabled; 1540 1538 1541 1539 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 1542 1540 if (ret) 1543 1541 return false; 1544 1542 1545 1545 - return !!(feature_enabled & SMC_DPM_FEATURE); 1543 1543 + return smu_feature_bits_test_mask(&feature_enabled, 1544 1544 + sienna_cichlid_dpm_features.bits); 1546 1545 } 1547 1546 1548 1547 static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,

+1 -1

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

reviewed

··· 751 751 uint32_t feature_mask[2]; 752 752 753 753 if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) || 754 754 - feature->feature_num < 64) { 754 754 + feature->feature_num < SMU_FEATURE_NUM_DEFAULT) { 755 755 ret = -EINVAL; 756 756 goto failed; 757 757 }

+16 -13

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

reviewed

··· 58 58 #define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff_MASK 0x00000001L 59 59 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK 0x00000006L 60 60 61 61 - #define FEATURE_MASK(feature) (1ULL << feature) 62 62 - #define SMC_DPM_FEATURE ( \ 63 63 - FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ 64 64 - FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \ 65 65 - FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \ 66 66 - FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \ 67 67 - FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) | \ 68 68 - FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \ 69 69 - FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \ 70 70 - FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \ 71 71 - FEATURE_MASK(FEATURE_GFX_DPM_BIT)) 61 61 + static const struct smu_feature_bits vangogh_dpm_features = { 62 62 + .bits = { 63 63 + SMU_FEATURE_BIT_INIT(FEATURE_CCLK_DPM_BIT), 64 64 + SMU_FEATURE_BIT_INIT(FEATURE_VCN_DPM_BIT), 65 65 + SMU_FEATURE_BIT_INIT(FEATURE_FCLK_DPM_BIT), 66 66 + SMU_FEATURE_BIT_INIT(FEATURE_SOCCLK_DPM_BIT), 67 67 + SMU_FEATURE_BIT_INIT(FEATURE_MP0CLK_DPM_BIT), 68 68 + SMU_FEATURE_BIT_INIT(FEATURE_LCLK_DPM_BIT), 69 69 + SMU_FEATURE_BIT_INIT(FEATURE_SHUBCLK_DPM_BIT), 70 70 + SMU_FEATURE_BIT_INIT(FEATURE_DCFCLK_DPM_BIT), 71 71 + SMU_FEATURE_BIT_INIT(FEATURE_GFX_DPM_BIT) 72 72 + } 73 73 + }; 72 74 73 75 static struct cmn2asic_msg_mapping vangogh_message_map[SMU_MSG_MAX_COUNT] = { 74 76 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0), ··· 506 504 { 507 505 struct amdgpu_device *adev = smu->adev; 508 506 int ret = 0; 509 509 - uint64_t feature_enabled; 507 507 + struct smu_feature_bits feature_enabled; 510 508 511 509 /* we need to re-init after suspend so return false */ 512 510 if (adev->in_suspend) ··· 517 515 if (ret) 518 516 return false; 519 517 520 520 - return !!(feature_enabled & SMC_DPM_FEATURE); 518 518 + return smu_feature_bits_test_mask(&feature_enabled, 519 519 + vangogh_dpm_features.bits); 521 520 } 522 521 523 522 static int vangogh_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type,

+2 -2

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

reviewed

··· 1434 1434 } 1435 1435 1436 1436 static int renoir_get_enabled_mask(struct smu_context *smu, 1437 1437 - uint64_t *feature_mask) 1437 1437 + struct smu_feature_bits *feature_mask) 1438 1438 { 1439 1439 if (!feature_mask) 1440 1440 return -EINVAL; 1441 1441 - memset(feature_mask, 0xff, sizeof(*feature_mask)); 1441 1441 + smu_feature_bits_fill(feature_mask); 1442 1442 1443 1443 return 0; 1444 1444 }

+15 -11

drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

reviewed

··· 61 61 [smu_feature] = {1, (aldebaran_feature)} 62 62 63 63 #define FEATURE_MASK(feature) (1ULL << feature) 64 64 - #define SMC_DPM_FEATURE ( \ 65 65 - FEATURE_MASK(FEATURE_DATA_CALCULATIONS) | \ 66 66 - FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ 67 67 - FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ 68 68 - FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ 69 69 - FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ 70 70 - FEATURE_MASK(FEATURE_DPM_LCLK_BIT) | \ 71 71 - FEATURE_MASK(FEATURE_DPM_XGMI_BIT) | \ 72 72 - FEATURE_MASK(FEATURE_DPM_VCN_BIT)) 64 64 + static const struct smu_feature_bits aldebaran_dpm_features = { 65 65 + .bits = { 66 66 + SMU_FEATURE_BIT_INIT(FEATURE_DATA_CALCULATIONS), 67 67 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT), 68 68 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK_BIT), 69 69 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_SOCCLK_BIT), 70 70 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_FCLK_BIT), 71 71 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_LCLK_BIT), 72 72 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_XGMI_BIT), 73 73 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_VCN_BIT) 74 74 + } 75 75 + }; 73 76 74 77 #define smnPCIE_ESM_CTRL 0x111003D0 75 78 ··· 1398 1395 static bool aldebaran_is_dpm_running(struct smu_context *smu) 1399 1396 { 1400 1397 int ret; 1401 1401 - uint64_t feature_enabled; 1398 1398 + struct smu_feature_bits feature_enabled; 1402 1399 1403 1400 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 1404 1401 if (ret) 1405 1402 return false; 1406 1406 - return !!(feature_enabled & SMC_DPM_FEATURE); 1403 1403 + return smu_feature_bits_test_mask(&feature_enabled, 1404 1404 + aldebaran_dpm_features.bits); 1407 1405 } 1408 1406 1409 1407 static int aldebaran_i2c_xfer(struct i2c_adapter *i2c_adap,

+1 -1

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

reviewed

··· 762 762 uint32_t feature_mask[2]; 763 763 764 764 if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) || 765 765 - feature->feature_num < 64) 765 765 + feature->feature_num < SMU_FEATURE_NUM_DEFAULT) 766 766 return -EINVAL; 767 767 768 768 smu_feature_list_to_arr32(smu, SMU_FEATURE_LIST_ALLOWED, feature_mask);

+13 -10

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

reviewed

··· 59 59 60 60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) 61 61 62 62 - #define FEATURE_MASK(feature) (1ULL << feature) 63 63 - #define SMC_DPM_FEATURE ( \ 64 64 - FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ 65 65 - FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ 66 66 - FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ 67 67 - FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ 68 68 - FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ 69 69 - FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)) 62 62 + static const struct smu_feature_bits smu_v13_0_0_dpm_features = { 63 63 + .bits = { 64 64 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT), 65 65 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK_BIT), 66 66 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_LINK_BIT), 67 67 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_SOCCLK_BIT), 68 68 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_FCLK_BIT), 69 69 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_MP0CLK_BIT) 70 70 + } 71 71 + }; 70 72 71 73 #define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE 0x4000 72 74 ··· 691 689 static bool smu_v13_0_0_is_dpm_running(struct smu_context *smu) 692 690 { 693 691 int ret = 0; 694 694 - uint64_t feature_enabled; 692 692 + struct smu_feature_bits feature_enabled; 695 693 696 694 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 697 695 if (ret) 698 696 return false; 699 697 700 700 - return !!(feature_enabled & SMC_DPM_FEATURE); 698 698 + return smu_feature_bits_test_mask(&feature_enabled, 699 699 + smu_v13_0_0_dpm_features.bits); 701 700 } 702 701 703 702 static int smu_v13_0_0_system_features_control(struct smu_context *smu,

+12 -8

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c

reviewed

··· 52 52 #define SMU_13_0_12_FEA_MAP(smu_feature, smu_13_0_12_feature) \ 53 53 [smu_feature] = { 1, (smu_13_0_12_feature) } 54 54 55 55 - #define FEATURE_MASK(feature) (1ULL << feature) 56 56 - #define SMC_DPM_FEATURE \ 57 57 - (FEATURE_MASK(FEATURE_DATA_CALCULATION) | \ 58 58 - FEATURE_MASK(FEATURE_DPM_GFXCLK) | FEATURE_MASK(FEATURE_DPM_FCLK)) 55 55 + static const struct smu_feature_bits smu_v13_0_12_dpm_features = { 56 56 + .bits = { 57 57 + SMU_FEATURE_BIT_INIT(FEATURE_DATA_CALCULATION), 58 58 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK), 59 59 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_FCLK) 60 60 + } 61 61 + }; 59 62 60 63 #define NUM_JPEG_RINGS_FW 10 61 64 #define NUM_JPEG_RINGS_GPU_METRICS(gpu_metrics) \ ··· 202 199 } 203 200 204 201 static int smu_v13_0_12_get_enabled_mask(struct smu_context *smu, 205 205 - uint64_t *feature_mask) 202 202 + struct smu_feature_bits *feature_mask) 206 203 { 207 204 int ret; 208 205 209 206 ret = smu_cmn_get_enabled_mask(smu, feature_mask); 210 207 211 208 if (ret == -EIO) { 212 212 - *feature_mask = 0; 209 209 + smu_feature_bits_clearall(feature_mask); 213 210 ret = 0; 214 211 } 215 212 ··· 375 372 bool smu_v13_0_12_is_dpm_running(struct smu_context *smu) 376 373 { 377 374 int ret; 378 378 - uint64_t feature_enabled; 375 375 + struct smu_feature_bits feature_enabled; 379 376 380 377 ret = smu_v13_0_12_get_enabled_mask(smu, &feature_enabled); 381 378 382 379 if (ret) 383 380 return false; 384 381 385 385 - return !!(feature_enabled & SMC_DPM_FEATURE); 382 382 + return smu_feature_bits_test_mask(&feature_enabled, 383 383 + smu_v13_0_12_dpm_features.bits); 386 384 } 387 385 388 386 int smu_v13_0_12_get_smu_metrics_data(struct smu_context *smu,

+18 -16

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

reviewed

··· 52 52 #define mmMP1_SMN_C2PMSG_90 0x029a 53 53 #define mmMP1_SMN_C2PMSG_90_BASE_IDX 1 54 54 55 55 - #define FEATURE_MASK(feature) (1ULL << feature) 56 56 - 57 55 #define SMU_13_0_4_UMD_PSTATE_GFXCLK 938 58 56 #define SMU_13_0_4_UMD_PSTATE_SOCCLK 938 59 57 #define SMU_13_0_4_UMD_PSTATE_FCLK 1875 60 58 61 61 - #define SMC_DPM_FEATURE ( \ 62 62 - FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ 63 63 - FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \ 64 64 - FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \ 65 65 - FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \ 66 66 - FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) | \ 67 67 - FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \ 68 68 - FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \ 69 69 - FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT) | \ 70 70 - FEATURE_MASK(FEATURE_ISP_DPM_BIT) | \ 71 71 - FEATURE_MASK(FEATURE_IPU_DPM_BIT) | \ 72 72 - FEATURE_MASK(FEATURE_GFX_DPM_BIT)) 59 59 + static const struct smu_feature_bits smu_v13_0_4_dpm_features = { 60 60 + .bits = { 61 61 + SMU_FEATURE_BIT_INIT(FEATURE_CCLK_DPM_BIT), 62 62 + SMU_FEATURE_BIT_INIT(FEATURE_VCN_DPM_BIT), 63 63 + SMU_FEATURE_BIT_INIT(FEATURE_FCLK_DPM_BIT), 64 64 + SMU_FEATURE_BIT_INIT(FEATURE_SOCCLK_DPM_BIT), 65 65 + SMU_FEATURE_BIT_INIT(FEATURE_MP0CLK_DPM_BIT), 66 66 + SMU_FEATURE_BIT_INIT(FEATURE_LCLK_DPM_BIT), 67 67 + SMU_FEATURE_BIT_INIT(FEATURE_SHUBCLK_DPM_BIT), 68 68 + SMU_FEATURE_BIT_INIT(FEATURE_DCFCLK_DPM_BIT), 69 69 + SMU_FEATURE_BIT_INIT(FEATURE_ISP_DPM_BIT), 70 70 + SMU_FEATURE_BIT_INIT(FEATURE_IPU_DPM_BIT), 71 71 + SMU_FEATURE_BIT_INIT(FEATURE_GFX_DPM_BIT) 72 72 + } 73 73 + }; 73 74 74 75 static struct cmn2asic_msg_mapping smu_v13_0_4_message_map[SMU_MSG_MAX_COUNT] = { 75 76 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), ··· 213 212 static bool smu_v13_0_4_is_dpm_running(struct smu_context *smu) 214 213 { 215 214 int ret = 0; 216 216 - uint64_t feature_enabled; 215 215 + struct smu_feature_bits feature_enabled; 217 216 218 217 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 219 218 220 219 if (ret) 221 220 return false; 222 221 223 223 - return !!(feature_enabled & SMC_DPM_FEATURE); 222 222 + return smu_feature_bits_test_mask(&feature_enabled, 223 223 + smu_v13_0_4_dpm_features.bits); 224 224 } 225 225 226 226 static int smu_v13_0_4_system_features_control(struct smu_context *smu, bool en)

+16 -13

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

reviewed

··· 51 51 #define mmMP1_C2PMSG_33 (0xbee261 + 0xb00000 / 4) 52 52 #define mmMP1_C2PMSG_33_BASE_IDX 0 53 53 54 54 - #define FEATURE_MASK(feature) (1ULL << feature) 55 55 - #define SMC_DPM_FEATURE ( \ 56 56 - FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ 57 57 - FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \ 58 58 - FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \ 59 59 - FEATURE_MASK(FEATURE_GFX_DPM_BIT) | \ 60 60 - FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \ 61 61 - FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT) | \ 62 62 - FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT)| \ 63 63 - FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT)| \ 64 64 - FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT)) 54 54 + static const struct smu_feature_bits smu_v13_0_5_dpm_features = { 55 55 + .bits = { 56 56 + SMU_FEATURE_BIT_INIT(FEATURE_CCLK_DPM_BIT), 57 57 + SMU_FEATURE_BIT_INIT(FEATURE_FCLK_DPM_BIT), 58 58 + SMU_FEATURE_BIT_INIT(FEATURE_LCLK_DPM_BIT), 59 59 + SMU_FEATURE_BIT_INIT(FEATURE_GFX_DPM_BIT), 60 60 + SMU_FEATURE_BIT_INIT(FEATURE_VCN_DPM_BIT), 61 61 + SMU_FEATURE_BIT_INIT(FEATURE_DCFCLK_DPM_BIT), 62 62 + SMU_FEATURE_BIT_INIT(FEATURE_SOCCLK_DPM_BIT), 63 63 + SMU_FEATURE_BIT_INIT(FEATURE_MP0CLK_DPM_BIT), 64 64 + SMU_FEATURE_BIT_INIT(FEATURE_SHUBCLK_DPM_BIT) 65 65 + } 66 66 + }; 65 67 66 68 static struct cmn2asic_msg_mapping smu_v13_0_5_message_map[SMU_MSG_MAX_COUNT] = { 67 69 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), ··· 232 230 static bool smu_v13_0_5_is_dpm_running(struct smu_context *smu) 233 231 { 234 232 int ret = 0; 235 235 - uint64_t feature_enabled; 233 233 + struct smu_feature_bits feature_enabled; 236 234 237 235 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 238 236 239 237 if (ret) 240 238 return false; 241 239 242 242 - return !!(feature_enabled & SMC_DPM_FEATURE); 240 240 + return smu_feature_bits_test_mask(&feature_enabled, 241 241 + smu_v13_0_5_dpm_features.bits); 243 242 } 244 243 245 244 static int smu_v13_0_5_mode_reset(struct smu_context *smu, int type)

+30 -24

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

reviewed

··· 76 76 [smu_feature] = { 1, (smu_13_0_6_feature) } 77 77 78 78 #define FEATURE_MASK(feature) (1ULL << feature) 79 79 - #define SMC_DPM_FEATURE \ 80 80 - (FEATURE_MASK(FEATURE_DATA_CALCULATION) | \ 81 81 - FEATURE_MASK(FEATURE_DPM_GFXCLK) | FEATURE_MASK(FEATURE_DPM_UCLK) | \ 82 82 - FEATURE_MASK(FEATURE_DPM_SOCCLK) | FEATURE_MASK(FEATURE_DPM_FCLK) | \ 83 83 - FEATURE_MASK(FEATURE_DPM_LCLK) | FEATURE_MASK(FEATURE_DPM_XGMI) | \ 84 84 - FEATURE_MASK(FEATURE_DPM_VCN)) 79 79 + static const struct smu_feature_bits smu_v13_0_6_dpm_features = { 80 80 + .bits = { 81 81 + SMU_FEATURE_BIT_INIT(FEATURE_DATA_CALCULATION), 82 82 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK), 83 83 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK), 84 84 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_SOCCLK), 85 85 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_FCLK), 86 86 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_LCLK), 87 87 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_XGMI), 88 88 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_VCN) 89 89 + } 90 90 + }; 85 91 86 92 #define smnPCIE_ESM_CTRL 0x93D0 87 93 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x1a340288 ··· 2272 2266 } 2273 2267 2274 2268 static int smu_v13_0_6_get_enabled_mask(struct smu_context *smu, 2275 2275 - uint64_t *feature_mask) 2269 2269 + struct smu_feature_bits *feature_mask) 2276 2270 { 2277 2271 int ret; 2278 2272 2279 2273 ret = smu_cmn_get_enabled_mask(smu, feature_mask); 2280 2274 2281 2275 if (ret == -EIO && !smu_v13_0_6_cap_supported(smu, SMU_CAP(DPM))) { 2282 2282 - *feature_mask = 0; 2276 2276 + smu_feature_bits_clearall(feature_mask); 2283 2277 ret = 0; 2284 2278 } 2285 2279 ··· 2289 2283 static bool smu_v13_0_6_is_dpm_running(struct smu_context *smu) 2290 2284 { 2291 2285 int ret; 2292 2292 - uint64_t feature_enabled; 2286 2286 + struct smu_feature_bits feature_enabled; 2293 2287 2294 2288 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12)) 2295 2289 return smu_v13_0_12_is_dpm_running(smu); ··· 2299 2293 if (ret) 2300 2294 return false; 2301 2295 2302 2302 - return !!(feature_enabled & SMC_DPM_FEATURE); 2296 2296 + return smu_feature_bits_test_mask(&feature_enabled, 2297 2297 + smu_v13_0_6_dpm_features.bits); 2303 2298 } 2304 2299 2305 2300 static int smu_v13_0_6_request_i2c_xfer(struct smu_context *smu, ··· 2564 2557 const u8 num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS_4_0_3; 2565 2558 int version = smu_v13_0_6_get_metrics_version(smu); 2566 2559 struct smu_v13_0_6_partition_metrics *xcp_metrics; 2567 2567 - MetricsTableV0_t *metrics_v0 __free(kfree) = NULL; 2560 2560 + struct smu_table_context *smu_table = &smu->smu_table; 2568 2561 struct amdgpu_device *adev = smu->adev; 2569 2562 int ret, inst, i, j, k, idx; 2563 2563 + MetricsTableV0_t *metrics_v0; 2570 2564 MetricsTableV1_t *metrics_v1; 2571 2565 MetricsTableV2_t *metrics_v2; 2572 2566 struct amdgpu_xcp *xcp; ··· 2587 2579 xcp_metrics = (struct smu_v13_0_6_partition_metrics *)table; 2588 2580 smu_v13_0_6_partition_metrics_init(xcp_metrics, 1, 1); 2589 2581 2590 2590 - metrics_v0 = kzalloc(METRICS_TABLE_SIZE, GFP_KERNEL); 2591 2591 - if (!metrics_v0) 2592 2592 - return -ENOMEM; 2593 2593 - 2594 2594 - ret = smu_v13_0_6_get_metrics_table(smu, metrics_v0, false); 2582 2582 + ret = smu_v13_0_6_get_metrics_table(smu, NULL, false); 2595 2583 if (ret) 2596 2584 return ret; 2585 2585 + 2586 2586 + metrics_v0 = (MetricsTableV0_t *)smu_table->metrics_table; 2597 2587 2598 2588 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == 2599 2589 IP_VERSION(13, 0, 12) && ··· 2599 2593 return smu_v13_0_12_get_xcp_metrics(smu, xcp, table, 2600 2594 metrics_v0); 2601 2595 2602 2602 - metrics_v1 = (MetricsTableV1_t *)metrics_v0; 2603 2603 - metrics_v2 = (MetricsTableV2_t *)metrics_v0; 2596 2596 + metrics_v1 = (MetricsTableV1_t *)smu_table->metrics_table; 2597 2597 + metrics_v2 = (MetricsTableV2_t *)smu_table->metrics_table; 2604 2598 2605 2599 per_inst = smu_v13_0_6_cap_supported(smu, SMU_CAP(PER_INST_METRICS)); 2606 2600 ··· 2676 2670 { 2677 2671 struct smu_v13_0_6_gpu_metrics *gpu_metrics; 2678 2672 int version = smu_v13_0_6_get_metrics_version(smu); 2679 2679 - MetricsTableV0_t *metrics_v0 __free(kfree) = NULL; 2673 2673 + struct smu_table_context *smu_table = &smu->smu_table; 2680 2674 struct amdgpu_device *adev = smu->adev; 2681 2675 int ret = 0, xcc_id, inst, i, j; 2676 2676 + MetricsTableV0_t *metrics_v0; 2682 2677 MetricsTableV1_t *metrics_v1; 2683 2678 MetricsTableV2_t *metrics_v2; 2684 2679 u16 link_width_level; 2685 2680 u8 num_jpeg_rings; 2686 2681 bool per_inst; 2687 2682 2688 2688 - metrics_v0 = kzalloc(METRICS_TABLE_SIZE, GFP_KERNEL); 2689 2689 - ret = smu_v13_0_6_get_metrics_table(smu, metrics_v0, false); 2683 2683 + ret = smu_v13_0_6_get_metrics_table(smu, NULL, false); 2690 2684 if (ret) 2691 2685 return ret; 2692 2686 2693 2693 - metrics_v2 = (MetricsTableV2_t *)metrics_v0; 2687 2687 + metrics_v0 = (MetricsTableV0_t *)smu_table->metrics_table; 2694 2688 gpu_metrics = (struct smu_v13_0_6_gpu_metrics *)smu_driver_table_ptr( 2695 2689 smu, SMU_DRIVER_TABLE_GPU_METRICS); 2696 2690 ··· 2701 2695 goto fill; 2702 2696 } 2703 2697 2704 2704 - metrics_v1 = (MetricsTableV1_t *)metrics_v0; 2705 2705 - metrics_v2 = (MetricsTableV2_t *)metrics_v0; 2698 2698 + metrics_v1 = (MetricsTableV1_t *)smu_table->metrics_table; 2699 2699 + metrics_v2 = (MetricsTableV2_t *)smu_table->metrics_table; 2706 2700 2707 2701 gpu_metrics->temperature_hotspot = 2708 2702 SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature, version));

+13 -10

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

reviewed

··· 59 59 60 60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) 61 61 62 62 - #define FEATURE_MASK(feature) (1ULL << feature) 63 63 - #define SMC_DPM_FEATURE ( \ 64 64 - FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ 65 65 - FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ 66 66 - FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ 67 67 - FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ 68 68 - FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ 69 69 - FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)) 62 62 + static const struct smu_feature_bits smu_v13_0_7_dpm_features = { 63 63 + .bits = { 64 64 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT), 65 65 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK_BIT), 66 66 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_LINK_BIT), 67 67 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_SOCCLK_BIT), 68 68 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_FCLK_BIT), 69 69 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_MP0CLK_BIT) 70 70 + } 71 71 + }; 70 72 71 73 #define smnMP1_FIRMWARE_FLAGS_SMU_13_0_7 0x3b10028 72 74 ··· 699 697 static bool smu_v13_0_7_is_dpm_running(struct smu_context *smu) 700 698 { 701 699 int ret = 0; 702 702 - uint64_t feature_enabled; 700 700 + struct smu_feature_bits feature_enabled; 703 701 704 702 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 705 703 if (ret) 706 704 return false; 707 705 708 708 - return !!(feature_enabled & SMC_DPM_FEATURE); 706 706 + return smu_feature_bits_test_mask(&feature_enabled, 707 707 + smu_v13_0_7_dpm_features.bits); 709 708 } 710 709 711 710 static uint32_t smu_v13_0_7_get_throttler_status(SmuMetrics_t *metrics)

+16 -13

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

reviewed

··· 55 55 #define SMU_13_0_1_UMD_PSTATE_SOCCLK 678 56 56 #define SMU_13_0_1_UMD_PSTATE_FCLK 1800 57 57 58 58 - #define FEATURE_MASK(feature) (1ULL << feature) 59 59 - #define SMC_DPM_FEATURE ( \ 60 60 - FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ 61 61 - FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \ 62 62 - FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \ 63 63 - FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \ 64 64 - FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) | \ 65 65 - FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \ 66 66 - FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \ 67 67 - FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \ 68 68 - FEATURE_MASK(FEATURE_GFX_DPM_BIT)) 58 58 + static const struct smu_feature_bits yellow_carp_dpm_features = { 59 59 + .bits = { 60 60 + SMU_FEATURE_BIT_INIT(FEATURE_CCLK_DPM_BIT), 61 61 + SMU_FEATURE_BIT_INIT(FEATURE_VCN_DPM_BIT), 62 62 + SMU_FEATURE_BIT_INIT(FEATURE_FCLK_DPM_BIT), 63 63 + SMU_FEATURE_BIT_INIT(FEATURE_SOCCLK_DPM_BIT), 64 64 + SMU_FEATURE_BIT_INIT(FEATURE_MP0CLK_DPM_BIT), 65 65 + SMU_FEATURE_BIT_INIT(FEATURE_LCLK_DPM_BIT), 66 66 + SMU_FEATURE_BIT_INIT(FEATURE_SHUBCLK_DPM_BIT), 67 67 + SMU_FEATURE_BIT_INIT(FEATURE_DCFCLK_DPM_BIT), 68 68 + SMU_FEATURE_BIT_INIT(FEATURE_GFX_DPM_BIT) 69 69 + } 70 70 + }; 69 71 70 72 static struct cmn2asic_msg_mapping yellow_carp_message_map[SMU_MSG_MAX_COUNT] = { 71 73 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), ··· 259 257 static bool yellow_carp_is_dpm_running(struct smu_context *smu) 260 258 { 261 259 int ret = 0; 262 262 - uint64_t feature_enabled; 260 260 + struct smu_feature_bits feature_enabled; 263 261 264 262 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 265 263 266 264 if (ret) 267 265 return false; 268 266 269 269 - return !!(feature_enabled & SMC_DPM_FEATURE); 267 267 + return smu_feature_bits_test_mask(&feature_enabled, 268 268 + yellow_carp_dpm_features.bits); 270 269 } 271 270 272 271 static int yellow_carp_post_smu_init(struct smu_context *smu)

+1 -1

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

reviewed

··· 747 747 uint32_t feature_mask[2]; 748 748 749 749 if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) || 750 750 - feature->feature_num < 64) 750 750 + feature->feature_num < SMU_FEATURE_NUM_DEFAULT) 751 751 return -EINVAL; 752 752 753 753 smu_feature_list_to_arr32(smu, SMU_FEATURE_LIST_ALLOWED, feature_mask);

+18 -15

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

reviewed

··· 72 72 #define SMU_14_0_4_UMD_PSTATE_GFXCLK 938 73 73 #define SMU_14_0_4_UMD_PSTATE_SOCCLK 938 74 74 75 75 - #define FEATURE_MASK(feature) (1ULL << feature) 76 76 - #define SMC_DPM_FEATURE ( \ 77 77 - FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ 78 78 - FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \ 79 79 - FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \ 80 80 - FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \ 81 81 - FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \ 82 82 - FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \ 83 83 - FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \ 84 84 - FEATURE_MASK(FEATURE_ISP_DPM_BIT)| \ 85 85 - FEATURE_MASK(FEATURE_IPU_DPM_BIT) | \ 86 86 - FEATURE_MASK(FEATURE_GFX_DPM_BIT) | \ 87 87 - FEATURE_MASK(FEATURE_VPE_DPM_BIT)) 75 75 + static const struct smu_feature_bits smu_v14_0_0_dpm_features = { 76 76 + .bits = { 77 77 + SMU_FEATURE_BIT_INIT(FEATURE_CCLK_DPM_BIT), 78 78 + SMU_FEATURE_BIT_INIT(FEATURE_VCN_DPM_BIT), 79 79 + SMU_FEATURE_BIT_INIT(FEATURE_FCLK_DPM_BIT), 80 80 + SMU_FEATURE_BIT_INIT(FEATURE_SOCCLK_DPM_BIT), 81 81 + SMU_FEATURE_BIT_INIT(FEATURE_LCLK_DPM_BIT), 82 82 + SMU_FEATURE_BIT_INIT(FEATURE_SHUBCLK_DPM_BIT), 83 83 + SMU_FEATURE_BIT_INIT(FEATURE_DCFCLK_DPM_BIT), 84 84 + SMU_FEATURE_BIT_INIT(FEATURE_ISP_DPM_BIT), 85 85 + SMU_FEATURE_BIT_INIT(FEATURE_IPU_DPM_BIT), 86 86 + SMU_FEATURE_BIT_INIT(FEATURE_GFX_DPM_BIT), 87 87 + SMU_FEATURE_BIT_INIT(FEATURE_VPE_DPM_BIT) 88 88 + } 89 89 + }; 88 90 89 91 enum smu_mall_pg_config { 90 92 SMU_MALL_PG_CONFIG_PMFW_CONTROL = 0, ··· 472 470 static bool smu_v14_0_0_is_dpm_running(struct smu_context *smu) 473 471 { 474 472 int ret = 0; 475 475 - uint64_t feature_enabled; 473 473 + struct smu_feature_bits feature_enabled; 476 474 477 475 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 478 476 479 477 if (ret) 480 478 return false; 481 479 482 482 - return !!(feature_enabled & SMC_DPM_FEATURE); 480 480 + return smu_feature_bits_test_mask(&feature_enabled, 481 481 + smu_v14_0_0_dpm_features.bits); 483 482 } 484 483 485 484 static int smu_v14_0_0_set_watermarks_table(struct smu_context *smu,

+10 -9

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

reviewed

··· 56 56 57 57 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) 58 58 59 59 - #define FEATURE_MASK(feature) (1ULL << feature) 60 60 - #define SMC_DPM_FEATURE ( \ 61 61 - FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ 62 62 - FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ 63 63 - FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ 64 64 - FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ 65 65 - FEATURE_MASK(FEATURE_DPM_FCLK_BIT)) 59 59 + static const struct smu_feature_bits smu_v14_0_2_dpm_features = { 60 60 + .bits = { SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT), 61 61 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK_BIT), 62 62 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_LINK_BIT), 63 63 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_SOCCLK_BIT), 64 64 + SMU_FEATURE_BIT_INIT(FEATURE_DPM_FCLK_BIT) } 65 65 + }; 66 66 67 67 #define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE 0x4000 68 68 #define DEBUGSMC_MSG_Mode1Reset 2 ··· 589 589 static bool smu_v14_0_2_is_dpm_running(struct smu_context *smu) 590 590 { 591 591 int ret = 0; 592 592 - uint64_t feature_enabled; 592 592 + struct smu_feature_bits feature_enabled; 593 593 594 594 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 595 595 if (ret) 596 596 return false; 597 597 598 598 - return !!(feature_enabled & SMC_DPM_FEATURE); 598 598 + return smu_feature_bits_test_mask(&feature_enabled, 599 599 + smu_v14_0_2_dpm_features.bits); 599 600 } 600 601 601 602 static uint32_t smu_v14_0_2_get_throttler_status(SmuMetrics_t *metrics)

+1 -1

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

reviewed

··· 716 716 uint32_t feature_mask[2]; 717 717 718 718 if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) || 719 719 - feature->feature_num < 64) 719 719 + feature->feature_num < SMU_FEATURE_NUM_DEFAULT) 720 720 return -EINVAL; 721 721 722 722 smu_feature_list_to_arr32(smu, SMU_FEATURE_LIST_ALLOWED, feature_mask);

+18 -15

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

reviewed

··· 70 70 #define SMU_15_0_UMD_PSTATE_FCLK 1800 71 71 72 72 73 73 - #define FEATURE_MASK(feature) (1ULL << feature) 74 74 - #define SMC_DPM_FEATURE ( \ 75 75 - FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ 76 76 - FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \ 77 77 - FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \ 78 78 - FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \ 79 79 - FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \ 80 80 - FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \ 81 81 - FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \ 82 82 - FEATURE_MASK(FEATURE_ISP_DPM_BIT)| \ 83 83 - FEATURE_MASK(FEATURE_NPU_DPM_BIT) | \ 84 84 - FEATURE_MASK(FEATURE_GFX_DPM_BIT) | \ 85 85 - FEATURE_MASK(FEATURE_VPE_DPM_BIT)) 73 73 + static const struct smu_feature_bits smu_v15_0_0_dpm_features = { 74 74 + .bits = { 75 75 + SMU_FEATURE_BIT_INIT(FEATURE_CCLK_DPM_BIT), 76 76 + SMU_FEATURE_BIT_INIT(FEATURE_VCN_DPM_BIT), 77 77 + SMU_FEATURE_BIT_INIT(FEATURE_FCLK_DPM_BIT), 78 78 + SMU_FEATURE_BIT_INIT(FEATURE_SOCCLK_DPM_BIT), 79 79 + SMU_FEATURE_BIT_INIT(FEATURE_LCLK_DPM_BIT), 80 80 + SMU_FEATURE_BIT_INIT(FEATURE_SHUBCLK_DPM_BIT), 81 81 + SMU_FEATURE_BIT_INIT(FEATURE_DCFCLK_DPM_BIT), 82 82 + SMU_FEATURE_BIT_INIT(FEATURE_ISP_DPM_BIT), 83 83 + SMU_FEATURE_BIT_INIT(FEATURE_NPU_DPM_BIT), 84 84 + SMU_FEATURE_BIT_INIT(FEATURE_GFX_DPM_BIT), 85 85 + SMU_FEATURE_BIT_INIT(FEATURE_VPE_DPM_BIT) 86 86 + } 87 87 + }; 86 88 87 89 enum smu_mall_pg_config { 88 90 SMU_MALL_PG_CONFIG_PMFW_CONTROL = 0, ··· 446 444 static bool smu_v15_0_0_is_dpm_running(struct smu_context *smu) 447 445 { 448 446 int ret = 0; 449 449 - uint64_t feature_enabled; 447 447 + struct smu_feature_bits feature_enabled; 450 448 451 449 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 452 450 453 451 if (ret) 454 452 return false; 455 453 456 456 - return !!(feature_enabled & SMC_DPM_FEATURE); 454 454 + return smu_feature_bits_test_mask(&feature_enabled, 455 455 + smu_v15_0_0_dpm_features.bits); 457 456 } 458 457 459 458 static int smu_v15_0_0_set_watermarks_table(struct smu_context *smu,

+39 -37

drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c

reviewed

··· 690 690 } 691 691 692 692 static int __smu_get_enabled_features(struct smu_context *smu, 693 693 - uint64_t *enabled_features) 693 693 + struct smu_feature_bits *enabled_features) 694 694 { 695 695 return smu_cmn_call_asic_func(get_enabled_mask, smu, enabled_features); 696 696 } ··· 699 699 enum smu_feature_mask mask) 700 700 { 701 701 struct amdgpu_device *adev = smu->adev; 702 702 - uint64_t enabled_features; 702 702 + struct smu_feature_bits enabled_features; 703 703 int feature_id; 704 704 705 705 if (__smu_get_enabled_features(smu, &enabled_features)) { ··· 712 712 * enabled. Also considering they have no feature_map available, the 713 713 * check here can avoid unwanted feature_map check below. 714 714 */ 715 715 - if (enabled_features == ULLONG_MAX) 715 715 + if (smu_feature_bits_full(&enabled_features, 716 716 + smu->smu_feature.feature_num)) 716 717 return 1; 717 718 718 719 feature_id = smu_cmn_to_asic_specific_index(smu, ··· 722 721 if (feature_id < 0) 723 722 return 0; 724 723 725 725 - return test_bit(feature_id, (unsigned long *)&enabled_features); 724 724 + return smu_feature_bits_is_set(&enabled_features, feature_id); 726 725 } 727 726 728 727 bool smu_cmn_clk_dpm_is_enabled(struct smu_context *smu, ··· 764 763 } 765 764 766 765 int smu_cmn_get_enabled_mask(struct smu_context *smu, 767 767 - uint64_t *feature_mask) 766 766 + struct smu_feature_bits *feature_mask) 768 767 { 769 769 - uint32_t *feature_mask_high; 770 770 - uint32_t *feature_mask_low; 768 768 + uint32_t features[2]; 771 769 int ret = 0, index = 0; 772 770 773 771 if (!feature_mask) 774 772 return -EINVAL; 775 773 776 776 - feature_mask_low = &((uint32_t *)feature_mask)[0]; 777 777 - feature_mask_high = &((uint32_t *)feature_mask)[1]; 778 778 - 779 774 index = smu_cmn_to_asic_specific_index(smu, 780 775 CMN2ASIC_MAPPING_MSG, 781 776 SMU_MSG_GetEnabledSmuFeatures); 782 777 if (index > 0) { 783 783 - ret = smu_cmn_send_smc_msg_with_param(smu, 784 784 - SMU_MSG_GetEnabledSmuFeatures, 785 785 - 0, 786 786 - feature_mask_low); 778 778 + ret = smu_cmn_send_smc_msg_with_param( 779 779 + smu, SMU_MSG_GetEnabledSmuFeatures, 0, &features[0]); 787 780 if (ret) 788 781 return ret; 789 782 790 790 - ret = smu_cmn_send_smc_msg_with_param(smu, 791 791 - SMU_MSG_GetEnabledSmuFeatures, 792 792 - 1, 793 793 - feature_mask_high); 783 783 + ret = smu_cmn_send_smc_msg_with_param( 784 784 + smu, SMU_MSG_GetEnabledSmuFeatures, 1, &features[1]); 794 785 } else { 795 795 - ret = smu_cmn_send_smc_msg(smu, 796 796 - SMU_MSG_GetEnabledSmuFeaturesHigh, 797 797 - feature_mask_high); 786 786 + ret = smu_cmn_send_smc_msg( 787 787 + smu, SMU_MSG_GetEnabledSmuFeaturesHigh, &features[1]); 798 788 if (ret) 799 789 return ret; 800 790 801 801 - ret = smu_cmn_send_smc_msg(smu, 802 802 - SMU_MSG_GetEnabledSmuFeaturesLow, 803 803 - feature_mask_low); 791 791 + ret = smu_cmn_send_smc_msg( 792 792 + smu, SMU_MSG_GetEnabledSmuFeaturesLow, &features[0]); 804 793 } 794 794 + 795 795 + if (!ret) 796 796 + smu_feature_bits_from_arr32(feature_mask, features, 797 797 + SMU_FEATURE_NUM_DEFAULT); 805 798 806 799 return ret; 807 800 } ··· 881 886 char *buf) 882 887 { 883 888 int8_t sort_feature[MAX(SMU_FEATURE_COUNT, SMU_FEATURE_MAX)]; 884 884 - uint64_t feature_mask; 889 889 + struct smu_feature_bits feature_mask; 890 890 + uint32_t features[2]; 885 891 int i, feature_index; 886 892 uint32_t count = 0; 887 893 size_t size = 0; ··· 890 894 if (__smu_get_enabled_features(smu, &feature_mask)) 891 895 return 0; 892 896 893 893 - size = sysfs_emit_at(buf, size, "features high: 0x%08x low: 0x%08x\n", 894 894 - upper_32_bits(feature_mask), lower_32_bits(feature_mask)); 897 897 + /* TBD: Need to handle for > 64 bits */ 898 898 + smu_feature_bits_to_arr32(&feature_mask, features, 64); 899 899 + size = sysfs_emit_at(buf, size, "features high: 0x%08x low: 0x%08x\n", 900 900 + features[1], features[0]); 895 901 896 902 memset(sort_feature, -1, sizeof(sort_feature)); 897 903 ··· 910 912 size += sysfs_emit_at(buf, size, "%-2s. %-20s %-3s : %-s\n", 911 913 "No", "Feature", "Bit", "State"); 912 914 913 913 - for (feature_index = 0; feature_index < SMU_FEATURE_MAX; feature_index++) { 915 915 + for (feature_index = 0; feature_index < smu->smu_feature.feature_num; 916 916 + feature_index++) { 914 917 if (sort_feature[feature_index] < 0) 915 918 continue; 916 919 917 917 - size += sysfs_emit_at(buf, size, "%02d. %-20s (%2d) : %s\n", 918 918 - count++, 919 919 - smu_get_feature_name(smu, sort_feature[feature_index]), 920 920 - feature_index, 921 921 - !!test_bit(feature_index, (unsigned long *)&feature_mask) ? 922 922 - "enabled" : "disabled"); 920 920 + size += sysfs_emit_at( 921 921 + buf, size, "%02d. %-20s (%2d) : %s\n", count++, 922 922 + smu_get_feature_name(smu, sort_feature[feature_index]), 923 923 + feature_index, 924 924 + smu_feature_bits_is_set(&feature_mask, feature_index) ? 925 925 + "enabled" : 926 926 + "disabled"); 923 927 } 924 928 925 929 return size; ··· 931 931 uint64_t new_mask) 932 932 { 933 933 int ret = 0; 934 934 - uint64_t feature_mask; 934 934 + struct smu_feature_bits feature_mask; 935 935 + uint64_t feature_mask_u64; 935 936 uint64_t feature_2_enabled = 0; 936 937 uint64_t feature_2_disabled = 0; 937 938 ··· 940 939 if (ret) 941 940 return ret; 942 941 943 943 - feature_2_enabled = ~feature_mask & new_mask; 944 944 - feature_2_disabled = feature_mask & ~new_mask; 942 942 + feature_mask_u64 = *(uint64_t *)feature_mask.bits; 943 943 + feature_2_enabled = ~feature_mask_u64 & new_mask; 944 944 + feature_2_disabled = feature_mask_u64 & ~new_mask; 945 945 946 946 if (feature_2_enabled) { 947 947 ret = smu_cmn_feature_update_enable_state(smu,

+1 -1

drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h

reviewed

··· 141 141 enum smu_clk_type clk_type); 142 142 143 143 int smu_cmn_get_enabled_mask(struct smu_context *smu, 144 144 - uint64_t *feature_mask); 144 144 + struct smu_feature_bits *feature_mask); 145 145 146 146 uint64_t smu_cmn_get_indep_throttler_status( 147 147 const unsigned long dep_status,

+1 -1

drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c

reviewed

··· 299 299 300 300 count = ACA_REG_MISC0_ERRCNT(bank->regs[ACA_REG_IDX__MISC0]); 301 301 if (bank->ecc_type == RAS_ERR_TYPE__UE) { 302 302 - if (ext_error_code != 0 && ext_error_code != 9) 302 302 + if (ext_error_code != 0 && ext_error_code != 1 && ext_error_code != 9) 303 303 count = 0ULL; 304 304 ecc->ue_count = count; 305 305 } else if (bank->ecc_type == RAS_ERR_TYPE__CE) {